JP2008517448A - リバーストーン処理を利用したリセス構造の形成方法 - Google Patents
リバーストーン処理を利用したリセス構造の形成方法 Download PDFInfo
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- XMLYCEVDHLAQEL-UHFFFAOYSA-N 2-hydroxy-2-methyl-1-phenylpropan-1-one Chemical compound CC(C)(O)C(=O)C1=CC=CC=C1 XMLYCEVDHLAQEL-UHFFFAOYSA-N 0.000 description 1
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
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- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 1
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- LNMQRPPRQDGUDR-UHFFFAOYSA-N hexyl prop-2-enoate Chemical compound CCCCCCOC(=O)C=C LNMQRPPRQDGUDR-UHFFFAOYSA-N 0.000 description 1
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- BPSIOYPQMFLKFR-UHFFFAOYSA-N trimethoxy-[3-(oxiran-2-ylmethoxy)propyl]silane Chemical compound CO[Si](OC)(OC)CCCOCC1CO1 BPSIOYPQMFLKFR-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00444—Surface micromachining, i.e. structuring layers on the substrate
- B81C1/0046—Surface micromachining, i.e. structuring layers on the substrate using stamping, e.g. imprinting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76817—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics using printing or stamping techniques
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- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
【選択図】図4
Description
組成1
アクリル酸イソボルニル
アクリル酸n−ヘキシル
エチレングリコールジアクリラート
2−ヒドロキシ−2−メチル−1−フェニル−プロパン−1−オン
組成2
ヒドロキシル−機能性ポリシロキサン
キサメトキシメチルメラミン
トルエンスルホン酸
メチルアミルケトン
組成3
ヒドロキシル−機能性ポリシロキサン
キサメトキシメチルメラミン
γ−グリシドキシプロピルトリメトキシシラン
トルエンスルホン酸
メチル アミル ケトン
Claims (10)
- 表面にリセス部を形成する方法であって、
前記表面上に第1の寸法と形状を備えたフューチャを有するパターン形成層を形成するステップと、
前記第1の寸法とは異なる第2の寸法を有する、前記形状の反転形状を前記表面に転写するステップと、
を含む方法。 - 前記転写ステップは、前記形状の反転形状を基板に転写するステップを更に含む請求項1に記載の方法。
- 前記転写ステップは、前記形状の反転形状を基層に転写するステップを更に含む請求項1に記載の方法。
- 前記転写ステップは、前記形状の反転形状を前記フューチャの1つと重なった前記表面領域に転写するステップを含む請求項1に記載の方法。
- 前記転写ステップは、前記フューチャと重なった基層領域に前記形状の反転形状を転写するステップを含む請求項1に記載の方法。
- 前記転写ステップは、前記フューチャから前記表面に延びる複数の突出部を生成するステップと、順応層で前記複数の突出部を覆うステップとを更に含み、前記順応層と前記突出部の小部分が同等のシリコン含有量を有する部材から形成されることを特徴とする請求項1に記載の方法。
- 前記転写ステップは、前記フューチャから前記表面に延びる複数の突出部を生成するステップと、順応層で前記複数の突出部を覆うステップとを更に含み、前記順応層と前記突出部の第1の小部分が同等のシリコン含有量を有する部材から形成されており、前記突出部の第2の小部分は前記第1の部分とは異なるシリコン含有量を有することを特徴とする請求項1に記載の方法。
- 前記転写ステップは、前記フューチャから前記表面に延びる複数の突出部を生成するステップと、順応層で前記複数の突出部を覆うステップとを更に含み、前記順応層と前記突出部の第1の部分は所与のエッチング化学作用に対して同様のエッチング特性を有し、前記突出部の第2の部分は前記所与のエッチング化学作用に対して前記順応層とは異なるエッチング特性を有することを特徴とする請求項1に記載の方法。
- 前記第2の寸法は前記第1の寸法よりも小さいことを特徴とする請求項1に記載の方法。
- 前記形成ステップは、前記パターン形成層と前記表面との間に転写層を配置するステップを更に含み、前記転写ステップは、前記転写層をエッチングし、第1の方向に沿った前記反転形状の寸法と実質的に等しい、前記第1の方向に沿った寸法を有する複数の突出部を生成するステップを更に含むことを特徴とする請求項1に記載の方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US85087604A | 2004-05-21 | 2004-05-21 | |
US10/850,876 | 2004-05-21 | ||
US10/946,570 | 2004-09-21 | ||
US10/946,570 US7186656B2 (en) | 2004-05-21 | 2004-09-21 | Method of forming a recessed structure employing a reverse tone process |
PCT/US2005/017756 WO2005114719A2 (en) | 2004-05-21 | 2005-05-19 | Method of forming a recessed structure employing a reverse tone process |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2011264596A Division JP5563544B2 (ja) | 2004-05-21 | 2011-12-02 | 表面にリセスを形成する方法 |
Publications (3)
Publication Number | Publication Date |
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JP2008517448A true JP2008517448A (ja) | 2008-05-22 |
JP2008517448A5 JP2008517448A5 (ja) | 2008-07-03 |
JP5059608B2 JP5059608B2 (ja) | 2012-10-24 |
Family
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Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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JP2007527480A Active JP5059608B2 (ja) | 2004-05-21 | 2005-05-19 | リバーストーン処理を利用したリセス構造の形成方法 |
JP2011264596A Active JP5563544B2 (ja) | 2004-05-21 | 2011-12-02 | 表面にリセスを形成する方法 |
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JP2011264596A Active JP5563544B2 (ja) | 2004-05-21 | 2011-12-02 | 表面にリセスを形成する方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7186656B2 (ja) |
EP (1) | EP1761949A4 (ja) |
JP (2) | JP5059608B2 (ja) |
KR (1) | KR101139302B1 (ja) |
CN (1) | CN101356303B (ja) |
TW (1) | TWI289326B (ja) |
WO (1) | WO2005114719A2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2012508978A (ja) * | 2008-11-13 | 2012-04-12 | モレキュラー・インプリンツ・インコーポレーテッド | ナノサイズ形状の大面積パターニング |
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US7323417B2 (en) * | 2004-09-21 | 2008-01-29 | Molecular Imprints, Inc. | Method of forming a recessed structure employing a reverse tone process |
US7396475B2 (en) * | 2003-04-25 | 2008-07-08 | Molecular Imprints, Inc. | Method of forming stepped structures employing imprint lithography |
US7906180B2 (en) | 2004-02-27 | 2011-03-15 | Molecular Imprints, Inc. | Composition for an etching mask comprising a silicon-containing material |
US7384569B1 (en) * | 2004-08-02 | 2008-06-10 | Advanced Micro Devices, Inc. | Imprint lithography mask trimming for imprint mask using etch |
US7252777B2 (en) * | 2004-09-21 | 2007-08-07 | Molecular Imprints, Inc. | Method of forming an in-situ recessed structure |
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JP2012054612A (ja) | 2012-03-15 |
TW200603261A (en) | 2006-01-16 |
TWI289326B (en) | 2007-11-01 |
WO2005114719A3 (en) | 2008-10-09 |
EP1761949A4 (en) | 2011-04-20 |
JP5059608B2 (ja) | 2012-10-24 |
CN101356303A (zh) | 2009-01-28 |
EP1761949A2 (en) | 2007-03-14 |
WO2005114719A2 (en) | 2005-12-01 |
KR20070013305A (ko) | 2007-01-30 |
US7186656B2 (en) | 2007-03-06 |
JP5563544B2 (ja) | 2014-07-30 |
CN101356303B (zh) | 2012-04-04 |
KR101139302B1 (ko) | 2012-05-25 |
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