CN101170095B - 半导体封装件和叠层式半导体封装件 - Google Patents

半导体封装件和叠层式半导体封装件 Download PDF

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CN101170095B
CN101170095B CN200710163745XA CN200710163745A CN101170095B CN 101170095 B CN101170095 B CN 101170095B CN 200710163745X A CN200710163745X A CN 200710163745XA CN 200710163745 A CN200710163745 A CN 200710163745A CN 101170095 B CN101170095 B CN 101170095B
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semiconductor chip
recess
substrate
pattern distribution
semiconductor package
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CN101170095A (zh
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山野孝治
小林壮
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Shinko Electric Industries Co Ltd
Shinko Electric Co Ltd
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Abstract

本发明公开一种通过多个封装件彼此堆叠而构成的叠层式半导体封装件，在该叠层式半导体封装件中，所述多个封装件包括半导体封装件，所述半导体封装件包括：半导体芯片；基板，其中形成有凹部，所述半导体芯片安装在所述凹部中；以及配线结构，其以这种方式构造，即：所述配线结构可以至少在所述半导体芯片的正上方和正下方与所述半导体芯片外部连接。

Description

半导体封装件和叠层式半导体封装件
技术领域
本发明涉及通过将半导体芯片安装在基板上而构造成的半导体封装件以及采用上述半导体封装件的叠层式半导体封装件。
背景技术
虽然提出了各种类型的半导体芯片封装件的结构，但是由于以高性能制造其上安装有封装件的电子器件，所以存在一些情况，即：例如，采用通过常规封装件彼此堆叠而制成的叠层式封装件(也称为“层叠封装件(PoP)”)。
当叠层式封装件具有以这种方式构造成的结构，即：多块包括半导体芯片的封装件彼此堆叠时，由于各种类型的封装件可以彼此结合，所以这些叠层式封装件可以容易地适用于按照不同规格制造的高性能电子器件(例如，参见专利文献1：JP-A-2005-347229)。
然而，在目前的半导体芯片中，连接端子的总数随着这些半导体芯片性能的提高而增加，也就是说，已经普及了半导体芯片的所谓“多插脚化(multiple pin)”。当构造可以适用于以上述“多插脚”形式制造的半导体芯片的封装件时，会增加这些封装件中采用的连接端子的总数。因此，存在这样的问题，即：难以使这些封装件彼此堆叠。
例如，当以所谓的“多插脚”形式制造的封装件彼此堆叠时，必须保证用于彼此电连接这些封装件的面积。因此，存在另一个问题，即：叠层式封装件体积变大。此外，由于存在叠层式封装件的厚度增加的问题，所以存在的另一个问题是难以使这些叠层式封装件制作得更薄。如前文所述，至于这种能够适用于“多插脚”并且还能够制作得紧凑的叠层式封装件，尚未提出具体的结构实例。
此外，在上述具有高性能并且以多插脚形式制造的半导体芯片中，由于半导体芯片的发热量增加，所以存在因半导体芯片的热循环而发生各种封装件失效的可能性。
例如，用硅制造通用半导体芯片。因此，在硅与插入物之间存在较大的热膨胀系数差异。这种插入物由通用封装件中采用的树脂材料制成。
因此，当重复进行半导体芯片的发热与散热时，存在这样的风险，即：发生封装件的导线断开以及因半导体芯片与插入物之间的热膨胀系数差异而使封装件损坏。这样，存在的另一个问题是这些封装件的可靠性降低。
发明内容
因此，本发明的总体目的是提供新颖、实用、能够解决上述问题的半导体封装件和叠层式半导体封装件。
本发明的具体目的是提供具有更高可靠性并且制作得紧凑、细小的半导体封装件以及具有更高可靠性并且制作得紧凑、细小的叠层式半导体封装件。
根据本发明第一个方面，通过这样的半导体封装件解决上述问题，所述半导体封装件的特征在于包括：半导体芯片；基板，其设置有凹部，所述半导体芯片安装在所述凹部中；以及配线结构，其以这种方式构造，即：所述配线结构可以至少在所述半导体芯片的正上方和正下方与所述半导体芯片外部连接。
此外，根据本发明的第二个方面，通过这样的叠层式半导体封装件解决上述问题，所述叠层式半导体封装件通过彼此堆叠多个封装件而构成，其中，作为半导体封装件的所述多个封装件包括：半导体芯片；基板，其设置有凹部，所述半导体芯片安装在所述凹部中；以及配线结构，其以这种方式构造，即：所述配线结构可以至少在所述半导体芯片的正上方和正下方与所述半导体芯片外部连接。
根据本发明，可以提供制作得紧凑、细小并具有更高可靠性的半导体封装件以及制作得紧凑、细小并具有更高可靠性的叠层式半导体封装件。
附图说明
图1是用于示出根据实施例1的半导体封装件的简图。
图2是用于示出根据实施例2的叠层式半导体封装件的简图。
图3是用于示出根据实施例3的叠层式半导体封装件的简图。
具体实施方式
根据本发明，半导体封装件的特征在于包括：半导体芯片；基板，其中形成有凹部，该半导体芯片安装在该凹部中；以及配线结构，其以这种方式构造，即：该配线结构可以至少在该半导体芯片的正上方和正下方与该半导体芯片外部连接。
在上述半导体封装件中，配线结构可以至少在位于该半导体芯片的正上方和正下方的位置上与该半导体芯片外部连接(提供有外部连接端子)。例如，在上述半导体封装件中，连接端子可以在第一主表面和第二主表面上布置成所谓的“完全栅格阵列”形式。因此，如果采用上述半导体封装件，则会使叠层式半导体封装件制作得紧凑。此外，在上述半导体封装件中，由于半导体芯片安装在硅基板的凹部中，所以可以使半导体封装件(叠层式半导体封装件)制作得细小。
换言之，由于采用上述半导体封装件，所以这种叠层式半导体封装件可以构造成紧凑、细小的尺寸，并且可以适用于高性能器件(通常被称为具有多个插脚的半导体芯片)以及移动器件。
此外，在上述半导体封装件中，硅基板可以优选用作其中形成用于安装半导体芯片的凹部的基板。例如，对于前文所述的具有高性能的半导体芯片来说，存在其发热量增加等一些情况。因此，在这种采用由常规树脂材料制成的基板(插入物)的封装件中，存在发生问题的风险，即封装件的配线断开或者因构成半导体芯片的硅与构成基板的树脂材料之间的热膨胀系数差异而损坏。
另一方面，在上述根据本发明的半导体封装件中，由于基本上不存在半导体芯片与基板之间的热膨胀系数差异，所以具有这种优点，即在安装有高性能半导体芯片(通常被称为配备有多个插脚的半导体芯片)的情况下，可以使可靠性更高。
此外，作为选择，可以采用诸如玻璃和陶瓷作为构成上述基板的材料。例如，通过调整玻璃与陶瓷的组分，可以使其热膨胀系数接近于半导体芯片(硅)的热膨胀系数。
下面，参考附图，对上述半导体封装件和使用该半导体封装件的上述叠层式半导体封装件的结构实例进行具体说明。
(实施例1)
图1是用于示意性示出根据本发明实施例1的半导体封装件100的剖视图。现在参照图1，根据实施例1的半导体封装件100基本上通过以下方式制造：在由硅制成的基板(硅基板)101中形成凹部101A，并以这样的方式安装半导体芯片301，即：将半导体芯片301放置在凹部101A中。
此外，在半导体封装件100中，通过以下方式形成有配线结构200，即：在第一主表面(即，位于凹部101A的开口侧的主表面)一侧以及在第二主表面(即，位于与凹部101A的开口侧相反的一侧的主表面)一侧，配线结构200可以与半导体芯片301外部连接。例如，分别在第一主表面和第二主表面上布置有多个形成于配线结构200上的外部连接端子(凸点)208和210。
从所在表面上看，上述外部连接端子208和210布置成阵列形状，也就是术语所称的“完全栅格阵列形状”。换言之，上述配线结构200根据下列特征点来制造：配线结构200不仅可以在第一主表面和第二主表面的周围部分而且可以至少在位于半导体芯片301的正上方和正下方的部分与半导体芯片301外部连接。
例如，上述配线结构200具有这种结构，即：配线结构200具有穿透基板101的导通塞201，并且用于将该导通塞201与外部端子208和210连接的导通塞和图案配线分别形成在基板101的两个表面中/上。
例如，在基板101的正面侧(即，安装有半导体芯片301的一侧)形成有与导通塞201连接的图案配线202，并且以这样的方式在该正面侧形成有绝缘层102，即：使得绝缘层102覆盖图案配线202。此外，以这样的方式形成有导通塞203，即：使得这些导通塞203穿透绝缘层102，并且在绝缘层102上形成有与导通塞203连接的图案配线(电极片)204。
此外，在图案配线204上形成有外部连接端子(焊料凸点)208，而从所在表面上看，外部连接端子208以这样的方式布置成完全栅格阵列，即：使得这些外部连接端子208布置为栅格形状。此外，如果需要，则在外部端子208与图案配线204之间形成有连接层207。连接层207由例如金/镍制成(由金层和镍层以这样的方式制成的叠层结构，即：使金层位于外部连接端子一侧)。此外，以这样的方式在外部连接端子208周围形成有阻焊层103，即：使得阻焊层103覆盖绝缘层102的一部分和图案配线204的一部分。
此外，在基板101的背面侧(即，与安装有半导体芯片301一侧相反的一侧)形成有绝缘层104。另外，以这样的方式形成有与导通塞201连接的导通塞205，即：使得这些导通塞205穿透绝缘层104，同样，在绝缘层104上形成有与导通塞205连接的图案配线(电极片)206。
此外，如前文所述，在图案配线206上形成有外部连接端子(焊料凸点)210，而从所在表面上看，外部连接端子210以这样的方式布置成完全栅格阵列，即：使得这些外部连接端子210布置为栅格形状。此外，如果需要，则在外部端子210与图案配线206之间形成有连接层209。连接层209由例如金/镍制成(由金层和镍层以这样的方式制成的叠层结构，即：使金层位于外部连接端子一侧)。此外，以这样的方式在外部连接端子210周围形成阻焊层105，即：使得阻焊层105覆盖绝缘层104的一部分和图案配线206的一部分。
在上述结构中，绝缘层102和104由例如环氧系树脂材料形成，该材料用作称为“增层”材料的主要材料。此外，配线结构200(由导通塞201、203和205以及图案配线202、204和206构成)由例如铜制成。然而，上述材料只是一个实例，因此本发明不仅仅限于这些材料。
在半导体芯片301的器件表面指向下方(凹部101A的底面侧)的状态下，即在所谓的“面朝下”状态下，半导体芯片301安装在凹部101A中。与形成在半导体芯片301的器件表面上的电极片(未示出)连接的凸点302与图案配线202连接，并且在半导体芯片301与基板101之间注入底部填充树脂(树脂材料)303。
从所在表面上看，在硅基板101的基本上整个表面中形成构成上述配线结构200的导通塞201，例如在凹部101A的底部、硅厚度较薄的部位以及在凹部101A周围、硅厚度较厚的其它部位中形成该导通塞。
此外，通过包括例如形成在凹部101A的侧壁表面上的部分，从而形成与导通塞201和半导体芯片301(凸点302)连接的图案配线202。例如，图案配线202在凹部101A的底面上与导通塞201和半导体芯片301(凸点302)二者连接。此外，图案配线202沿着凹部101A的内壁表面从凹部101A的底面形成到凹部101A的侧壁表面，而且以这样的方式朝向凹部101A的外侧形成，即：使得图案配线202在基板101的表面上延伸。
另一方面，在绝缘层102上形成的图案配线204包括以这种方式形成的部分，即：该部分从位于凹部101A外侧的部分延伸到与该凹部重叠(位于半导体芯片301的正上方)的另一部分。
由于以上述方式形成了配线结构200，所以可以以这样的方式在包括位于半导体芯片301正上方的表面的第一主表面的基本整个表面上制成与配线结构200连接的外部连接端子208，即：使得这些外部连接端子208布置成所谓的“完全栅格阵列”。
此外，在上述半导体封装件100中，可以以这样的方式在包括位于半导体芯片301正下方的表面的第二主表面的基本整个表面上制成与配线结构200连接的外部连接端子210，即：使得这些外部连接端子210布置成所谓的“完全栅格阵列”。此外，作为选择，如果需要，则可以在基板101的背面上设置有与图案配线202对应并与导通塞201连接的图案配线。
由于上述半导体封装件100以这样的方式构造，即：半导体芯片301可以与半导体芯片301正上方和正下方的配线结构200(例如，布置成完全栅格阵列)外部连接，所以半导体封装件100可以容易地适用于半导体芯片301的多个插脚(即，增加凸点302的总数)。
因此，即使在将半导体封装件适用于以多插脚方式制成的半导体芯片的情况下，也可以限制半导体封装件的面积的增加量并且可以使半导体封装件具有紧凑的结构。此外，由于采用了上述半导体封装件，所以叠层式半导体封装件可以制作得紧凑。也就是说，在上述半导体封装件彼此堆叠的情况下，由于两个表面(即，第一主表面和第二主表面)都是完全栅格阵列，所以这些半导体封装件可以在节省空间的条件下更高效地彼此连接。
此外，在上述半导体封装件100中，由于半导体芯片301安装在硅基板101的凹部101A中，所以半导体封装件100(使用半导体封装件100的叠层式半导体封装件)可以制作得细小。
换言之，由于采用了上述半导体封装件100，所以这种半导体封装件100可适用于这种高性能器件(通常被称为以多插脚方式制成的半导体芯片301)，而且可以构成能够同时满足(移动器件等中需要的)细小和紧凑要求的叠层式半导体封装件。
此外，在上述半导体封装件100中，基板101由硅制成，这也可以构成一个特征。例如，存在这样一些情况，即：在具有高性能和多插脚的半导体芯片(即，半导体芯片301)中，其发热量增加等。为了解决这种大量发热的问题，在上述半导体封装件100中，使用硅形成的半导体芯片301和硅基板101以这种方式构成，即：在半导体芯片301与基板101之间基本上不存在热膨胀系数差异。因此，在安装有高性能半导体芯片(通常被称为以多插脚方式制成的半导体芯片)的情况下的可靠性更高。
此外，在上述半导体封装件100中，配线结构200以这样的方式布置，即：能够允许半导体芯片301的工作测试(operation test)，以便也可以执行半导体芯片301的工作测试。例如，在多个半导体封装件100彼此堆叠从而构成叠层式半导体封装件的情况下，在这些半导体封装件100彼此堆叠之前，对这多个半导体芯片301单独执行封装件的工作测试。因此，可以提高得到的叠层式半导体封装件的制造产量。
可以根据公知的制造方法(例如，硅的RIE(活性离子蚀刻)方法、通过电镀法形成配线结构200等)制造上述半导体封装件100。现在参照图1，示意性地简单说明半导体封装件100的制造。
在制造上述半导体封装件100的情况下，首先通过RIE(活性离子蚀刻)方法在硅基板101(例如，硅晶片等)中形成与凹部101A对应的结构和穿透基板101的通孔。此外，在形成热氧化物膜(未在图1中示出)从而使基板101的表面绝缘之后，通过电镀法形成由铜制成并嵌入通孔中的导通塞201。
接下来，通过半加成法形成铜制的图案配线202。在这种情况下，作为选择，如果需要，则也可以在基板101的背面上形成图案配线。随后，通过应用超声波或者通过执行加热方法将半导体芯片30 1的凸点(金)302与图案配线202连接，然后，将底部填充树脂(流体树脂)303注入到半导体芯片301与基板101之间(倒装芯片安装)。
接下来，通过在真空环境下层压树脂膜，分别在基板101的两个表面上形成绝缘层102和104，然后对这些形成的绝缘层102和104进行加热以便使其硬化。应当注意到，作为选择，可以通过涂布并加热树脂以形成绝缘层102和104。此外，在绝缘层102和104中形成通孔之后(如果需要，还进行去污处理)，通过半加成法形成导通塞203和205以及图案配线204和206。
接下来，如果需要，则在形成阻焊层103和105之后，通过执行例如电镀法，分别在从阻焊层103和105露出的图案配线204和206上形成连接层207和209。随后，分别在连接层207和209上(在图案配线204和206上)形成由焊料凸点制成的外部连接端子208和210。此后，切割基板(硅晶片)101，从而可以制造出单独的半导体封装件100。
(实施例2)
图2是用于示出叠层式半导体封装件400的简图，该叠层式半导体封装件采用根据实施例1形成的半导体封装件100制成。应当注意到，采用前述实施例1中给出的相同附图标记作为表示相同结构元件的附图标记，并且省略其说明。
现在参照图2，根据本发明的实施例2，通过彼此堆叠3块根据实施例1形成的上述半导体封装件100来制成叠层式半导体封装件400。虽然在彼此堆叠的半导体封装件100之间形成了绝缘层UF并且将流体树脂注入到该绝缘层中并使其硬化，但是也可以省略这些绝缘层UF。作为选择，可以通过在彼此堆叠封装件时，在封装件之间安装树脂膜的方式形成绝缘层UF。
在上述结构中，半导体封装件100的位于最下层的外部连接端子210与母板S连接。此外，例如，可以在半导体封装件100的位于最上层的图案配线204(连接层207)上安装其它半导体芯片或诸如电容器、电阻器和电感器等电子元件(表面封装元件)。此外，可以从叠层式半导体封装件400中省去半导体封装件100的设置在最上层的外部连接端子208。
如前文所述，由于采用了根据实施例1制成的半导体封装件100，所以可以构成具有更高可靠性的紧凑、细小的叠层式半导体封装件。
此外，彼此堆叠的封装件的总数不仅仅限于3块。例如，彼此堆叠的半导体封装件100的总数可以选为2块。作为选择，彼此堆叠的半导体封装件100的总数可以选为4块或更多块。
(实施例3)
图3是用于示出叠层式半导体封装件600的简图，该叠层式半导体封装件采用根据实施例1形成的半导体封装件100制成。应当注意到，采用前述实施例1中给出的相同附图标记作为表示相同结构元件的附图标记，并且省略其说明。
参照图3，通过在根据实施例1的上述半导体封装件100上堆叠半导体封装件500来构成根据实施例3的叠层式半导体封装件600，其中半导体封装件500不同于半导体封装件100。
上述半导体封装件500具有所谓的“F-BGA”结构，即，半导体芯片502和503堆叠在插入物501上的结构。此外，在半导体芯片502和503分别通过导线504和505与插入物501电连接的同时，这些半导体芯片502和503通过模制树脂506密封在插入物501上。
作为选择，上述结构可以变成另一种结构，在这种结构中，半导体芯片502与插入物501倒装芯片连接，并且安装在半导体芯片502的背面(上表面)上的半导体芯片503通过导线与插入物501连接。
如前文所述，可以选择具有各种结构和各种布置的封装件作为堆叠在根据实施例1的半导体封装件100上的封装件。
虽然结合优选实施例对本发明进行了说明，但是本发明不仅仅限于上述特定实施例，而是可以在权利要求书描述的要旨所限定的范围内以各种方式进行修改和变化。
例如，可以可选择地采用多个安装在凹部101A中的半导体芯片(例如，层叠式半导体芯片)。此外，可以可选择地在基板101中形成多个凹部101A，也可以可选择地安装多个半导体芯片。
根据本发明，可以提供制作得紧凑、细小并具有更高可靠性的半导体封装件以及制作得紧凑、细小并具有更高可靠性的叠层式半导体封装件。

Claims (8)

1.一种半导体封装件，包括：
半导体芯片；
基板，其设置有凹部，所述半导体芯片安装在所述凹部中；以及
配线结构，其以这种方式构造，即：所述配线结构可以至少在所述半导体芯片的正上方和正下方与所述半导体芯片外部连接，所述配线结构包括图案配线和穿透所述基板的导通塞，所述图案配线以这样的方式沿着所述凹部的内壁表面从所述凹部的底面形成到所述凹部的侧壁表面，即：所述图案配线在所述基板的表面上延伸，并且所述图案配线与穿透所述基板的所述导通塞连接，所述半导体芯片在面朝下的状态下与所述凹部的底面上的所述图案配线连接。
2.根据权利要求1所述的半导体封装件，其中，
所述配线结构包括导通塞，所述导通塞穿透所述基板的所述凹部的底部。
3.根据权利要求1所述的半导体封装件，其中，
所述基板包括设置有所述凹部的第一表面和与所述第一表面相反的第二表面，
第一绝缘层形成于所述基板的所述第一表面上以覆盖所述图案配线、所述凹部和所述半导体芯片，
第二绝缘层形成于所述基板的所述第二表面上，
第二图案配线形成于所述第一绝缘层和所述第二绝缘层上并且与形成于所述基板上的所述图案配线或所述导通塞连接。
4.根据权利要求3所述的半导体封装件，其中，
所述第二图案配线设置有外部连接端子。
5.一种叠层式半导体封装件，其通过多个封装件彼此堆叠而构成，其中，
作为半导体封装件的所述多个封装件包括：
半导体芯片；
基板，其设置有凹部，所述半导体芯片安装在所述凹部中；以及
配线结构，其以这种方式构造，即：所述配线结构可以至少在所述半导体芯片的正上方和正下方与所述半导体芯片外部连接，所述配线结构包括图案配线和穿透所述基板的导通塞，所述图案配线以这样的方式沿着所述凹部的内壁表面从所述凹部的底面形成到所述凹部的侧壁表面，即：所述图案配线在所述基板的表面上延伸，并且所述图案配线与穿透所述基板的所述导通塞连接，所述半导体芯片在面朝下的状态下与所述凹部的底面上的所述图案配线连接。
6.根据权利要求5所述的叠层式半导体封装件，其中，
所述配线结构包括导通塞，所述导通塞穿透所述基板的所述凹部的底部。
7.根据权利要求5所述的叠层式半导体封装件，其中，
所述基板包括设置有所述凹部的第一表面和与所述第一表面相反的第二表面，
第一绝缘层形成于所述基板的所述第一表面上以覆盖所述图案配线、所述凹部和所述半导体芯片，
第二绝缘层形成于所述基板的所述第二表面上，
第二图案配线形成于所述第一绝缘层和所述第二绝缘层上并且与形成于所述基板上的所述图案配线或所述导通塞连接。
8.根据权利要求7所述的叠层式半导体封装件，其中，
所述第二图案配线设置有外部连接端子。
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Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2829623B1 (en) * 2007-12-04 2018-02-07 Arconic Inc. Improved aluminum-copper-lithium alloys
US8618669B2 (en) * 2008-01-09 2013-12-31 Ibiden Co., Ltd. Combination substrate
US8378475B1 (en) * 2008-05-30 2013-02-19 Wavefront Research, Inc. Optoelectronic chip carriers
CN101872757B (zh) * 2009-04-24 2012-05-23 南茂科技股份有限公司 凹穴芯片封装结构及使用其的层叠封装结构
CN101872749B (zh) * 2009-04-24 2012-05-23 南茂科技股份有限公司 凹穴芯片封装结构及使用其的层叠封装结构
US8310835B2 (en) * 2009-07-14 2012-11-13 Apple Inc. Systems and methods for providing vias through a modular component
US8895358B2 (en) * 2009-09-11 2014-11-25 Stats Chippac, Ltd. Semiconductor device and method of forming cavity in PCB containing encapsulant or dummy die having CTE similar to CTE of large array WLCSP
KR101046713B1 (ko) * 2009-12-17 2011-07-06 삼성전기주식회사 패키지 기판 및 패키지 기판의 제조방법
KR101676620B1 (ko) * 2010-02-05 2016-11-16 에스케이하이닉스 주식회사 적층 반도체 패키지
JP5218460B2 (ja) * 2010-03-26 2013-06-26 セイコーエプソン株式会社 焦電型光検出器、焦電型光検出装置及び電子機器
CN102215043A (zh) * 2010-04-09 2011-10-12 国民技术股份有限公司 一种无线通信模块
JP5517800B2 (ja) * 2010-07-09 2014-06-11 キヤノン株式会社 固体撮像装置用の部材および固体撮像装置の製造方法
US8847376B2 (en) * 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
CN102403275B (zh) * 2010-09-17 2014-01-15 深南电路有限公司 一种堆叠封装结构及其制作方法
CN102064159B (zh) * 2010-11-05 2013-09-18 中国兵器工业集团第二一四研究所苏州研发中心 一种多模块封装组件
JP5357241B2 (ja) * 2011-08-10 2013-12-04 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
WO2013070207A1 (en) 2011-11-09 2013-05-16 Intel Corporation Thermal expansion compensators for controlling microelectronic package warpage
US8749043B2 (en) * 2012-03-01 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package structure
CN103811444B (zh) * 2012-11-07 2016-11-23 环旭电子股份有限公司 电子装置、系统级封装模块及系统级封装模块的制造方法
US9627325B2 (en) * 2013-03-06 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package alignment structure and method of forming same
JP2014209091A (ja) * 2013-03-25 2014-11-06 ローム株式会社 半導体装置
CN103390717B (zh) * 2013-07-30 2016-02-03 广东洲明节能科技有限公司 叠层led发光模组及制作方法
CN103579206B (zh) * 2013-11-07 2016-09-21 华进半导体封装先导技术研发中心有限公司 堆叠封装器件及其制造方法
JP5958454B2 (ja) * 2013-12-05 2016-08-02 株式会社村田製作所 部品内蔵モジュール
TW201526198A (zh) * 2013-12-18 2015-07-01 Innovative Turnkey Solution Corp 具有堆疊元件的封裝模組
DE102014206601A1 (de) * 2014-04-04 2015-10-08 Siemens Aktiengesellschaft Verfahren zum Montieren eines elektrischen Bauelements, bei der eine Haube zum Einsatz kommt, und zur Anwendung in diesem Verfahren geeignete Haube
DE102014206608A1 (de) 2014-04-04 2015-10-08 Siemens Aktiengesellschaft Verfahren zum Montieren eines elektrischen Bauelements, bei der eine Haube zum Einsatz kommt, und zur Anwendung in diesem Verfahren geeignete Haube
KR101565690B1 (ko) * 2014-04-10 2015-11-03 삼성전기주식회사 회로기판, 회로기판 제조방법, 전자부품 패키지 및 전자부품 패키지 제조방법
KR102262907B1 (ko) * 2014-05-30 2021-06-09 삼성전기주식회사 패키지 기판, 패키지, 적층 패키지 및 패키지 기판 제조 방법
JP6554338B2 (ja) * 2014-07-28 2019-07-31 ローム株式会社 半導体装置
TWI571185B (zh) * 2014-10-15 2017-02-11 矽品精密工業股份有限公司 電子封裝件及其製法
JP6606331B2 (ja) * 2015-02-16 2019-11-13 ローム株式会社 電子装置
JP6557481B2 (ja) * 2015-02-26 2019-08-07 ローム株式会社 電子装置
JP6676308B2 (ja) * 2015-08-07 2020-04-08 ローム株式会社 半導体装置
JP2017037900A (ja) * 2015-08-07 2017-02-16 ローム株式会社 半導体装置およびその製造方法
CN105118815B (zh) * 2015-08-13 2017-09-29 上海航天电子通讯设备研究所 一种基于铝基板的三维封装用垂直互连结构及其制备方法
CN105489589B (zh) * 2016-01-26 2018-06-01 兰微悦美（北京）科技有限公司 可堆叠的集成电路及其封装方法
JP2017175000A (ja) * 2016-03-24 2017-09-28 ローム株式会社 電子部品およびその製造方法、ならびに、インターポーザ
JP6770331B2 (ja) * 2016-05-02 2020-10-14 ローム株式会社 電子部品およびその製造方法
US10497846B2 (en) * 2017-07-11 2019-12-03 Lg Innotek Co., Ltd. Light emitting device package
KR102448248B1 (ko) * 2018-05-24 2022-09-27 삼성전자주식회사 Pop형 반도체 패키지 및 그 제조 방법
US11309285B2 (en) * 2019-06-13 2022-04-19 Micron Technology, Inc. Three-dimensional stacking semiconductor assemblies and methods of manufacturing the same
KR20210076292A (ko) * 2019-12-13 2021-06-24 삼성전자주식회사 반도체 패키지

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6032355A (en) * 1998-04-22 2000-03-07 World Wiser Electronics, Inc. Method of forming thermal conductive structure on printed circuit board
US6175497B1 (en) * 1998-09-30 2001-01-16 World Wiser Electronics Inc. Thermal vias-provided cavity-down IC package structure
CN1333560A (zh) * 2000-07-07 2002-01-30 索尼公司 半导体封装及其制造方法
US7070207B2 (en) * 2003-04-22 2006-07-04 Ibiden Co., Ltd. Substrate for mounting IC chip, multilayerd printed circuit board, and device for optical communication

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0774175B1 (en) * 1995-06-06 2004-09-08 The Chamberlain Group, Inc. Movable barrier operator having force and position learning capability
JPH11168150A (ja) * 1997-12-04 1999-06-22 Mitsubishi Electric Corp 半導体集積回路装置
JPH11289023A (ja) 1998-04-02 1999-10-19 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
KR100266693B1 (ko) 1998-05-30 2000-09-15 김영환 적층가능한 비지에이 반도체 칩 패키지 및 그 제조방법
JP2001230515A (ja) * 2000-02-15 2001-08-24 Matsushita Electric Ind Co Ltd 電子部品の実装体、電子部品の実装体の製造方法、および実装体の二次実装構造。
EP1990833A3 (en) 2000-02-25 2010-09-29 Ibiden Co., Ltd. Multilayer printed circuit board and multilayer printed circuit board manufacturing method
JP2001274324A (ja) * 2000-03-24 2001-10-05 Hitachi Chem Co Ltd 積層型半導体装置用半導体搭載用基板、半導体装置及び積層型半導体装置
CN1543298A (zh) * 2000-06-27 2004-11-03 ���µ�����ҵ��ʽ���� 陶瓷叠层器件
US20020020898A1 (en) 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
EP1400820A1 (en) * 2002-09-20 2004-03-24 Corning O.T.I. SRL Integrated optical chip
CN100377337C (zh) * 2002-11-21 2008-03-26 日本电气株式会社 半导体装置、布线基板和布线基板制造方法
JP4137659B2 (ja) 2003-02-13 2008-08-20 新光電気工業株式会社 電子部品実装構造及びその製造方法
KR20040078807A (ko) 2003-03-05 2004-09-13 삼성전자주식회사 볼 그리드 어레이 적층 패키지
JP2004363351A (ja) * 2003-06-05 2004-12-24 Mitsubishi Electric Corp 積層型の半導体装置
JP4298559B2 (ja) * 2004-03-29 2009-07-22 新光電気工業株式会社 電子部品実装構造及びその製造方法
JP2005347299A (ja) 2004-05-31 2005-12-15 Shinko Electric Ind Co Ltd チップ内蔵基板の製造方法
JP2005347229A (ja) 2004-06-04 2005-12-15 Teruo Kamagata 専用リモコン不用の「リモコン照明器具」
KR100673354B1 (ko) * 2004-06-18 2007-01-24 주식회사 네패스 반도체 촬상소자 패키지 및 그 제조방법
DE602004016483D1 (de) * 2004-07-16 2008-10-23 St Microelectronics Sa Elektronische Schaltungsanordnung, Vorrichtung mit solcher Anordnung und Herstellungsverfahren
KR100669830B1 (ko) * 2004-11-16 2007-04-16 삼성전자주식회사 이방성 도전막을 이용한 적층 패키지
KR100618892B1 (ko) 2005-04-13 2006-09-01 삼성전자주식회사 와이어 본딩을 통해 팬 아웃 구조를 달성하는 반도체패키지
JP2006351565A (ja) 2005-06-13 2006-12-28 Shinko Electric Ind Co Ltd 積層型半導体パッケージ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6032355A (en) * 1998-04-22 2000-03-07 World Wiser Electronics, Inc. Method of forming thermal conductive structure on printed circuit board
US6175497B1 (en) * 1998-09-30 2001-01-16 World Wiser Electronics Inc. Thermal vias-provided cavity-down IC package structure
CN1333560A (zh) * 2000-07-07 2002-01-30 索尼公司 半导体封装及其制造方法
US7070207B2 (en) * 2003-04-22 2006-07-04 Ibiden Co., Ltd. Substrate for mounting IC chip, multilayerd printed circuit board, and device for optical communication

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