TWI233192B - The wafer level structure of system packaging with stacked packaging units - Google Patents

The wafer level structure of system packaging with stacked packaging units Download PDF

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Publication number
TWI233192B
TWI233192B TW093112483A TW93112483A TWI233192B TW I233192 B TWI233192 B TW I233192B TW 093112483 A TW093112483 A TW 093112483A TW 93112483 A TW93112483 A TW 93112483A TW I233192 B TWI233192 B TW I233192B
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Taiwan
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electronic
packaging
package
aforementioned
microelectronic
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TW093112483A
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Chinese (zh)
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TW200537662A (en
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Chang-Chun Lee
Kuo-Ning Chiang
Cheng-Nan Han
Ming-Chih Yew
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Kuo-Ning Chiang
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Publication of TWI233192B publication Critical patent/TWI233192B/en
Publication of TW200537662A publication Critical patent/TW200537662A/en

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    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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Abstract

A stacked electronic packaging structure with packaging units, which could both reduce the mounting area and increase the high density assemblies of devices to satisfy the requirement of diminishing the volume of packaging structure and reducing the transmissive time and the path of electronic signals among devices to increase the operated efficiency, would be proposed in this invention. In additions, this proposed packaging structure composed of one or plural packaging units could be designed and stacked by depending on the applied environment and the functional demand of electronic products. Furthermore, the various packaging units could be batch-manufactured by using current semiconductor technologies, and then the plural bonding structures are used to connect the packaging units to form the stacked structure. Therefore, the microelectronic devices within each packaging units could be electrically conducted both the adjacent packaging units and the substrate.

Description

1233192 五、發明說明（1) 【發明所屬之技術領域】 裝單元電子封裝結構，特別是-種多重封 且您電子封裝結構。 【先前技術】 隨著電早甚口 丄么卜 亦繼續朝著护> 此與應用急遽增加之需求，封裝技術 度到三微小型、單晶片到多“、二維尺 傳統封裝“in 故目前出現了較以往所見到之 同之先進封；=亡、製作上，以及材料應用上截然不 Package) 一、、，°維構私继如晶圓級封裝WLP (ffafer Lml 、 一維封哀、多晶片封裝MCP (Multi-Chip 高密度' 封和裝系开統'級封其裝中s 1P』Sy s 11233192 V. Description of the invention (1) [Technical field to which the invention belongs] An electronic package structure for mounting a unit, in particular, a multi-package and your electronic package structure. [Previous technology] As electricity has been very popular, and the demand for this and applications has increased sharply, the packaging technology has reached three micro-small, single-chip to multi- ", two-dimensional traditional packaging" in At present, there are advanced seals that are the same as those seen in the past; = no package in terms of production, production, and material applications) 1. ,, ° The structure of the structure is as follows as wafer-level packaging WLP (ffafer Lml, one-dimensional seal) 、 Multi-chip package MCP (Multi-Chip high-density 'seal and package system is open system' grade package s 1P "Sy s 1

内，能將所2 /式。其中，最理想的狀況為在一個矽晶片 、斤有的電路容納進去，即系統化晶片SoCWithin, can be so 2 / type. Among them, the most ideal situation is to accommodate it in a silicon chip and some circuits, that is, a system-on-chip SoC

Chip)為最佳，然而，將逐漸複雜化之電路 二：於一晶片Μ，除了技術上有困難外，晶片大小會 曰大，晶片的製程會複雜化，使得良率下降，成本上升； 故與SoC技術比較，強調體積小、高步員、高冑、生產週期 短與低成本之系統化封裝技術SIp (System in package) 為達成前述目標，及整合具不同電路功能晶片的較佳方 法。根據應用需求之不同可分為平面式的多晶片模組mcm (Multi-Chip Module )，多晶片封裝Mcp (MuUi—ChipChip) is the best. However, circuit 2 will be gradually complicated. In addition to technical difficulties, the size of the wafer will be large, and the process of the wafer will be complicated, which will reduce the yield and increase the cost. Compared with SoC technology, SIp (System in package), a system packaging technology that emphasizes small size, high steps, high speed, short production cycle, and low cost, is a better method to achieve the aforementioned goals and integrate chips with different circuit functions. According to different application requirements, it can be divided into planar multi-chip module mcm (Multi-Chip Module), multi-chip package Mcp (MuUi-Chip

Package )，以及為了更有效率地縮減封裝面積，而發展 出具多重晶片之立體堆疊式封裝結構，並進一步地使用薄Package), and in order to reduce the packaging area more efficiently, a three-dimensional stacked package structure with multiple wafers has been developed, and

第9頁 1233192 五、發明說明（2) =以㈣、缩料㈣裝於厚度方向之尺寸與封裝體本身 重里’而滿足先進封裝結構之輕薄短小需求。 按，習知之堆疊型積體電路晶片封裝係如美國第 6,387,728號專利所揭露者，請參閱第1圖，該封裝1〇()係Page 9 1233192 V. Description of the invention (2) = Dimensions in the thickness direction and the package itself are weighted with ㈣ and shrink material to meet the requirements of light, thin and short for advanced packaging structures. According to the conventional stacked integrated circuit chip package, as disclosed in US Patent No. 6,387,728, please refer to FIG. 1. The package 10 () is

於一基板102之頂面設有一第一積體電路晶片1〇3，並於該 第一積體電路晶片1〇3上進行打線作業，形成複數焊線1〇4 電性連接該第一積體電路晶片1〇3與該基板1〇2，接著，於 該第一積體電路晶片103頂面塗覆一層黏著層1〇5，可將二 第一積體電路晶片106黏附於其頂面，同樣利用打線作業 开> 成複數焊線1 0 7連接該第二積體電路晶片1 〇 6鱼該基板 m之後，再利用-封裝膠1Q8佈設於該基板且基將板各 組件全部包覆其中，即完成一堆疊型積體電路晶片之封裝 程序。堆疊型積體電路封裝將二個或二個以上之晶片堆疊 在一起共用一基板，在增加晶片個數之同時可有效地節省 空間，然而，晶片間運作與電訊之傳遞皆須透過焊線連接 基板之後才可進行，故容易產生訊號延遲現象，由於此種 封裝結構電訊傳遞路徑過長，將無法適用於高頻操作環 境；再者，焊線1 04裸露在外，當黏著該第二積體電路晶 片106於該黏著層上時，可能意外造成該等焊線1〇4之碰 損，形成不良品。 請參閱第2圖’其所繪為一多晶片堆疊式半導體封裝 件之剖面圖。此多晶片堆疊式半導體封裝件係如中華民國 專利公告號568, 35 1所揭露，其係包括一基板24〇 ; 一第一 晶片241接置至該基板240上；一第二晶片242接置至該第A first integrated circuit wafer 103 is provided on the top surface of a substrate 102, and a wire bonding operation is performed on the first integrated circuit wafer 103 to form a plurality of bonding wires 104 which are electrically connected to the first integrated circuit. The body circuit wafer 103 and the substrate 102 are then coated with an adhesive layer 105 on the top surface of the first integrated circuit wafer 103, so that the two first integrated circuit wafers 106 can be adhered to the top surface. Also, use a wire bonding operation to open the plurality of bonding wires 1 0 7 to connect the second integrated circuit wafer 1 106 to the substrate m, and then use-encapsulant 1Q8 to lay on the substrate and package all components of the board. After covering it, the packaging process of a stacked integrated circuit chip is completed. The stacked integrated circuit package stacks two or more wafers together and shares a substrate, which can effectively save space while increasing the number of wafers. However, the operation between chips and the transmission of telecommunications must be connected by bonding wires. Only after the substrate can be carried out, it is prone to signal delay. Due to the long transmission path of this package structure, it will not be suitable for high-frequency operation environment. Furthermore, the bonding wire 1 04 is exposed outside, when the second body is adhered When the circuit wafer 106 is on the adhesive layer, the bond wires 104 may be accidentally damaged, and defective products may be formed. Please refer to FIG. 2 'which is a cross-sectional view of a multi-chip stacked semiconductor package. The multi-chip stacked semiconductor package is disclosed in the Republic of China Patent Publication No. 568, 351, which includes a substrate 240; a first chip 241 is connected to the substrate 240; a second chip 242 is connected To the first

1233192 五、發明說明（3) 一晶片241上；多數焊線244、245用以分別電性連接該第 一、第二晶片241、242以及該焊線244、245 ;以及多數録 球247用以電性連接該半導體封裝件至外界裝置。其中， 基板2 40具有一上表面2〇〇及一相對之下表面2〇1，而該上 表面200界定有一晶片接置區2〇2及一環繞晶片接置區202 之上知線區2 〇 3。於約該晶片接置區2 〇 2之中心位置處形成 有一開口 204，並使該開口 204貫穿基板240之上、下表面 20 0、201。同時，該基板240之下表面201界定有一環繞開 口 204之下焊線區2〇5及一環繞下焊線區20 5之植球區2〇6， 並以封裝膠體246包覆堆疊晶片部分，及基板240之開口 2 04部分，以保護該焊線244、245。此堆疊晶片結構，已 經利用基板開口之方式，並分別配合第一、第二晶片 241、242作用表面220、210上之銲墊221、211面向方向相 反i以進行打線作業，故可減少此封裝件之厚度與焊線位 置漂移之現象；然而，一旦堆疊的晶片數目增加，則打線 作業之困難度增加，且晶片堆疊之位置與數目將受 |j 士 β、 曰曰 乃表面之電路圖案之配置與打線作業區域位置間的配合。 因此，鑑於具系統整合之多微電子元件堆疊電子封裝 將成為微電子、高頻通訊或致動感測器等電子結構模 並且為減低堆叠封裝之技術成本，與達成封裝後體 f微小化，故如何發展出一種具高密度多微電子元件 m攝’且設計、組裝可依據應用需求功能作適當地彈性 S整’實為當前急需解決的問題。1233192 V. Description of the invention (3) On a chip 241; most of the bonding wires 244, 245 are used to electrically connect the first and second chips 241, 242 and the bonding wires 244, 245, respectively; and most of the recording balls 247 are used The semiconductor package is electrically connected to an external device. The substrate 2 40 has an upper surface 200 and a relatively lower surface 201, and the upper surface 200 defines a wafer receiving area 202 and a surrounding area 2 above the wafer receiving area 202. 〇3. An opening 204 is formed at a position about the center of the wafer receiving area 202, and the opening 204 penetrates the upper and lower surfaces 200, 201 of the substrate 240. At the same time, the lower surface 201 of the substrate 240 defines a bonding wire area 205 surrounding the lower opening 204 and a ball planting area 206 surrounding the lower bonding wire area 20 5. And an opening 204 portion of the substrate 240 to protect the bonding wires 244, 245. This stacked wafer structure has already used the method of opening the substrate and cooperated with the pads 221 and 211 on the active surfaces 220 and 210 of the first and second wafers 241 and 242, respectively, to face the opposite direction i for wire bonding operations, so the package can be reduced. The thickness of the component and the position of the bonding wire drift; however, once the number of stacked wafers increases, the difficulty of the wire bonding operation increases, and the position and number of wafer stacking will be affected by the circuit pattern on the surface. The coordination between the configuration and the location of the line operation area. Therefore, in view of the fact that multiple microelectronic component stacked electronic packages with system integration will become electronic structural molds such as microelectronics, high-frequency communication or actuated sensors, and to reduce the technical cost of stacked packages and achieve miniaturization of the packaged body f, How to develop a high-density multi-microelectronic component m-photographer, and design and assembly can be properly elasticized according to application requirements and functions is a problem that needs to be solved urgently.

五、發明說明（4) 【發明目的及概述】 鏗於前述先前技術之勒l 件堆疊電子封穿將# 、失及具系統整合之多微電子元 電子結構模組之趨冑，本*明⑯:頻通戒或致動感測器等 單元體，盆上下Ϊ:曰具多重微電子元件之晶圓級封莱 之需求，彈性地進扞I % ^ 7茶了依應用％境與功能 構，以減少電訊in 個堆疊組裝微小化封裝結 工作頻率盥效能。本L笋：與時間而提升此堆疊封裝模組之 裝結構；；；單ί: ;Γ目的在於提供-種電子封 低早-封裝單元體之製作成本。本發明2:ί，故可降 電子封裝結構，其堆疊使用…以提 故堆疊電子封裝結構模屐早70體厚度薄， 用更為經濟與節省。、、又 田又地降低，且空間利 為達成别揭目的，本發明 含有單或複數個封裝單元^電子封裝結構，包 複數個微電子元件，充填 „二5 f個空穴區域，單或 固著結構，單戋禮數彳督 早或稷數絕緣膜層，複數個 傅早a複數個貫通孔；其中， 吸双似 用半導體技術批次製作完成其Ί早元體，為 :結構連接與其相同或相異之封 =面之複數個固 構，以構成封裝結構之主冑，而，:形成立體堆疊 定，該單或複數個空=用；=功能上之需要而決 …域，形成於前述該封裝單元體内 【較佳實施例之詳細描述】 1233192 五、發明說明（5) 之主晶片表面，該空穴區域於主晶片之上或下表面形成單 或极數個凹八二間’該卓或複數個微電子元件，配置於該 早或複數之二八£域中或該主晶片之表面，並具電訊傳遞 結構使其電子訊號可與該主晶片，其他單或複數個微電子 元件，以及相連接之封裝單元體間相互連通，該充填物， 填充於前述之單或複數個空穴區域内以保護該空穴區域内 之微電子元件；該單或複數絕緣膜層，塗佈於前述主晶片 之表面’用以電訊電性之絕緣，該複數個固著結構，其具 電訊傳遞功能使接著之該封裝單元體内之電子訊號可與其 他封裝單元體和基板相互連通，該單或複數個貫通孔，形 成於前述主晶片内，其内充填滿具導電性質之金屬，用以 連接該主晶片上表面與下表面之電路，以及連接前述之單 或複數個微電子元件。 本發明之前述與其他目的、特徵、以及優點，將藉由 下文中參照圖示之較佳實施例之詳細說明得以更明確。 一錄本發明揭露一種電子構裝結構。詳言之，本發明提供 多重封裝單元體之晶圓級系統封裝結構，利用堆 夕重相同或相異封裝單元體以滿足高密度電子元件 :且^，和微小化封裝結構之需求，並提供其實施例。其詳 二L如下，唯所述之較佳實施例只做一說明，並非用以V. Description of the invention (4) [Objective and summary of the invention] The trend of the multi-microelectronic element electronic structure module with integrated system, which is based on the above-mentioned prior art, stacking electronic seals, and this system ⑯: Units such as frequency communication or actuating sensors, top and bottom of the basin Ϊ: The demand for wafer-level sealing with multiple microelectronic components, to flexibly defend I% ^ 7 In order to reduce telecommunications in a stack assembly miniaturization package frequency operation efficiency. Book L: To improve the packaging structure of this stacked package module with time; The single purpose of: Γ is to provide-a kind of electronic seal-low production cost of the package unit. The present invention 2: Therefore, the electronic packaging structure can be reduced, and its stacking is used ... In order to improve the thickness of the stacked electronic packaging structure, the thickness of the body is 70, which is more economical and economical. In order to achieve another purpose, the present invention contains a single or a plurality of packaging units, an electronic packaging structure, a plurality of microelectronic elements, and two or five f cavity regions filled with a single or Fixed structure, single 戋 彳 彳 早 or 绝缘 绝缘 insulation film layer, a plurality of Fu za a a plurality of through holes; Among them, the suction double seems to use semiconductor technology batch to complete its Ίearly element body, as follows: structural connection and The same or different seals = multiple solid structures of the surface to form the main structure of the package structure, and: forming a three-dimensional stacking set, the single or multiple empty = use; = functional needs depend on ... [Detailed description of the preferred embodiment] in the aforementioned packaging unit [1233192] 5. The main wafer surface of the invention description (5), the cavity area forms a single or pole recess on the main wafer surface The micro-electronic component or the micro-electronic component is arranged in the early or plural spheres or on the surface of the main chip, and has a telecommunication transmission structure so that the electronic signal can communicate with the main chip, other single or plural Microelectronic components, and phase The connected packaging unit bodies communicate with each other, and the filler is filled in the aforementioned single or plural cavity areas to protect the microelectronic elements in the cavity areas; the single or plural insulation film layers are coated on the aforementioned main The surface of the chip is used for telecommunication electrical insulation. The plurality of fixed structures have a telecommunication transmission function so that the electronic signals in the subsequent packaging unit can communicate with other packaging unit bodies and substrates. The single or plural Through-holes are formed in the main chip, and are filled with conductive metal to connect the upper and lower surfaces of the main chip, and to connect the single or multiple microelectronic components described above. The foregoing and other objects, features, and advantages will be made clearer by the following detailed description of the preferred embodiments with reference to the drawings. The present invention discloses an electronic packaging structure. In particular, the present invention provides multiple packages The wafer-level system package structure of the unit body uses the same or different package units to meet high-density electronic components: and ^, and miniaturized package structure The requirements of the structure are provided, and the embodiments are provided. The details of the second L are as follows.

1233192 五、發明說明（6) 電路:發明之封裝單元群體示意圖，具同-邏輯 σ又冲與相關元件之gp番 比 技術如微$ ^ μ千之配置，皆可利用晶圓級半導體封裝 作完塗佈、沈績等製造程序之設計批次製 成不同的經ί不同的製作流a，可於晶圓300上形 封裝盤你私二 體之主體結構。於晶圓3〇〇上，待所有 等^丌I序皆完成後，藉由切割道302利用切割、钱刻 立的複數個封裝單元體301予以相互… 不同的二姑Γ圓級封裝結構設計與製作程序，則可以形成 組日i可饮、單70體3〇ι;之後，組裝堆疊電子封裝結構模 羼的1ΐ此封裝結構模組應用環境與功能之需求以決定堆 :::數及欲堆疊封裝單元體的種類與式樣。❿第3a圖中 圖1作之單一封裝單元體301，其空穴區域之位置俯視 圖’將由第3b圖詳示之。 第3b圖為本發明之單一封裝單元體之俯視示意圖。封 裝早疋體301内具一主晶片3〇7，係構成封裝單元體3〇ι之 主體…構，該主晶片3 0 7材料可為矽晶，或前述材料之聚 化合物組合；目前常見之積體電路晶片即可用作為該主晶 片3|)7、，其上表面具邏輯電路功能之工作區域（如·⑽⑽元 件區域），故於該主晶片307之其他非工作區域處（如下表 面）可利用切割、蝕刻等微機電技術形成數個開口面積大 小不一致的空穴區域（304,305,30 6 )。前述空穴區域 (304, 305, 306 )内可埋入預製或直接地形成單或複數個 微電子元件’亦可同時於主晶片30 7表面安置形成複數個 微電子元件；待封裝單元體3〇 1經多重堆疊後，此電子封 第14頁 12331921233192 V. Description of the invention (6) Circuit: a schematic diagram of the package unit group of the invention, with the same-logic sigma and gp fan technology of related components, such as micro $ ^ μ thousand configuration, can use wafer-level semiconductor packaging as After completing the design batches of coating, Shen Ji and other manufacturing processes, different manufacturing flows a can be made, and the main structure of your private body can be packaged on the wafer 300. On the wafer 300, after all the processes are completed, a plurality of packaging unit bodies 301 are used to cut each other through a cutting line 302 using cutting and engraving ... Different two-in-a-round packaging structure design With the production process, you can form a group of drinkable, single 70-body 30mm; after that, assemble 1 of the stacking electronic package structure module. This package structure module application environment and function requirements to determine the stack ::: 数 和The type and style of the package unit to be stacked.图 中 In FIG. 3a, a plan view of the position of the cavity region of the single package unit 301 made in FIG. 1 will be shown in detail in FIG. 3b. FIG. 3b is a schematic top view of a single package unit body according to the present invention. There is a main wafer 307 in the packaged early die 301, which is the main body of the package unit 300. The material of the main wafer 307 can be silicon crystal, or a combination of the foregoing materials; The integrated circuit chip can be used as the main chip 3 |) 7. The upper surface has a working area for logic circuit functions (such as the ⑽⑽ component area), so it is in other non-working areas of the main chip 307 (as shown below) Micro-electromechanical technologies such as cutting and etching can be used to form several cavity areas with inconsistent opening areas (304,305,30 6). The aforementioned cavity regions (304, 305, 306) can be embedded in a prefabricated or directly formed single or multiple microelectronic elements' can also be placed on the surface of the main wafer 30 7 to form multiple microelectronic elements; the unit body to be packaged 3 〇1 After multiple stacking, this electronic seal page 14 1233192

裝結構模組藉由具電訊傳遞之固著結 電子裝置或外界相連接導通。此外，== :空穴區域(3〇4,305,3。6)，其幾何形狀可： 狀、擴圓盤狀、多邊形平板狀、多邊形狀、二3非回盤 圓盤狀、頂©非平面之糖圓盤狀、頂面非平面之 圓盤狀或以上形狀之組合。而第3b圖中含空穴區 ' U〇4,305,306 )之封裝單元體3〇1 ’將以虛線剖面 孑細側面結構圖為例，於下文中將由第4圖至第7圖詳示 之0The structural module is connected and connected through a fixed electronic device with an electronic communication or an external connection. In addition, ==: cavity area (304, 305, 3.6), its geometric shape can be: shape, expanded disk shape, polygonal flat plate shape, polygonal shape, two 3 non-return disk shape, top © non-planar Sugar disk-shaped, non-planar top surface or a combination of the above. The package unit body 301 containing the cavity region 'U〇4,305,306 in Figure 3b' will take the dotted cross-section and the thin side structure diagram as an example. In the following, it will be detailed from Figure 4 to Figure 7.

第4a圖為本發明之第一實施例，其為第一封裝單元體 400之A-A斷面示意圖。主晶片4〇1下表面經微影、蝕刻等 技術後形成之空穴區域内可平行配置第一微電子元件4〇 7 和第二微電子元件4〇8，其微電子元件電極410皆與主晶片 401内空穴區域底部之電路圖案411接觸，並藉由充填物 409充填滿空穴區域。而主晶片4〇1與上述第一微電子元件 407及第二微電子元件4〇8間的電訊導通可藉由主晶片之電 極406、微電子元件之電極41〇、貫通孔414和電路圖案411 予以連接達成；其中，貫通孔414為穿透主晶片401之上下 表面’其開口於上述第一微電子元件4〇7及第二微電子元 件408配置於主晶片401空穴區域底部，可以用雷射鑽孔或 Μ刻等方式定義出貫通孔414位置；其内含導電金屬可由 電缚方式填滿。此外，於主晶片40 1表面上方依序塗佈一 第一絕緣膜層402、一第二絕緣膜層403及一第三絕緣膜層 4〇4 ’其功能除可用以避免電路短路與保護電路圖案4UFIG. 4a is a first embodiment of the present invention, which is a schematic cross-sectional view of A-A of the first package unit 400. FIG. The first microelectronic element 407 and the second microelectronic element 408 can be arranged in parallel in the cavity area formed by the lithography, etching and other techniques on the lower surface of the main wafer 401. The microelectronic element electrodes 410 and The circuit pattern 411 at the bottom of the cavity region in the main wafer 401 contacts, and the cavity region is filled with a filler 409. The electrical conduction between the main chip 401 and the first microelectronic element 407 and the second microelectronic element 408 can be performed by the electrode 406 of the main chip, the electrode 41 of the microelectronic element, the through hole 414, and the circuit pattern. 411 is connected; among them, the through hole 414 penetrates the upper and lower surfaces of the main wafer 401, and its openings are located at the bottom of the first microelectronic element 407 and the second microelectronic element 408 at the bottom of the cavity region of the main wafer 401, and can be The position of the through-hole 414 is defined by laser drilling or M-engraving; the conductive metal contained in it can be filled by electrical binding. In addition, a first insulating film layer 402, a second insulating film layer 403, and a third insulating film layer 400 are sequentially coated on the surface of the main wafer 401 in order to avoid short circuits and protect the circuits. 4U

第15頁 1233192 五 發明說明（8) 外，亦提供第一封裝w 一 子裝置連接組裝時，^ =，400藉由固著結構412與其他電 生應力，進而提升封事2其，材料熱膨脹係數不匹配所產 之充填物409、第一绍結構模組使用之可靠度壽命；前述 把緣腺厗4 η 9 咕 二絕緣膜層4 0 4，其村料、、曰 第一絕緣膜層4 0 3及第 高分子塑膠等化合物或、、可為環氧樹脂、高分子聚合物、 了裸露封裝單元體之=、上化口物之組合。另一方面，除 發明之第一封裝單元體^413用以接合固著結構412外，本 405覆蓋住，以保譆碟扭〇之其他頂面處皆由電路保護層 電路保護層405之材料可關微電子元件；而前述 分子塑膠等化合物咬 〜衣虱樹脂、高分子聚合物、高 前述具電訊導通之物= 金、錫銀銅合金、踢銀：=，、其材料可為金、錫錯合 前述之封裝單元體之 4或以上材料之任意組合。而 路圖案411，其材料 3加微電子元件電極，和電 鎮或以上金屬材料合了金為二導銅雷：、鈹、銅、鎳、姥、 當本發明之第一封裝上=電性之材料的組合。 裝單元體堆疊連接^，其 欲^以其他相同或相異之封 透過主晶片401」下出表複面數:貫通孔414，並於貫通孔414穿 Ϊ Κ封含導電金屬材料填滿作業之進行；接 4! 2 ' ^ 早70體4 00的下表面定義出接合固著結構 以便於第一封裝單元體4 00於堆疊組裝時與其 1233192 五、發明說明（9) 下端電子裝置之電性遠4 414、貫通孔電極415、電路封裝單元體内之貫通孔 413，以及封裝單元體4〇〇上下表、封裝單元體之電極 件，則可達成堆疊時封裝單元體結構412等元 於主晶片401下表面塗佑一 4的連接導通。此外， 提供封裝單元體4〇0於連：二③$層416 ’其功能亦為 絕緣膜層416之材料^減緩應力之用，該第四 .«- 說明，除了裸露固著結構412外，於口 ;一方面’同前述 面處皆由電路保護芦4ης爱— 、、裝早兀體400下方頂 微電子元件。° Β覆盍住，以保護邏輯電路與相關 第5a圖為本發明之第二實施例，其為第二封裝 技術面圖。主晶片501下表面經微影、餘刻等 "/成之空穴區域内可平行配置第一微電子元件507 和第二微電子元件5〇8，其微電子元件電極510皆不與主晶 片内玉八區域底部接觸，而方向朝下，並藉由充填物 509充填滿空穴區域。而主晶片5〇1與上述第一微電子元件 507及第二微電子元件508間的電訊導通可藉由主晶片之電 極506、微電子元件之電極51〇、貫通孔514和電路圖案5U 予以連接達成；其中，貫通孔514為穿透主晶片5〇1之上下 表面，其開口於上述第一微電子元件507及第二微電子元 件508兩側之主晶片501空穴區域的底部，可以用雷射鑽孔 或敍刻等方式定義出貫通孔514位置；其内含導電金屬可 由電鑄方式填滿。此外，於主晶片50 1表面上方依序塗佈Page 15 1233192 Five descriptions of the invention (8) In addition, the first package w is also provided when a sub-device is connected and assembled, ^ =, 400 through the fixing structure 412 and other electro-stresses, thereby improving the seal 2 and the material's thermal expansion The coefficient does not match the reliability life of the produced filling material 409 and the first Shao structure module; the marginal gland 厗 4 η 9 and the second insulating film layer 4 0 4, the material, and the first insulating film layer Compounds such as 403 and the first polymer plastic may be a combination of epoxy resin, high molecular polymer, bare packaging unit, and chemical compounds. On the other hand, except for the first package unit 413 of the invention, which is used to join the fixing structure 412, the cover 405 is covered to ensure that the other top surfaces of the disk are covered with the circuit protection layer 405 Microelectronic components can be turned off; and the aforementioned molecular plastics and other compounds bite ~ clothes lice resin, high molecular polymers, high telecommunication-conducting objects = gold, tin-silver-copper alloy, kick silver: =, and its material can be gold, Tin is combined with any combination of 4 or more materials of the aforementioned package unit. For the road pattern 411, the material 3 plus the microelectronic element electrode is combined with an electric ballast or above metal material to form a two-conductor copper mine: beryllium, copper, nickel, rhenium, and when the first package of the present invention = electrical Of materials. Units are stacked and connected ^, and they want to ^ pass through the main wafer 401 with other identical or different seals. The number of surfaces is as follows: through-holes 414, and the through-holes 414 are penetrated. 2; ^ as early as the bottom surface of the 70 body 4 00 defines a bonding and fixing structure to facilitate the first package unit body 4 00 and 1233192 when stacked and assembled V. Description of the invention (9) Electricity of the lower electronic device The distance of 4 414, the through-hole electrode 415, the through-hole 413 in the circuit package unit, and the upper and lower tables of the package unit 400, and the electrode components of the package unit, can achieve the package unit structure 412 equivalent when stacked. The connection on the lower surface of the main chip 401 is Tu You-1. In addition, a package unit 400 is provided: two ③ $ layer 416 'its function is also the material of the insulating film layer 416 ^ to reduce stress, the fourth. «-Description, in addition to the bare fixed structure 412, In the mouth; on the one hand, the same as the aforementioned surfaces are protected by the circuit 4 芦 ς love, and the microelectronic components are mounted below the early body 400. ° Β cover to protect the logic circuit and related Figure 5a is a second embodiment of the present invention, which is a technical diagram of the second package. A first microelectronic element 507 and a second microelectronic element 508 can be arranged in parallel in the cavity area of the lower surface of the main wafer 501 through lithography, engraving, etc., and neither of the microelectronic element electrodes 510 is connected to the main The bottom of the jade region in the chip is in contact with the direction facing downward, and the cavity region is filled with the filler 509. The communication between the main chip 501 and the first microelectronic element 507 and the second microelectronic element 508 can be performed by the electrode 506 of the main chip, the electrode 51 of the microelectronic element, the through hole 514, and the circuit pattern 5U. The connection is achieved; the through hole 514 penetrates the upper and lower surfaces of the main wafer 501, and is opened at the bottom of the cavity area of the main wafer 501 on both sides of the first microelectronic element 507 and the second microelectronic element 508. The position of the through hole 514 is defined by laser drilling or engraving; the conductive metal contained therein can be filled by electroforming. In addition, it is sequentially coated on the surface of the main wafer 501.

瞧 第17頁 1233192 五、發明說明（10) 一第一絕緣膜層502、一筮一紹从 侧，其功能除可用以】；電=5。3及一第三絕緣膜 子裝置連接組裝時藉由固著結細與其他電 之充填物509、第一絕使用之可靠度壽命；前述 三絕緣膜層504，其材料7、二〇2、第二絕緣膜層503及第 高分子塑膠等化合其物材二可上為樹脂、高…^ 了裸露封裝單元體之電 0物之組合。另一方面，除 發明之第二封裝單元體5·〇〇13 =二接合固著結構512外，本 505覆蓋住，以保護邏輯電路二他處皆由電路保護層 電路保護層505之材料可0 = ^電子70件；而前述 化合物或 :錫其材料可為金、_* 前述之封裝單元體之=:等或以上材料之任意組合。 路圖咖其材 Λ. . ιν , ^ j兩金銅、銘、鈹、銅、鉾、奴 鎢或以上金屬材料合金式 ^ ^螺銬、 當本發明之第二封奘二-導電性之材料的組合。 裝單元體堆疊；接；早干欲二 構剖面圖與第5&圖大致上：Ϊ ’其結 定Λ上:二 性連接；且裝時與其下端電子裝置之： 精甶封裝早兀體内之貫通孔514、電路圖案 Η 第18頁 1233192 " 1 _-- 五、發明說明（11) 511、封裝單元體之電極513，以及 面之固著結構512等元#， 裝早^體500上下表 間的連接導通。此外，同前述說明成？時封，單元體之 512外，於封裝單元體5〇〇下方頂面〆稞露固著結構 覆蓋住，以保護邏輯電路與相關微路保護層505 第6a圖為本發明之第二者 600之A-A斷面示意圖。主：：:歹下’其為第三封裝單元體 技術後形成之空穴區域内可表第面1微影、㈣等 盥主曰Ηκηι办弟从電子兀件607之底面 607 /Λ 2 : 部相接合，且該第-微電子元件 ^ . 又大於該第二微電子元件6〇8，使該第一微電 ,執啻工電極610能不被該第二微電子元件608所覆蓋住， ίΓ 件電極㈣之方向皆朝下，並藉由充填物6〇9充填 / :八區域。而主晶片6〇1與上述第一微電子元件6〇7及第 =微電子元件608間的電訊導通可藉由主晶片之電極6〇6、 Μ電子元件之電極61〇、貫通孔614和電路圖案61ι予以連 接達成；其中，貫通孔614為穿透主晶片6〇1之上下表面， f開口於上述堆疊多重微電子元件（5〇7, 5〇8 ) 一側之主 =片601空穴區域的底部，可以用雷射鑽孔或蝕刻等方式 定義出貫通孔614位置；其内含導電金屬可由電鱗方式填 滿此外’於主晶片601表面上方依序塗佈一第一絕緣膜 層602、一第二絕緣膜層6〇3及一第三絕緣膜層6〇4，其功 能除可用以避免電路短路與保護電路圖案6丨1外，亦提供 第三封裝單元體6〇〇藉由固著結構612與其他電子裝置連接 第19頁 1233192 五、發明說明（12) 組裝時’減緩其因 "*〜 ( 而提升封裝結構模組；斗熱膨脹係數不匹配所產生應力，進 6〇9、第-絕緣膜用之可靠度壽命；冑述之充填物 層604，其材料可^严知'第二絕緣膜層603及第三絕緣膜 膠等化合物或以上樹脂、高分子聚合物、高分子塑 裝單元體之電極613二物之2且合。另-方面，除了裸露封 三封裝單元體6〇〇之龙j接合固著結構612外，本發明之第 住，以保護邏輯雷牧^頂面處皆由電路保護層6〇5覆蓋 層605之材料可為严/、相關微電子元件；而前述電路保護 等化合物或以上化人：对月曰、尚分子聚合物、高分子塑膠 前述具電訊導通之w t Ί σ ° 金、錫銀鋼合金、錫：：構612，其材料可為金、錫鉛合 前述之封裝單元體金等或以上材料之任意組合。而 路圖案611，其材料可^13、微電子元件電極610，和電 ^ VI μ ^ Μ X枓了為金、銅、鋁、鈹、銅、鎳、鍺、 ^ ^ 屬材料合金或具導電性之材料的組合。 :單元封裝單元體600欲以其他相同或相異之封 =立丨品 且連接時，其斷面示意圖請參閱第6b圖，其結 元；6。〇圖的與第：圖-大致上相同，差別在於需在第三封裴單 ^下表面定義出接合固著結構61 2之位置，以便於 第二封裝單元體6〇〇於堆疊組裝時與其下端電子裝置之電 性連接。而藉由封裝單元體内之貫通孔614、電路圖案 611、封^裝單元體之電極613，以及封裝單元體6〇〇上下表 面之固著結構61 2等元件，則可達成堆疊時封裝單元體之 間的連接導通。此外，同前述說明，除了裸露固著結構See page 1233192. V. Description of the invention (10) A first insulating film layer 502, one side and one side from the side, its function can be divided by]; electricity = 5.3 and a third insulating film sub-device when connected and assembled With the fixed junction and other electrical fillers 509, the first reliable use life; the aforementioned three insulating film layer 504, its material 7, 202, the second insulating film layer 503, and the first polymer plastic, etc. The combination of the two materials can be made of resin, high ... ^ a combination of electrical materials of the bare package unit. On the other hand, in addition to the second package unit body 5.0 · 0013 = two-junction fixing structure 512 of the invention, the 505 is covered to protect the logic circuit. The other parts are covered by the material of the circuit protection layer 505. 0 = ^ 70 electronics; and the aforementioned compound or: tin and its material may be gold, _ * the aforementioned packaging unit body =: etc. or any combination of the above materials. Road map coffee material Λ. Ιν, ^ j two gold copper, Ming, beryllium, copper, rhenium, slave tungsten or above metal material alloy formula ^ ^ shackles, when the second seal of the present invention-conductive material The combination. Assembly unit stacking; connection; early drying and second structure sectional view and Figure 5 & roughly: Ϊ 'its final Λ: bisexual connection; and when installed with its lower electronic device: precision packaged in the early Wu body Through-hole 514, circuit pattern Η page 18 1233192 " 1 _-- V. Description of the invention (11) 511, electrode 513 of the packaging unit body, and fixed structure 512 etc. on the surface. The connection between the upper and lower tables is on. In addition, as described above? Time seal, outside the 512 unit body, is covered by an exposed structure on the top surface of the package unit 500 to protect the logic circuit and the related microcircuit protection layer 505. Figure 6a is the second person 600 of the present invention. AA cross-section diagram. Master ::: Your Majesty ', which is the bottom surface of the third package unit body technology that can be formed in the cavity area 1 lithography, ㈣ and other toilet masters Ηκηι to do the bottom surface 607 / Λ 2 of the electronic component 607: And the first microelectronic element ^. Is larger than the second microelectronic element 608, so that the first microelectronic and working electrode 610 can not be covered by the second microelectronic element 608 The directions of the electrode electrodes 皆 are all facing downwards, and are filled with a filling material 609 /: eight areas. The electrical communication between the main chip 601, the first microelectronic element 607, and the third microelectronic element 608 can be performed by the electrode 606 of the main chip, the electrode 61 of the M electronic element, the through hole 614, and The circuit pattern 61m is connected; the through-hole 614 penetrates the upper and lower surfaces of the main wafer 601, and f is opened on the side of the above-mentioned stacked multiple microelectronic element (507, 508) = sheet 601 is empty At the bottom of the cavity area, the position of the through-hole 614 can be defined by laser drilling or etching; the conductive metal contained therein can be filled by electric scales. In addition, a first insulating film is sequentially coated over the surface of the main wafer 601. The layer 602, a second insulating film layer 603, and a third insulating film layer 604, in addition to their functions to avoid circuit short circuit and protect the circuit pattern 6 丨 1, also provide a third package unit 600. Connection with other electronic devices through the fixing structure 612 Page 19 1233192 V. Description of the invention (12) The assembly structure module is 'slowed down' during assembly ** ~ (and the package structure module is promoted; the thermal expansion coefficient of the bucket does not match the stress generated, and 609. Reliability life of the first-insulation film; The material of the filling layer 604 mentioned above can be used for the second insulating film layer 603 and the third insulating film adhesive, or compounds of the resin, polymer, and polymer molded unit electrode 613. In addition, in addition to the above, in addition to the bare j-bonding fixing structure 612 of the sealed three-package unit body 600, the first aspect of the present invention is to protect the logic thunder, and the top surface is protected by a circuit protection layer 605. The material of the cover layer 605 may be strict / relevant microelectronic components; and the aforementioned compounds for circuit protection or the like are converted to: 对 σ σ ° gold and tin for telecommunication conduction to the moon, polymer, and polymer plastic Silver-steel alloy, tin: structure 612, whose material can be gold, tin-lead, or any combination of the foregoing packaging unit body gold, etc., and road pattern 611, whose material can be ^ 13, microelectronic element electrode 610, And electricity ^ VI μ ^ Μ 枓 is a combination of gold, copper, aluminum, beryllium, copper, nickel, germanium, ^ ^ metal alloy or conductive material. The seal of the difference = standing product and connected Figure 6b, its structure; Figure 6.0 is roughly the same as Figure 1: The difference is that the position of the bonding fixing structure 61 2 needs to be defined on the lower surface of the third seal sheet ^ to facilitate the second package. The unit body 600 is electrically connected to its lower electronic device during stack assembly. The package body is packaged with a through hole 614, a circuit pattern 611, an electrode 613 for packaging the unit body, and a package unit body 600. The components such as the fixing structure 61 2 on the upper and lower surfaces can achieve the connection and conduction between the packaging unit bodies when stacked. In addition, as described above, except for the bare fixing structure

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五、發明說明（13) 覆蓋卜住於以封佯破：疋體6。°下方頂面處皆由電路保護層605 覆盍：以保護邏輯電路與相關微電子元件。 = = = =域㈡:7…面經微影，等 701 ^ Λ ^ ^ ^ t ^ ^ # f „71 0 , # ^ ,a , 體700岸用二光與^之電路圖案7U接觸接合。當封裝單元 篮700應用於先學感測領域時 ^"#708 ^ 了接收先線才可發揮其作用，是故，於主 下 面接合一透明基板71 5 ,使得 之下表 元件〔707 7ns、如吏侍主日日片701中内含多重微電子 ， ）之工穴區域形成一密閉空間7 〇 9，s #嬙 能穿透過上述之透明基板715， ^09讓先線 -微電子元_或第二微電二感 收，同時，亦保護第一微電子元件7 、_微° )所, T免於外界環境對其之污染與損 子:件 第一微電子元件707及第二微電子元件7ns 片7〇/與上述 藉由主晶片之電極m、微f i j的電訊導通可 7U和電路圖案711予以連接電達子/.件/電極71〇、貫通孔 透主曰違成中’貫通孔714為穿 1日曰片701之上下表面’其開口於上 70Υ及第二微電子元件7〇8配置於主曰 被電子兀件 部，可以用雷射鑽孔或蝕刻等方式穴區域底 置，·其内含導電金屬可由電Π以== 位 701表面上方依序塗佈-第-絕緣膜物1 卜第：：：： 1233192 五、發明說明（14) 層703及一第三絕緣膜層7〇4，其功处 路與保護電路圖案711外，亦接报J犯除可用以避免電路短 固著結構712與其他電子裝置連接：：$裝單元體700藉由 熱膨脹係數不匹配所產生應力， 衣/，減緩其因材料 用之可靠度壽命；前述之第'絕緣：二:封裝結構模組使 聚合物、高分子塑膝等化合物氧樹脂、高分子 方面，除了裸露封裝單元體 =之人組合。另- m外’本發明之第四封裝單元體7:用二= :保護讓覆蓋住，以保護邏輯 相他:面處皆由電 件，·而前述電路保護·5之材料 F 2 =電子几 聚合物、高分子塑膠等化合物或高分子 金、錫銀銅合金、錫銀合金等或以上材材科可為金音^人錯合 述之透明基板m，其材料可為玻璃、石英、？透且二前 分子塑膠等化合物或以上化合物之挺：。 別述之封裝早兀體之電極713、微電子元件電極71〇, 口 路圖案川，*材料可為金、鋼、銘、鈹件】桎7j〇和電 以上金屬材料合金或具導電性之材料的組合、。、、 =文已經將第4圖至第？时具不同結構之封裝單元體， 其杈佳實施例詳細說明之。其中， 比 半導體技術批次製作完成，禆刺用直^早兀體，白為利用 或相異之封裝單元體而形成立體堆叠結〜 冓成封裝結構之主體，而該封裝結構所堆疊之封裝 第22頁 1233192 五、發明說明（15) ^元體個數將取決於其應用環境與功能上之需要而決定， 並提供其實施例。其詳細說 實： 只做-說明，並非用以限定本發明。τ 罕又隹““列 第8a圖為本發明封裝結構第五實施例沿α_α斷面之二 層2單兀體之堆疊示意圖。此實施例中所使用的 π體為二結構相同之封裝單元體例；此封 、 :二圖中詳細說明之。因每-封裝單元體400於1上下 者結構804與基板802上之電極8〇3連接结合 藉由固 二裝置或外界電性導通’傳遞電 气、導、他 8。3，其材料可為金、銅、銘、二刖这之基板電極 上金屬材料合金或具導電性之材料的组合、。而、^或以 8〇2 ’其材料可為具方向性之 ’ = 之基板 維、高分子朔瞪齡M i 回刀卞I合物纖 複合材料。/纖維或以上纖維之組合與樹脂基質合成之 再堆:施例之ί層封裝單元體，欲 重堆疊結構時：发斷：:」圖：：裝早疋體以形成三層多 圖與第8a圖大致二相同不！別：於構剖面 體4。0頂面處定義出最頂層之封裝單元體 1233192 *** · 五、發明說明（16) 8:Λ接接合第二層冑裝單元體4。〇的位置。料，因每-叶二：體4—00一於其上下表面處皆有相同連接位置處之設 裝單：體4〇Γ連接二早第:Τ◦亦可翻轉後，再與其他封 裝單元體400為經過翻2圖^為例，其中最頂層的封 接接合。 猢轉後，在與下端之封裝單元體400連 声封Γ:圖i本發？封裝結構第六實施例沿Η斷面之二 二體：：：错f堆登不意圖。此實施例中所使用的封裝單 於第5圖二：ΒΒ 疋體5〇0 ; &封裝單元體5〇〇已 ΪΓΛ中痒、兒明《。因每-封裝單元體500於其上下表 面處皆有相同連接位置處之設計，是故， 單=表 500之間可用固著結構9〇4予以連接，以 ^體 1訊導通；而最底層之封裝單元70體5GG ^ ^固 ==，904與基板902上之電極903連接結合， 9 電子裝置或外界電性導通，傳遞電訊 進而^其他 其材料可為金、錫錯合金、錫銀電鋼^ :銀合金等或以上材料之任意組合。前述之基板電:金 90 3’其材料可為金、銅、鋁、鈹、鋼、鎳、姥、 上金屬材料合金或具導電性之材料的組合。而前述/以 9〇2，其材料可為具方向性之碳纖維、高分子聚合物土板 Ϊ合ST塑膠纖維或以上纖維之組合與樹脂基質合成之 當本發明封裝結構第六實施例之二層封裝 再堆疊連接一其他相同或相異之封裴單元體以形成三層^V. Description of the invention (13) Covering the burial in the seal: Carcass 6. ° The top surface below is covered by circuit protection layer 605: to protect logic circuits and related microelectronic components. = = = = Domain ㈡: 7… face lithography, and so on 701 ^ Λ ^ ^ ^ t ^ ^ # f „71 0, # ^, a, the body 700 is connected to the circuit pattern 7U of ^ with two lights. When the packaging unit basket 700 is applied in the field of pre-sensing sensing ^ "# 708 ^ The receiving front line can only play its role. Therefore, a transparent substrate 71 5 is bonded under the main, so that the lower table component [707 7ns For example, there are multiple microelectronics contained in the daily film 701 of the clerk and servant, and the area of the working hole forms a closed space 7 009, s # 嫱 can pass through the transparent substrate 715 mentioned above, ^ 09 let the front line-microelectronics element _ Or the second microelectronic two sense and receive, at the same time, also protect the first microelectronic element 7, _ micro °), T from the external environment of its pollution and damage: pieces of the first microelectronic element 707 and the second The microelectronic element 7ns chip 70 / and the above-mentioned telecommunications through the electrode m of the main chip, micro fij can be connected to the 7U and the circuit pattern 711 by the electronics / piece / electrode 71. The 'through hole 714 is through the upper and lower surfaces of the Japanese film 701', and its opening is at the upper 70Υ and the second microelectronic component 708 is arranged in the main electronic part, and can be used. The laser cavity is drilled or etched at the bottom of the hole area, and the conductive metal contained in it can be sequentially coated on the surface of the == bit 701 above-the first-insulating film 1 b: :: 1233192 V. Invention Note (14) The layer 703 and a third insulating film layer 704, in addition to the power circuit and the protective circuit pattern 711, are also reported to be used in addition to avoiding short circuit fixing structures 712 and other electronic devices: The installed unit body 700 reduces the stress caused by the thermal expansion coefficient mismatch, and reduces its reliability life due to the use of materials; the aforementioned 'Insulation: II: Encapsulated structural module enables polymers, polymer knees and other compounds In terms of oxygen resins and polymers, in addition to the naked combination of the packaging unit = person. In addition-m 'the fourth packaging unit of the present invention 7: use two =: protect to cover, to protect the logical other: all sides By electrical parts, and the aforementioned circuit protection, the material of F 5 = electronic polymer, polymer plastic and other compounds, or polymer gold, tin-silver-copper alloy, tin-silver alloy, etc. or more. The transparent substrate m described by people is made of glass, quartz, Transparent and two compounds such as molecular plastics or above: Others: the electrodes 713 that encapsulate the early body, the microelectronic element electrodes 71, the pattern of the mouth, the material can be gold, steel, inscription, beryllium 】 桎 7j〇 and the combination of metal materials or alloys with electrical or conductive materials, the above has been shown in Figures 4 to? With different structure of the packaging unit body, the preferred embodiment of the detailed description. Among them, compared with the batch production of semiconductor technology, the stabbing is made of a straight body, and the white is a three-dimensional stacking junction using or different packaging unit bodies. The main body of the packaging structure is formed, and the packages stacked by the packaging structure are packaged. Page 22 1233192 V. Description of the invention (15) The number of elements will be determined according to its application environment and functional needs, and examples will be provided. The details are as follows: It is only for description and not for limiting the present invention. Figure 8a is a schematic diagram of the stacking of two layers and two units along the α_α cross section of the fifth embodiment of the packaging structure of the present invention. The π body used in this embodiment is two package units with the same structure; this seal is described in detail in the two figures. Because the per-packaged unit 400 is connected to the electrode 803 on the substrate 802 by the upper and lower structure 804, the electrical, conduction, and other components are transferred through the solid-state device or the external electrical conduction. The material can be gold. Metal, alloy, or combination of conductive materials on the substrate electrodes of copper, copper, Ming, and Er. In addition, ^ or 802 ′ may be used as the material of the substrate with the directivity of ′ =, the high molecular age M i, and the composite fiber composite material. / Fiber or the combination of the above fibers and the resin matrix are re-stacked: the encapsulation unit body of the tier of the example, when the structure is to be re-stacked: break :: "Figure :: Install the early carcass to form a three-layer multi-map Figure 8a is roughly the same. Do not define the topmost packaging unit body at the top surface of the section 4.0. 1233192 *** · V. Description of the invention (16) 8: Λ is connected to the second-layer outfit unit body 4. 〇's position. Material, because each-leaf two: body 4—00 has the same connection position at the upper and lower surfaces: the body 4〇Γ is connected to the second one: Τ◦ It can also be flipped, and then with other packaging units The body 400 is shown in FIG. 2 as an example, in which the topmost layer is sealed and joined. After turning around, it is connected with the lower package unit 400 to seal it. The sixth embodiment of the packaging structure is along the second cross-section of the second body. The package list used in this embodiment is shown in Figure 5: BB 疋 body 500; & the package unit 500 has been 痒 ΓΛ in itching, it is clear. Because each package unit 500 has the same connection position design on its upper and lower surfaces, it is possible to connect the unit 500 with the fixing structure 904 to connect it with the body 1 signal; and the bottom layer The packaging unit 70 body 5GG ^ ^ Solid ==, 904 is connected and combined with the electrode 903 on the substrate 902, 9 The electronic device or the outside is electrically connected, and the telecommunication is transmitted. ^ Other materials can be gold, tin alloy, tin silver Steel ^: silver alloy or any combination of the above materials. The material of the aforementioned substrate: gold 90 3 ′ may be gold, copper, aluminum, beryllium, steel, nickel, hafnium, a metal alloy or a combination of conductive materials. The material mentioned above can be directional carbon fiber, high molecular polymer soil plate combined with ST plastic fiber, or a combination of the above fiber and resin matrix. The sixth embodiment of the packaging structure of the present invention is the second. The layer package is then stacked and connected with other identical or different sealing units to form three layers ^

第24頁Page 24

1233192 五、發明說明（17) 重堆疊結構時，其斷面示意圖表 圖與第9a圖大致上相同，差^多閱第9b圖，該結構剖面 體500頂面處定義出最頂層之於。需在該第二層封裝單元 9〇4連接接合第二層封裝單元俨二早70體500，其固著結構 封裝單元體5 0。於其上古的位置。此外，因每-計，是故，每-封裝單元^2有相同連接位置處之設 裝單元侧連接;以第:體圖5°所0亦：翻轉後’再 裝單元體500為經過翻轉後 丨：η的封 單元體為Μ，若該堆疊多重施例之三層封裝 ^ 斷 忍圖睛參閱第9c圖，該妙槿立，丨而m命够 =圖大致上相同’差別在於最頂層之封裝單元體川回為且 早或複數個光感測微電子元件之封裝單元體裝單，、一 體700已於第7圖中詳細說明之。」裝早兀 非且、泰姐i C： u 4封裝早兀體700於其 1 = ΐ : 侧表面有與其他封裝單元體相同之 連接位置處的δ又计，是故其固著結構9〇4可連接接人 =!!體5Γ的位置。經上述多重封裝單元體：堆i ' :y成二層封裝模組後，可使光線由該封裝模組之上 方直接穿透透明基板71 5而進行光學感測。 第10a圖為本發明封裝結構第七實施例沿a — a斷面之二 層封裝單元體之堆疊示意圖。此實施例中所使用的封裝i π體為二結構相同之封裝單元體6〇〇 ;此封裝單元體“Ο 於第6圖中詳細說明之。因每一封裝單元體6〇〇於其上下 面處皆有相同連接位置處之設計，是故，二封裝單元體1233192 V. Description of the invention (17) The schematic diagram of the cross-section when the structure is re-stacked is roughly the same as that of Fig. 9a, but read more from Fig. 9b. The top surface of the structure section 500 is defined at the top. The second-level packaging unit 904 needs to be connected and bonded to the second-level packaging unit, the second body 70-500, and its fixed structure, the packaging unit body 50. In its ancient place. In addition, because of the per-meter, each of the packaged units has the same connection position at the installation unit side; the first: Figure 5 °, 0: also: after reversing, reinstalling the unit 500 is reversed Back 丨: The sealing unit body of η is M. If the three-layer package of the stacked multiple embodiment is shown in Figure 9c, this is wonderful, and the life of m is enough to be equal. The difference lies in the most The packaging unit body on the top layer is the packaging unit body package of the photo-sensing microelectronic element, or the package 700, which is described in detail in FIG. 7. I ’m pretending to be early, and Taijie i C: u 4 encapsulates the early body 700 at its 1 = ΐ: The side surface has δ at the same connection position as other packaging unit bodies, so its fixed structure 9 〇4 can be connected to access = !! body 5Γ position. After the above-mentioned multiple packaging unit bodies: stacking i ': y into a two-layer packaging module, light can be directly transmitted through the transparent substrate 71 5 from above the packaging module for optical sensing. Fig. 10a is a stacking diagram of a two-layer packaging unit body along a-a cross section of the seventh embodiment of the packaging structure of the present invention. The package i π body used in this embodiment is two package units with the same structure 600; this package unit “0” is described in detail in FIG. 6 because each package unit 600 is above it. The design of the same connection position is below, so the two package unit body

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第25頁 五、發明說明（18) 60 0之間可先經翻轉後再用固著結構1 004予以連接，以完 成多重封裝單元體600間的電訊導通；而最底層之封裝單 元體600可以藉由固著結構1〇04與基板1〇〇2上之電極1〇〇3 連接結合，進而與其他電子裝置或外界電性導通，傳遞電 訊。前述具電訊導通之固著結構1〇〇4，其材料可為金、錫 鉛合金、錫銀銅合金、錫銀合金等或以上材料之任意組 合。前述之基板電極1〇〇3，其材料可為金、銅、鋁、鈹、 銅、鎳、铑、鎢或以上金屬材料合金或具導電性之材料 :合=前述之基板1 002 ’其材料可為具方向性之碳纖、 1间为子聚合物纖維、高分子塑膠纖維或以上纖 曰與，脂基質合成之複合材料。 、、' 、’、 再雄ΐίΓ月封裝結構第七實施例之二層封裝單元體，欲 ί:;連接一其他相㈤或相異之封裝單元體以形成三声ί 面Ιϋ:ϊ構時’其斷面示意圖請參閱第10b圖，該姓構V" 面圖與第l〇a圖大致上相同，差別在於 X :構剖 單元體60。頂面處定義出最頂層之封裝J元體? -層封裝 :,10 04連接接合第二層封裝單元體6〇〇 。’其固著 因母一封裝單元體600於其上下 此外， 處之設計，是故，每一封裝單 二：相同連接位置 其他封裝單元體_連接;亦可翻轉後，再與 梦、^ 一層的封裝早元體6〇〇為經過翻轉後，其中最底 封裝早π體600連接接合。此外， 在與頂端之 實施例之三層封裝單 本毛月封裝結構第七 用於先學感測之用途上時，其夕重封裝結構為 吟其斷面不意圖請參閱第1〇c 1233192 五、發明說明（19) 圖’该結構剖面圖與第1 層之封裝單元辦7 η η炎^ 致上相同，差別在於最頂 封裝單元體，_封裝、、/單或複數個光感測微電子元件之 因該封裝ί元體V:二早 其他封裝單元體相同之連接位//板715之一侧表面有與 構1 0 04可連接接合第處的設計，是故其固著結 多重封裝單元體之堆裝：元體600的位置。經上述 光線由該封裝模組之：；；=:;=裝7模組後，可使 學感測。 万1接穿透透明基板71 5而進行光 展夕ί U f為本發明封裝結構第八實施例沿A — A斷面之四 ;:-j Ϊ單元體之堆疊示意圖。此實施例中所使用的封 四種結構不相同之封裝單元體，由最底層至最 單二上0:堆楚疊’分別為第-封裝單元體4°°、第三封裝 二體第二封裝單元體500，以及第四封裝單元體 ，而上述各封裝單元體之結構已於第4圖至第7圖中詳 細說明之。除了第四封裝單元體700於其非具透明基板715 之一，表面有與其他封裝單元體相同之連接位置處的設計 外，每厂封裝單元體（4〇〇 5〇〇 6〇())於其上下表面處皆 有相同連接位置處之設計，是故，每一封裝單元體 (400,500,600 )之間可先經翻轉後再用固著結構11〇4予 以連接接合，以完成四層之多重封裝單元體 ( 400, 500, 60 0, 700 )間的電訊導通；而最底層之封裝單 元體400可以藉由固著結構11〇4與基板11〇2上之電極丨丨” 連接接合，進而與其他電子裝置或外界電性導通，傳遞電 Η 第27頁Page 25 V. Description of the invention (18) 60 0 can be reversed and then connected with the fixing structure 1 004 to complete the electrical communication between the multiple packaging unit 600; and the bottom packaging unit 600 can The fixed structure 1004 is connected to the electrode 1003 on the substrate 1002, and is then electrically connected with other electronic devices or the outside world to transmit telecommunications. The above-mentioned fixed structure with telecommunication connection 1004 can be made of gold, tin-lead alloy, tin-silver-copper alloy, tin-silver alloy, or any combination of the above materials. The material of the aforementioned substrate electrode 1003 may be gold, copper, aluminum, beryllium, copper, nickel, rhodium, tungsten or the above metal material alloy or a conductive material: together = the aforementioned substrate 1 002 'its material It can be a directional carbon fiber, a sub-polymer fiber, a high-molecular plastic fiber, or a composite material synthesized from a lipid matrix. ，， ，，， Re Xiong ΐ ΐ Γ 月 month packaging structure of the seventh embodiment of the two-layer packaging unit body, want to :; connect another similar or different packaging unit body to form a three-tone surface I: when the structure 'For a schematic diagram of the cross section, please refer to FIG. 10b. The surname structure V " is substantially the same as that of FIG. 10a, with the difference being X: Section unit 60. The topmost packaged J-element body is defined at the top surface? -Layer package: 10,04 connection to the second-level package unit body 600. 'It is fixed because the mother-package unit 600 is above and below, and the design is so that each package is single: other package units at the same connection position _ connected; can also be flipped over, and then one layer with the dream, ^ The packaged early element body 600 is after the flip, and the bottommost packaged early element body 600 is connected and bonded. In addition, when compared with the top three-layer package of the three-layer package, the single-moon package structure is used for the prior learning sensing, the package structure is not intended to refer to its cross-section. Please refer to Section 10c 1233192. V. Description of the invention (19) Figure 'The cross-sectional view of the structure is the same as that of the packaging unit office 7 on the first layer. The difference is that the top packaging unit body, package, / / single or multiple light sensors Because of the packaging of the microelectronic component, the body V: the same as the other packaging units of the second package // one side surface of the board 715 has a design that can be connected to the structure 1 0 04, so it is fixed. Stacking of multiple packaging unit bodies: the location of the unit body 600. After the above light is used by the package module: ;; =:; = After 7 modules are installed, the sensor can be sensed. In the first embodiment, the transparent substrate 71-5 is used for light development. U f is a stacking schematic diagram of the eighth embodiment of the packaging structure of the present invention along the A-A cross-section; In this embodiment, four kinds of packaging unit bodies with different structures are used, from the bottom layer to the single one. 0: Stacking stacks are the first package unit body 4 °, the third package body second The package unit body 500 and the fourth package unit body, and the structures of the above package unit bodies have been described in detail in FIGS. 4 to 7. Except for the design of the fourth packaging unit body 700 on one of its non-transparent substrates 715, the surface has the same connection position as other packaging unit bodies, each factory packaging unit body (4,005,006 ()) The upper and lower surfaces have the same connection position design. Therefore, each package unit (400,500,600) can be reversed and then connected with the fixing structure 1104 to complete the four-layer multiple The communication between the packaging unit bodies (400, 500, 60 0, 700) is conducted; and the bottommost packaging unit body 400 can be connected and bonded by the fixing structure 1104 and the electrodes on the substrate 1102, and further Conducts electrical conduction with other electronic devices or the outside world. Page 27

12331921233192

=。至於最頂層之封裝單元體7〇〇，由於其為具有單 ^個光感測微電子元件之封裝單元體，故需連接接合^复 疊=構模組之最頂層，以便^光線由上方射人穿透透明上 f 5以接收光源進行感測；因該封裝單元體7〇〇於其^ 透明基板715之-側|面有與其他封裝單元體相同之連接、 的設計，是故，其固著結構11〇4可連接接合第三芦 、、單元體500的位置。前述具電訊導通之固著結構=. As for the top-level package unit 700, since it is a package unit with a single light-sensing microelectronic component, it is necessary to connect and bond ^ stack = the topmost layer of the module so that the light is emitted from above The person penetrates the transparent upper f 5 to receive the light source for sensing; because the package unit 700 has the same connection and design as the other side of the package substrate 715 of the transparent substrate 715, it is The fixing structure 1104 can be connected to the position of the third unit and the unit body 500. The aforementioned fixed structure with telecommunication

其材料可為金、錫錯合金、錫銀銅合金、錫銀合金 口或以上材料之任意組合。前述之基板電極1103，其材料 可為金、銅、鋁、鈹、銅、鎳、铑、鎢或以上金屬材料合 ^或具導電性之材料的組合。而前述之基板1102，其材料 可為具方向性之碳纖維、高分子聚合物纖維、高分子塑膠 、纖維或以上纖維之組合與樹脂基質合成之複合材料。 本發明意欲涵蓋對於熟習此項技藝之人士而言係明顯的各 種修，與相似配置。因此，申請專利範圍之範圍應根據最 廣的1全釋’以包容所有此類修改與相似配置。The material can be gold, tin alloy, tin-silver-copper alloy, tin-silver alloy port or any combination of the above materials. The material of the aforementioned substrate electrode 1103 may be gold, copper, aluminum, beryllium, copper, nickel, rhodium, tungsten, or a combination of metal materials or a combination of conductive materials. The material of the aforementioned substrate 1102 may be a directional carbon fiber, a polymer polymer fiber, a polymer plastic, a combination of fibers or more, and a composite material synthesized with a resin matrix. This invention is intended to cover various modifications and similar arrangements that would be apparent to a person skilled in the art. Therefore, the scope of patent application should be based on the broadest 1 full release 'to accommodate all such modifications and similar configurations.

第28頁 1233192Page 1212 33192

【圖式之簡單說明】 本發明之較佳實施例將於下述說明中輔以形做 更詳細的闡述·· S ΐϊ Γ堆疊型積體電路晶片封裝之示意圖。 =圖Λ 寸堆疊式半導體封裝件之示意圖。 =&圖為本發明之封裝單元群體示意圖。 ^圖為本發明之封裝單元體之俯視示意圖。 第4a圖為本發明之笛[Brief description of the drawings] The preferred embodiment of the present invention will be supplemented with a detailed description in the following description ... S ΐϊ Γ stacked type integrated circuit chip package schematic diagram. = Figure Λ Schematic diagram of stacked semiconductor package. = & The figure is a schematic diagram of the packaging unit group of the present invention. ^ Figure is a schematic top view of a packaging unit body of the present invention. Figure 4a is the flute of the invention

斷面示意圖。第一實施例，4第-封裝單元體之A-A 為第一封裝單元體於堆疊 0 為第二封裝單元體之A-a 為第二封裝 。衮早70體於堆疊 為第三封裝單元㈣ 卞70體之Α〜a 為第三封裝單元 f疋體於堆- 第4b圖為本發明之第一實施例 封裝結構使用之A-A斷面示意圖 第5a圖為本發明之第二實施例 斷面示意圖。 第5b圖為本發明之第二實施例！ 封裝結構使用之A斷面示意圖 第6a圖為本發明之第三實施例， 斷面示意圖。 第6b圖為本發明之第三實施例， 封裝結構使用之A〜A斷面示意圖— ，、卞 第7圖為本發明之第四實施例，為第四Sectional diagram. In the first embodiment, A-A of the 4th-package unit body is the first package unit body on the stack 0-A of the second package unit body is the second package.衮 Early 70 bodies are stacked as the third packaging unit. 卞 70 ~ A ~ a is the third packaging unit f. The body is stacked.-Figure 4b is a schematic cross-sectional view of the AA used in the packaging structure of the first embodiment of the present invention. 5a is a schematic sectional view of a second embodiment of the present invention. Figure 5b is a second embodiment of the present invention! Schematic cross-section of A used in the packaging structure. Fig. 6a is a schematic cross-sectional view of the third embodiment of the present invention. Fig. 6b is a third embodiment of the present invention, and A ~ A cross-sectional view of the packaging structure is used,-, 卞 Fig. 7 is a fourth embodiment of the present invention, which is the fourth

面示意圖。 衮早70體之A〜A 第8a圖為本發明封裝結構第五實施例沿A_a斷面 __ 之二層耷 1233192 圖式簡單說明 裝單元體之堆疊示意圖。 裝單元體之堆疊Ϊί結構第五實施例沿A~A斷面之三層封 思圖。 第9 a圖為本發明tB： 裝單元體之堆疊^結構第六實施例沿A-A斷面之二層封 、愿*圖。 第9 b圖為本發明封姑 裝單元體之堆叠矛ΐ、、、D構第六實施例A斷面之三層封 小忍圖。 第9 C圖為本發明4+ 測元件之三層封f ^結構第六實施^斷面之具光感 冰 、 了裝早元體之堆疊示意圖。 第1 0 a圖為本發明私 裝單元體之堆叠示封意裝圖结構第七實施例沿A_A斷面之二層封 Γ:元圖體為之本堆發：封裝結構第七實施例沿a-a斷面之三層封 褒早7G體之堆疊示意圖。 ，10c圖為本發明封裝結構實施例沿卜 :?牛之三層封裝單元體之堆番示意圖。 具“ 為：發明封裝結構第八實施例沿Η斷 封裝早兀體之四層堆疊結構示意圖。 【圖式符號說明】 片封裝面 Schematic.衮 Early 70-body A ~ A Figure 8a is the second embodiment of the fifth embodiment of the packaging structure of the present invention along the A_a section __ two layers 耷 1233192 Schematic illustration of the stacking of the unit body. The fifth embodiment of the stacking structure of the unit body is a three-layer sealing plan along the A-A cross section. Fig. 9a is a tB of the present invention. A stacking structure of a unit body. The sixth embodiment is a two-layer seal along the A-A cross section. Fig. 9b is a three-layer seal ninth diagram of the cross section A of the sixth embodiment of the stacked spear unit assembly of the sealed unit body of the present invention. Fig. 9C is a schematic diagram of the stacking of the three-layer sealing f ^ structure of the 4+ measuring element of the present invention, the sixth embodiment, and the cross-section with light-sensitive ice and an early element. Fig. 10a is a stacking diagram of a private unit body according to the seventh embodiment of the invention. The seventh embodiment is a two-layer seal along the A_A cross section. Schematic diagram of the stacking of the three-layer sealed early 7G body in the aa section. Fig. 10c is a schematic diagram of a three-layer packaging unit body of a packaging structure according to an embodiment of the present invention. With "is: the eighth embodiment of the invention of the packaging structure is broken along the four-layer stacking structure of the package early package. [Illustration of symbolic symbols] Chip package

100 102 103 104 堆疊型積體電路晶 基板 第一積體電路晶片 焊線100 102 103 104 Stacked integrated circuit crystal substrate First integrated circuit wafer Bonding wire

第30頁 1233192 圖式簡單說明 1 0 5黏著層 1 0 6第二積體電路晶片 1 0 7焊線 1 0 8封裝膠 200 上表面 201 下表面 202 晶片接置區 203 上焊線區 204 開口 20 5 下焊線區 20 6 植球區 210 作用表面 211 焊墊 212 非作用表面 220 作用表面 221 焊墊 222 非作用表面 223 邊緣 240 基板 241 第一晶片 242 第二晶片 243 絕緣性構件 244 第一焊線 245 第二焊線Page 30 1233192 Brief description of the drawings 1 0 5 Adhesive layer 1 0 6 Second integrated circuit wafer 1 0 7 Welding wire 1 0 8 Packaging adhesive 200 Upper surface 201 Lower surface 202 Wafer receiving area 203 Upper bonding area 204 Opening 20 5 Lower bonding wire area 20 6 Ball planting area 210 Active surface 211 Solder pad 212 Non-active surface 220 Active surface 221 Solder pad 222 Non-active surface 223 Edge 240 Substrate 241 First wafer 242 Second wafer 243 Insulating member 244 First Bonding wire 245 Second bonding wire

第31頁 1233192 圖式簡單說明 246 封裝膠體 24 7 鲜球 30 0 晶圓 301 封裝單元體 302 切割道 303 具電訊傳遞之固著結構 304 第一空穴區域 305 第二空穴區域 306 第三空穴區域 3 0 7 主晶片 400 第一封裝單元體 401 主晶片 402 第一絕緣膜層 403 第二絕緣膜層 404 第三絕緣膜層 405 電路保護層 4 0 6 主晶片之電極 407 第一微電子元件 408 第二微電子元件 409 充填物 410 微電子元件電極 411 電路圖案 412 具電訊傳遞之固著結構 413 封裝單元體之電極Page 31 1233192 Brief description of the diagram 246 Encapsulant 24 7 Fresh ball 30 0 Wafer 301 Encapsulated unit 302 Cutting path 303 Fixed structure with telecommunications 304 First cavity area 305 Second cavity area 306 Third empty Cavity area 3 0 7 Main chip 400 First package unit 401 Main chip 402 First insulating film layer 403 Second insulating film layer 404 Third insulating film layer 405 Circuit protection layer 4 0 6 Electrode of main chip 407 First microelectronics Element 408 Second microelectronic element 409 Filler 410 Microelectronic element electrode 411 Circuit pattern 412 Fixed structure with telecommunication transmission 413 Electrode of package unit

第32頁 1233192 圖式簡單說明 414 貫通孔 415 貫通孔電極 416 第四絕緣膜層 500 第二封裝單元體 501 主晶片 502 第一絕緣膜層 503 第二絕緣膜層 504 第三絕緣膜層 505 電路保護層 506 主晶片之電極 507 第一微電子元件 508 第二微電子元件 509 充填物 510 微電子元件電極 511 電路圖案 512 具電訊傳遞之固著結構 513 封裝單元體之電極 514 貫通孔 600 第三封裝單元體 601 主晶片 602 第一絕緣膜層 603 第二絕緣膜層 604 第三絕緣膜層 605 電路保護層Page 32 1233192 Brief description of drawings 414 through hole 415 through hole electrode 416 fourth insulating film layer 500 second package unit 501 main chip 502 first insulating film layer 503 second insulating film layer 504 third insulating film layer 505 circuit Protective layer 506 Electrode of main chip 507 First microelectronic element 508 Second microelectronic element 509 Filler 510 Microelectronic element electrode 511 Circuit pattern 512 Fixed structure with telecommunication transmission 513 Electrode of package unit 514 Through hole 600 Third Package unit 601 Main wafer 602 First insulating film layer 603 Second insulating film layer 604 Third insulating film layer 605 Circuit protection layer

第33頁 1233192 圖式簡單說明 606 主晶片之電極 607 第一微電子元件 608 第二微電子元件 609 充填物 610 微電子元件電極 611 電路圖案 612 具電訊傳遞之固著結構 613 封裝單元體之電極 614 貫通子匕 700 第四封裝單元體 701 主晶片 702 第一絕緣膜層 703 第二絕緣膜層 704 第三絕緣膜層 705 電路保護層 706 主晶片之電極 707 第一微電子元件 708 第二微電子元件 709 密閉空間 710 微電子元件電極 711 電路圖案 712 具電訊傳遞之固著結構 713 封裝單元體之電極 714 貫通孔Page 33 1233192 Schematic description 606 Electrode of main chip 607 First microelectronic element 608 Second microelectronic element 609 Filler 610 Microelectronic element electrode 611 Circuit pattern 612 Fixed structure with telecommunication transmission 613 Electrode of package unit 614 Pass-through 700 Fourth package unit 701 Main chip 702 First insulating film layer 703 Second insulating film layer 704 Third insulating film layer 705 Circuit protection layer 706 Electrode of main chip 707 First microelectronic element 708 Second micro Electronic component 709 Closed space 710 Microelectronic component electrode 711 Circuit pattern 712 Fixed structure with telecommunication transmission 713 Package unit electrode 714 Through hole

1233192 圖式簡單說明 715 透明基板 801 電路保護層 802 基板 8 0 3 基板電極 804 具電訊傳遞之固著結構 901 電路保護層 902 基板 9 0 3 基板電極 904 具電訊傳遞之固著結構 1 0 0 1電路保護層 1 0 0 2基板 1 0 0 3基板電極 I 004具電訊傳遞之固著結構 II 0 1電路保護層 1102基板 11 0 3基板電極 1104具電訊傳遞之固著結構1233192 Schematic description 715 Transparent substrate 801 Circuit protection layer 802 Substrate 8 0 3 Substrate electrode 804 Fixed structure with telecommunications 901 Circuit protection layer 902 Substrate 9 0 3 Substrate electrode 904 Fixed structure with telecommunications 1 0 0 1 Circuit protection layer 1 0 0 2 substrate 1 0 0 3 substrate electrode I 004 fixed structure with telecommunication transmission II 0 1 circuit protection layer 1102 substrate 11 0 3 substrate electrode 1104 with fixed transmission structure

第35頁Page 35

Claims (1)

1233192 六、申請專利範圍 1 · 一種具複數個封聿 少包含： & 複數個封裝單元體，係 與其相同或相異之封裝 成封裝結構之主體· 單或複數個空穴區域， 述之空穴區域於主晶片 單或複數個微電子元件 主晶片之表面，並具電 片’其他單或複數個微 體間相互連通； 主晶片，係構成封裝單 作區域’而於該表面上 複數個凹穴空間，以承 充填物，填充於前述空 電子元件； 元體之立體堆疊電子封裝結構，至 利用其表面之複數個固著結構連接 單元體而形成立體堆疊結構，以構 形成於前述封裝單元體之内部，前 之表面形成早或複數個凹穴空間· ，配置於前述之空穴區域中^^述 訊傳遞結構使其電子訊號可與主晶 電子元件，以及相連接之封裝單元 元體之主體，其表面具電子電路工 非電子電路作用之區域可形成單或 載單或複數個微電子元件； 穴區域内以保護該空穴區域内之微 單或複數絕緣膜層’塗佈於前述主晶片之表面，用以 電性之絕緣； f或複數個固著結構，具電訊傳遞功能使固著之前述封裝 單兀體之電子訊號可與其他封裝單元體和基板相互連通。 單或複數個貫通孔，形成於前述之主晶片内，其内充填滿 具導電性質之金屬，用以連接主晶片上表面與下表面之電 路，以及連接前述之單或複數個微電子元件。 1233192 六、申請專利範圍 2裝圍第1Λ之電子封袭結構’其中所述之封 疊結構。 罨路連接位置以連接並形成堆 麥ί申：專，範圍第、項之電子封裝結構，其中所述之封 叙其内部之單或複數個微電子元件可為主動電子 組皮動電子元彳、光感測電子元件或以上電子元件之 _ 4電ΪΓί專利範圍第1項之電子封裝結構，其中所述之具 Ρ傳遞之固著結構，其可為踢、銀、金、銘、皱、銅、 :、铑、鎢或以上金屬材料合金或具導電性之材料的組 .如申請專利範圍第1項之電子封裝結構，其中所述之絕 緣膜層’可於其表面佈有電路圖案，以利上述主晶片表面 上與該空穴區域内之微電子元件，以及相鄰封裝單元體間 之電子訊號相互連通。 11申請專利範圍第1項之電子封裝結構，其中所述之空 二區域，其幾何形狀可包含：圓盤狀、橢圓盤狀、多邊形 平板狀、多邊形狀、頂面非平面之圓盤狀、頂面非平面之 橢圓盤狀、頂面非平面之不規則形圓盤狀或以上形狀之組 合。1233192 VI. Scope of patent application 1 · A type with multiple seals and less: & multiple packaging unit bodies, which are the same or different from the main body encapsulated into a packaging structure · single or multiple cavity areas, empty The cavity area is on the surface of the main wafer of the main wafer or a plurality of microelectronic components, and there is an electrical slice 'the other single or plural micro bodies are in communication with each other; the main wafer constitutes a package single operation area' and a plurality of the surface The cavity space is filled with the filling material and filled in the aforementioned empty electronic components; the three-dimensional stacked electronic packaging structure of the element body, to the three-dimensional stacked structure using a plurality of fixed structures on its surface to connect the unit body to form the aforementioned package Inside the unit body, the front surface forms an early or a plurality of cavity spaces. It is arranged in the aforementioned cavity area. The signal transmission structure allows the electronic signal to be connected to the main crystal electronic component and the packaged unit cells connected to it. The main body of the body, the surface of which has the function of electronic circuit and non-electronic circuit can form a single or a single load or a plurality of microelectronic components; within the cavity area The micro-single or multiple insulating film layers in the cavity area are coated on the surface of the aforementioned main wafer for electrical insulation; f or a plurality of fixing structures with a telecommunication transmission function for fixing the aforementioned packaging sheet The electronic signals of the body can communicate with other packaging unit bodies and substrates. A single or a plurality of through holes are formed in the aforementioned main wafer, and are filled with a conductive metal to connect the circuit between the upper surface and the lower surface of the main wafer, and the aforementioned single or plural microelectronic components. 1233192 VI. Scope of patent application 2 Enclose the structure described in “Electronic Sealing Structure 1” of 1Λ. The connection position of the road is connected to form and form a pile of wheat. The electronic package structure of the scope, item, and the single or multiple microelectronic components in the package can be active electronic components. , Photo-sensing electronic component or above__Electronic packaging structure of the first scope of the patent of the 4th electronic patent, the fixed structure with P-transmission described in the above, which can be kick, silver, gold, inscription, wrinkle, Copper,:, rhodium, tungsten or more metal material alloys or groups of conductive materials. For example, the electronic package structure of the scope of application for patents, wherein said insulating film layer can be provided with a circuit pattern on its surface, In order to facilitate the communication between the electronic signals on the surface of the main wafer and the microelectronic elements in the cavity region, and the adjacent packaging unit bodies. 11 The electronic package structure of the scope of application for the first item of the patent, wherein the geometrical shape of the empty two areas may include: disc shape, elliptical disc shape, polygonal flat plate shape, polygonal shape, disc shape with non-planar top surface, The top surface is non-planar elliptical disc shape, the top surface is non-planar irregular disc shape or a combination of the above shapes. 第37頁 1233192 六、申請專利範圍 7. 如申請專利範圍第1項之電子封裝結構，其中達成前述 單或複數個微電子元件之電訊傳遞結構，包括複數個佈於 主晶片表面之電極、前述之電路圖案、佈於每一微電子元 件之複數個微電子元件電極、複數個前述之固著結構、佈 於絕緣層内之單或複數個貫通孔或以上各項結構之組合。 8. 如申請專利範圍第1項之電子封裝結構，其中所述之單 或複數個貫通孔，其内部所充填之導電金屬可為錫、銀、 金、紹、鈹、銅、鎳、铑、鶴或以上金屬材料合金或具導 _ 電性之材料的組合。Page 37 1233192 6. Application scope of patent 7. For the electronic package structure of the first scope of application for patent, the telecommunication transmission structure of the single or multiple microelectronic components mentioned above is achieved, including a plurality of electrodes arranged on the surface of the main wafer, the aforementioned A circuit pattern, a plurality of microelectronic element electrodes arranged on each microelectronic element, a plurality of the aforementioned fixed structures, a single or a plurality of through holes arranged in an insulating layer, or a combination of the above structures. 8. According to the electronic package structure of the scope of patent application, the conductive metal filled in the single or plural through-holes mentioned above may be tin, silver, gold, shaw, beryllium, copper, nickel, rhodium, Crane or above metal material alloy or combination of conductive materials. 第38頁Page 38
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US8525320B2 (en) 2007-08-16 2013-09-03 Micron Technology, Inc. Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods

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US8847376B2 (en) * 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
TWI571595B (en) * 2015-11-16 2017-02-21 江昆淵 Omni-directional led lamps

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8525320B2 (en) 2007-08-16 2013-09-03 Micron Technology, Inc. Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods

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