CN101150118A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN101150118A
CN101150118A CNA2007101380366A CN200710138036A CN101150118A CN 101150118 A CN101150118 A CN 101150118A CN A2007101380366 A CNA2007101380366 A CN A2007101380366A CN 200710138036 A CN200710138036 A CN 200710138036A CN 101150118 A CN101150118 A CN 101150118A
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China
Prior art keywords
semiconductor chip
semiconductor
semiconductor device
chip
electrodes
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CNA2007101380366A
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English (en)
Chinese (zh)
Inventor
菊池卓
金本光一
宫崎忠一
盐月敏弘
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Renesas Technology Corp
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Renesas Technology Corp
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Publication of CN101150118A publication Critical patent/CN101150118A/zh
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    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
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    • H10W72/01331Manufacture or treatment of die-attach connectors using blanket deposition
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    • H10W72/547Dispositions of multiple bond wires
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    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
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    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
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    • H10W90/24Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
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    • H10W90/732Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
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    • H10W90/736Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
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  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
CNA2007101380366A 2006-09-21 2007-08-02 半导体装置 Pending CN101150118A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006255548 2006-09-21
JP2006255548A JP2008078367A (ja) 2006-09-21 2006-09-21 半導体装置

Publications (1)

Publication Number Publication Date
CN101150118A true CN101150118A (zh) 2008-03-26

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CNA2007101380366A Pending CN101150118A (zh) 2006-09-21 2007-08-02 半导体装置

Country Status (5)

Country Link
US (3) US7795741B2 (https=)
JP (1) JP2008078367A (https=)
KR (1) KR101397203B1 (https=)
CN (1) CN101150118A (https=)
TW (1) TWI419240B (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102969285A (zh) * 2011-09-01 2013-03-13 株式会社东芝 半导体装置及其制造方法
CN106102340A (zh) * 2015-04-29 2016-11-09 巴伦电子有限公司 利用印刷电路板的多裸片堆叠方法及利用其的半导体封装件
CN107301993A (zh) * 2017-06-08 2017-10-27 太极半导体(苏州)有限公司 一种增加非功能性芯片的封装结构及其制作工艺

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JP5164533B2 (ja) * 2007-11-14 2013-03-21 オンセミコンダクター・トレーディング・リミテッド 半導体モジュールおよび撮像装置
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JP5647312B2 (ja) * 2013-09-04 2014-12-24 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
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JP6766758B2 (ja) * 2017-06-15 2020-10-14 株式会社デンソー 半導体装置およびその製造方法
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US7923292B2 (en) 2011-04-12
US8518744B2 (en) 2013-08-27
US7795741B2 (en) 2010-09-14
KR101397203B1 (ko) 2014-05-20
US20110159641A1 (en) 2011-06-30
TWI419240B (zh) 2013-12-11
US20080251897A1 (en) 2008-10-16

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