JP2008078367A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2008078367A
JP2008078367A JP2006255548A JP2006255548A JP2008078367A JP 2008078367 A JP2008078367 A JP 2008078367A JP 2006255548 A JP2006255548 A JP 2006255548A JP 2006255548 A JP2006255548 A JP 2006255548A JP 2008078367 A JP2008078367 A JP 2008078367A
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Japan
Prior art keywords
semiconductor chip
semiconductor
semiconductor device
wiring board
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006255548A
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English (en)
Japanese (ja)
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JP2008078367A5 (https=
Inventor
Taku Kikuchi
卓 菊池
Koichi Kanemoto
光一 金本
Chuichi Miyazaki
忠一 宮崎
Toshihiro Shiotsuki
敏弘 塩月
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
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Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2006255548A priority Critical patent/JP2008078367A/ja
Priority to TW096124032A priority patent/TWI419240B/zh
Priority to CNA2007101380366A priority patent/CN101150118A/zh
Priority to US11/851,982 priority patent/US7795741B2/en
Priority to KR1020070095593A priority patent/KR101397203B1/ko
Publication of JP2008078367A publication Critical patent/JP2008078367A/ja
Publication of JP2008078367A5 publication Critical patent/JP2008078367A5/ja
Priority to US12/846,616 priority patent/US7923292B2/en
Priority to US13/044,525 priority patent/US8518744B2/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01331—Manufacture or treatment of die-attach connectors using blanket deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07141—Means for applying energy, e.g. ovens or lasers
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07521—Aligning
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
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    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
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    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/755—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a laterally-adjacent insulating package substrate, interpose or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass

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  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
JP2006255548A 2006-09-21 2006-09-21 半導体装置 Pending JP2008078367A (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2006255548A JP2008078367A (ja) 2006-09-21 2006-09-21 半導体装置
TW096124032A TWI419240B (zh) 2006-09-21 2007-07-02 Semiconductor device
CNA2007101380366A CN101150118A (zh) 2006-09-21 2007-08-02 半导体装置
US11/851,982 US7795741B2 (en) 2006-09-21 2007-09-07 Semiconductor device
KR1020070095593A KR101397203B1 (ko) 2006-09-21 2007-09-20 반도체 장치
US12/846,616 US7923292B2 (en) 2006-09-21 2010-07-29 Semiconductor device
US13/044,525 US8518744B2 (en) 2006-09-21 2011-03-09 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006255548A JP2008078367A (ja) 2006-09-21 2006-09-21 半導体装置

Publications (2)

Publication Number Publication Date
JP2008078367A true JP2008078367A (ja) 2008-04-03
JP2008078367A5 JP2008078367A5 (https=) 2009-08-27

Family

ID=39250550

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006255548A Pending JP2008078367A (ja) 2006-09-21 2006-09-21 半導体装置

Country Status (5)

Country Link
US (3) US7795741B2 (https=)
JP (1) JP2008078367A (https=)
KR (1) KR101397203B1 (https=)
CN (1) CN101150118A (https=)
TW (1) TWI419240B (https=)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010040955A (ja) * 2008-08-08 2010-02-18 Renesas Technology Corp 半導体装置及びその製造方法
JP2011029492A (ja) * 2009-07-28 2011-02-10 Mitsubishi Electric Corp 電力用半導体装置
JP2014003324A (ja) * 2013-09-04 2014-01-09 Renesas Electronics Corp 半導体集積回路装置の製造方法
JP2019004053A (ja) * 2017-06-15 2019-01-10 株式会社デンソー 半導体装置およびその製造方法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009021499A (ja) * 2007-07-13 2009-01-29 Toshiba Corp 積層型半導体装置
JP5164532B2 (ja) * 2007-11-14 2013-03-21 オンセミコンダクター・トレーディング・リミテッド 半導体モジュールおよび撮像装置
JP5164533B2 (ja) * 2007-11-14 2013-03-21 オンセミコンダクター・トレーディング・リミテッド 半導体モジュールおよび撮像装置
JP2010245383A (ja) * 2009-04-08 2010-10-28 Elpida Memory Inc 半導体装置および半導体装置の製造方法
KR20110006482A (ko) * 2009-07-14 2011-01-20 삼성전자주식회사 메모리 링크 아키텍쳐를 갖는 멀티 프로세서 시스템에 적합한 멀티 칩 패키지 구조
JP2013055150A (ja) * 2011-09-01 2013-03-21 Toshiba Corp 半導体装置及びその製造方法
JP5959097B2 (ja) * 2012-07-03 2016-08-02 ルネサスエレクトロニクス株式会社 半導体装置
CN103984012B (zh) * 2014-04-16 2016-06-29 刘豫宝 基于叠前高斯束深度偏移的绕射波场分离方法
KR101685545B1 (ko) * 2015-04-29 2016-12-12 주식회사 바른전자 인쇄회로기판을 이용한 멀티 다이 스태킹 방법 및 이를 이용한 반도체 패키지
KR102538175B1 (ko) 2016-06-20 2023-06-01 삼성전자주식회사 반도체 패키지
CN107301993A (zh) * 2017-06-08 2017-10-27 太极半导体（苏州）有限公司 一种增加非功能性芯片的封装结构及其制作工艺
JP2019165046A (ja) * 2018-03-19 2019-09-26 東芝メモリ株式会社 半導体装置およびその製造方法
US11723154B1 (en) * 2020-02-17 2023-08-08 Nicholas J. Chiolino Multiwire plate-enclosed ball-isolated single-substrate silicon-carbide-die package

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01235363A (ja) * 1988-03-16 1989-09-20 Hitachi Ltd 半導体装置
JPH08288455A (ja) * 1995-04-11 1996-11-01 Oki Electric Ind Co Ltd 半導体装置およびその製造方法
JP2001094046A (ja) * 1999-09-22 2001-04-06 Seiko Epson Corp 半導体装置
JP2001217383A (ja) * 2000-01-31 2001-08-10 Hitachi Ltd 半導体装置およびその製造方法
US20040007782A1 (en) * 2002-05-15 2004-01-15 Harry Hedler Connecting circuit devices and assemblies thereof
JP2004072009A (ja) * 2002-08-09 2004-03-04 Fujitsu Ltd 半導体装置及びその製造方法
JP2004071838A (ja) * 2002-08-06 2004-03-04 Renesas Technology Corp 半導体装置
US6753613B2 (en) * 2002-03-13 2004-06-22 Intel Corporation Stacked dice standoffs
JP2004221568A (ja) * 2002-12-27 2004-08-05 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
JP2004523912A (ja) * 2001-03-02 2004-08-05 クゥアルコム・インコーポレイテッド 混合アナログおよびデジタル集積回路
JP2005150478A (ja) * 2003-11-17 2005-06-09 Renesas Technology Corp マルチチップモジュール
JP2006041258A (ja) * 2004-07-28 2006-02-09 Renesas Technology Corp ゲッタリング層を有する半導体チップとその製造方法
WO2006017224A2 (en) * 2004-07-13 2006-02-16 Chippac, Inc. Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
JP2006164302A (ja) * 2006-01-17 2006-06-22 Renesas Technology Corp 不揮発性記憶装置
JP2006332161A (ja) * 2005-05-24 2006-12-07 Seiko Epson Corp 半導体装置および半導体装置の製造方法
JP2007096071A (ja) * 2005-09-29 2007-04-12 Toshiba Corp 半導体メモリカード
JP2007214305A (ja) * 2006-02-09 2007-08-23 Denso Corp 半導体装置

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US753613A (en) * 1903-10-26 1904-03-01 George W Mcgill Spring-clip.
US5502667A (en) * 1993-09-13 1996-03-26 International Business Machines Corporation Integrated multichip memory module structure
US5604377A (en) * 1995-10-10 1997-02-18 International Business Machines Corp. Semiconductor chip high density packaging
JP3822768B2 (ja) * 1999-12-03 2006-09-20 株式会社ルネサステクノロジ Ｉｃカードの製造方法
KR100610916B1 (ko) * 2000-06-12 2006-08-09 앰코 테크놀로지 코리아 주식회사 반도체패키지
KR100600176B1 (ko) 2000-09-19 2006-07-12 앰코 테크놀로지 코리아 주식회사 반도체패키지
JP3839323B2 (ja) * 2001-04-06 2006-11-01 株式会社ルネサステクノロジ 半導体装置の製造方法
US6831370B2 (en) * 2001-07-19 2004-12-14 Micron Technology, Inc. Method of using foamed insulators in three dimensional multichip structures
US6569709B2 (en) * 2001-10-15 2003-05-27 Micron Technology, Inc. Assemblies including stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween, packages including the assemblies, and methods
KR20030046794A (ko) * 2001-12-06 2003-06-18 삼성전자주식회사 다중 적층 칩 패키지
US6867500B2 (en) * 2002-04-08 2005-03-15 Micron Technology, Inc. Multi-chip module and methods
JP4471563B2 (ja) 2002-10-25 2010-06-02 株式会社ルネサステクノロジ 半導体装置の製造方法
JP4068974B2 (ja) * 2003-01-22 2008-03-26 株式会社ルネサステクノロジ 半導体装置
US7378725B2 (en) * 2004-03-31 2008-05-27 Intel Corporation Semiconducting device with stacked dice
DE102004036909B4 (de) * 2004-07-29 2007-04-05 Infineon Technologies Ag Halbleiterbasisbauteil mit Verdrahtungssubstrat und Zwischenverdrahtungsplatte für einen Halbleiterbauteilstapel sowie Verfahren zu deren Herstellung
JP4651359B2 (ja) * 2004-10-29 2011-03-16 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR20060054811A (ko) 2004-11-16 2006-05-23 삼성전자주식회사 표시장치용 구동칩과, 이를 갖는 표시장치
TWI250597B (en) * 2004-12-31 2006-03-01 Chipmos Technologies Inc Method for manufacturing multi-chip package having encapsulated bond-wires between stack chips
JP5077977B2 (ja) 2005-05-30 2012-11-21 ルネサスエレクトロニクス株式会社 液晶ディスプレイ駆動制御装置及び携帯端末システム
JP4726640B2 (ja) * 2006-01-20 2011-07-20 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01235363A (ja) * 1988-03-16 1989-09-20 Hitachi Ltd 半導体装置
JPH08288455A (ja) * 1995-04-11 1996-11-01 Oki Electric Ind Co Ltd 半導体装置およびその製造方法
JP2001094046A (ja) * 1999-09-22 2001-04-06 Seiko Epson Corp 半導体装置
JP2001217383A (ja) * 2000-01-31 2001-08-10 Hitachi Ltd 半導体装置およびその製造方法
JP2004523912A (ja) * 2001-03-02 2004-08-05 クゥアルコム・インコーポレイテッド 混合アナログおよびデジタル集積回路
US6753613B2 (en) * 2002-03-13 2004-06-22 Intel Corporation Stacked dice standoffs
US20040007782A1 (en) * 2002-05-15 2004-01-15 Harry Hedler Connecting circuit devices and assemblies thereof
JP2004071838A (ja) * 2002-08-06 2004-03-04 Renesas Technology Corp 半導体装置
JP2004072009A (ja) * 2002-08-09 2004-03-04 Fujitsu Ltd 半導体装置及びその製造方法
JP2004221568A (ja) * 2002-12-27 2004-08-05 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
JP2005150478A (ja) * 2003-11-17 2005-06-09 Renesas Technology Corp マルチチップモジュール
WO2006017224A2 (en) * 2004-07-13 2006-02-16 Chippac, Inc. Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
JP2006041258A (ja) * 2004-07-28 2006-02-09 Renesas Technology Corp ゲッタリング層を有する半導体チップとその製造方法
JP2006332161A (ja) * 2005-05-24 2006-12-07 Seiko Epson Corp 半導体装置および半導体装置の製造方法
JP2007096071A (ja) * 2005-09-29 2007-04-12 Toshiba Corp 半導体メモリカード
JP2006164302A (ja) * 2006-01-17 2006-06-22 Renesas Technology Corp 不揮発性記憶装置
JP2007214305A (ja) * 2006-02-09 2007-08-23 Denso Corp 半導体装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010040955A (ja) * 2008-08-08 2010-02-18 Renesas Technology Corp 半導体装置及びその製造方法
JP2011029492A (ja) * 2009-07-28 2011-02-10 Mitsubishi Electric Corp 電力用半導体装置
JP2014003324A (ja) * 2013-09-04 2014-01-09 Renesas Electronics Corp 半導体集積回路装置の製造方法
JP2019004053A (ja) * 2017-06-15 2019-01-10 株式会社デンソー 半導体装置およびその製造方法

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US8518744B2 (en) 2013-08-27
US7795741B2 (en) 2010-09-14
KR101397203B1 (ko) 2014-05-20
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US20080251897A1 (en) 2008-10-16

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