CN101013700A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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Abstract
本发明涉及半导体器件及其制造方法。本发明提供一种CMOS半导体器件,该器件具有双功函数金属栅极结构,所述结构利用能够实现对PMOS和NMOS器件的独立功函数控制并且显著降低或消除对栅极电介质可靠性的影响的制造技术形成。
Description
技术领域
本发明总体上涉及具有双功函数金属栅极结构的CMOS半导体器件,以及制造为PMOS和NMOS晶体管提供分开的栅极功函数控制的双金属栅极叠层结构的方法。
背景技术
通常,利用彼此协同工作的成对的p沟道MOS(PMOS)和n沟道MOS(NMOS)晶体管来形成互补金属氧化物硅(CMOS)半导体集成电路。与仅利用PMOS晶体管形成的半导体器件相比,CMOS半导体器件具有更高的工作效率和速度。此外,CMOS技术具有良好的微缩特性(scalingcharacteristics),其允许开发具有越来越高的集成密度的半导体集成电路器件。由于这些和其他原因,CMOS技术通常用来制造用于高集成度和高性能应用的半导体器件。然而,随着CMOS技术按比例缩小至纳米级及其以下,也必须不断地按比例减小电源电压和MOS晶体管阈值电压以保持高性能和高可靠性。CMOS晶体管的迅速的按比例缩小(downscaling)已经对具有良好控制的和可再现的功函数/阈值电压的栅极叠层结构的发展提出了技术挑战。
常规的CMOS制造技术已经应用了多晶硅(poly-Si)栅电极工艺技术。图1A示出了用于MOS器件的常规CMOS栅极结构。图1A示出了形成在半导体衬底11上的栅极结构10。栅极结构10包括多晶硅(poly-Si)栅电极10a以及置于栅电极10a和半导体衬底11之间的栅极介电层10b。在常规的栅极叠层设计中,栅极介电层10b例如由热生长氧化硅形成。常规栅极结构10不足以满足纳米级CMOS技术的性能需求。例如,在纳米级设计规则中,多晶硅栅电极10a的接触面积显著缩小,由此需要栅极介电层10b-比如氧化硅-的厚度减小从而保持适当的器件性能所需的栅极电容。
当利用超薄栅极介电层来形成多晶硅栅极叠层结构(比如图1A中所示的)时,器件性能可能会由于多晶硅栅极损耗(即PDE(poly-gate depletion)效应)、高栅极电阻(更小的多晶栅极)、增大的栅极电介质隧穿泄漏电流以及其他公知问题而显著劣化。特别是,由于多晶硅栅极损耗,在多晶硅栅电极10a和薄的栅极介电层10b之间形成了薄的损耗层(depletion layer),这增大了等效栅极氧化物厚度,导致总栅极电容的减小。
对于多晶硅栅极叠层,为了克服与超薄栅极介电层相关的问题,考虑将高K栅极介电材料用作多晶硅栅极叠层的栅极介电层,这在相同有效氧化物厚度(same effective oxide thickness)下允许更厚的栅极介电层。这种方法对于消除栅极电介质隧穿泄漏是有效的,但在将高K介电材料与多晶硅栅电极界面连接时存在兼容性问题。例如,在没有扩散阻挡层(diffusion barrier)时,高K介电层中的氧化剂能容易地扩散到多晶硅栅电极中,在界面处形成氧化硅层,导致减小的栅极电容。而且,利用与多晶硅栅电极界面连接的高K介电层形成的栅极叠层结构不能克服PDE效应。
用于纳米级CMOS器件的先进栅极叠层解决方案应用了高K栅极介电层和金属栅电极以消除栅极损耗问题、栅极电介质隧穿泄漏问题、以及电容等效厚度按比例缩小中的限制的问题。图1B示出了形成在半导体衬底21上的常规CMOS栅极结构20。栅极结构20包括多晶硅栅电极20a、栅极介电层20b以及置于多晶硅电极20a和栅极介电层20b之间的金属栅极层20c。在某些常规设计中,对于PMOS和NMOS栅极叠层两者,使用相同的金属性材料(metallic material)来形成金属栅极层20c。尽管金属栅极层20c对于防止栅极损耗效应以及从多晶硅栅极到栅极介电层之中的掺杂剂渗透是有效的,但此方法的缺点在于PMOS和NMOS晶体管的阈值电压主要由插入的金属栅极层20c的功函数确定。
理想地,对于体硅(bulk-Si)NMOS和PMOS晶体管,具有对应于Si的导带边缘和价带边缘的功函数的金属栅极分别是最佳的。然而,单功函数金属栅极技术必须在NMOS和PMOS晶体管的最佳功函数之间进行平衡。例如,用于NMOS和PMOS晶体管的金属栅极层可以由具有在半导体层的导带和价带能级之间的费米能级的金属形成。此方法的缺点在于,晶体管的阈值电压Vth增大到不能用沟道反掺杂技术有效降低的水平。因此,单功函数金属栅极CMOS技术对于满足阈值电压减小的需求是无效的,该需求是实现低功耗和高速器件性能所需要的。
因此,已经提出了双功函数金属栅极CMOS技术,其中NMOS和PMOS栅极叠层的栅极金属层由其费米能级或功函数对应Si的导带边缘和价带边缘的不同的金属形成。例如,NMOS栅极叠层中的金属层可以由其费米能级与n+掺杂硅层的导带能级相似的金属形成,而PMOS栅极叠层中的金属层可以由其费米能级与p+掺杂硅层的价带能级相似的金属形成。
双功函数金属栅极技术的发展已经对金属的选择提出了技术挑战,所述金属具有允许单独控制NMOS和PMOS栅极功函数且适于与CMOS工艺技术整合的材料特性。作为具体示例,对于双金属栅极制造工艺,应当考虑用于形成栅极叠层的栅极金属/电介质材料的材料特性,从而实现栅极功函数的严格控制和可再现性。而且,应当考虑器件制造所用的薄膜工艺技术的类型,从而防止对栅极介电层的损坏,该损坏会劣化电性能或者会降低栅极叠层结构的可靠性和预期寿命。
例如,常规双金属栅极叠层制造工艺包括在半导体衬底上形成栅极介电层并在栅极介电层上形成第一金属层,其中选择所述第一金属层以设定用于例如NMOS栅极的功函数。之后,构图第一金属层从而去除第一金属层的在PMOS区域中的部分。然后在PMOS区域中暴露的栅极介电层之上形成第二金属层,其中选择所述第二金属层以设定用于例如PMOS栅极的功函数。然后蚀刻第二金属层以去除第二金属层的在NMOS区域中的形成在第一金属层之上的部分。在这种工艺中,当蚀刻第一金属层时,PMOS有源区中的栅极介电层用作蚀刻停止物。因此,PMOS叠层中的栅极介电层会被工艺步骤损坏。
在另一常规方法中,在构图第一金属层(金属蚀刻工艺)之后,去除该栅极介电层并形成新的栅极介电层(即去除可能已损坏的栅极介电层)。这种方法对于改善栅极介电层的质量是有效的,但会在新栅极介电层的制造过程中导致对第一金属层的损坏。例如,当应用氧化工艺以热生长用于栅极电介质的氧化物层时,可能氧化第一金属层。而且,当利用薄膜沉积技术(例如PVD)形成新介电层时,在等离子体工艺过程中会损伤有源硅和栅极介电层的暴露区域。
发明内容
总体上,本发明的示例性实施例包括具有双功函数金属栅极结构的CMOS半导体器件以及制造双金属栅极叠层结构的方法,所述双金属栅极叠层结构为PMOS和NMOS晶体管提供了双栅极功函数控制。根据本发明的示例性制造技术考虑了材料特性和薄膜加工技术,从而显著减小或者消除了对栅极电介质可靠性的影响。
在本发明的一个示例性实施例中,一种半导体器件包括半导体衬底,所述半导体衬底具有形成在所述半导体衬底前侧上的双栅极CMOS器件。所述双栅极CMOS器件包括PMOS器件和NMOS器件。所述PMOS器件具有第一栅极叠层,所述第一栅极叠层由形成在所述半导体衬底上的栅极绝缘体层、形成在所述栅极绝缘体层上的第一导电层、形成在所述第一导电层上的第二导电层和形成在所述第二导电层上的第三导电层形成。所述NMOS器件具有第二栅极叠层,所述第二栅极叠层包括形成在所述半导体衬底上的栅极绝缘体层、形成在所述栅极绝缘体层上的第一导电层和形成在所述第一导电层上的第二导电层。
在一个示例性实施例中,所述第一和第二栅极叠层的第二导电层由不同的导电材料形成。在另一实施例中,所述第一和第二栅极叠层的第一导电层由具有基本相同的厚度的相同的导电材料形成。例如,所述第一和第二栅极叠层的第一导电层由TaN或TiN形成。所述第一和第二栅极叠层的第一导电层的厚度和导电材料被选择以调整所述NMOS器件的功函数。所述第一栅极叠层的第二导电层的厚度和导电材料被选择以调整所述PMOS器件的功函数。
在一个示例性实施例中,所述第一栅极叠层的第一、第二和第三导电层由不同的导电材料形成。例如,所述第一导电层优选由相对于HF蚀刻溶液其蚀刻速率比形成所述第一栅极叠层的第二和第三导电层的不同材料的蚀刻速率更小的材料形成。这使得能够在制造过程期间去除所述第二和第三层的在第二栅极叠层区域中的部分。例如,所述PMOS器件的第一栅极叠层的第一、第二和第三导电层分别由TaN、AlN和HfN形成。
在另一示例性实施例中,所述第一和第二栅极叠层的栅极绝缘层由介电常数在约8及更大的范围内的电介质材料形成。可以在所述栅极绝缘层和所述半导体衬底之间插入界面层以防止所述高K电介质材料和所述硅衬底之间的反应。所述第一和第二栅极叠层的栅极绝缘层可以由氧化铪、铪硅氧化物(hafnium silicon oxide)、氧化镧、氧化锆、锆硅氧化物(zirconiumsilicon oxide)、氧化钽、氧化钇或氧化铝形成。
由以下对示例性实施例的详细描述,本发明的这些和其他示例性实施例、方面、目的、特征及优点将变得明显,该详细描述将结合附图得以说明。
附图说明
图1A是MOSFET晶体管的常规栅极叠层结构的截面示意图;
图1B是MOSFET晶体管的另一常规栅极叠层结构的截面示意图;
图2是根据本发明一示例性实施例的具有双功函数金属栅极结构的CMOS晶体管对的截面示意图;
图3A-3E是图2的CMOS晶体管对在根据本发明一示例性实施例的CMOS制造工艺的各阶段的截面示意图;
图4A至4B是作为NMOS和PMOS器件的栅极金属层厚度的函数的阈值电压实验数据的示例性图表。
具体实施方式
现将参照附图更充分地描述本发明的示例性实施例,其中应理解的是,为了清楚起见,夸大了层和区域的厚度和尺寸。还应进一步理解的是,当某层被描述为在另一层或衬底“上”或“之上”时,该层可以直接在该另一层或衬底上,或者也可以存在插入层。此外,全部附图中所使用的类似的附图标记表示具有相同或相似功能的元件。
图2是根据本发明一示例性实施例的具有双功函数金属栅极叠层结构的CMOS晶体管对的截面示意图。更具体而言,图2示出了半导体器件100,半导体器件100包括具有NMOS晶体管区域101a和PMOS晶体管区域101b的半导体衬底101。NMOS晶体管区域101a包括NMOS晶体管,该NMOS晶体管包括:形成在p掺杂器件阱中的n掺杂源极/漏极扩散区170;以及包括栅极介电层103a和栅电极141的栅极叠层结构140。栅电极141包括形成在栅极介电层103a上的第一导电层111a以及形成在第一导电层111a上的第二导电层120a。可选的界面层102a置于栅极介电层103a和衬底之间。
PMOS晶体管区域101b包括PMOS晶体管,该PMOS晶体管包括:形成在n掺杂器件阱中的p掺杂漏极/源极扩散区171;以及包括栅极介电层103b和栅电极151的栅极叠层结构150。栅电极151包括形成在栅极介电层103b之上的第一导电层111b、第二导电层113b、第三导电层115b和第四导电层120b。各NMOS和PMOS晶体管的栅极结构140和150具有形成在侧壁表面上的各自的绝缘间隙壁(spacer)160a、160b,以及形成在各自的栅极叠层140、150的顶表面上的绝缘盖层130a、130b。
在图2的CMOS晶体管的一个示例性实施例中,NMOS栅极结构140包括金属插入栅极层(metal-inserted gate layer),该金属插入栅极层包括介于栅极介电层103a和多晶硅层120a之间的第一导电层111a(单金属层)。可选的界面层102b置于栅极介电层103b和衬底之间。PMOS栅极结构150包括金属插入栅极层,该金属插入栅极层包括介于栅极介电层103b和多晶硅层120b之间的三个导电金属层111b、113b、115b的叠层。金属层111a由第一金属性材料和厚度形成,从而NMOS栅极具有与p掺杂硅的功函数类似的功函数,并控制NMOS晶体管的阈值电压。PMOS栅极叠层150的金属插入层由三个金属层111b、113b、115b形成,所述三个金属层的材料和厚度被选择以提供与n掺杂硅的功函数相同或类似的PMOS有效功函数并控制PMOS器件的阈值电压。
已考虑了各种电介质/金属材料系统以用于构建栅极叠层140和150,从而实现被良好控制的双栅极功函数。例如,已经考虑了作为插入金属的TaN对CMOS晶体管的阈值电压特性的影响。总体上,NMOS晶体管的阈值电压作为TaN栅极层厚度增加的函数而显著增大,然而PMOS晶体管的阈值电压随着TaN栅极层厚度增大而轻微减小并达到稳定。例如,以TaN作为插入金属且以HfO2作为栅极介电层的NMOS和PMOS晶体管的阈值电压的结果分别示于图4A和4B中。如图所示,可以认为,将TaN薄层(10埃)用于NMOS器件和将厚TaN(40埃)用于PMOS器件,一般能够实现NMOS和PMOS晶体管各自的约0.55和-0.6的阈值电压。
已进一步确定的是,例如AlN的材料金属栅极层能够进一步减小PMOS晶体管的阈值电压。例如,对于图4B所示的以TaN作为插入金属(40埃厚)以及HfO2作为栅极介电层的PMOS晶体管,通过在两个厚度为20埃的TaN层(或具有与TaN类似特性的金属层)之间插入AlN(或具有相似特性的材料)的薄层(例如10埃),能够实现PMOS器件的阈值电压的进一步减小。
在一个示例性实施例中,形成第一导电层111从而为NMOS栅电极提供约4.0eV至约4.4eV的功函数。第一导电层111可以由例如W、Mo、Ti、Ta、Al、Hf或Zr的金属,或者这些金属的氮化物,或者掺了Al或Si的这些金属的氮化物形成。更具体而言,第一导电层111a可以由具有适当功函数的如TiN或TaN的金属性氮化物材料形成,以设定NMOS器件的阈值电压。
此外,在本发明的一个示例性实施例中,导电层111b、113b、115b的叠层用被选择从而对于PMOS栅电极确定约4.7eV至约5.1eV的PMOS栅电极有效功函数的导电材料和厚度形成。更具体而言,假定第一导电层111b的材料和厚度被选定从而确定了NMOS栅电极的功函数(栅极叠层140的第一导电层111a具有与n型硅的功函数相似的适当的功函数),则设置第二导电层113b以利用具有适当功函数的金属来调整PMOS栅极150的功函数,从而有效增大PMOS栅电极的功函数。
第二导电层113b可以由例如Al、La、Y的金属,或者这些金属的氧化物或氮化物形成。第三导电层115b用进一步降低PMOS晶体管阈值电压的导电材料和厚度形成。第三导电层115b可以由与第一导电层111b的材料相同或相似的材料形成。例如,第三导电层可以由W、Mo、Ti、Ta、Al、Hf或Zr,或者这些金属的氮化物,或者掺Al或Si的这些金属的氮化物形成。
在本发明的一个示例性实施例中,对于其中NMOS栅极叠层140由高k介电层/薄TaN金属层/多晶硅栅电极形成且PMOS栅极叠层150由高k介电层/薄TaN金属层/薄AlN层/薄HfN层/多晶硅栅电极形成的CMOS晶体管,能够获得双功函数控制。在此示例性实施例中,PMOS栅极的第一、第二和第三导电层111b、113b、115b分别由不同的导电材料TaN(或TiN)、AlN(或AlO)和HfN(或TaN)形成。TaN和HfN层具有为PMOS器件提供相对稳定的阈值电压的有效厚度,而插入的AlN层提供了功函数调整从而进一步可控地减小PMOS器件的阈值电压。
在本发明的其他示例性实施例中,CMOS晶体管可以被构建为具有一NMOS栅极结构,该结构具有插入在栅极介电层和多晶硅层之间的包括三个导电金属层的叠层的金属插入栅极层。可以利用三个金属层来形成NMOS栅极叠层的金属插入层,所述三个金属层具有为提供与p掺杂硅的功函数相同或相似的NMOS有效功函数且控制PMOS器件的阈值电压而选取的材料和厚度。此外,PMOS栅极结构可以包括金属插入栅极层,所述金属插入栅极层包括插入在栅极介电层和多晶硅层之间的第一导电层(单金属层),其中该金属层优选用第一金属性材料和厚度形成,使得PMOS栅极具有与n掺杂硅的功函数相似的功函数,并控制PMOS晶体管的阈值电压。
应理解的是,可以根据应用和所需的功函数控制来改变用于形成栅极叠层的各种材料,并且以上叠层结构仅仅是示例性的。此外,可以根据兼容性问题(例如栅极层界面处的相互作用)和所采用的制造工艺来改变用于形成栅极层的材料。
图3A至3E是示意性截面图,示出根据本发明一示例性实施例的制造双功函数金属栅极CMOS半导体器件的方法。图3A示出初始工艺步骤,其以体半导体衬底101开始,并利用公知技术形成了NMOS晶体管区101a和PMOS晶体管区101b,NMOS晶体管区101a和PMOS晶体管区101b包括硅衬底101的表面中的各自的p掺杂器件阱和n掺杂器件阱(即有源区)。例如,可以利用浅槽隔离(STI)方法或硅的局部氧化(LOCOS)来形成隔离区以界定NMOS有源区101a和PMOS有源区101b,并利用离子注入技术掺杂有源区从而形成所需的n掺杂和p掺杂器件阱。
之后,可以在衬底101之上形成可选的界面层102,并在界面层102上形成栅极介电层103。在一个实施例中,栅极介电层103可以是通过热氧化工艺形成的氧化硅。在另一实施例中,栅极介电层103可以是通过氮气氛中的热处理工艺形成的氮化硅层。当栅极介电层103由氧化硅或氮化硅形成时,不需要界面层102。当由氧化硅或氮化硅形成时,栅极介电层103优选形成为具有约10埃至约60埃范围内的厚度。
当栅极介电层103由高k电介质材料形成时,优选形成界面层102,从而防止栅极电介质材料和硅衬底101之间的反应。可以通过形成厚度约小于1.5nm的薄界面层的包括臭氧气体和臭氧化液体(ozonized liquid)的清洁工艺来形成界面层102。
栅极介电层103可以由高k电介质材料形成,所述高k电介质材料具有比氧化硅的相对介电常数高的相对介电常数。例如,高k介电层103可以由具有8或更高介电常数的材料形成,比如氧化铪、铪硅氧化物、氧化镧、氧化锆、锆硅氧化物、氧化钽、氧化钛、GdO、氧化钇或氧化铝,硅酸盐,或者其任何组合。可以用公知的沉积技术来形成高k栅极介电层103,比如CVD、PVD或ALD。
为了高k介电层103的致密化,可以在具有N2、NO、N2O、O2或HNH3气体的环境下以及约750℃至约1050℃的温度下,包括N2、NO、N2O、O2或HNH3气体,执行沉积后退火(PDA)工艺。可以由介电常数在约8或更大的范围内的电介质材料来形成栅极介电层103。栅极介电层103的厚度根据用于形成栅极介电层103的高k电介质材料的相对介电常数而改变。例如,高k介电层的厚度可以在约10埃至约200埃的范围内。
接着,参照图3B,执行一系列沉积工艺,从而在栅极介电层103上形成第一导电层111,在第一导电层111上形成第二导电层113,在第二导电层113上形成第三导电层115。导电层111、113、115用以下金属性材料和厚度形成,该金属性材料和厚度被选择,从而确定NMOS和PMOS栅电极的双功函数,同时使得能够利用得以良好控制的工艺步骤来形成栅极叠层从而消除或显著减轻制造过程中对栅极叠层的损伤。
在本发明的一个示例性实施例中,第一导电层111用被选取以确定NMOS栅电极的功函数(这确定了NMOS晶体管的阈值电压)的导电材料和厚度形成。在一个示例性实施例中,第一导电层111被形成,从而提供NMOS栅电极的约4.0eV至约4.4eV的功函数。第一导电层111可以由如W、Mo、Ti、Ta、Al、Hf或Zr的金属,或者这些金属的氮化物,或者掺Al或Si的这些金属的氮化物形成。具体而言,第一导电层111可以由例如TiN或TaN的金属性氮化物材料形成,对于为如下所述的后续蚀刻工艺提供相对于第二导电层113和第三导电层115的蚀刻选择性,它们是优选的。第一导电层111优选形成为具有约5埃至约60埃范围内的厚度。
此外,在本发明的一个示例性实施例中,导电层111、113、115的叠层用被选取以确定PMOS栅电极的有效功函数(这确定了PMOS晶体管的阈值电压)的导电材料和厚度形成。在一个示例性实施例中,导电层111、113、115的叠层被形成,从而提供PMOS栅电极的约4.7eV至约5.1 eV的有效功函数。具体而言,假定选取第一导电层111从而确定了NMOS栅电极的功函数(第一导电层111具有与n型硅的功函数相似的适当的功函数),则用具有适当功函数的金属制备第二导电层113以调整PMOS栅极的功函数,从而有效增大PMOS栅电极的功函数以提供与p型硅的功函数相似的功函数。如上所述,第二导电层113可以由氧化硅、氮化硅、或者如Al、La、Y的金属、或者这些金属的氧化物或氮化物形成。依据所使用的材料,第二导电层113优选形成为具有约1埃至约30埃范围内的厚度。
此外,在本发明的一个示例性实施例中,第三导电层115用进一步降低PMOS晶体管的阈值电压的导电材料和厚度形成。第三导电层115可以由与第一导电层111的材料相同或相似的材料形成。例如,第三导电层可以由W、Mo、Ti、Ta、Al、Hf或Zr,或者这些金属的氮化物,或者掺Al或Si的这些金属的氮化物形成。
参照图3C,在第三导电层115上形成光致抗蚀剂图案117,以暴露NMOS区域101a并覆盖PMOS区域101b。然后第三导电层115和第二导电层113被顺序蚀刻并从NMOS区域101a去除。可以利用防止对金属和栅极介电层的损伤的蚀刻技术来执行该蚀刻工艺。例如,在本发明的一个示例性实施例中,选择第一导电层111的材料,使其具有比形成第二导电层113和第三导电层115的材料的蚀刻速率小的蚀刻速率。
作为具体示例,可以使用采用HF溶液的湿法蚀刻工艺来执行该蚀刻工艺,其中对于HF溶液的第一导电层111的蚀刻速率小于第二导电层113和第三导电层115的蚀刻速率。在这点上,利用第一导电层111作为蚀刻停止物用HF湿法蚀刻可以容易地去除第二导电层113和第三导电层115,同时避免了对第一导电层111的蚀刻损伤,并避免了对NMOS栅极介电层103a的损伤(由于其在蚀刻步骤期间未暴露)。
例如,由TaN或TiN形成的栅极层不能溶解在200∶1的HF溶液中,但由例如HfN和AlN的材料形成的栅极层在这样的HF溶液中是易溶解的。在这点上,假定第一导电层111由TaN形成,第二导电层113由AlN形成,且第三导电层115由HfN形成,则AlN和HfN第二和第三导电层的在NMOS区域101a中的部分可以被容易地蚀刻掉(高蚀刻速率),从而暴露TaN第一导电层111,而不会蚀刻或损伤第一导电层111。
接着,参照图3D,利用公知技术去除光致抗蚀剂图案117。例如,可以利用O2气氛下、或者H2、N2、NH3或He气氛下的灰化工艺来去除光致抗蚀剂图案117。在非O2气氛下,可以产生等离子体并且可以添加比如CF4的氟化气体以增大光致抗蚀剂图案117的去除速率。非O2灰化工艺对于避免对栅极介电层103的暴露部分的劣化或损伤是有利的。
接着,在衬底101之上形成另一层导电材料120。例如,该层导电材料120可以是多晶硅、金属氧化物、金属氮化物、硅化物或任何适合的金属。导电材料120用于形成NMOS栅极叠层140的第三导电层120a以及PMOS栅极叠层150的第四导电层120b(图2)。依据所使用的材料,可以利用公知技术沉积该层导电材料120,然后利用公知技术对其进行平坦化。
接着,利用公知技术沉积硬掩模层130并对其构图以形成掩模图案130a、130b,所述掩模图案130a、130b分别在NMOS区域101a和PMOS区域101b中界定了栅极叠层区域。例如,可以利用例如CVD(化学气相沉积)或ALD(原子层沉积)由氮化硅或其他适合的绝缘材料形成硬掩模层130,随后利用公知的光刻方法对其构图。之后,利用掩模图案130a、130b作为蚀刻掩模执行各向异性蚀刻工艺,从而向下蚀刻至衬底101的表面并形成栅极叠层结构140和150,如图3E所示。之后,可以使用公知的工艺步骤形成用于栅极叠层140、150的侧壁间隙壁160a、160b、以及用于NMOS和PMOS晶体管的漏极-源极扩散区170、171。
尽管此处已参照附图描述了示例性实施例,但应理解的是,本发明不限于此处所描述的示例性实施例,在不偏离本发明的范围或精神的前提下,本领域普通技术人员可以容易地构想各种其他的变化和修改。所有这些变化和修改包括于所附权利要求限定的本发明的范围之内。
Claims (40)
1.一种半导体器件,包括:
半导体衬底,所述半导体衬底具有形成在所述半导体衬底上的双栅极CMOS器件,所述双栅极CMOS器件包括PMOS器件和NMOS器件,
其中所述PMOS器件具有第一栅极叠层,所述第一栅极叠层包括:
形成在所述半导体衬底上的栅极绝缘体层;
形成在所述栅极绝缘体层上的第一导电层;
形成在所述第一导电层上的第二导电层;以及
形成在所述第二导电层上的第三导电层,
其中所述NMOS器件具有第二栅极叠层,所述第二栅极叠层包括:
形成在所述半导体衬底上的栅极绝缘体层;
形成在所述栅极绝缘体层上的第一导电层;以及
形成在所述第一导电层上的第二导电层,
其中所述第一和第二栅极叠层的第二导电层由不同的导电材料形成。
2.根据权利要求1所述的半导体器件,其中所述第一和第二栅极叠层的第一导电层由相同的导电材料形成并具有基本相同的厚度。
3.根据权利要求2所述的半导体器件,其中所述第一和第二栅极叠层的第一导电层由金属性氮化物形成。
4.根据权利要求3所述的半导体器件,其中所述第一和第二栅极叠层的第一导电层由TaN或TiN形成。
5.根据权利要求2所述的半导体器件,其中所述第一和第二栅极叠层的第一导电层的厚度和导电材料被选择从而调整所述NMOS器件的功函数。
6.根据权利要求2所述的半导体器件,其中所述第一栅极叠层的第二导电层的厚度和导电材料被选择从而调整所述PMOS器件的功函数。
7.根据权利要求1所述的半导体器件,其中所述第一栅极叠层的第一和第二导电层由不同的金属性氮化物材料形成。
8.根据权利要求7所述的半导体器件,其中所述金属性氮化物材料包括TiN、TaN或A1N。
9.根据权利要求1所述的半导体器件,其中所述第一栅极叠层的第一、第二和第三导电层由不同的导电材料形成。
10.根据权利要求9所述的半导体器件,其中所述第一导电层由相对于HF蚀刻溶液其蚀刻速率比形成所述第一栅极叠层的第二和第三导电层的不同材料的蚀刻速率小的材料形成。
11.根据权利要求10所述的半导体器件,其中所述PMOS器件的第一栅极叠层的第一、第二和第三导电层分别由TaN、AlN和HfN形成。
12.根据权利要求10所述的半导体器件,其中所述PMOS器件的第一栅极叠层的第一、第二和第三导电层分别由HfN、AlN和TaN形成。
13.根据权利要求1所述的半导体器件,其中所述第一和第二栅极叠层的栅极绝缘层由介电常数在约8及更大的范围内的电介质材料形成。
14.根据权利要求13所述的半导体器件,还包括插入在所述栅极绝缘层和所述半导体衬底之间的界面层。
15.根据权利要求13所述的半导体器件,其中所述第一和第二栅极叠层的栅极绝缘层由氧化铪、铪硅氧化物、氧化镧、氧化锆、锆硅氧化物、氧化钽、氧化钇或氧化铝形成。
16.根据权利要求1所述的半导体器件,其中所述PMOS器件的第一栅极叠层还包括形成在所述第三导电层上的第四导电层。
17.根据权利要求16所述的半导体器件,其中所述第二栅极叠层的第二导电层和所述第一栅极叠层的第四导电层由相同的导电材料形成。
18.根据权利要求16所述的半导体器件,其中所述第二栅极叠层的第二导电层和所述第一栅极叠层的第四导电层由多晶硅材料形成。
19.根据权利要求1所述的半导体器件,其中所述第一和第二栅极叠层的第一导电层的厚度在约5埃至约60埃的范围内。
20.一种半导体器件,包括:
半导体衬底,所述半导体衬底具有形成在所述半导体衬底前侧上的双栅极CMOS器件,所述双栅极CMOS器件包括具有第一MIPS栅极叠层的PMOS器件和具有第二MIPS栅极叠层的NMOS器件,
其中所述第一和第二MIPS栅极叠层均包括:
形成在所述半导体衬底上的栅极绝缘体层;
多晶硅电极;以及
插入在所述栅极绝缘层和所述多晶硅电极之间的金属插入层,
其中所述第一MIPS栅极叠层的金属插入层包括至少第一、第二和第三金属性层的叠层;以及
其中所述第二MIPS栅极叠层的金属插入层包括至少第一金属性层。
21.根据权利要求20所述的半导体器件,其中所述第一和第二MIPS栅极叠层的第一金属性层由相同的金属性材料形成并具有约5埃至约60埃范围内的相同的厚度。
22.根据权利要求21所述的半导体器件,其中所述第一和第二MIPS栅极叠层的第一金属性层由金属性氮化物形成。
23.根据权利要求22所述的半导体器件,其中所述第一和第二MIPS栅极叠层的第一导电层的厚度和金属性氮化物材料被选择以调整所述NMOS器件的功函数。
24.根据权利要求21所述的半导体器件,其中所述第一MIPS栅极叠层的第二金属性层的厚度和导电材料被选择以调整所述PMOS器件的功函数。
25.根据权利要求20所述的半导体器件,其中所述第一MIPS栅极叠层的第一、第二、第三金属性层由不同的导电材料形成。
26.根据权利要求25所述的半导体器件,其中所述第一MIPS栅极叠层的第一、第二和第三金属性层分别由TaN、AlN和HfN形成。
27.根据权利要求25所述的半导体器件,其中所述第一MIPS栅极叠层的第一、第二和第三金属性层分别由HfN、AlN和TaN形成。
28.根据权利要求20所述的半导体器件,其中所述第一和第二MIPS栅极叠层的栅极绝缘层由介电常数在约8及更大的范围内的电介质材料形成。
29.根据权利要求20所述的半导体器件,还包括插入在所述栅极绝缘层和所述半导体衬底之间的界面层。
30.一种制造具有双栅极CMOS器件的半导体器件的方法,该方法包括:
在半导体衬底上界定CMOS器件的有源区,所述有源区包括NMOS器件区域和PMOS器件区域;
在所述半导体衬底上形成栅极绝缘层;
在所述栅极绝缘层上形成第一导电层;
在所述第一导电层上形成第二导电层;
在所述第二导电层上形成第三导电层;
进行蚀刻工艺,从而在所述NMOS器件区域中向下蚀刻所述第三和第二导电层至所述第一导电层;以及
在所述PMOS区域中形成第一栅极结构并在所述NMOS区域中形成第二栅极结构,其中所述第一栅极结构是由所述栅极绝缘层以及第一和第二导电层形成的叠层结构,其中所述第二栅极结构是由所述栅极绝缘层和所述第一导电层形成的叠层结构。
31.根据权利要求30所述的方法,其中利用蚀刻工艺蚀刻所述第三和第二导电层,在所述蚀刻工艺中,所述第二和第三导电层的蚀刻速率大于所述第一导电层的蚀刻速率从而所述第一导电层用作蚀刻停止物。
32.根据权利要求31所述的方法,其中所述蚀刻工艺是利用HF溶液的湿法蚀刻工艺。
33.根据权利要求32所述的方法,其中所述第一导电层由TaN形成,其中所述第二导电层由AlN形成,其中所述第三导电层由HfN形成。
34.根据权利要求30所述的方法,其中形成所述第一和第二栅极结构包括:
在所述NMOS和PMOS区域之上形成第四导电层;
在所述第四导电层上形成蚀刻掩模,其中所述蚀刻掩模界定了用于所述第一和第二栅极结构的栅极图案;
向下蚀刻所述第四导电层至所述衬底,从而形成所述第一和第二栅极结构。
35.根据权利要求34所述的方法,其中所述第四导电层包括多晶硅。
36.根据权利要求34所述的方法,其中所述第四导电层包括金属性材料。
37.根据权利要求36所述的方法,其中所述第四导电层包括金属硅化物或氮化物材料。
38.根据权利要求30所述的方法,其中形成所述栅极绝缘层包括:
在所述半导体衬底上形成界面层;以及
在所述界面层之上形成栅极电介质材料层。
39.根据权利要求38所述的方法,其中所述栅极电介质材料具有在约8及更大的范围内的介电常数。
40.根据权利要求39所述的方法,其中所述第一和第二栅极叠层的栅极绝缘层的栅极电介质材料由氧化铪、铪硅氧化物、氧化镧、氧化锆、锆硅氧化物、氧化钽、氧化钇或氧化铝形成。
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US20070178634A1 (en) | 2007-08-02 |
US7829953B2 (en) | 2010-11-09 |
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