JP5139023B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 42
- 238000004519 manufacturing process Methods 0.000 title claims description 35
- 229910052751 metal Inorganic materials 0.000 claims description 127
- 239000002184 metal Substances 0.000 claims description 126
- 238000000034 method Methods 0.000 claims description 23
- 238000010438 heat treatment Methods 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 11
- 239000000470 constituent Substances 0.000 claims description 10
- 229910052735 hafnium Inorganic materials 0.000 claims description 8
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 8
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 5
- 229910052726 zirconium Inorganic materials 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- 239000010410 layer Substances 0.000 description 41
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 31
- 229910010037 TiAlN Inorganic materials 0.000 description 27
- 238000009792 diffusion process Methods 0.000 description 21
- 229910052581 Si3N4 Inorganic materials 0.000 description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 20
- 150000002500 ions Chemical class 0.000 description 16
- 238000005530 etching Methods 0.000 description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 239000011229 interlayer Substances 0.000 description 11
- 238000006243 chemical reaction Methods 0.000 description 9
- 229910000167 hafnon Inorganic materials 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 239000012298 atmosphere Substances 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- HDWLUGYOLUHEMN-UHFFFAOYSA-N Dinobuton Chemical compound CCC(C)C1=CC([N+]([O-])=O)=CC([N+]([O-])=O)=C1OC(=O)OC(C)C HDWLUGYOLUHEMN-UHFFFAOYSA-N 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910004491 TaAlN Inorganic materials 0.000 description 3
- 241000425573 Talanes Species 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004381 surface treatment Methods 0.000 description 3
- 229910018516 Al—O Inorganic materials 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 229910052746 lanthanum Inorganic materials 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000005191 phase separation Methods 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
図1乃至図9は、本発明の第1の実施形態に係る半導体装置の製造方法の一部を模式的に示した断面図である。
Ga+HfSiO4=Ga2O3+HfO2+Si+ΔG ・・・・・式(2)
In+HfSiO4=In2O3+HfO2+Si+ΔG ・・・・・式(3)
Alを含むゲート絶縁膜109の形成後、図7に示すように、シリコン窒化膜を堆積し、エッチバックを行うことによって、ゲート電極108の側壁部分にシリコン窒化膜110を形成する。さらに、このゲート電極108をマスクにして、NMOS領域にはAs+イオンをイオン注入し、PMOS領域にはB+イオンをイオン注入し、800℃で5秒間加熱処理を施すことによって、浅い拡散層111をそれぞれ形成する。
図10乃至図15は、本発明の第2の実施形態に係る半導体装置の製造方法の一部を模式的に示した断面図である。
また、2族であってもこの関係が成立する。例えば、ゲート絶縁膜としてHfSiO4を用い、それに対してMgを接触させた場合、式(5)に示すように左辺から右辺へと反応が進む。
続いて、厚さ10nmのNi膜を全面に堆積し、350℃で30秒程度の加熱処理を行い、Niとシリコン基板を反応させた後、未反応Ni膜を硫酸と過酸化水素水の混合液により除去する。そして、500℃で30秒程度の加熱処理によって、浅い拡散層210上にシリサイド層215を形成する。この時、ゲート電極208上のシリコン窒化膜207を残すことによりW膜203は露出しないため、W膜203が上記硫酸と過酸化水素水の混合液によって除去されることはない。
図16乃至図22は、本発明の第3の実施形態に係る半導体装置の製造方法の一部を模式的に示した断面図である。
101、201、301 素子分離層
102、202、302 ゲート絶縁膜
103 第一の金属膜(WSi膜)
104 第二の金属膜(TiAlN膜)
105 第三の金属膜(TiN膜)
106、307 導電層(多結晶シリコン膜)
107、110、113、207、209、212、308、310、313 シリコン窒化膜
108、208、309 ゲート電極
109、214、316 Alを含むゲート絶縁膜
111、210、311 浅い拡散層
112、211、312 シリコン酸化膜
114、213、314 深い拡散層
115、215、317 シリサイド層
116、216、318 第一の層間膜
117、217、319 コンタクト
118、218、320 第二の層間膜
119、219、321 Cu配線
203 第一の金属膜(W膜)
204 第二の金属膜(TiTbN膜)
205 第三の金属膜(TiN膜)
206 導電層(W膜)
303 第一の金属膜(W膜)
304 第二の金属膜(TiLaN膜)
305 第三の金属膜(TiAlN膜)
306 第四の金属膜(TiN膜)
315 Laを含むゲート絶縁膜
Claims (5)
- 半導体基板の主面に第一及び第二の領域を形成する工程と、
前記第一及び第二の領域上にハフニウム又はジルコニウムと酸素を含有するゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上に第一の金属膜を形成する工程と、
前記第一の金属膜上に第二の金属膜を形成する工程と、
前記第一の領域上の前記第二の金属膜を残し、前記第二の領域上の前記第二の金属膜を除去する工程と、
前記第二の金属膜上および前記第二の金属膜が除去された領域の前記第一の金属膜上に第三の金属膜を形成する工程と、
前記第二の金属膜の構成元素を前記第一の金属膜を通して前記ゲート絶縁膜中へ導入する加熱工程を備えることを特徴とする半導体装置の製造方法。 - 前記第二の領域がNMOSを形成する領域であり、前記第二の金属膜がアルミニウムを構成元素として含むことを特徴とする請求項1記載の半導体装置の製造方法。
- 前記第二の領域がPMOSを形成する領域であり、前記第二の金属膜が2族もしくは3a族の元素を構成元素として含むことを特徴とする請求項1記載の半導体装置の製造方法。
- 前記第二の金属膜が第三の金属膜の構成金属元素を含むことを特徴とする請求項1乃至3のいずれか1項記載の半導体装置の製造方法。
- 半導体基板の主面に第一及び第二の領域を形成する工程と、
前記第一及び第二の領域上にハフニウム又はジルコニウムと酸素を含有するゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上に第一の金属膜を形成する工程と、
前記第一の金属膜上に第二の金属膜を形成する工程と、
前記第一の領域上の前記第二の金属膜を残し、前記第二の領域上の前記第二の金属膜を除去して前記第二の領域上の前記第一の金属膜を露出させる工程と、
前記第二の金属膜上及び露出された前記第一の金属膜上に第三の金属膜を形成する工程と、
前記第二の領域上の前記第三の金属膜を残し、前記第一の領域上の前記第三の金属膜を除去して前記第一の領域上の前記第二の金属膜を露出させる工程と、
露出された前記第二の金属膜上及び前記第三の金属膜上に第四の金属膜を形成する工程と、
前記第二の金属膜及び前記第三の金属膜の構成元素を前記第一の金属膜を通してそれぞれ前記第一及び第二の領域上の前記ゲート絶縁膜中へ導入する加熱工程を備えることを特徴とする半導体装置の製造方法。
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JP2007269556A JP5139023B2 (ja) | 2007-10-16 | 2007-10-16 | 半導体装置の製造方法 |
US12/248,143 US7820476B2 (en) | 2007-10-16 | 2008-10-09 | Method for manufacturing a semiconductor device |
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JP2007269556A JP5139023B2 (ja) | 2007-10-16 | 2007-10-16 | 半導体装置の製造方法 |
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JP2009099747A JP2009099747A (ja) | 2009-05-07 |
JP5139023B2 true JP5139023B2 (ja) | 2013-02-06 |
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Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5349903B2 (ja) * | 2008-02-28 | 2013-11-20 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
JP2009283770A (ja) * | 2008-05-23 | 2009-12-03 | Renesas Technology Corp | 半導体装置の製造方法 |
DE102009021486B4 (de) * | 2009-05-15 | 2013-07-04 | Globalfoundries Dresden Module One Llc & Co. Kg | Verfahren zur Feldeffekttransistor-Herstellung |
US7989902B2 (en) * | 2009-06-18 | 2011-08-02 | International Business Machines Corporation | Scavenging metal stack for a high-k gate dielectric |
DE102009031155B4 (de) * | 2009-06-30 | 2012-02-23 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Einstellen einer Schwellwertspannung für komplexe Transistoren durch Diffundieren einer Metallsorte in das Gatedielektrikum vor der Gatestrukturierung |
DE102009039418B4 (de) * | 2009-08-31 | 2013-08-22 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Einstellung der Austrittsarbeit in Gate-Stapeln mit großem ε, die Gatedielektrika mit unterschiedlicher Dicke enthalten |
US20110147851A1 (en) * | 2009-12-18 | 2011-06-23 | Thomas Christopher D | Method For Depositing Gate Metal For CMOS Devices |
WO2011077536A1 (ja) * | 2009-12-24 | 2011-06-30 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP5937297B2 (ja) | 2010-03-01 | 2016-06-22 | キヤノンアネルバ株式会社 | 金属窒化膜、該金属窒化膜を用いた半導体装置、および半導体装置の製造方法 |
JP2012044013A (ja) * | 2010-08-20 | 2012-03-01 | Renesas Electronics Corp | 半導体装置の製造方法 |
US9859392B2 (en) | 2015-09-21 | 2018-01-02 | Samsung Electronics Co., Ltd. | Integrated circuit device and method of manufacturing the same |
US10665450B2 (en) * | 2017-08-18 | 2020-05-26 | Applied Materials, Inc. | Methods and apparatus for doping engineering and threshold voltage tuning by integrated deposition of titanium nitride and aluminum films |
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JP4237332B2 (ja) * | 1999-04-30 | 2009-03-11 | 株式会社東芝 | 半導体装置の製造方法 |
JP2001257344A (ja) * | 2000-03-10 | 2001-09-21 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
US6573134B2 (en) * | 2001-03-27 | 2003-06-03 | Sharp Laboratories Of America, Inc. | Dual metal gate CMOS devices and method for making the same |
JP4091530B2 (ja) * | 2003-07-25 | 2008-05-28 | 株式会社東芝 | 半導体装置の製造方法 |
JP2007134456A (ja) * | 2005-11-09 | 2007-05-31 | Toshiba Corp | 半導体装置の製造方法 |
KR100647472B1 (ko) * | 2005-11-23 | 2006-11-23 | 삼성전자주식회사 | 반도체 장치의 듀얼 게이트 구조물 및 그 형성 방법. |
US7425497B2 (en) * | 2006-01-20 | 2008-09-16 | International Business Machines Corporation | Introduction of metal impurity to change workfunction of conductive electrodes |
US20070178634A1 (en) * | 2006-01-31 | 2007-08-02 | Hyung Suk Jung | Cmos semiconductor devices having dual work function metal gate stacks |
JP4828982B2 (ja) * | 2006-03-28 | 2011-11-30 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
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2007
- 2007-10-16 JP JP2007269556A patent/JP5139023B2/ja not_active Expired - Fee Related
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2008
- 2008-10-09 US US12/248,143 patent/US7820476B2/en not_active Expired - Fee Related
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JP2009099747A (ja) | 2009-05-07 |
US7820476B2 (en) | 2010-10-26 |
US20090098693A1 (en) | 2009-04-16 |
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