CN100435326C - 集成电路芯片i/o单元及其制造方法 - Google Patents
集成电路芯片i/o单元及其制造方法 Download PDFInfo
- Publication number
- CN100435326C CN100435326C CNB2004800094982A CN200480009498A CN100435326C CN 100435326 C CN100435326 C CN 100435326C CN B2004800094982 A CNB2004800094982 A CN B2004800094982A CN 200480009498 A CN200480009498 A CN 200480009498A CN 100435326 C CN100435326 C CN 100435326C
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- metal
- pad
- chip
- layer
- insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48233—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a potential ring of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/409,766 US6717270B1 (en) | 2003-04-09 | 2003-04-09 | Integrated circuit die I/O cells |
| US10/409,766 | 2003-04-09 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1771598A CN1771598A (zh) | 2006-05-10 |
| CN100435326C true CN100435326C (zh) | 2008-11-19 |
Family
ID=32030641
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004800094982A Expired - Lifetime CN100435326C (zh) | 2003-04-09 | 2004-04-08 | 集成电路芯片i/o单元及其制造方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6717270B1 (enExample) |
| JP (1) | JP4647594B2 (enExample) |
| KR (1) | KR101054665B1 (enExample) |
| CN (1) | CN100435326C (enExample) |
| TW (1) | TWI337773B (enExample) |
| WO (1) | WO2004093188A1 (enExample) |
Families Citing this family (66)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4170103B2 (ja) * | 2003-01-30 | 2008-10-22 | Necエレクトロニクス株式会社 | 半導体装置、および半導体装置の製造方法 |
| TWI220565B (en) * | 2003-02-26 | 2004-08-21 | Realtek Semiconductor Corp | Structure of IC bond pad and its formation method |
| JP4357862B2 (ja) * | 2003-04-09 | 2009-11-04 | シャープ株式会社 | 半導体装置 |
| US7566964B2 (en) * | 2003-04-10 | 2009-07-28 | Agere Systems Inc. | Aluminum pad power bus and signal routing for integrated circuit devices utilizing copper technology interconnect structures |
| JPWO2004093191A1 (ja) * | 2003-04-11 | 2006-07-06 | 富士通株式会社 | 半導体装置 |
| WO2004093184A1 (ja) | 2003-04-15 | 2004-10-28 | Fujitsu Limited | 半導体装置及びその製造方法 |
| US20050082677A1 (en) * | 2003-10-15 | 2005-04-21 | Su-Chen Fan | Interconnect structure for integrated circuits |
| JP4242336B2 (ja) * | 2004-02-05 | 2009-03-25 | パナソニック株式会社 | 半導体装置 |
| US7208837B2 (en) * | 2004-02-10 | 2007-04-24 | United Microelectronics Corp. | Semiconductor chip capable of implementing wire bonding over active circuits |
| US6900541B1 (en) * | 2004-02-10 | 2005-05-31 | United Microelectronics Corp. | Semiconductor chip capable of implementing wire bonding over active circuits |
| US7071561B2 (en) * | 2004-06-08 | 2006-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture thereof with two or more bond pad connections for each input/output cell |
| US20060022353A1 (en) * | 2004-07-30 | 2006-02-02 | Ajuria Sergio A | Probe pad arrangement for an integrated circuit and method of forming |
| US20060060845A1 (en) * | 2004-09-20 | 2006-03-23 | Narahari Ramanuja | Bond pad redistribution layer for thru semiconductor vias and probe touchdown |
| CN100362657C (zh) * | 2004-12-22 | 2008-01-16 | 中芯国际集成电路制造(上海)有限公司 | 半导体集成电路的内连焊盘 |
| JP2006229186A (ja) * | 2005-01-18 | 2006-08-31 | Matsushita Electric Ind Co Ltd | 半導体集積回路およびその製造方法 |
| DE102006008454B4 (de) * | 2005-02-21 | 2011-12-22 | Samsung Electronics Co., Ltd. | Kontaktstellenstruktur, Kontaktstellen-Layoutstruktur, Halbleiterbauelement und Kontaktstellen-Layoutverfahren |
| JP4449824B2 (ja) * | 2005-06-01 | 2010-04-14 | カシオ計算機株式会社 | 半導体装置およびその実装構造 |
| KR100610025B1 (ko) * | 2005-07-12 | 2006-08-08 | 삼성전자주식회사 | 멀티 패드 레이아웃구조 및 그를 구비하는 반도체 장치 |
| JP4671814B2 (ja) | 2005-09-02 | 2011-04-20 | パナソニック株式会社 | 半導体装置 |
| US7531903B2 (en) * | 2005-09-02 | 2009-05-12 | United Microelectronics Corp. | Interconnection structure used in a pad region of a semiconductor substrate |
| US8319343B2 (en) | 2005-09-21 | 2012-11-27 | Agere Systems Llc | Routing under bond pad for the replacement of an interconnect layer |
| US7952206B2 (en) * | 2005-09-27 | 2011-05-31 | Agere Systems Inc. | Solder bump structure for flip chip semiconductor devices and method of manufacture therefore |
| US7741716B1 (en) * | 2005-11-08 | 2010-06-22 | Altera Corporation | Integrated circuit bond pad structures |
| US8552560B2 (en) * | 2005-11-18 | 2013-10-08 | Lsi Corporation | Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing |
| JP4995455B2 (ja) | 2005-11-30 | 2012-08-08 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US20070194451A1 (en) * | 2006-02-22 | 2007-08-23 | Chih-Hung Wu | Apparatus for integrated input/output circuit and verification method thereof |
| KR100834828B1 (ko) * | 2006-03-17 | 2008-06-04 | 삼성전자주식회사 | 정전방전 특성을 강화한 반도체 장치 |
| US7808117B2 (en) * | 2006-05-16 | 2010-10-05 | Freescale Semiconductor, Inc. | Integrated circuit having pads and input/output (I/O) cells |
| KR20090025239A (ko) * | 2006-05-16 | 2009-03-10 | 프리스케일 세미컨덕터, 인크. | 패드 및 입출력(i/o) 셀을 갖는 집적 회로 |
| JP5208936B2 (ja) * | 2006-08-01 | 2013-06-12 | フリースケール セミコンダクター インコーポレイテッド | チップ製造および設計における改良のための方法および装置 |
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| JP2008198916A (ja) * | 2007-02-15 | 2008-08-28 | Spansion Llc | 半導体装置及びその製造方法 |
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| US20090051050A1 (en) * | 2007-08-24 | 2009-02-26 | Actel Corporation | corner i/o pad density |
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| JP5331891B2 (ja) * | 2009-09-21 | 2013-10-30 | 株式会社東芝 | 半導体装置 |
| CN101697344B (zh) * | 2009-10-28 | 2012-10-31 | 上海宏力半导体制造有限公司 | 一种降低芯片电源焊盘键合引线上电流的方法 |
| CN102136462B (zh) * | 2010-01-27 | 2013-10-30 | 晨星软件研发(深圳)有限公司 | 通用输出入单元及相关装置与方法 |
| US20110186899A1 (en) * | 2010-02-03 | 2011-08-04 | Polymer Vision Limited | Semiconductor device with a variable integrated circuit chip bump pitch |
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| JP5485132B2 (ja) * | 2010-12-28 | 2014-05-07 | パナソニック株式会社 | 半導体装置 |
| US8982574B2 (en) * | 2010-12-29 | 2015-03-17 | Stmicroelectronics S.R.L. | Contact and contactless differential I/O pads for chip-to-chip communication and wireless probing |
| US8549257B2 (en) * | 2011-01-10 | 2013-10-01 | Arm Limited | Area efficient arrangement of interface devices within an integrated circuit |
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| JP2013206905A (ja) * | 2012-03-27 | 2013-10-07 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
| US20130320522A1 (en) * | 2012-05-30 | 2013-12-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Re-distribution Layer Via Structure and Method of Making Same |
| JP5968713B2 (ja) * | 2012-07-30 | 2016-08-10 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| KR20150101762A (ko) * | 2014-02-27 | 2015-09-04 | 에스케이하이닉스 주식회사 | 반도체 장치 |
| CN107112280B (zh) * | 2014-10-24 | 2020-08-04 | 株式会社索思未来 | 半导体集成电路装置 |
| JP2016139711A (ja) * | 2015-01-28 | 2016-08-04 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| US9922947B2 (en) * | 2016-04-28 | 2018-03-20 | Stmicroelectronics S.R.L. | Bonding pad structure over active circuitry |
| US10410934B2 (en) * | 2017-12-07 | 2019-09-10 | Micron Technology, Inc. | Apparatuses having an interconnect extending from an upper conductive structure, through a hole in another conductive structure, and to an underlying structure |
| JP2019169525A (ja) * | 2018-03-22 | 2019-10-03 | 東芝メモリ株式会社 | 半導体記憶装置 |
| US20200006122A1 (en) * | 2018-06-27 | 2020-01-02 | Qualcomm Incorporated | Integrated circuits (ics) made using extreme ultraviolet (euv) patterning and methods for fabricating such ics |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2584259A1 (fr) * | 1985-06-26 | 1987-01-02 | Gen Ceramics Inc | Procede de fabrication d'un substrat ceramique multicouche comportant un circuit et le substrat ainsi obtenu |
| WO1999054934A1 (en) * | 1998-04-22 | 1999-10-28 | Cvc Products, Inc. | Ultra high-speed chip interconnect using free-space dielectrics |
| US6174803B1 (en) * | 1998-09-16 | 2001-01-16 | Vsli Technology | Integrated circuit device interconnection techniques |
| CN1281257A (zh) * | 1999-06-28 | 2001-01-24 | 株式会社东芝 | 半导体器件 |
| US6489228B1 (en) * | 1997-12-05 | 2002-12-03 | Stmicroelectronics S.R.L. | Integrated electronic device comprising a mechanical stress protection structure |
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| JPH03148132A (ja) * | 1989-11-04 | 1991-06-24 | Ricoh Co Ltd | スタンダードセル方式の半導体集積回路装置 |
| JP2900555B2 (ja) * | 1990-07-30 | 1999-06-02 | 日本電気株式会社 | 半導体集積回路 |
| WO1995028005A2 (en) | 1994-04-07 | 1995-10-19 | Vlsi Technology, Inc. | Staggered pad array |
| US5514892A (en) | 1994-09-30 | 1996-05-07 | Motorola, Inc. | Electrostatic discharge protection device |
| JP3493118B2 (ja) | 1997-07-25 | 2004-02-03 | 沖電気工業株式会社 | 半導体素子及び半導体装置 |
| JP3022819B2 (ja) | 1997-08-27 | 2000-03-21 | 日本電気アイシーマイコンシステム株式会社 | 半導体集積回路装置 |
| JP3259763B2 (ja) * | 1997-11-14 | 2002-02-25 | 日本電気株式会社 | 半導体lsi |
| US6242814B1 (en) | 1998-07-31 | 2001-06-05 | Lsi Logic Corporation | Universal I/O pad structure for in-line or staggered wire bonding or arrayed flip-chip assembly |
| JP2000252363A (ja) * | 1999-03-01 | 2000-09-14 | Kawasaki Steel Corp | 半導体集積回路 |
| US6329278B1 (en) | 2000-01-03 | 2001-12-11 | Lsi Logic Corporation | Multiple row wire bonding with ball bonds of outer bond pads bonded on the leads |
| US6291898B1 (en) | 2000-03-27 | 2001-09-18 | Advanced Semiconductor Engineering, Inc. | Ball grid array package |
| US6476506B1 (en) | 2001-09-28 | 2002-11-05 | Motorola, Inc. | Packaged semiconductor with multiple rows of bond pads and method therefor |
| JP2003289104A (ja) * | 2002-03-28 | 2003-10-10 | Ricoh Co Ltd | 半導体装置の保護回路及び半導体装置 |
| KR100476900B1 (ko) * | 2002-05-22 | 2005-03-18 | 삼성전자주식회사 | 테스트 소자 그룹 회로를 포함하는 반도체 집적 회로 장치 |
-
2003
- 2003-04-09 US US10/409,766 patent/US6717270B1/en not_active Expired - Lifetime
-
2004
- 2004-04-08 CN CNB2004800094982A patent/CN100435326C/zh not_active Expired - Lifetime
- 2004-04-08 WO PCT/US2004/010813 patent/WO2004093188A1/en not_active Ceased
- 2004-04-08 JP JP2006509808A patent/JP4647594B2/ja not_active Expired - Fee Related
- 2004-04-08 KR KR1020057019121A patent/KR101054665B1/ko not_active Expired - Fee Related
- 2004-04-09 TW TW093109990A patent/TWI337773B/zh not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2584259A1 (fr) * | 1985-06-26 | 1987-01-02 | Gen Ceramics Inc | Procede de fabrication d'un substrat ceramique multicouche comportant un circuit et le substrat ainsi obtenu |
| US6489228B1 (en) * | 1997-12-05 | 2002-12-03 | Stmicroelectronics S.R.L. | Integrated electronic device comprising a mechanical stress protection structure |
| WO1999054934A1 (en) * | 1998-04-22 | 1999-10-28 | Cvc Products, Inc. | Ultra high-speed chip interconnect using free-space dielectrics |
| US6174803B1 (en) * | 1998-09-16 | 2001-01-16 | Vsli Technology | Integrated circuit device interconnection techniques |
| CN1281257A (zh) * | 1999-06-28 | 2001-01-24 | 株式会社东芝 | 半导体器件 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1771598A (zh) | 2006-05-10 |
| WO2004093188A1 (en) | 2004-10-28 |
| JP2006523036A (ja) | 2006-10-05 |
| US6717270B1 (en) | 2004-04-06 |
| KR20060004930A (ko) | 2006-01-16 |
| TW200501380A (en) | 2005-01-01 |
| KR101054665B1 (ko) | 2011-08-08 |
| JP4647594B2 (ja) | 2011-03-09 |
| TWI337773B (en) | 2011-02-21 |
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