CN100435284C - 具有低接触电阻的半导体设备及其制造方法 - Google Patents

具有低接触电阻的半导体设备及其制造方法 Download PDF

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CN100435284C
CN100435284C CNB2005100023396A CN200510002339A CN100435284C CN 100435284 C CN100435284 C CN 100435284C CN B2005100023396 A CNB2005100023396 A CN B2005100023396A CN 200510002339 A CN200510002339 A CN 200510002339A CN 100435284 C CN100435284 C CN 100435284C
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epitaxial layers
layer
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安台恒
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SK Hynix Inc
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Abstract

本发明关于一种具有低接触电阻的半导体设备及其制造方法。所述半导体设备包括：一衬底结构，其具有一接触孔以暴露其预定的部分；及一形成于该接触孔上的接触塞，其中所述接触塞具有填充于接触孔一部分中的外延硅层，及填充于接触孔其余部分中并形成于外延硅层上的金属层。用以制造该半导体设备的方法包括以下步骤：暴露一衬底结构的一部分，由此形成一接触孔；及在接触孔上顺序地形成一外延硅层及一金属层，从而获得接触塞。

Description

具有低接触电阻的半导体设备及其制造方法
技术领域
本发明关于一种半导体技术，更具体地，是关于一种具有低接触电阻的半导体设备及其制造方法。
背景技术
由于半导体设备的高度集成化，半导体设备的尺寸变得更小。因此，就动态随机存取存储器(DRAM)装置而言，大规模的集成及缩小的尺寸已经对单元晶体管(cell transistor)的接触区造成极大的影响。换句话说，由于半导体设备被高度集成化和小型化，接触区的面积也被缩小；但是，这种缩小的面积导致接触电阻的增加及驱动电流的减少，由此进一步造成半导体设备的退化，例如，刷新(refresh)特性及写恢复特性(tWR)等的退化。
因此，为了减小接触电阻和提高驱动电流，在衬底的结区被掺入高浓度的掺杂剂，或是将普遍用于多晶硅层内用于接触的掺杂剂磷(P)的浓度提高。但是，这些方法的缺点是漏电流增加且刷新特性(tREF)及数据保留时间均将降低。
上述多晶硅层是在批次型炉内使用硅烷(SiH4)/磷化氢(PH3)气体在约500℃至约600℃的温度范围内沉积而成。此时，磷的掺杂浓度范围是0.1×1020原子/cm3到3.0×1020原子/cm3。再者，即使多晶硅层的沉积是在大气压力下使用氮气作为净化气体进行的，但是由于所产生的氧的浓度有若干ppm，故在多晶硅层及衬底间的界面形成一个薄的氧化物层。这种薄氧化物层是增加接触电阻的原因之一，多晶硅层具有很高的接触电阻。结果，随着半导体设备被高度集成化，上述使用多晶硅层形成接触的方法对于改善接触电阻及装置特性具有局限性。
因此，一种用于克服上述问题及局限性的方法是使用单一型化学气相沉积(CVD)设备形成一外延硅层。一个代表性的方法是选择外延生长(SEG)法，是从暴露的衬底选择地生长外延硅层。虽然使用SEG法能够获得具有所需厚度的高质量的外延硅层，但是SEG法须在850℃的高温作氢烘(hydrogen bake)并在800℃温度为生长该外延硅层进行高温热处理。因此很难将SEG法应用到半导体设备的制造工艺。
图1为半导体衬底结构图，其中接触塞是利用多晶硅层或外延硅层形成。此处，参考数字101、102、103、104、及105分别为硅衬底、栅极结构、结区、绝缘层、及掺杂质的多晶硅层或掺杂质的外延硅层。
近来，使用固相外延(SPE)法形成外延硅结构的方法成为一种焦点提案，可用以克服多晶硅层产生的问题和使用SEG法的上述局限性。SPE法最近成为焦点的理由是使在低温下形成具有低掺杂浓度的外延硅结构成为可能。再者，使用低掺杂浓度即可完成SPE法。
依照SPE法，在约500℃至约650℃的温度范围下使用SiH4/PH3气体掺杂相对低浓度的磷，即可形成非晶硅层。特别的是，磷的浓度范围为1×1019原子/cm3至1×1020原子/cm3。在SPE法实施中，外延硅层是形成在底部而非晶硅层形成在外延硅层上。
之后，在约550℃至约650℃的温度范围下，于一氮气环境中实行约30分钟至10小时的热处理。经此热处理，外延硅层从衬底的界面再生长至接触的上方区域，因而，SPE乃引用于此一再生长的外延硅层。
如上所述，多晶硅层用作接触材料时，磷的掺入浓度须大于1×1020原子/cm3以减小接触电阻。但是，仍有刷新特性降低的问题。由于外延硅层改善了界面特性，所以即使施加低浓度的磷，也可保持相当低的接触电阻。
但是，亚-100nm半导体技术中的大规模集成需要保持更低的接触电阻。由于外延硅的电阻率约为1×10-3mΩ-cm且很难获得低于该值的电阻率，因此外延硅层对于克服电阻仍有其局限性。从而，如果将外延硅层应用于亚-100nm或下一代半导体技术中，需开发一种用以形成接触塞的工艺，其中该接触塞的接触电阻比使用外延硅层的接触电阻必须低得多。还有必须保证半导体设备的可靠性及产能。
发明内容
因此本发明的目的是提供一种具有低接触电阻，足以获得超高集成化半导体设备的电特性的半导体设备及其制造方法。
依据本发明的一个方面，提供一种半导体设备，包括：具有接触孔以暴露其预定部分的衬底结构；及形成在该接触孔上的接触塞，其中接触塞具有填充部分接触孔的外延硅层及填充接触孔剩余部分的形成在外延硅层上的金属层。
依据本发明的另一个方面，提供一种用于制造半导体设备的方法，包括以下步骤：暴露衬底结构的一部分以形成接触孔；及在接触孔上顺序地形成外延硅层及金属层，由此获得一接触塞。
附图说明
本发明的上述及其它目的和特色将通过下述优选实施例的描述并结合附图而更容易理解，其中：
图1为一半导体衬底结构图，其中，利用多晶硅和外延硅两者之一形成一传统的接触塞。
图2为半导体衬底结构图，其中，依据本发明的一优选实施例形成一接触塞。
图3A到3D为剖面图，用以示出依据本发明优选实施例形成接触塞的方法。
具体实施方式
下面将参考附图详细说明依据本发明优选实施例的具有低接触电阻的半导体设备及其制造方法。
在以下本发明的优选实施例中，除了使用外延硅以获得较低的接触电阻外，建议另外使用金属作为接触塞的材料。如众所周知，因为金属的电阻率低于硅约1000倍，故使用金属作为接触塞的材料就接触电阻而言是有利的。另外，由于没有掺杂剂从接触塞向结区扩散，故有可能排除掺杂剂对刷新特性的影响。此外，当金属原子直接接触外延硅时发生的那些污染及深阶杂质等问题，可通过使用硅化物处理以引起所使用的金属与生长有一预定厚度的外延硅层反应而解决。之后，将对此种接触塞的特殊结构详细描述。
图2为动态随机存取存储器(DRAM)装置的一部分图示，其中接触塞是依本发明的一优选实施例形成的。
如图所示，包含多个栅极结构202及一结区203的多个晶体管形成在一硅衬底201上，接触塞220形成在设置于接触孔100之间的结区203上，所述接触孔100是通过蚀刻围绕在所述栅极结构202周围的绝缘层204的一预定部分所形成的。
具体而言，接触塞220包括：形成在衬底201上并填充入接触孔100一部分的一外延硅层205A；薄薄地形成在外延硅层205A上及接触孔100侧壁上的一金属硅化物层206A及一阻挡金属层207；以及形成在阻挡金属层207上并填充入接触孔100内其余部分的一金属层208。特别地，金属硅化物层206A是对一原始沉积的金属层施加热处理而获得的，所述金属层基于从包括钛(Ti)、钴(Co)及镍(Ni)的组中选择的材料。亦即，金属硅化物层206A可为硅化钛(TiSi2)层、硅化钴(CoSi2)层及硅化镍(NiSi)层三者中的一个。阻挡金属层207是以例如氮化钛(TiN)或氮化钨(WN)的材料制成。金属层208则由钨(W)制成。
特别地，外延硅层205A采用固相外延(SPE)法形成而不经过热处理。此时，外延硅层205A的磷(P)或砷(As)的掺杂浓度范围从约1×1018原子/cm3至约1×1021原子/cm3之间，且其电阻率约为1×10-3mΩ-cm。与多晶硅相比，外延硅层205A在相对低的掺杂浓度下具有较低的电阻率值。另外，金属硅化物层206A、阻挡金属层207及金属层208的电阻率值均较外延硅层205A为低。因此，依本发明获得的接触塞的电阻率比传统接触塞低。
图3A～3D为剖面图，用以说明形成依本发明优选实施例的接触塞的方法。此处，相同的参考数字用于图2中的相同配置元件。
如图3A所示，通过在衬底201上形成栅极结构202，且之后，在栅极结构202间设置的衬底201的一部分中形成一结区203而形成多个晶体管。在形成所述晶体管的过程中并在晶体管形成后形成覆盖每个栅极结构202底部、上部、及侧壁的绝缘层204。尽管所举例的绝缘层204为一层，但绝缘层204通过包括栅极绝缘层、掩模绝缘层及间隔绝缘层而多层化。之后，将绝缘层204的一部分露出以形成一接触孔100，其被填充有塞材料。
如图3B所示，利用固相外延(SPE)法在约500℃～约700℃的范围中使用硅烷(SiH4)/磷化氢(PH3)的气体形成外延硅结构205。再者，在一化学气相沉积(CVD)装置中执行SPE法。以下，采用SPE法获取的外延硅结构被称为SPE-硅结构。不经过热处理的SPE-硅结构205包括形成在衬底201的界面，例如结区203上的外延硅层205A；及形成在外延硅层205A上的一非晶硅层205B。此时，SPE-硅结构205A被搀杂了浓度范围从约1×1018原子/cm3～约1×1021原子/cm3的磷(P)或砷(As)。
如上述，在传统的方法中，衬底的界面上最先所形成的外延硅层，通过在约550℃～约650℃的温度范围内施行热处理方式约30分钟至约10小时的时间，被引发向非晶硅层再生长，此种外延硅层的再生长的结果是使得接触孔被填充外延硅层。
但是，除了使外延硅层205A再生长以填充接触孔100之外，本发明提供另外一种填充接触孔100的方法，亦即，依本发明，是将非晶硅层205B从SPE-硅结构205除去，且之后，在外延硅层205A上顺序地形金属硅化物层、阻挡金属层及金属层，从而填充接触孔100。如图3C所示，将提供对接触孔掩埋的详细说明。
如图3C所示，通过执行湿式蚀刻处理和/或干式蚀刻处理将非晶硅层205B去除，之后，在外延的硅层205A上依次形成第一金属层206、第二金属层207及第三金属层208。此处，第一金属层是基于从包括Ti、Co、及Ni的组中选择的材料。作为阻挡金属层的第二金属层207，由TiN及WN制成，而第三金属层则以W制成。
如图3D所示，执行回蚀刻处理或化学机械抛光(CMP)处理，直到第一金属层206、第二金属层207及第三金属层208保留于接触孔100内为止。此处，在后续的热处理之后，第一金属层206成为一金属硅化物层206A，亦即，第一金属层206成为TiSi2、CoSi2或NiSi层。
在使用SPE法之前，在衬底201的暴露部分，即衬底201的结区203上优选执行一种异位(ex-situ)湿清洁(wet cleaning)和/或干清洁处理，以使外延硅层205A由自衬底201作良好的生长。湿清洁处理使用氟化氢(HF)的清洁化学制品，对于干清洁处理，可使用应用氢(H2)气或氢(H2)与氮气(N2)的混合气体的等离子体处理过程。湿清洁处理及等离子体处理过程是在约室温～400℃的温度范围内执行的。
而且，在实施异位的湿洗或干清洁处理之后，可使用氢基气体对置入CVD装置中的结果得到的衬底结构进行热处理。此时，此种热处理过程被作为一种原位清洁处理执行，且亦可被省略。亦即，无论是否执行热处理过程，均可获得SPE-硅结构205。
另外，在从约500℃～约700℃的温度范围内形成SPE-硅结构205后，亦可在从约550℃～约650℃的温度范围内在氮环境中施行热处理过程约30分钟～约10小时的时间，使外延硅层205A再生长。
将非晶硅层205B去除后，在形成第一～第三金属层206、207与208之前，可湿洗和/或干清洁处理对外延的硅层205A作预处理。
特别的是，其上形成有SPE-硅结构205的CVD装置的各种范例，均为一种低压(LP)CVD装置、非常低压(VLP)CVD装置、等离子体增强(DE)CVD装置、超高真空(UHV)CVD装置、快热(RT)CVD装置、大气压(AP)CVD装置、及分子束外延(MBE)。第一～第三金属层206～208可形成于上述所列出中的CVD装置及一物理气相沉积(PVD)装置中之一。此外，SPE-硅结构205被掺杂以磷或砷。
依本优选实施例，具有第一～第三金属层、及不执行用于外延层再生长的热处理过程所获得的SPE-硅结构的接触孔的掩埋(burial)，具有降低接触塞的电阻率的效果。同样的，由于在外延硅层保留于接触孔内的同时将非晶硅层去除，故不须施行后续在约550℃～约650℃温度范围中用以令外延层再生长的热处理过程。结果，可以获得简化的处理以及热预算的减少。另外，还有一种功效为，依本发明所形成的接触塞具有低的接触电阻，故可提高半导体设备的可靠性与产出。
本申请包括涉及2004年6月9日向韩国专利局所提交的第KR42309号韩国专利申请的主题，这里参考引用其全部内容。
此外，上面已经描述了本发明的若干特定实施例，很明显，对本专业技术人员而言，在不脱离如权利要求所限定的本发明的精神和范围的情况下，可对本发明进行多种变化或修饰。
主要元件符号说明
100接触孔
101硅衬底
102栅极结构
103结区
104绝缘层
105掺有杂质的硅层
201硅衬底
202栅极结构
203结区
204绝缘层
205SPE-硅结构
206第一金属层
207阻挡金属层
208金属层
220接触塞

Claims (27)

1.一种半导体设备，包括：
一衬底结构，其具有一接触孔以暴露其一预定的部分；及
一在该接触孔上形成的接触塞，其中该接触塞具有填充于该接触孔一部分中的一外延硅层，及通过填充所述接触孔的剩余部分形成于该外延硅层上的一金属层，其中该外延硅层是一初始外延硅结构的一组成部分，该初始外延硅结构是通过在不伴随热处理的情况下执行固相外延方法获得的。
2.如权利要求1的半导体设备，其中该初始外延硅结构包括所述外延硅层及一非晶硅层。
3.如权利要求1的半导体设备，其中该初始外延硅结构是在范围从500℃至700℃的温度下使用硅烷SiH4/磷化氢PH3形成的。
4.如权利要求1的半导体设备，其中该外延硅层被掺杂浓度范围从1×1018原子/cm3至1×1021原子/cm3的磷P及砷As中的一种。
5.如权利要求1的半导体设备，其中该初始外延硅结构的获得与使用一种氢基气体并在初始外延硅结构形成之前被原位应用的热处理无关。
6.如权利要求1的半导体设备，其中在初始外延硅结构形成之后，执行用于再生长外延硅层的热处理。
7.如权利要求1的半导体设备，还包括在该外延硅层及该金属层间顺序地形成一金属硅化物层及一阻挡金属层。
8.如权利要求1的半导体设备，其中该金属层包括钨。
9.如权利要求7的半导体设备，其中该金属硅化物层是基于从包括硅化钛TiSi2、硅化钴CoSi2及硅化镍NiSi的组中选择的材料。
10.如权利要求7的半导体设备，其中该阻挡金属层是基于从氮化钛TiN及氮化钨WN中选择的一种材料。
11.如权利要求1的半导体设备，其中该衬底结构包括：
形成在一衬底上的多个栅极结构；
形成在设置于所述多个栅极结构间的该衬底的若干部分上的多个结区；及
覆盖所述多个栅极结构的一绝缘层。
12.如权利要求11的半导体设备，其中该接触孔暴露一单元区中的晶体管的结区。
13.一种用以制造一半导体设备的方法，包括以下步骤：
暴露衬底结构的一部分，由此形成一接触孔；
在该接触孔上顺序地形成一外延硅层及一金属层，由此获得一接触塞；
其中形成该接触塞的步骤包括以下步骤：通过执行一种固相外延方法在接触孔上形成含有所述外延硅层及一非晶硅层的一外延硅结构；
去除所述非晶硅层；及
在所述外延硅层上形成所述金属层。
14.如权利要求13的方法，其中，形成所述外延硅结构的步骤是在范围从500℃至700℃的温度下使用SiH4/PH3气体进行的。
15.如权利要求13的方法，其中该外延硅结构掺杂有磷及砷两者之一，其浓度范围在1×1018原子/cm3至1×1021原子/cm3之间。
16.如权利要求13的方法，其中，形成接触塞的步骤进一步包括在形成外延硅结构的步骤后，执行热处理用于再生长该外延硅层的步骤。
17.如权利要求13的方法，进一步包括以下步骤：在外延硅层及金属层之间顺序地形成一金属硅化物层及一阻挡金属层。
18.如权利要求13的方法，其中形成金属层的步骤包括以下步骤：
在该外延硅层上顺序地形成金属硅化物层及阻挡金属层；
在该阻挡金属层上形成所述金属层；及
执行回蚀刻处理及化学机械抛光处理中的一种处理，直到所述金属硅化物层、阻挡金属层、及金属层保留在接触孔的内部为止。
19.如权利要求18的方法，其中该金属硅化物层基于从包含TiSi2、CoSi2及NiSi的组中选择的材料。
20.如权利要求18的方法，其中该阻挡金属层包括从TiN及WN中选择的一种材料。
21.如权利要求18的方法，其中该金属层包括钨。
22.如权利要求13的方法，其中，形成该接触塞的步骤进一步包括以下步骤：在通过执行固相外延方法形成外延硅结构前，使用湿清洁处理和干清洁处理之一对衬底结构的暴露部分实施清洁。
23.如权利要求13的方法，其中，形成接触塞的步骤进一步包括以下步骤：在执行固相外延方法形成外延硅结构前，使用湿清洁处理和干清洁处理对衬底结构的暴露部分实施清洁。
24.如权利要求13的方法，其中，形成接触塞的步骤进一步包括以下步骤：在形成金属层前，对去除非晶硅层后所暴露的外延硅层执行湿清洁处理和干清洁处理中的一种处理。
25.如权利要求13的方法，其中，形成接触塞的步骤进一步包括以下步骤：在形成金属层前，对去除非晶硅层后所暴露的外延硅层执行湿清洁处理和干清洁处理。
26.如权利要求13的方法，其中，形成接触塞的步骤进一步包括以下步骤：在形成外延硅层前，使用氢基气体执行原位热处理。
27.如权利要求13的方法，其中，在形成该接触孔的步骤，该衬底结构是通过以下步骤而准备的：
在一衬底上形成多个栅极结构；
在设置于所述多个栅极结构之间的衬底的若干部分上形成多个结区；
在所述多个栅极结构及衬底上形成一绝缘层；及
蚀刻该绝缘层，以围绕所述多个栅极结构。
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