TWI303098B - Semiconductor device with low contact resistance and method for fabricating the same - Google Patents
Semiconductor device with low contact resistance and method for fabricating the same Download PDFInfo
- Publication number
- TWI303098B TWI303098B TW093139348A TW93139348A TWI303098B TW I303098 B TWI303098 B TW I303098B TW 093139348 A TW093139348 A TW 093139348A TW 93139348 A TW93139348 A TW 93139348A TW I303098 B TWI303098 B TW I303098B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- epitaxial
- contact plug
- forming
- metal layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 59
- 239000004065 semiconductor Substances 0.000 title claims description 34
- 229910052751 metal Inorganic materials 0.000 claims description 67
- 239000002184 metal Substances 0.000 claims description 67
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 37
- 229910052732 germanium Inorganic materials 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 33
- 238000000348 solid-phase epitaxy Methods 0.000 claims description 19
- 238000010438 heat treatment Methods 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 claims description 13
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 11
- 229910052698 phosphorus Inorganic materials 0.000 claims description 11
- 239000011574 phosphorus Substances 0.000 claims description 11
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 claims description 10
- 239000007789 gas Substances 0.000 claims description 9
- 238000012545 processing Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 7
- DIOQZVSQGTUSAI-UHFFFAOYSA-N decane Chemical compound CCCCCCCCCC DIOQZVSQGTUSAI-UHFFFAOYSA-N 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 5
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 239000004576 sand Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 229910005883 NiSi Inorganic materials 0.000 claims description 2
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims 2
- NZIHMSYSZRFUQJ-UHFFFAOYSA-N 6-chloro-1h-benzimidazole-2-carboxylic acid Chemical compound C1=C(Cl)C=C2NC(C(=O)O)=NC2=C1 NZIHMSYSZRFUQJ-UHFFFAOYSA-N 0.000 claims 1
- IAOQICOCWPKKMH-UHFFFAOYSA-N dithieno[3,2-a:3',2'-d]thiophene Chemical group C1=CSC2=C1C(C=CS1)=C1S2 IAOQICOCWPKKMH-UHFFFAOYSA-N 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- MWRJCEDXZKNABM-UHFFFAOYSA-N germanium tungsten Chemical compound [Ge].[W] MWRJCEDXZKNABM-UHFFFAOYSA-N 0.000 claims 1
- 238000011065 in-situ storage Methods 0.000 claims 1
- 238000005360 mashing Methods 0.000 claims 1
- CXXKWLMXEDWEJW-UHFFFAOYSA-N tellanylidenecobalt Chemical compound [Te]=[Co] CXXKWLMXEDWEJW-UHFFFAOYSA-N 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 description 13
- 125000004429 atom Chemical group 0.000 description 10
- 238000004140 cleaning Methods 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 6
- 238000005108 dry cleaning Methods 0.000 description 4
- 150000002431 hydrogen Chemical class 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical group [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910018999 CoSi2 Inorganic materials 0.000 description 2
- 229910008479 TiSi2 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- -1 at this time Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- DDHRUTNUHBNAHW-UHFFFAOYSA-N cobalt germanium Chemical compound [Co].[Ge] DDHRUTNUHBNAHW-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000003303 reheating Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02428—Structure
- H01L21/0243—Surface structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02576—N-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02592—Microstructure amorphous
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
Description
1303098 九、發明說明: 【發明所屬之技術領域】 本發明係關於一種半導體技術,尤指一種具有低接觸 電阻的裝置(device,或稱元件,下稱裝置)及其製造方法。 【先前技術】 因半導體裝置業已高度積體化,故半導體裝置之尺寸 乃成爲小型化。因此,就動態隨機存取記憶體(DRAM)裝置 而言,大規模的聚積及尺寸的減小業已對胞電晶體(cell transistor)之接觸區形成極大的衝擊。亦即,因半導體裝置 業已高度積體化及小型化,故用於接觸區之面積乃亦因之 而減縮;但是,此種減縮的面積將導致接觸電阻的增加及 驅動電流的減少,此將更造成半導體裝置的降級,例如, 再新(refresh)特性及寫回復特性(tWR)等的降級。 因此,爲了減少接觸電阻並改善驅動電流,乃在一基 板之接合區摻入以高濃度的摻雜劑,或是在多矽層內摻入 目前用作摻雜劑之某種濃度的磷(p),用以增加接觸。但是 ,該等方法之缺點爲將增加洩漏電流且再新特性(tREF)及 資料保留時間均將降級。 上述之多矽層,係在一個批次型之爐內使用矽烷 (SiH4)/磷化氫(PH3)之氣體在約5 00°C至600°C的溫度範圍 內生成,此際,磷的摻入濃度範圍係自O.ixiO20原子/ cm3 至3.0x1 02G原子/ cm3。再者,即使多矽層之沈積生成係在 大氣壓力下使用氮氣作爲排氣氣體進行之’但是由於所產 生之氧的濃度有若千P Pm ’故多矽層及基板間之介面將形 1303098 $ _•個I薄的氧化層。此種薄氧化層即是增加接觸電阻的因 素之一,將使多砍層具有高準位的接觸電阻。結果,因半 導H裝置業已大幅積體化,上述使用多矽層用以形成接觸 的方法,對於改善接觸電阻及裝置特性極爲有限。 因此,乃有一種克服上述問題及限制的提案,係使用 一種單一型化學蒸汽沈積生長(CVD)裝置用以形成一外延 的矽層。其中一個代表性的方法係一種選擇性外延生長 (S E G)法,其係由一顯露的基板選擇性的生長一個外延之矽 層。雖然,經由s E G法之使用作成所希冀厚度而獲得良好 品質的外延矽層,但是S E G法須在8 5 0 °C之高溫作氫烘 (hydrogen bake)並在800 °C溫度成長該延展的砂層等的處 理,故實難以把SEG法應用於半導體裝置的製造加工上。 第1圖爲半導體基板構造圖,其中係利用一多矽層或 一外延矽層形成一接觸插塞。此處,101、102、103、104 、及1 〇 5分別爲一矽基板、一閘構造、一接合區、一絕緣 層、及一摻雜質的多矽層或摻雜質的外延矽層。 近來,使用固相外延(SPE)法用以形成一外延之矽構造 的方法成爲一種焦點提案,可用以克服使用S E G法之多矽 層所導致上述的問題與限制。SPE法最近成爲焦點的理由 係以低溫即可形成外延之矽構造且其摻雜物濃度不高。再 者,使用低摻雜物濃度即可完成SPE法。 依S P E法,摻雜以相當低濃度的磷暨使用S i η 4 / ρ η 3氣 體而在約5 00 °C至65 0 °C之溫度範圍下,即可形成無定形的 矽層。特別的是,磷的濃度範圍爲自lxl〇19原子/ cm3至1 -6- 1303098 χ102()原子/cm3。且實現SPE法後’外延之矽層係形成在底 部而無定形的矽層形成在外延之矽層上。 之後,在約5 5 0°C至650°C之溫度範圍下,於一氮氣環 境中實行約3 0分鐘至1 0小時的熱處理,則經此種的熱處 理,外延之矽層乃自基板之介面至一接觸的上方區域作再 生長,並因而,SPE乃引用於此一再生長之外延矽層。 如上述,把多矽層用作接觸材料時,磷的摻入濃度須 大於1x1 02()原子/cm3俾可減少接觸電阻。但是,對於再新 特性仍爲降級,故仍爲一大問題。因外延之矽層係以介面 特性作改善,故即使是施加低濃度的磷,其亦可保持相當 低準位的接觸電阻。 但是,100nm以下半導體技術中之大規模積體更須保 持極低的接觸電阻。故而,因外延矽之電阻性約爲Ιχΐ 〇·3 m Ω -cm且其甚難獲得低於上述數値的電阻性,故對於克服 電阻性仍有其限制。因之,倘將外延矽層應用於1 〇〇nm以 下或次一代的半導體技術中時,仍需開發一種用以形成接 觸插塞的方法,其中該插塞的接觸電阻在比較使用外延矽 層時之接觸電阻必須低下極多方可,再者,亦須可確實半 導體裝置之可靠性及產能等。 【發明內容】 本發明之目的,係提供一種具有低接觸電阻的半導體 裝置及其製造方法,足以獲得超高積體化半導體裝置之各 種電氣特性。 依本發明之一態樣,係提供一種半導體裝置,包括: 1303098 一具有一接觸孔之基板構造,用以顯露一預設的部分;及 一形成在接觸孔上之接觸插塞,其中接觸插塞設有充塡於 接觸孔內一部分之外延的矽層及形成在該外延矽層上之一 金屬層,係充塡於接觸孔內之其餘部分。 依本發明之另一態樣,係提供一種用於製造半導體裝 置的製造方法,包括以下步驟:將一基板構造的一部分顯 露而形成一接觸孔;及在接觸孔上依序形成一外延的矽層 及一金屬層,因而獲致一接觸插塞。 【實施方式】 依本發明具有低接觸電阻之半導體裝置及其製造方法 ,將舉示實施例並佐以附圖詳細說明如後。 在以下本發明之實施例中,除了使用外延之矽以獲得 較低的接觸電阻外,並建議使用金屬作爲接觸插塞的材料 。如眾所周知,因爲金屬的電阻性低於矽約1 0 0 0倍,故就 接觸電阻而言,使用金屬作爲接觸插塞之材料自屬最佳。 又者,使用金屬時,由接觸插塞至一接合面即無摻雜劑的 擴散,故於再新特性上即未有摻雜劑的效應存在。此外, 發生如同諸多金屬原子直接接觸外延矽之雜質及深準位雜 質等問題,可使用矽化物處理方式用以引起所使用的金屬 和以預定厚度生長的外延矽層一起作反應而解決之。嗣後 ,將對此種特殊構成的接觸插塞詳述之。 第2圖爲動態隨機存取記憶體(DRAM)裝置之一部分圖 示,其中接觸插塞係依本發明之一實施例作成。 如圖所示,包含多個閘構造202及一接合區203的多 1303098 數電晶體係形成在一矽基板201上。在一包圍閘構造202 之絕緣層204的一個預定部分上作蝕刻以形成一接觸孔 100,而位設在該接觸孔1〇〇間之該接合區203上則形成一 接觸插塞220。 詳言之,接觸插塞220係包括:形成在基板201上並 充塡入接觸孔1〇〇 —部分之一外延的矽層205A ;以薄形成 在外延矽層205 A及接觸孔100側壁上之一金屬矽化物層 206A及一阻擋金屬層207;以及形成在阻擋金屬層207上 並充塡入接觸孔1〇〇內其餘部分之一金屬層208。特別者 ,金屬矽化物層206A係在一原始沈積生長之金屬層、此一 金屬層之基礎材料係選自以鈦(Ti)、鈷(Co)及鎳(Ni)等組成 之群組、施作熱處理而獲得者。亦即,金屬矽化物層206A 可爲鈦矽化物(TiSi2)層、鈷矽化物(CoSi2)層及鎳矽化物 (Ni Si)層三者中的一者。阻擋金屬層207係以例如鈦氮化物 (TiN)或鎢氮化物(WN)之材料製成。金屬層20 8則爲鎢(W) 特別者,外延矽層205A係使用固相外延(SPE)法作成 而非爲熱處理方式。此時,外延矽層205 A之磷(P)或砷(As) 的摻雜濃度範圍約在lxl〇18原子/cm3至ΐχΐ〇2ι原子/cm3 間,且其電阻性約爲1 X 1 0_3m Ω - cm。較諸於多矽,外延矽 層205A在相當低的摻入濃度中即具有較低的電阻値。又者 ,金屬矽化物層20 6A、阻擋金屬層207及金屬層2〇8之電 低P 爲低 A者 05塞 2 插 層觸 矽接 延用 外習 較 比 均阻 値電 阻的 cbM 插 觸 接 之 明 發 本 依 之 因 1303098 第3 A〜3 D圖爲剖面圖,用以說明形成依本發明實施 例之接觸插塞的方法。此處,與第2圖之相同元件使用相 同符號。 如第3 A圖所示,在基板201上形成複數個閘構造202 因而形成多數的電晶體,之後,閘構造202間之基板201 的一部分上形成一接合區20 3。覆蓋各閘構造202底部、 上部、及諸側壁之一絕緣層204,係在形成諸電晶體的當 中並在電晶體形成後予以形成之。雖所舉示之絕緣層爲一 層,但絕緣層204亦可爲包括閘絕緣層、掩罩絕緣層及隔 片絕緣層等之複層式。之後,將絕緣層204之一部分敞開 以形成一接觸孔1 〇〇,係充塡有插塞材料者。 如第3B圖所示,利用固相外延(SPE)法在約5 00°C〜 7〇〇°C之範圍中使用矽烷(SiH4)/磷化氫(PH3)之氣體形成外 延的矽構造205。再者,於一化學性蒸汽沈積生成(CVD) 裝置中完成SPE法。嗣後,引用SPE法於SPE-矽構造而獲 取外延之矽構造。非爲熱處理之SPE-矽構造205包括形成 在基板201之介面,例如接合區203上的外延矽層205A; 及形成在外延矽層205A上之一無定形矽層205B。此時, SPE-砂構造205A係摻入濃度範圍約在ιχι〇18原子/cm3〜1 xlO21原子/ cm3的磷(P)或砷(As)。 如上述,在習用的方法中,基板之介面上最先所形成 的外延矽層,係施行熱處理方式,在約5 5 0 °C〜6 5 0 °C之溫 度範圍中,以約3 0分鐘至1 〇小時時間,將其朝向無定形 砂層作引伸的再成長,此種外延矽層之再成長結果,乃使 -10- 1303098 得接觸孔充塡以外延的矽層。 但是,除了使外延矽層再成長以充塡接觸孔1 〇〇的方 式外,關於充塡接觸孔1 00,本發明另提供一種不同的方 法,亦即,依本發明,係將無定形之矽層2 0 5 B由SPE-矽 構造205去除之,且之後,在外延的矽層205A上依序形成 以金屬矽化物層、阻擋金屬層及金屬層,因而亦可充塡接 觸孔1 00。如第3 C圖所示,可就接觸孔埋底作詳細說明。 如第3 C圖所示,施行濕式蝕刻加工及/或乾式蝕刻加 工將無定形之矽層205B去除之,之後,在外延之矽層205A 上依次形成第1金屬層206、第2金屬層207及第3金屬 層20 8。此處,第1金屬層之基礎材料係選自以Ti、Co、 及Ni所組成的群組。作爲阻擋金屬層之第2金屬層207, 係以TiN及WN製成,而第3金屬層則以W製成。 如第3D圖所示,遂行蝕回處理或化學機械拋光(CMP) 處理,直到第1金屬層206、第2金屬層207及第3金屬 層20 8殘留於接觸孔100內爲止。此處,在後續的熱處理 之後,第1金屬層206乃成爲一金屬矽化物層20 6A,亦即 ,第1金屬層206係成爲TiSi2、CoSi2或NiSi層。 在使用SPE法之前,於基板201之顯露部分,例如基 板201之接合區203上最好施作一種在位的濕式清理及/或 乾式清理過程,俾可令外延的矽層205A由基板201作良好 的生長。濕式清理過程係使用氫氟(HF)之清理用化學物, 而乾式清理過程者,係使用氫(H2)氣或氫(H2)與氮氣(N2) 的混合氣體的電漿處理過程。濕式清理過程及電漿處理過 -11- 1303098 程係室溫〜400 °C的溫度範圍內達成之。 實施在位的濕式清理或乾式清理過程之後的基板構造 係置入CVD裝置中,其可使用氫基氣體作熱處理。此際, 此種熱處理過程係作爲一種在位的清理過程遂行之,且亦 可省略。亦即,無論是否有施作熱處理過程,均可獲得SPE-矽構造2 0 5。 又者,於溫度範圍約5 00t〜700°C中形成SPE-矽構造 205後,亦可在溫度範圍約5 5 0 °C〜6 5 0 °C之氮環境中以約 3 0分鐘〜1 0小時之時間施行熱處理過程,使外延的矽層 205A作再成長。 將無定形之矽層205B去除後,於形成第1〜第3金屬 層206、207與208之前,可將外延之矽層205A以濕式清 理或乾式清理過程作預處理。 特別的是,其上形成有SPE-矽構造205之CVD裝置 各種範例,均爲一種低壓(LP)CVD裝置、極低壓(VLP)CVD 裝置、電漿增強(PE)CVD裝置、超高真空(UHV)CVD裝置 、急熱(RT)CVD裝置、大氣壓(AP)CVD裝置、及分子束外 延(MB E)。上述所列出中之任何一種CVD裝置及一物理性 蒸汽沈積生成(PVD)裝置均可用以形成第1〜第3金屬層 206〜20 8 〇此外,SPE-矽構造205係摻雜以磷或砷。 依本實施例,具有第1〜第3金屬層、及不須實行熱 處理過程用以令外延層再生長所獲得的SPE-矽構造、等之 接觸孔的埋底(burial),具有降低接觸插塞之電阻的功效。 同樣的,當外延矽層殘留於接觸孔內之同時係將無定形矽 -12- 1303098 層去除,故不須施行後續5 5 0°C〜6 5 0 °C溫度範圍中用以令 外延矽層再生長的熱處理過程.。結果,除了可簡化加工處 理流程外並可減除熱處理之費用。又者,另一種功效爲, 依本發明所形成之接觸插塞,其接觸電阻甚低,故可改善 半導體裝置之可靠性與產能。 本申請案所含之主題與意旨係對應於2004年6月9日 在韓國專利局所申請之第KR 42309號專利申請案,該韓國 專利申請案之全篇內容可供本案之參照。 另者,本發明業已舉示某些實施例說明如上,惟應陳 明者,乃此道技術行家自可作不同的改變與修飾,但均不 脫離本發明之創新精神與技術思想,均應屬本發明專利保 護範疇。 【圖式簡單說明】 弟1圖爲半導體基板構造之圖不,其中係利用多砂及 外延矽兩者中之一者形成習用之接觸插塞。 弟2圖爲半導體基板構造之圖不,其中係依本發明之 一實施例形成接觸插塞。 第3A〜3D圖爲剖面圖,用以說明製造依本發明一實 施例之接觸插塞的方法。 【主要元件符號說明】 100 接觸孔 10 1 矽基板 102 閘構造 103 接合區 -13- 絕緣層 摻有雜物之矽層 矽基板 閘構造 接合區 絕緣層 S P E -矽構造 第1金屬層 阻擋金屬層 金屬層 接觸插塞 -14-
Claims (1)
1303098— X
^?n ί B 方法」專利案 _ 具有低接觸電阻的半導體元件及其製造 (2007年3月修正) 十、申請專利範圍: 1 . 一種具有外延矽層之半導體接觸插塞’包括: 基板構造,設有一接觸孔用以顯露一預定的部分; 形成在該接觸孔上之接觸插塞,其中該接觸插塞設 有充塡於該接觸孔一部分中的一外延矽層,及形成於該 外延矽層上之一金屬層,係用以充塡該接觸孔之其餘部 # 分;以及 依序形成在該外延矽層及該金屬層間之一金屬矽化 物層及一阻障金屬層。 2 ·如申請專利範圍第1項之半導體接觸插塞,其中該外延 矽層係一原始外延之矽構造的一個成分,該原始外延之 矽構造係不須伴同熱處理而僅遂行一種固相外延即可獲 得者。 3 ·如申請專利範圍第2項之半導體接觸插塞,其中該原始 ® 外延之矽構造包括外延的矽層及一無定形的矽層。 4·如申請專利範圍第2項之半導體接觸插塞,其中該原始 外延之矽構造係在約5 0 0 °C至7 0 0 °C之溫度範圍內使用矽 烷(SiH4)/磷化氫(PH3)形成者。 5 .如申請專利範圍第2項之半導體接觸插塞,其中該外延 之矽層係摻雜濃度範圍約在1 X 1018原子/cm3至1 X 1〇21 原子/cm3之磷(P)及砷(As)兩者中之一者。 1303098 6 ·如申請專利範圍第2項之半導體接觸插塞’其中該原始 外延之矽構造的獲得與熱處理不相關聯,而係使用一種 氫基氣體,並在原始外延之矽層形成前在原位作施加者 〇 7 .如申請專利範圍第2項之半導體接觸插塞,其中在原始 外延之矽構造形成之後,可選用遂行熱處理,用以令外 延之矽層作再生長。 8·如申請專利範圍第1項之半導體接觸插塞,其中該金屬 層包括鎢。 9.如申請專利範圍第1項之半導體接觸插塞,其中該金屬 矽化物層係以選自以鈦矽化物(TiSi2)、鈷矽化物(C〇Si2) 及鎳矽化物(NiSi)所構成群組(group)之材料爲基礎者。 1 〇 .如申請專利範圍第1項之半導體接觸插塞,其中該阻障 金屬層係以選自鈦氮化物(TiN)及鎢氮化物(WN)兩者中 之一的材料爲基礎者。 1 1 ·如申請專利範圍第1項之半導體接觸插塞,其中該基板 構造包括: 形成在一基板上多數個閘構造; 形成在該基板之複數個部分上之複數個接合區,該 基板則係位設在該等閘構造間;及 用以覆蓋該等閘構造之一絕緣層。 1 2 .如申請專利範圍第 1 0項之半導體接觸插塞,其中該接 觸孔係顯露一胞區(cell region)中之一電晶體的接合區 -2- 1303098 1 3 · —種用以製造具有外延矽層之半導體接觸插塞之方法, 包括以下步驟: 將一基板構造的一部分予以顯露,因而形成一接觸 孔; 在該接觸孔上依次形成一外延的矽層及一金屬層, 因而獲得一接觸插塞;以及 在外延的矽層及金屬層之間依序形成一金屬矽化物 層及一阻障金屬層。 1 4 ·如申請專利範圍第 1 3項之方法,其中用以形成該接觸 0 插塞之步驟所包括之步驟爲·· 在接觸孔上以遂行一種固相外延(SPE)之方法形成 含有外延矽層及一無定形矽層之一外延矽構造; 去除該無定形矽層;及 在外延之矽層上形成金屬層。 15·如申請專利範圍第 14項之方法,其中用以形成外延之 矽構造係在約5 0 0 °C至7 0 0 °C之溫度範圍內使用S i Η 4 / Ρ Η 3 之氣體進行者。 · 1 6 ·如申請專利範圍第 1 4項之方法,其中該外延之矽構造 摻雜有磷及砷兩者中之一者,其濃度範圍在約1Χ1018 原子/cm3至1Χ1021原子/cm3之間。 1 7 ·如申請專利範圔第 1 4項之方法,其中用以形成接觸插 塞之步驟尙包括以下步驟:在形成外延之矽構造之步驟 後,可作熱處理以令該外延的矽層作再生長。 1 8 .如申請專利範圍第 1 3項之方法,其中形成金屬層之步 1303098 驟包括以下的步驟: 在該外延的矽層上依次形成金屬矽化物層及阻障金 屬層; 在阻障金屬層上形成金屬層;及 遂行蝕回(etch-back)處理及化學機械拋光處理兩種 中之一種處理,直到金屬矽化物層、阻障金屬層、及金 屬層殘留於接觸孔的內側爲止。 1 9 ·如申請專利範圍第 1 8項之方法,其中該金屬矽化物層 係以選用來自Ti Si 2、CoS i2及Ni Si所構成群組之材料 ® 爲基礎者。 20·如申請專利範圍第 1 8項之方法,其中該阻障金屬層之 材料係選自TiN及WN兩者中之一者。 2 1 ·如申請專利範圍第 1 8項之方法,其中該金屬層包括鎢 〇 22·如申請專利範圍第 14項之方法,其中用以形成該接觸 插塞之步驟尙包括以下步驟:在以S P E法形成外延之矽 構造前,使用濕式淸理加工或乾式淸理加工方式對基板 β 構造之顯露部分實施淸理。 2 3 ·如申請專利範圍第 1 4項之方法,其中用以形成接觸插 塞之步驟尙包括以下步驟:以SPE法形成外延之矽構造 前,使用濕式淸理加工及乾式淸理加工對基板構造之顯 露部分實施淸理。 2 4 ·如申請專利範圍第 1 4項之方法,其中用以形成接觸插 塞之步驟尙包括以下步驟:在形成金屬層前,對去除無 -4- 1303098 定形之矽層後所顯露的外延矽層以濕式淸理加工或乾式 淸理加工作淸理。 25.如申請專利範圍第14項之方法,其中用以形成接觸插 塞之步驟尙包括以下步驟:在形成金屬層前,對去除無 定形之砂層後所顯露的外延矽層以濕式淸理加工或乾式 淸理加工作淸理。 26·如申請專利範圍第I4項之方法,其中用以形成接觸插 塞之步驟尙包括以下步驟:在實現外延之矽層前,利用 一種氫基氣體遂行一種在位的(in-situ)熱處理。 馨 27·如申請專利範圍第13項之方法,其中在形成該接觸孔 之步驟上,該基板構造係經由以下諸步驟而作成: 在一基板上形成多數個閘構造; 在位於.複數個閘構造間之基板的複數個部分上形成 複數個接合區; 在閘構造及基板上形成一絕緣層;及 蝕刻該絕緣層,以圍住該等閛構造。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040042309A KR100603588B1 (ko) | 2004-06-09 | 2004-06-09 | 낮은 콘택 저항을 갖는 반도체 소자 및 그 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200541052A TW200541052A (en) | 2005-12-16 |
TWI303098B true TWI303098B (en) | 2008-11-11 |
Family
ID=35459687
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093139348A TWI303098B (en) | 2004-06-09 | 2004-12-17 | Semiconductor device with low contact resistance and method for fabricating the same |
Country Status (5)
Country | Link |
---|---|
US (1) | US7498218B2 (zh) |
JP (1) | JP2005354029A (zh) |
KR (1) | KR100603588B1 (zh) |
CN (1) | CN100435284C (zh) |
TW (1) | TWI303098B (zh) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100681208B1 (ko) | 2004-12-29 | 2007-02-09 | 주식회사 하이닉스반도체 | 이중층 구조의 랜딩플러그콘택을 구비하는 반도체 소자 및그의 제조 방법 |
KR100637690B1 (ko) * | 2005-04-25 | 2006-10-24 | 주식회사 하이닉스반도체 | 고상에피택시 방식을 이용한 반도체소자 및 그의 제조 방법 |
JP2008047720A (ja) * | 2006-08-17 | 2008-02-28 | Elpida Memory Inc | 半導体装置の製造方法 |
JP2009200255A (ja) * | 2008-02-21 | 2009-09-03 | Toshiba Corp | 半導体装置及びその製造方法 |
US8815710B2 (en) * | 2008-06-10 | 2014-08-26 | Sumco Corporation | Silicon epitaxial wafer and method for production thereof |
JP2011243960A (ja) * | 2010-04-21 | 2011-12-01 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP6009237B2 (ja) * | 2012-06-18 | 2016-10-19 | Sumco Techxiv株式会社 | エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ |
JP5845143B2 (ja) | 2012-06-29 | 2016-01-20 | 株式会社Sumco | エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ |
KR102269228B1 (ko) | 2014-07-31 | 2021-06-25 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
US9330972B2 (en) * | 2014-08-12 | 2016-05-03 | Globalfoundries Inc. | Methods of forming contact structures for semiconductor devices and the resulting devices |
US9805973B2 (en) * | 2015-10-30 | 2017-10-31 | International Business Machines Corporation | Dual silicide liner flow for enabling low contact resistance |
US9685389B1 (en) * | 2016-02-03 | 2017-06-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Formation of getter layer for memory device |
KR20180076424A (ko) * | 2016-12-27 | 2018-07-06 | 에스케이하이닉스 주식회사 | 반도체장치 및 그 제조 방법 |
JP2020043163A (ja) * | 2018-09-07 | 2020-03-19 | キオクシア株式会社 | 半導体装置 |
JP2020043162A (ja) | 2018-09-07 | 2020-03-19 | キオクシア株式会社 | 半導体装置 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4966868A (en) * | 1988-05-16 | 1990-10-30 | Intel Corporation | Process for selective contact hole filling including a silicide plug |
JPH0234930A (ja) | 1988-07-25 | 1990-02-05 | Matsushita Electron Corp | 半導体装置の製造方法 |
JPH02125615A (ja) * | 1988-11-04 | 1990-05-14 | Nec Corp | 半導体装置の形成方法 |
JPH0311737A (ja) * | 1989-06-09 | 1991-01-21 | Seiko Epson Corp | 固相エピタキシャル |
KR960004095B1 (en) | 1993-02-17 | 1996-03-26 | Hyundai Electronics Ind | Manufacturing method of metal plug in contact-hole |
JPH07130682A (ja) * | 1993-11-02 | 1995-05-19 | Nippon Steel Corp | 半導体装置の製造方法 |
JP2877108B2 (ja) * | 1996-12-04 | 1999-03-31 | 日本電気株式会社 | 半導体装置およびその製造方法 |
US6372566B1 (en) | 1997-07-03 | 2002-04-16 | Texas Instruments Incorporated | Method of forming a silicide layer using metallic impurities and pre-amorphization |
KR100559029B1 (ko) | 1998-12-29 | 2006-06-16 | 주식회사 하이닉스반도체 | 반도체 소자의 메탈 콘택 형성 방법 |
JP2001148472A (ja) * | 1999-09-07 | 2001-05-29 | Nec Corp | 半導体装置及びその製造方法 |
US6455424B1 (en) * | 2000-08-07 | 2002-09-24 | Micron Technology, Inc. | Selective cap layers over recessed polysilicon plugs |
JP2003188252A (ja) * | 2001-12-13 | 2003-07-04 | Toshiba Corp | 半導体装置及びその製造方法 |
US6511905B1 (en) * | 2002-01-04 | 2003-01-28 | Promos Technologies Inc. | Semiconductor device with Si-Ge layer-containing low resistance, tunable contact |
KR100637690B1 (ko) * | 2005-04-25 | 2006-10-24 | 주식회사 하이닉스반도체 | 고상에피택시 방식을 이용한 반도체소자 및 그의 제조 방법 |
-
2004
- 2004-06-09 KR KR1020040042309A patent/KR100603588B1/ko active IP Right Grant
- 2004-12-17 TW TW093139348A patent/TWI303098B/zh not_active IP Right Cessation
- 2004-12-28 US US11/025,487 patent/US7498218B2/en active Active
- 2004-12-28 JP JP2004382103A patent/JP2005354029A/ja active Pending
-
2005
- 2005-01-17 CN CNB2005100023396A patent/CN100435284C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR100603588B1 (ko) | 2006-07-24 |
US20050275102A1 (en) | 2005-12-15 |
KR20050117107A (ko) | 2005-12-14 |
US7498218B2 (en) | 2009-03-03 |
TW200541052A (en) | 2005-12-16 |
JP2005354029A (ja) | 2005-12-22 |
CN100435284C (zh) | 2008-11-19 |
CN1707756A (zh) | 2005-12-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100435284C (zh) | 具有低接触电阻的半导体设备及其制造方法 | |
TWI261309B (en) | Semiconductor device with epitaxial C49-titanium silicide (TiSi2) layer and method for fabricating the same | |
TWI255007B (en) | Method of fabricating a semiconductor device having reduced contact resistance | |
US8741710B2 (en) | Methods of fabricating semiconductor devices using a plasma process with non-silane gas including deuterium | |
JP4967313B2 (ja) | 半導体装置の製造方法 | |
JP4345875B2 (ja) | 半導体素子のコンタクトプラグ形成方法 | |
JP4748408B2 (ja) | 半導体装置のメタルシリサイド層形成方法 | |
KR20020003625A (ko) | 금속 게이트 모스팻 소자의 제조방법 | |
TW200425411A (en) | Integrating n-type and p-type metal gate transistors | |
JP2006310717A (ja) | 固相エピタキシー方式を用いた半導体素子及びその製造方法 | |
TW200423400A (en) | Schottky barrier transistor and method of manufacturing the same | |
KR100637101B1 (ko) | 에피택셜 스택과 금속층의 이중 구조로 된 콘택플러그를구비하는 반도체소자 및 그의 제조 방법 | |
TW200539323A (en) | Polycrystalline SiGe junctions for advanced devices | |
TW200845157A (en) | Stable silicide films and methods for making the same | |
US7407871B2 (en) | Method for passivation of plasma etch defects in DRAM devices | |
TW201126576A (en) | Plasma doping method and method for fabricating semiconductor device using the same | |
TWI732976B (zh) | 形成矽化物的方法 | |
JP2004128314A (ja) | 半導体装置の製造方法 | |
EP2562803B1 (fr) | Procédé de réalisation d'un dispositif à transistors contraints à l'aide d'une couche externe, et dispositif | |
JP3923014B2 (ja) | トレンチを備えたメモリーセルおよびその製造方法 | |
JP2007158259A (ja) | 半導体装置およびその製造方法 | |
US20060286756A1 (en) | Semiconductor process and method for reducing parasitic capacitance | |
JP4510707B2 (ja) | エピタキシャル膜の形成方法と、これを用いた薄膜形成方法、及び半導体装置の製造方法 | |
KR20070035362A (ko) | 반도체 소자 및 그 제조방법 | |
JPH1174507A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |