TWI732976B - 形成矽化物的方法 - Google Patents

形成矽化物的方法 Download PDF

Info

Publication number
TWI732976B
TWI732976B TW106142844A TW106142844A TWI732976B TW I732976 B TWI732976 B TW I732976B TW 106142844 A TW106142844 A TW 106142844A TW 106142844 A TW106142844 A TW 106142844A TW I732976 B TWI732976 B TW I732976B
Authority
TW
Taiwan
Prior art keywords
type silicon
highly doped
silicon layers
titanium silicide
substrate
Prior art date
Application number
TW106142844A
Other languages
English (en)
Other versions
TW201828340A (zh
Inventor
華 仲
馬蒂亞斯 包爾
紹芳 諸
沙堤西 古波若
Original Assignee
美商應用材料股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商應用材料股份有限公司 filed Critical 美商應用材料股份有限公司
Publication of TW201828340A publication Critical patent/TW201828340A/zh
Application granted granted Critical
Publication of TWI732976B publication Critical patent/TWI732976B/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02142Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H01L21/02153Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing titanium, e.g. TiSiOx
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051Deposition of metallic or metal-silicide layers
    • H01L21/32053Deposition of metallic or metal-silicide layers of metal-silicide layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02043Cleaning before device manufacture, i.e. Begin-Of-Line process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本案揭露內容大致上關於在基板上選擇性形成矽化鈦的方法。大致上與接觸件結構整合方案一併利用該等方法。一個實施例中,在基板上選擇性形成矽化鈦材料而作為源極/汲極區域上的界面層。可在約攝氏400度至約攝氏500度的範圍內的溫度形成矽化鈦層。

Description

形成矽化物的方法
本案揭露內容之實施例大致上關於矽化物的形成,諸如用在接觸件整合方案中的矽化物。
矽化鈦是半導體元件製造中用於矽化物接觸件的大有可為的材料。然而,矽化鈦的化學氣相沉積(CVD)在低於800°C的溫度不具選擇性。此外,習知的矽化鈦具有低於期望的正形度,造成矽化物形成期間矽的消耗。再者,習知矽化鈦形成製程經常與後沉積退火一併使用以形成低電阻率相的矽化物。上述變數經常耗時且與先進節點接觸件結構整合方案的熱預算不相容。
因此,需要改善的矽化物形成方法。
一個實施例中,一種形成矽化鈦層的方法包括:在處理腔室中將基板加熱到範圍在約攝氏400度至約攝氏500度內的溫度;在將處理腔室內的壓力維持在約10托耳至約100托耳之間的同時,同步地將該基板暴露至矽前驅物及鈦前驅物,該鈦前驅物包括TiCl4 ;以及在該基板上形成矽化鈦層。
另一實施例中,一種形成矽化鈦層的方法包括:在處理腔室中將基板加熱到範圍在約攝氏400度至約攝氏500度內的溫度,其中該基板包括矽層,該矽層具有濃度範圍在約1x1018 原子/cm3 至約4x1021 原子/cm3 內的n型摻雜劑;在將處理腔室內的壓力維持在約80托耳至約100托耳之間的同時,同步地將該基板暴露至矽前驅物及鈦前驅物,該鈦前驅物包括TiCl4 ;以及在該矽層上形成矽化鈦層。
另一實施例中,一種形成矽化鈦層的方法包括:在處理腔室中將基板加熱到範圍在約攝氏400度至約攝氏500度內的溫度,其中該基板包括在該基板上的鍺層;在將處理腔室內的壓力維持在約80托耳至約100托耳之間的同時,同步地將該基板暴露至矽前驅物及鈦前驅物,該鈦前驅物包括TiCl4 ;以及在該鍺層上形成矽化鈦層。
本案揭露內容大致上關於在基板上選擇性形成矽化鈦的方法。大致上與接觸件結構整合方案一併利用該等方法。一個實施例中,在基板上選擇性形成矽化鈦材料而作為源極/汲極區域上的界面層。可在約攝氏400度至約攝氏500度的範圍內的溫度形成矽化鈦層。所得的矽化鈦呈現期望的接觸電阻及在先進接觸件整合方案中的可應用性。
第1圖說明根據本文所述之一個實施例的方法100的操作。在操作102,基板經受預清潔製程。該基板為矽基板(諸如n型矽基板),然而,作為替代方案,該基板可為鍺或矽鍺基板。該基板包括形成於該基板上的一或多個源極/汲極(S/D)區域、接觸件溝槽、或類似物。該S/D區域是由磊晶材料形成或包括沉積在該S/D區域上的磊晶材料。該S/D區域是各別以n型或p型摻雜劑摻雜的矽、鍺、或矽鍺。
本文所述的磊晶材料包括下述之一或多者:矽、摻雜磷的矽、高度應變摻雜磷的矽、鍺、摻雜磷的鍺、矽鍺、或摻雜磷的矽鍺。雖然可針對n型摻雜劑(諸如磷)描述本文的實施例,但考慮可利用其他的摻雜劑,包括砷及銻。也可利用p型摻雜劑,包括硼、鋁、鎵及銦。
預清潔製程從基板、S/D區域、及/或S/D區域上形成的磊晶層的表面移除原生氧化物或其他污染物。適合的預清潔製程包括可購自美國加州Santa Clara的應用材料公司的SICONI®預清潔製程。然而,考量也可根據本文所述之實施例實行來自其他製造商的適合的清潔製程。
於操作102清潔基板之後,在操作104將n型矽層沉積在S/D區域上方。該n型矽層是在低溫(例如約攝氏400度至約攝氏500度)化學氣相沉積(CVD)製程中沉積。n型矽是透過矽前驅物沉積,該矽前驅物諸如甲矽烷(SiH4 )或更高級的矽烷,包括Si2 H6 、Si3 H8 、及Si4 H10 。在CVD製程期間可將n型摻雜劑(諸如磷摻雜劑,例如磷化氫)納入處理氣體中,以摻雜n型矽達到期望的摻雜劑水準。可利用遮蔽及/或蝕刻操作以在期望區域沉積n型矽層。操作104中,若視情況任選的磊晶材料存在於S/D區域上,則n型矽層沉積在該視情況任選的磊晶材料上。
接著,於操作106,將高度摻雜的n型矽層沉積在n型矽層上。該高度摻雜的n型矽層可為非晶、結晶、或多晶矽。該高度摻雜的矽層是以與操作104中沉積的n型矽層相同的方式沉積。這樣的範例中,使用相同的前驅物與摻雜劑沉積該n型矽層,但該n型矽層被摻雜至更大的n型摻雜劑濃度。一個範例中,將該高度摻雜的n型矽層摻雜到約1x1018 原子/cm3 至約4x1021 原子/cm3 的濃度。相對更高的摻雜劑濃度有助於在上面生長金屬矽化物膜,如針對操作108所討論。可將該高度摻雜的n型矽層沉積達範圍為約1奈米至約10奈米內的厚度,諸如3奈米至約7奈米,例如約5奈米或更小。
在操作108中,矽化鈦層形成於操作106的高度摻雜的n型矽層上。該矽化鈦層是在範圍為約10托耳至約100托耳(諸如約80托耳至約100托耳)內的腔室壓力形成。形成矽化鈦層期間,基板的溫度維持在約攝氏400度至約攝氏500度的範圍內。相信本文所述的溫度及壓力範圍助於矽化鈦層的成核。矽化鈦層的沉積速率隨著溫度而不同。一個範例中,矽化鈦層的生長速率範圍是從在攝氏400度每分鐘約3.5埃至在攝氏500度每分鐘約100埃。
矽化鈦層是在CVD製程中使用矽前驅物與鈦前驅物形成,該CVD製程諸如單一沉積步驟熱CVD(例如無電漿)製程,該矽前驅物與該鈦前驅物透過同步流動進入處理腔室而同步地暴露至基板。一個範例中,矽前驅物是甲矽烷,且是以約10-120sccm(諸如約100sccm)的流速提供該矽前驅物。視情況任選,可與該甲矽烷同步提供乙矽烷或更高級的矽烷,以助於矽化。鈦前驅物是TiCl4 ,且是以約0.1至約1sccm(諸如約0.2sccm)的流速提供該鈦前驅物。該矽前驅物氣體與該鈦前驅物氣體可與載氣共同流動,該載氣諸如氫氣,流速為10sccm至約100sccm,諸如約20sccm。
一個範例中,根據本文所述之製程生長的矽化鈦層具有約Si0.95Ti0.05的組成。另一範例的矽化鈦層具有25微歐姆/cm或更小的電阻率,諸如20微歐姆/cm或更小。此外,根據上述製程生長的矽化鈦層呈現對抗氧化物及氮化物(諸如氧化矽、氮化矽、及氧碳化矽)的選擇性。
視情況任選地,在操作110中,可執行一或多個後矽化製程。後矽化製程可包括用於完成元件處理的額外製程。示範性製程包括矽化鈦層的鈍化。鈍化可包括將該矽化鈦層暴露至氮電漿,或將氮化鈦層沉積在矽化鈦層上方。另外,後矽化製程包括動態表面退火、金屬插塞形成(例如鎢或鈷插塞)、及類似操作。
雖然第1圖說明一個實施例,但也考慮其他實施例。另一實施例中,考慮可排除操作104。另一範例中,該高度摻雜的n型矽層(於操作106中形成)可視情況任選地由鍺層或高度摻雜的n型鍺層所取代。另一範例中,作為替代方案或附加方案,該高度摻雜的n型矽層可包括鈦以作為摻雜劑。這樣的範例中,TiCl4可與其他前驅物共流,該其他前驅物諸如矽前驅物及視情況任選的n型摻雜劑。可以約0.1sccm至約1sccm(諸如約0.2sccm)的流速提供TiCl4。納入鈦有助於在操作108中形成的矽化鈦層的成核。
另一實施例中,可在操作106與108之間執行視情況任選的TiCl4 浸泡,以助於在操作108中形成的矽化鈦層的成核。TiCl4 浸泡可在約80托耳至約100托耳的壓力及約攝氏450度至約攝氏600度的溫度執行。可以50sccm至約100sccm的流速將TiCl4 引入處理腔室達約15秒至約120秒,諸如約30秒至90秒。
一個範例中,矽化鈦層根據本文所述之實施例生長。矽化鈦層形成於鍺膜上。所得的膜形成C49相,且呈現約90微歐姆/cm的電阻率。另一實施例中,矽化鈦層生長於以磷摻雜的結晶矽層上,該磷是在約1x1018 原子/cm3 至約4x1021 原子/cm3 的範圍內。所得的膜是形成於C49相,且呈現約140微歐姆/cm的電阻率。
另一實施例中,矽化鈦層生長於以磷摻雜的非晶矽層上,該磷是在約1x1018 原子/cm3 至約4x1021 原子/cm3 的範圍內。所得的膜是形成於C49相,且呈現約60微歐姆/cm的電阻率。另一實施例中,矽化鈦層生長於暴露至TiCl4 浴的矽層上,或是在TiCl4 存在下沉積的矽層上。所得的膜是形成於C54相,且呈現約25微歐姆/cm的電阻率。
本文態樣描述用於特定應用的各種流速。應注意,所提供的流速是針對300毫米(mm)基板,諸如300mm的半導體晶圓。考慮用於類似尺寸及不同尺寸基板的其他流速。
第2A圖與第2B圖說明根據本案揭露內容的實施例在各種條件下的矽化鈦膜。第2A圖說明不同溫度下甲矽烷流速為10sccm及50sccm的矽化鈦的生長速率的圖表220。如所說明,矽化鈦的生長溫度受溫度影響更甚於受流速影響。
第2B圖說明各種基板上矽化鈦的生長速率的圖表230。如第2B圖中所說明,矽化鈦生長在鍺、結晶高度摻雜SiP(例如,磷濃度為約1x1018 原子/cm3 至約4x1021 原子/cm3 )、非晶高度摻雜SiP、及鈦摻雜或TiCl4 浸泡的矽上。與此成對比,本案揭露內容的矽化鈦並未可觀地生長在氧化物、氮化物或磷濃度小於約1x1018 原子/cm3 的矽上(例如,選擇性抵抗上述氧化物、氮化物或磷濃度小於約1x1018 原子/cm3 的矽)。
第3圖說明根據本案揭露內容之一個實施例形成的元件350。該元件350包括基板351,該基板351具有形成在該基板351上的S/D區域356。場氧化物層352形成為鄰近S/D區域356以界定該S/D區域356。閘極絕緣層353與閘電極354配置在基板351上方。絕緣層355配置在閘電極354之上表面與側面上方。
該元件也包括一或多個第一n型矽層359(於操作104中沉積)、一或多個高度摻雜的n型矽層360(於操作106中沉積)、及矽化鈦層361(於操作108中形成)。考量可利用其他元件及其他層堆疊。
本案揭露內容的優點包括在比習知技術還要低溫所形成的矽化鈦方法,從而緩和習知矽化物形成操作中常見的熱預算問題。此外,本文所述之態樣以相較於習知途徑更為減少的培養時間形成矽化物層。再者,根據本文之態樣形成的矽化鈦層選擇性對抗氧化物與氮化物層,藉此減少習知途徑中所用的遮蔽/蝕刻操作。
雖上文是針對本案揭露內容之實施例,但可不背離本案揭露內容之基本範疇設計本案揭露內容之其他與進一步之實施例,且本案揭露內容之範疇由下文的申請專利範圍所決定。
100‧‧‧方法102-110‧‧‧操作220‧‧‧圖表230‧‧‧圖表350‧‧‧元件351‧‧‧基板352‧‧‧場氧化物層353‧‧‧閘極絕緣層354‧‧‧閘電極355‧‧‧絕緣層356‧‧‧S/D區域359‧‧‧第一n型矽層360‧‧‧高度摻雜的n型矽層361‧‧‧矽化鈦層
透過參考其中一些在附圖中說明的實施例,可得到上文簡要總結的本案揭露內容之更特定的敘述,而能夠詳細瞭解本案揭露內容的上述特徵。然而,注意附圖所說明的僅為示範性實施例,故不應被視為限制範疇,因本案揭露內容可容許其他等效實施例。
第1圖說明根據本案揭露內容之一個實施例的方法的操作。
第2A圖與第2B圖說明根據本案揭露內容之實施例的各種條件下的矽化鈦膜。
第3圖說明根據本案揭露內容之一個實施例形成的元件。
為了助於瞭解,如可能則已使用相同的元件符號指定各圖共通的相同元件。考慮一個實施例的元件及特徵可有利地併入其他實施例中而無須贅述。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無
100‧‧‧方法
102-110‧‧‧操作

Claims (20)

  1. 一種形成矽化鈦層的方法,包括下述步驟:在一處理腔室中將一基板加熱到範圍在攝氏400度至攝氏500度內的溫度,該基板包括:一或多個源極/汲極區域;一或多個第一n型矽層,配置在該一或多個源極/汲極區域上;及一或多個高度摻雜的n型矽層,配置在該一或多個第一n型矽層上,該一或多個高度摻雜的n型矽層之每一者具有範圍在約1x1018原子/cm3至約4x1021原子/cm3內的一n型摻雜劑濃度;及在將該處理腔室內的壓力維持在10托耳至100托耳之間的同時,同步地將該基板暴露至一矽前驅物及一鈦前驅物,該鈦前驅物包括TiCl4;以及在該一或多個高度摻雜的n型矽層上形成一矽化鈦層。
  2. 如請求項1所述之方法,其中該n型摻雜劑是磷。
  3. 如請求項2所述之方法,其中該一或多個高度摻雜的n型矽層之至少一者包括非晶矽。
  4. 如請求項2所述之方法,其中該一或多個高度摻雜的n型矽層之至少一者包括結晶矽。
  5. 如請求項1所述之方法,其中該n型摻雜劑是砷或銻。
  6. 如請求項1所述之方法,其中該一或多個高度摻雜的n型矽層之至少一者包括鈦。
  7. 如請求項1所述之方法,其中該處理腔室內的壓力是在80托耳至100托耳的範圍內。
  8. 如請求項1所述之方法,其中該一或多個高度摻雜的n型矽層之至少一者具有1奈米至10奈米的厚度。
  9. 如請求項1所述之方法,其中該一或多個高度摻雜的n型矽層之至少一者具有5奈米或更小的厚度。
  10. 如請求項1所述之方法,進一步包括下述步驟:形成該矽化鈦層之前,將該基板暴露至一TiCl4浸泡。
  11. 如請求項10所述之方法,其中該TiCl4浸泡執行達15秒至120秒。
  12. 如請求項1所述之方法,其中該矽化鈦層是C49相。
  13. 如請求項1所述之方法,其中該矽化鈦層是C54相。
  14. 如請求項1所述之方法,其中該一或多個 高度摻雜的n型矽層包括鍺。
  15. 如請求項1所述之方法,其中該基板進一步包括多個場氧化物層,且相對於該等場氧化物層,該矽化鈦之形成是選擇性的(selective)。
  16. 如請求項1所述之方法,其中該一或多個高度摻雜的n型矽層之至少一者的摻雜劑濃度高於該一或多個第一n型矽層的每一者。
  17. 一種形成矽化鈦層的方法,包括下述步驟:在一處理腔室中將一基板加熱到範圍在攝氏400度至攝氏500度內的溫度,該基板包括:一或多個第一n型矽層;及一或多個高度摻雜的n型矽層,配置在該一或多個第一n型矽層上面,該一或多個高度摻雜的n型矽層具有範圍在約1x1018原子/cm3至約4x1021原子/cm3內的一n型摻雜劑濃度;在將處理腔室內的壓力維持在80托耳至100托耳之間的同時,同步地將該基板暴露至一矽前驅物及一鈦前驅物,該鈦前驅物包括TiCl4;以及在該一或多個高度摻雜的n型矽層上形成一矽化鈦層。
  18. 如請求項17所述之方法,其中該一或多個高度摻雜的n型矽層之至少一者的摻雜劑濃度高於該 一或多個第一n型矽層的每一者。
  19. 如請求項17所述之方法,其中該一或多個高度摻雜的n型矽層之至少一者的厚度是在1奈米至10奈米的範圍內。
  20. 如請求項19所述之方法,其中該n型摻雜劑是磷。
TW106142844A 2016-12-12 2017-12-07 形成矽化物的方法 TWI732976B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662432844P 2016-12-12 2016-12-12
US62/432,844 2016-12-12

Publications (2)

Publication Number Publication Date
TW201828340A TW201828340A (zh) 2018-08-01
TWI732976B true TWI732976B (zh) 2021-07-11

Family

ID=62489598

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106142844A TWI732976B (zh) 2016-12-12 2017-12-07 形成矽化物的方法

Country Status (5)

Country Link
US (1) US10312096B2 (zh)
EP (1) EP3552228A4 (zh)
KR (1) KR102163383B1 (zh)
TW (1) TWI732976B (zh)
WO (1) WO2018111628A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10971366B2 (en) * 2018-07-06 2021-04-06 Applied Materials, Inc. Methods for silicide deposition
US20200283896A1 (en) * 2019-03-08 2020-09-10 Applied Materials, Inc. Methods for low temperature silicide formation
US20210408246A1 (en) * 2020-06-25 2021-12-30 Intel Corporation Contact resistance reduction in transistor devices with metallization on both sides

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6010929A (en) * 1996-12-11 2000-01-04 Texas Instruments Incorporated Method for forming high voltage and low voltage transistors on the same substrate
US6287967B1 (en) * 1999-11-30 2001-09-11 United Microelectronics Corp. Self-aligned silicide process
US20150061010A1 (en) * 2013-08-27 2015-03-05 International Business Machines Corporation Structure for improved contact resistance and extension diffusion control

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4766006A (en) * 1986-05-15 1988-08-23 Varian Associates, Inc. Low pressure chemical vapor deposition of metal silicide
US5240739A (en) * 1992-08-07 1993-08-31 Micron Technology Chemical vapor deposition technique for depositing titanium silicide on semiconductor wafers
JP3714995B2 (ja) * 1995-07-05 2005-11-09 シャープ株式会社 半導体装置
US6777759B1 (en) * 1997-06-30 2004-08-17 Intel Corporation Device structure and method for reducing silicide encroachment
US20030042614A1 (en) * 2001-08-30 2003-03-06 Ammar Deraa Metal silicide adhesion layer for contact structures
US6767823B2 (en) * 2002-03-06 2004-07-27 Micron Technology, Inc. Plasma enhanced chemical vapor deposition method of forming titanium silicide comprising layers
KR100477816B1 (ko) * 2002-12-30 2005-03-22 주식회사 하이닉스반도체 반도체 소자의 티타늄 실리사이드 콘택 형성 방법
KR100538806B1 (ko) 2003-02-21 2005-12-26 주식회사 하이닉스반도체 에피택셜 c49상의 티타늄실리사이드막을 갖는 반도체소자 및 그 제조 방법
KR20060079144A (ko) * 2003-06-18 2006-07-05 어플라이드 머티어리얼스, 인코포레이티드 배리어 물질의 원자층 증착
US7005376B2 (en) 2003-07-07 2006-02-28 Advanced Micro Devices, Inc. Ultra-uniform silicides in integrated circuit technology
KR100840786B1 (ko) * 2006-07-28 2008-06-23 삼성전자주식회사 저저항 게이트 전극을 구비하는 반도체 장치 및 이의제조방법
US7776675B1 (en) 2007-10-29 2010-08-17 Newport Fab, Llc Method for forming a reduced resistivity poly gate and related structure
US7855153B2 (en) * 2008-02-08 2010-12-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8088665B2 (en) * 2008-08-11 2012-01-03 Intel Corporation Method of forming self-aligned low resistance contact layer
US8901537B2 (en) * 2010-12-21 2014-12-02 Intel Corporation Transistors with high concentration of boron doped germanium
EP2786427A4 (en) * 2011-12-01 2016-08-17 Quarkstar Llc SOLID BODY LIGHTING DEVICE AND METHOD OF MANUFACTURING THEREOF
US9018639B2 (en) * 2012-10-26 2015-04-28 Dow Corning Corporation Flat SiC semiconductor substrate
US20150060101A1 (en) 2013-09-05 2015-03-05 Bruce H. Turner Electrical shock and burn protection system
JP6426893B2 (ja) * 2013-12-25 2018-11-21 東京エレクトロン株式会社 コンタクト層の形成方法
JP6306411B2 (ja) * 2014-04-17 2018-04-04 株式会社日立国際電気 半導体装置の製造方法、基板処理装置およびプログラム
WO2016048306A1 (en) * 2014-09-24 2016-03-31 Intel Corporation Scaled tfet transistor formed using nanowire with surface termination
IL237775B (en) * 2015-03-16 2019-03-31 Redler Tech Ltd Automatic, highly reliable, fully redundant electornic circuit breaker that includes means for preventing short-circuit overcurrent

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6010929A (en) * 1996-12-11 2000-01-04 Texas Instruments Incorporated Method for forming high voltage and low voltage transistors on the same substrate
US6287967B1 (en) * 1999-11-30 2001-09-11 United Microelectronics Corp. Self-aligned silicide process
US20150061010A1 (en) * 2013-08-27 2015-03-05 International Business Machines Corporation Structure for improved contact resistance and extension diffusion control

Also Published As

Publication number Publication date
US20180166288A1 (en) 2018-06-14
EP3552228A1 (en) 2019-10-16
KR102163383B1 (ko) 2020-10-08
KR20190077132A (ko) 2019-07-02
TW201828340A (zh) 2018-08-01
US10312096B2 (en) 2019-06-04
WO2018111628A1 (en) 2018-06-21
EP3552228A4 (en) 2020-08-05

Similar Documents

Publication Publication Date Title
CN101154576A (zh) 形成具有低电阻的钨多金属栅极的方法
US8367548B2 (en) Stable silicide films and methods for making the same
TWI732976B (zh) 形成矽化物的方法
TW201805469A (zh) 金屬矽化物的選擇性形成
TWI738207B (zh) 用於金屬矽化物沉積的方法及設備
KR20050117107A (ko) 낮은 콘택 저항을 갖는 반도체 소자 및 그 제조 방법
US8822312B2 (en) Method of forming high growth rate, low resistivity germanium film on silicon substrate
US10964544B2 (en) Contact integration and selective silicide formation methods
KR100818397B1 (ko) 반도체 소자의 티타늄 나이트라이드 실리사이드막 제조방법
US20220336469A1 (en) System and methods for dram contact formation
Chung et al. Methods for titanium silicide formation using TiCl 4 precursor and silicon-containing precursor
Kim et al. CVD-cobalt for low resistance word line electrode of 3D NAND flash memory
KR100784100B1 (ko) 반도체 소자의 콘택 플러그 형성 방법
KR20020002561A (ko) 반도체 소자의 게이트전극 형성 방법
KR20060000585A (ko) 반도체 소자의 콘택플러그 형성방법
KR20050104822A (ko) 반도체 소자의 콘택 플러그 형성방법