ATE220808T1 - Anordnung für eine halbleitervorrichtung mit redundanten elementen - Google Patents
Anordnung für eine halbleitervorrichtung mit redundanten elementenInfo
- Publication number
- ATE220808T1 ATE220808T1 AT97920417T AT97920417T ATE220808T1 AT E220808 T1 ATE220808 T1 AT E220808T1 AT 97920417 T AT97920417 T AT 97920417T AT 97920417 T AT97920417 T AT 97920417T AT E220808 T1 ATE220808 T1 AT E220808T1
- Authority
- AT
- Austria
- Prior art keywords
- columns
- rows
- banks
- planes
- address
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/81—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a hierarchical redundancy scheme
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/637,875 US5706292A (en) | 1996-04-25 | 1996-04-25 | Layout for a semiconductor memory device having redundant elements |
PCT/US1997/006348 WO1997040444A1 (en) | 1996-04-25 | 1997-04-16 | Layout for a semiconductor memory device having redundant elements |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE220808T1 true ATE220808T1 (de) | 2002-08-15 |
Family
ID=24557721
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT97920417T ATE220808T1 (de) | 1996-04-25 | 1997-04-16 | Anordnung für eine halbleitervorrichtung mit redundanten elementen |
Country Status (8)
Country | Link |
---|---|
US (5) | US5706292A (de) |
EP (1) | EP0931288B1 (de) |
JP (1) | JP3697266B2 (de) |
KR (1) | KR100392557B1 (de) |
AT (1) | ATE220808T1 (de) |
AU (1) | AU2461597A (de) |
DE (1) | DE69714060T2 (de) |
WO (1) | WO1997040444A1 (de) |
Families Citing this family (78)
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JP2850953B2 (ja) * | 1996-07-30 | 1999-01-27 | 日本電気株式会社 | 半導体装置 |
US5734617A (en) * | 1996-08-01 | 1998-03-31 | Micron Technology Corporation | Shared pull-up and selection circuitry for programmable cells such as antifuse cells |
JP3613622B2 (ja) * | 1996-09-27 | 2005-01-26 | 株式会社日立製作所 | 半導体メモリ |
US6104209A (en) | 1998-08-27 | 2000-08-15 | Micron Technology, Inc. | Low skew differential receiver with disable feature |
US5953276A (en) * | 1997-12-18 | 1999-09-14 | Micron Technology, Inc. | Fully-differential amplifier |
US6005813A (en) * | 1997-11-12 | 1999-12-21 | Micron Technology, Inc. | Device and method for repairing a semiconductor memory |
US6077211A (en) * | 1998-02-27 | 2000-06-20 | Micron Technology, Inc. | Circuits and methods for selectively coupling redundant elements into an integrated circuit |
US6212482B1 (en) | 1998-03-06 | 2001-04-03 | Micron Technology, Inc. | Circuit and method for specifying performance parameters in integrated circuits |
US6163863A (en) * | 1998-05-22 | 2000-12-19 | Micron Technology, Inc. | Method and circuit for compressing test data in a memory device |
US6061291A (en) * | 1998-07-14 | 2000-05-09 | Winbond Electronics Corporation America | Memory integrated circuit supporting maskable block write operation and arbitrary redundant column repair |
JP3880210B2 (ja) * | 1998-08-04 | 2007-02-14 | エルピーダメモリ株式会社 | 半導体装置 |
US6199177B1 (en) * | 1998-08-28 | 2001-03-06 | Micron Technology, Inc. | Device and method for repairing a semiconductor memory |
US6910152B2 (en) * | 1998-08-28 | 2005-06-21 | Micron Technology, Inc. | Device and method for repairing a semiconductor memory |
US6246615B1 (en) | 1998-12-23 | 2001-06-12 | Micron Technology, Inc. | Redundancy mapping in a multichip semiconductor package |
JP3866451B2 (ja) * | 1999-06-24 | 2007-01-10 | Necエレクトロニクス株式会社 | 冗長プログラム回路及びこれを内蔵した半導体記憶装置 |
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JP3844917B2 (ja) * | 1999-07-26 | 2006-11-15 | 株式会社東芝 | 半導体記憶装置 |
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US6480990B1 (en) * | 2000-05-01 | 2002-11-12 | Hewlett-Packard Company | Application specific integrated circuit with spaced spare logic gate subgroups and method of fabrication |
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US6504768B1 (en) | 2000-08-25 | 2003-01-07 | Micron Technology, Inc. | Redundancy selection in memory devices with concurrent read and write |
US6445625B1 (en) | 2000-08-25 | 2002-09-03 | Micron Technology, Inc. | Memory device redundancy selection having test inputs |
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US20020133769A1 (en) * | 2001-03-15 | 2002-09-19 | Cowles Timothy B. | Circuit and method for test and repair |
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JP5119563B2 (ja) * | 2001-08-03 | 2013-01-16 | 日本電気株式会社 | 不良メモリセル救済回路を有する半導体記憶装置 |
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US7415641B1 (en) * | 2003-11-05 | 2008-08-19 | Virage Logic Corp. | System and method for repairing a memory |
KR100587076B1 (ko) | 2004-04-28 | 2006-06-08 | 주식회사 하이닉스반도체 | 메모리 장치 |
US7162825B2 (en) * | 2004-05-18 | 2007-01-16 | Calculations Made Simple | Method and means for adjusting the scope of a firearm |
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US7638850B2 (en) | 2004-10-14 | 2009-12-29 | Saifun Semiconductors Ltd. | Non-volatile memory structure and method of fabrication |
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US7156570B2 (en) * | 2004-12-30 | 2007-01-02 | Cotapaxi Custom Design And Manufacturing, Llc | Implement grip |
JP4524636B2 (ja) * | 2005-03-24 | 2010-08-18 | エルピーダメモリ株式会社 | 半導体記憶装置 |
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JP5094085B2 (ja) * | 2005-09-29 | 2012-12-12 | エスケーハイニックス株式会社 | 半導体装置のデータ入出力マルチプレクサ |
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US7692961B2 (en) * | 2006-02-21 | 2010-04-06 | Saifun Semiconductors Ltd. | Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection |
US7701779B2 (en) | 2006-04-27 | 2010-04-20 | Sajfun Semiconductors Ltd. | Method for programming a reference cell |
KR100791348B1 (ko) * | 2006-12-15 | 2008-01-03 | 삼성전자주식회사 | 반도체 메모리 장치 및 그 병렬 비트 테스트 방법 |
KR100798792B1 (ko) | 2006-12-27 | 2008-01-28 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
KR100801309B1 (ko) * | 2007-01-03 | 2008-02-05 | 주식회사 하이닉스반도체 | 라이트레벨링 동작을 하는 메모리장치. |
KR100825002B1 (ko) * | 2007-01-10 | 2008-04-24 | 주식회사 하이닉스반도체 | 효과적으로 직렬로 입출력되는 데이터의 오류를 검사할 수있는 반도체 메모리 장치 및 그 구동방법 |
KR100920830B1 (ko) * | 2007-04-11 | 2009-10-08 | 주식회사 하이닉스반도체 | 라이트 제어 신호 생성 회로 및 이를 이용하는 반도체메모리 장치 및 그의 동작 방법 |
US20080291760A1 (en) * | 2007-05-23 | 2008-11-27 | Micron Technology, Inc. | Sub-array architecture memory devices and related systems and methods |
KR100907928B1 (ko) * | 2007-06-13 | 2009-07-16 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
KR100933668B1 (ko) * | 2008-04-30 | 2009-12-23 | 주식회사 하이닉스반도체 | 출력회로 |
US7903457B2 (en) * | 2008-08-19 | 2011-03-08 | Macronix International Co., Ltd. | Multiple phase change materials in an integrated circuit for system on a chip application |
US8412987B2 (en) * | 2009-06-30 | 2013-04-02 | Micron Technology, Inc. | Non-volatile memory to store memory remap information |
US8495467B1 (en) | 2009-06-30 | 2013-07-23 | Micron Technology, Inc. | Switchable on-die memory error correcting engine |
US8412985B1 (en) | 2009-06-30 | 2013-04-02 | Micron Technology, Inc. | Hardwired remapped memory |
KR101163035B1 (ko) * | 2009-09-04 | 2012-07-09 | 에스케이하이닉스 주식회사 | 데이터 라인 구동 회로 |
KR101277479B1 (ko) * | 2010-08-31 | 2013-06-21 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
US8473679B2 (en) * | 2011-03-31 | 2013-06-25 | Ceva D.S.P. Ltd. | System, data structure, and method for collapsing multi-dimensional data |
US8719648B2 (en) | 2011-07-27 | 2014-05-06 | International Business Machines Corporation | Interleaving of memory repair data compression and fuse programming operations in single fusebay architecture |
US8467260B2 (en) | 2011-08-05 | 2013-06-18 | International Business Machines Corporation | Structure and method for storing multiple repair pass data into a fusebay |
US8484543B2 (en) | 2011-08-08 | 2013-07-09 | International Business Machines Corporation | Fusebay controller structure, system, and method |
US8537627B2 (en) | 2011-09-01 | 2013-09-17 | International Business Machines Corporation | Determining fusebay storage element usage |
US10726939B2 (en) * | 2017-09-27 | 2020-07-28 | SK Hynix Inc. | Memory devices having spare column remap storages |
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TWI752704B (zh) * | 2020-11-03 | 2022-01-11 | 華邦電子股份有限公司 | 記憶體儲存裝置及其操作方法 |
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-
1996
- 1996-04-25 US US08/637,875 patent/US5706292A/en not_active Expired - Lifetime
-
1997
- 1997-04-16 DE DE69714060T patent/DE69714060T2/de not_active Expired - Lifetime
- 1997-04-16 KR KR10-1998-0708732A patent/KR100392557B1/ko not_active IP Right Cessation
- 1997-04-16 WO PCT/US1997/006348 patent/WO1997040444A1/en active IP Right Grant
- 1997-04-16 AU AU24615/97A patent/AU2461597A/en not_active Abandoned
- 1997-04-16 EP EP97920417A patent/EP0931288B1/de not_active Expired - Lifetime
- 1997-04-16 JP JP53816697A patent/JP3697266B2/ja not_active Expired - Lifetime
- 1997-04-16 AT AT97920417T patent/ATE220808T1/de not_active IP Right Cessation
- 1997-08-14 US US08/911,669 patent/US6018811A/en not_active Expired - Lifetime
-
1999
- 1999-10-08 US US09/415,472 patent/US6163860A/en not_active Expired - Lifetime
-
2000
- 2000-12-20 US US09/747,352 patent/US6560728B2/en not_active Expired - Lifetime
-
2003
- 2003-04-30 US US10/428,151 patent/US7043672B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6560728B2 (en) | 2003-05-06 |
EP0931288B1 (de) | 2002-07-17 |
US6163860A (en) | 2000-12-19 |
US6018811A (en) | 2000-01-25 |
JP2000509182A (ja) | 2000-07-18 |
AU2461597A (en) | 1997-11-12 |
EP0931288A1 (de) | 1999-07-28 |
DE69714060T2 (de) | 2003-03-13 |
DE69714060D1 (de) | 2002-08-22 |
US20010016893A1 (en) | 2001-08-23 |
KR20000010683A (ko) | 2000-02-25 |
US5706292A (en) | 1998-01-06 |
US7043672B2 (en) | 2006-05-09 |
WO1997040444A1 (en) | 1997-10-30 |
KR100392557B1 (ko) | 2003-11-20 |
US20040010737A1 (en) | 2004-01-15 |
JP3697266B2 (ja) | 2005-09-21 |
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