ZA918831B - A process for the treatment of silicon wafers in order to achieve controlled precipitation profiles therein adapted for manufacturing electronic components - Google Patents

A process for the treatment of silicon wafers in order to achieve controlled precipitation profiles therein adapted for manufacturing electronic components

Info

Publication number
ZA918831B
ZA918831B ZA918831A ZA918831A ZA918831B ZA 918831 B ZA918831 B ZA 918831B ZA 918831 A ZA918831 A ZA 918831A ZA 918831 A ZA918831 A ZA 918831A ZA 918831 B ZA918831 B ZA 918831B
Authority
ZA
South Africa
Prior art keywords
face
treatment
electronic components
order
silicon wafers
Prior art date
Application number
ZA918831A
Other languages
English (en)
Inventor
Robert Falster
Falster Robert
Giancarlo Ferrero
Ferrero Giancarlo
Graham Fisher
Fisher Graham
Massimiliano Olmo
Olmo Massimiliano
Marco Pagani
Pagani Marco
Original Assignee
Memc Electronic Materials
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Memc Electronic Materials filed Critical Memc Electronic Materials
Publication of ZA918831B publication Critical patent/ZA918831B/xx

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Formation Of Insulating Films (AREA)
  • Silicon Compounds (AREA)
  • Surgical Instruments (AREA)
  • Safety Valves (AREA)
  • Vessels, Lead-In Wires, Accessory Apparatuses For Cathode-Ray Tubes (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
ZA918831A 1990-11-15 1991-11-07 A process for the treatment of silicon wafers in order to achieve controlled precipitation profiles therein adapted for manufacturing electronic components ZA918831B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT48481A IT1242014B (it) 1990-11-15 1990-11-15 Procedimento per il trattamento di fette di silicio per ottenere in esse profili di precipitazione controllati per la produzione di componenti elettronici.

Publications (1)

Publication Number Publication Date
ZA918831B true ZA918831B (en) 1992-08-26

Family

ID=11266818

Family Applications (1)

Application Number Title Priority Date Filing Date
ZA918831A ZA918831B (en) 1990-11-15 1991-11-07 A process for the treatment of silicon wafers in order to achieve controlled precipitation profiles therein adapted for manufacturing electronic components

Country Status (17)

Country Link
US (1) US5403406A (ja)
EP (1) EP0557415B1 (ja)
JP (2) JP3412636B2 (ja)
KR (1) KR100247464B1 (ja)
AT (1) ATE176084T1 (ja)
AU (1) AU9033591A (ja)
CZ (1) CZ84993A3 (ja)
DE (1) DE69130802T2 (ja)
FI (1) FI932024A (ja)
IL (1) IL99979A (ja)
IT (1) IT1242014B (ja)
MY (1) MY110258A (ja)
SG (1) SG64901A1 (ja)
SK (1) SK47093A3 (ja)
TW (1) TW205110B (ja)
WO (1) WO1992009101A1 (ja)
ZA (1) ZA918831B (ja)

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US5788763A (en) * 1995-03-09 1998-08-04 Toshiba Ceramics Co., Ltd. Manufacturing method of a silicon wafer having a controlled BMD concentration
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US6485807B1 (en) 1997-02-13 2002-11-26 Samsung Electronics Co., Ltd. Silicon wafers having controlled distribution of defects, and methods of preparing the same
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US5994761A (en) * 1997-02-26 1999-11-30 Memc Electronic Materials Spa Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
DE69841714D1 (de) 1997-04-09 2010-07-22 Memc Electronic Materials Silicium mit niedriger Fehlerdichte und idealem Sauerstoffniederschlag
TW429478B (en) * 1997-08-29 2001-04-11 Toshiba Corp Semiconductor device and method for manufacturing the same
US5882989A (en) * 1997-09-22 1999-03-16 Memc Electronic Materials, Inc. Process for the preparation of silicon wafers having a controlled distribution of oxygen precipitate nucleation centers
US6340392B1 (en) 1997-10-24 2002-01-22 Samsung Electronics Co., Ltd. Pulling methods for manufacturing monocrystalline silicone ingots by controlling temperature at the center and edge of an ingot-melt interface
JPH11150119A (ja) * 1997-11-14 1999-06-02 Sumitomo Sitix Corp シリコン半導体基板の熱処理方法とその装置
JP3746153B2 (ja) * 1998-06-09 2006-02-15 信越半導体株式会社 シリコンウエーハの熱処理方法
US6828690B1 (en) * 1998-08-05 2004-12-07 Memc Electronic Materials, Inc. Non-uniform minority carrier lifetime distributions in high performance silicon power devices
JP4405083B2 (ja) 1998-09-02 2010-01-27 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド 理想的な酸素析出シリコンウエハの製造方法
JP2002524845A (ja) * 1998-09-02 2002-08-06 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド 欠陥密度が低い単結晶シリコンから得られるシリコン・オン・インシュレーター構造体
JP4405082B2 (ja) 1998-09-02 2010-01-27 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド 内部ゲッタリング性の改良された熱アニーリングされたウエハ
US6336968B1 (en) 1998-09-02 2002-01-08 Memc Electronic Materials, Inc. Non-oxygen precipitating czochralski silicon wafers
JP4875800B2 (ja) 1998-10-14 2012-02-15 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド 単結晶シリコンウエハの製造方法
JP2000154070A (ja) * 1998-11-16 2000-06-06 Suminoe Textile Co Ltd セラミックス三次元構造体及びその製造方法
US6284384B1 (en) 1998-12-09 2001-09-04 Memc Electronic Materials, Inc. Epitaxial silicon wafer with intrinsic gettering
DE19924649B4 (de) * 1999-05-28 2004-08-05 Siltronic Ag Halbleiterscheiben mit Kristallgitter-Defekten und Verfahren zur Herstellung derselben
US20030051656A1 (en) 1999-06-14 2003-03-20 Charles Chiun-Chieh Yang Method for the preparation of an epitaxial silicon wafer with intrinsic gettering
US6635587B1 (en) 1999-09-23 2003-10-21 Memc Electronic Materials, Inc. Method for producing czochralski silicon free of agglomerated self-interstitial defects
KR100378184B1 (ko) * 1999-11-13 2003-03-29 삼성전자주식회사 제어된 결함 분포를 갖는 실리콘 웨이퍼, 그의 제조공정및 단결정 실리콘 잉곳의 제조를 위한 초크랄스키 풀러
JP2001308101A (ja) * 2000-04-19 2001-11-02 Mitsubishi Materials Silicon Corp シリコンウェーハの熱処理方法及びシリコンウェーハ
DE10024710A1 (de) 2000-05-18 2001-12-20 Steag Rtp Systems Gmbh Einstellung von Defektprofilen in Kristallen oder kristallähnlichen Strukturen
US6599815B1 (en) 2000-06-30 2003-07-29 Memc Electronic Materials, Inc. Method and apparatus for forming a silicon wafer with a denuded zone
CN1441961A (zh) * 2000-06-30 2003-09-10 Memc电子材料有限公司 形成具有洁净区的硅片的方法和装置
US6339016B1 (en) 2000-06-30 2002-01-15 Memc Electronic Materials, Inc. Method and apparatus for forming an epitaxial silicon wafer with a denuded zone
JP4055343B2 (ja) * 2000-09-26 2008-03-05 株式会社Ｓｕｍｃｏ シリコン半導体基板の熱処理方法
JP4106862B2 (ja) * 2000-10-25 2008-06-25 信越半導体株式会社 シリコンウェーハの製造方法
US6897084B2 (en) * 2001-04-11 2005-05-24 Memc Electronic Materials, Inc. Control of oxygen precipitate formation in high resistivity CZ silicon
US20020179006A1 (en) * 2001-04-20 2002-12-05 Memc Electronic Materials, Inc. Method for the preparation of a semiconductor substrate with a non-uniform distribution of stabilized oxygen precipitates
FR2827078B1 (fr) * 2001-07-04 2005-02-04 Soitec Silicon On Insulator Procede de diminution de rugosite de surface
US7883628B2 (en) * 2001-07-04 2011-02-08 S.O.I.Tec Silicon On Insulator Technologies Method of reducing the surface roughness of a semiconductor wafer
US7749910B2 (en) * 2001-07-04 2010-07-06 S.O.I.Tec Silicon On Insulator Technologies Method of reducing the surface roughness of a semiconductor wafer
JP4567251B2 (ja) * 2001-09-14 2010-10-20 シルトロニック・ジャパン株式会社 シリコン半導体基板およびその製造方法
US6955718B2 (en) * 2003-07-08 2005-10-18 Memc Electronic Materials, Inc. Process for preparing a stabilized ideal oxygen precipitating silicon wafer
JP2005051040A (ja) * 2003-07-29 2005-02-24 Matsushita Electric Ind Co Ltd 半導体装置の製造方法及び半導体基板
KR100531552B1 (ko) * 2003-09-05 2005-11-28 주식회사 하이닉스반도체 실리콘 웨이퍼 및 그 제조방법
US7485928B2 (en) * 2005-11-09 2009-02-03 Memc Electronic Materials, Inc. Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
US20090004458A1 (en) * 2007-06-29 2009-01-01 Memc Electronic Materials, Inc. Diffusion Control in Heavily Doped Substrates
US20090004426A1 (en) * 2007-06-29 2009-01-01 Memc Electronic Materials, Inc. Suppression of Oxygen Precipitation in Heavily Doped Single Crystal Silicon Substrates
JP2009177194A (ja) * 2009-03-19 2009-08-06 Sumco Corp シリコンウェーハの製造方法、シリコンウェーハ
WO2018125565A1 (en) * 2016-12-28 2018-07-05 Sunedison Semiconductor Limited Method of treating silicon wafers to have intrinsic gettering and gate oxide integrity yield

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US5228927A (en) * 1988-03-25 1993-07-20 Shin-Etsu Handotai Company Limited Method for heat-treating gallium arsenide monocrystals
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Also Published As

Publication number Publication date
US5403406A (en) 1995-04-04
DE69130802T2 (de) 1999-08-19
EP0557415A1 (en) 1993-09-01
KR100247464B1 (ko) 2000-03-15
TW205110B (ja) 1993-05-01
FI932024A (fi) 1993-06-29
MY110258A (en) 1998-03-31
JP2003243402A (ja) 2003-08-29
JP3412636B2 (ja) 2003-06-03
IT9048481A0 (it) 1990-11-15
CZ84993A3 (en) 1993-11-17
IT9048481A1 (it) 1992-05-15
FI932024A0 (fi) 1993-05-05
WO1992009101A1 (en) 1992-05-29
IL99979A0 (en) 1992-08-18
ATE176084T1 (de) 1999-02-15
EP0557415B1 (en) 1999-01-20
IT1242014B (it) 1994-02-02
JPH06504878A (ja) 1994-06-02
SG64901A1 (en) 1999-05-25
IL99979A (en) 1995-07-31
DE69130802D1 (de) 1999-03-04
AU9033591A (en) 1992-06-11
SK47093A3 (en) 1993-08-11

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