JPS647625A - Treating method for semiconductor substrate - Google Patents

Treating method for semiconductor substrate

Info

Publication number
JPS647625A
JPS647625A JP16328487A JP16328487A JPS647625A JP S647625 A JPS647625 A JP S647625A JP 16328487 A JP16328487 A JP 16328487A JP 16328487 A JP16328487 A JP 16328487A JP S647625 A JPS647625 A JP S647625A
Authority
JP
Japan
Prior art keywords
oxygen
operation region
region
oxygen concentration
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16328487A
Other languages
Japanese (ja)
Inventor
Nobuyuki Izawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP16328487A priority Critical patent/JPS647625A/en
Publication of JPS647625A publication Critical patent/JPS647625A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)

Abstract

PURPOSE:To surely form a dunuded zone on an operation region of a semiconductor element and to have an oxygen precipitated region approach the operation region by forming grooves on a semiconductor substrate, and then heat treating it to form a low oxygen concentration region in the depth of the operation region of an element formed at least on the surface of the substrate. CONSTITUTION:After grooves 3 are formed on a semiconductor substrate 1, it is heat treated to form a low oxygen concentration region over the depth of an operation region of an element formed at least on the surface of the substrate 1. For example, an SiO2 film and an Si3N4 film, etc., are formed on an Si wafer 1, trenches 3 are formed, an outer diffusion of oxygen is conducted at a temperature at which oxygen is not precipitated by heat treating in an inert gas. The oxygen near the surface of the wafer 1 is easily externally diffused particularly from the exposed part of the silicon of the trenches 3 at this time, and a denuded zone (DZ layer) 4 is surely formed on the operation region of a semiconductor element. Then, a low temperature heat treatment is so added that the oxygen precipitation does not occur in the low oxygen concentration in the DZ layer 4 but the oxygen precipitation occurs at the place other than that low oxygen concentration.
JP16328487A 1987-06-30 1987-06-30 Treating method for semiconductor substrate Pending JPS647625A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16328487A JPS647625A (en) 1987-06-30 1987-06-30 Treating method for semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16328487A JPS647625A (en) 1987-06-30 1987-06-30 Treating method for semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS647625A true JPS647625A (en) 1989-01-11

Family

ID=15770893

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16328487A Pending JPS647625A (en) 1987-06-30 1987-06-30 Treating method for semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS647625A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0964444A2 (en) * 1998-06-09 1999-12-15 Siemens Aktiengesellschaft Semiconductors having denuded zones
KR100450676B1 (en) * 2001-06-28 2004-10-01 삼성전자주식회사 Method of fabricating silicon wafers including argon/ammonia rapid thermal annealing process, silicon wafers fabricated thereby
JP2006156973A (en) * 2004-10-25 2006-06-15 Toyota Motor Corp Manufacturing method of metal insulator semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60140830A (en) * 1983-12-28 1985-07-25 Fujitsu Ltd Manufacture of semicoductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60140830A (en) * 1983-12-28 1985-07-25 Fujitsu Ltd Manufacture of semicoductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0964444A2 (en) * 1998-06-09 1999-12-15 Siemens Aktiengesellschaft Semiconductors having denuded zones
KR100450676B1 (en) * 2001-06-28 2004-10-01 삼성전자주식회사 Method of fabricating silicon wafers including argon/ammonia rapid thermal annealing process, silicon wafers fabricated thereby
JP2006156973A (en) * 2004-10-25 2006-06-15 Toyota Motor Corp Manufacturing method of metal insulator semiconductor device

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