ZA918831B - A process for the treatment of silicon wafers in order to achieve controlled precipitation profiles therein adapted for manufacturing electronic components - Google Patents

A process for the treatment of silicon wafers in order to achieve controlled precipitation profiles therein adapted for manufacturing electronic components

Info

Publication number
ZA918831B
ZA918831B ZA918831A ZA918831A ZA918831B ZA 918831 B ZA918831 B ZA 918831B ZA 918831 A ZA918831 A ZA 918831A ZA 918831 A ZA918831 A ZA 918831A ZA 918831 B ZA918831 B ZA 918831B
Authority
ZA
South Africa
Prior art keywords
face
treatment
electronic components
order
silicon wafers
Prior art date
Application number
ZA918831A
Other languages
English (en)
Inventor
Robert Falster
Falster Robert
Giancarlo Ferrero
Ferrero Giancarlo
Graham Fisher
Fisher Graham
Massimiliano Olmo
Olmo Massimiliano
Marco Pagani
Pagani Marco
Original Assignee
Memc Electronic Materials
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Memc Electronic Materials filed Critical Memc Electronic Materials
Publication of ZA918831B publication Critical patent/ZA918831B/xx

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Formation Of Insulating Films (AREA)
  • Vessels, Lead-In Wires, Accessory Apparatuses For Cathode-Ray Tubes (AREA)
  • Surgical Instruments (AREA)
  • Safety Valves (AREA)
  • Silicon Compounds (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
ZA918831A 1990-11-15 1991-11-07 A process for the treatment of silicon wafers in order to achieve controlled precipitation profiles therein adapted for manufacturing electronic components ZA918831B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT48481A IT1242014B (it) 1990-11-15 1990-11-15 Procedimento per il trattamento di fette di silicio per ottenere in esse profili di precipitazione controllati per la produzione di componenti elettronici.

Publications (1)

Publication Number Publication Date
ZA918831B true ZA918831B (en) 1992-08-26

Family

ID=11266818

Family Applications (1)

Application Number Title Priority Date Filing Date
ZA918831A ZA918831B (en) 1990-11-15 1991-11-07 A process for the treatment of silicon wafers in order to achieve controlled precipitation profiles therein adapted for manufacturing electronic components

Country Status (17)

Country Link
US (1) US5403406A (xx)
EP (1) EP0557415B1 (xx)
JP (2) JP3412636B2 (xx)
KR (1) KR100247464B1 (xx)
AT (1) ATE176084T1 (xx)
AU (1) AU9033591A (xx)
CZ (1) CZ84993A3 (xx)
DE (1) DE69130802T2 (xx)
FI (1) FI932024A (xx)
IL (1) IL99979A (xx)
IT (1) IT1242014B (xx)
MY (1) MY110258A (xx)
SG (1) SG64901A1 (xx)
SK (1) SK47093A3 (xx)
TW (1) TW205110B (xx)
WO (1) WO1992009101A1 (xx)
ZA (1) ZA918831B (xx)

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US6485807B1 (en) 1997-02-13 2002-11-26 Samsung Electronics Co., Ltd. Silicon wafers having controlled distribution of defects, and methods of preparing the same
SG64470A1 (en) 1997-02-13 1999-04-27 Samsung Electronics Co Ltd Methods of manufacturing monocrystalline silicon ingots and wafers by controlling pull rate profiles in a hot zone furnace and ingots and wafers manufactured thereby
US6503594B2 (en) 1997-02-13 2003-01-07 Samsung Electronics Co., Ltd. Silicon wafers having controlled distribution of defects and slip
US5994761A (en) * 1997-02-26 1999-11-30 Memc Electronic Materials Spa Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
DE69841714D1 (de) * 1997-04-09 2010-07-22 Memc Electronic Materials Silicium mit niedriger Fehlerdichte und idealem Sauerstoffniederschlag
TW429478B (en) * 1997-08-29 2001-04-11 Toshiba Corp Semiconductor device and method for manufacturing the same
US5882989A (en) * 1997-09-22 1999-03-16 Memc Electronic Materials, Inc. Process for the preparation of silicon wafers having a controlled distribution of oxygen precipitate nucleation centers
US6340392B1 (en) 1997-10-24 2002-01-22 Samsung Electronics Co., Ltd. Pulling methods for manufacturing monocrystalline silicone ingots by controlling temperature at the center and edge of an ingot-melt interface
JPH11150119A (ja) * 1997-11-14 1999-06-02 Sumitomo Sitix Corp シリコン半導体基板の熱処理方法とその装置
JP3746153B2 (ja) * 1998-06-09 2006-02-15 信越半導体株式会社 シリコンウエーハの熱処理方法
US6828690B1 (en) * 1998-08-05 2004-12-07 Memc Electronic Materials, Inc. Non-uniform minority carrier lifetime distributions in high performance silicon power devices
US6336968B1 (en) 1998-09-02 2002-01-08 Memc Electronic Materials, Inc. Non-oxygen precipitating czochralski silicon wafers
WO2000013226A1 (en) 1998-09-02 2000-03-09 Memc Electronic Materials, Inc. Process for preparing an ideal oxygen precipitating silicon wafer
DE69941196D1 (de) 1998-09-02 2009-09-10 Memc Electronic Materials Wärmebehandelte Siliziumscheiben mit verbesserter Eigengetterung
EP1114454A2 (en) 1998-09-02 2001-07-11 MEMC Electronic Materials, Inc. Silicon on insulator structure from low defect density single crystal silicon
EP1125008B1 (en) * 1998-10-14 2003-06-18 MEMC Electronic Materials, Inc. Thermally annealed, low defect density single crystal silicon
JP2000154070A (ja) * 1998-11-16 2000-06-06 Suminoe Textile Co Ltd セラミックス三次元構造体及びその製造方法
US6284384B1 (en) 1998-12-09 2001-09-04 Memc Electronic Materials, Inc. Epitaxial silicon wafer with intrinsic gettering
DE19924649B4 (de) * 1999-05-28 2004-08-05 Siltronic Ag Halbleiterscheiben mit Kristallgitter-Defekten und Verfahren zur Herstellung derselben
US20030051656A1 (en) 1999-06-14 2003-03-20 Charles Chiun-Chieh Yang Method for the preparation of an epitaxial silicon wafer with intrinsic gettering
US6635587B1 (en) 1999-09-23 2003-10-21 Memc Electronic Materials, Inc. Method for producing czochralski silicon free of agglomerated self-interstitial defects
KR100378184B1 (ko) * 1999-11-13 2003-03-29 삼성전자주식회사 제어된 결함 분포를 갖는 실리콘 웨이퍼, 그의 제조공정및 단결정 실리콘 잉곳의 제조를 위한 초크랄스키 풀러
JP2001308101A (ja) * 2000-04-19 2001-11-02 Mitsubishi Materials Silicon Corp シリコンウェーハの熱処理方法及びシリコンウェーハ
DE10024710A1 (de) * 2000-05-18 2001-12-20 Steag Rtp Systems Gmbh Einstellung von Defektprofilen in Kristallen oder kristallähnlichen Strukturen
EP1295324A1 (en) * 2000-06-30 2003-03-26 MEMC Electronic Materials, Inc. Method and apparatus for forming a silicon wafer with a denuded zone
US6599815B1 (en) 2000-06-30 2003-07-29 Memc Electronic Materials, Inc. Method and apparatus for forming a silicon wafer with a denuded zone
US6339016B1 (en) 2000-06-30 2002-01-15 Memc Electronic Materials, Inc. Method and apparatus for forming an epitaxial silicon wafer with a denuded zone
JP4055343B2 (ja) * 2000-09-26 2008-03-05 株式会社Ｓｕｍｃｏ シリコン半導体基板の熱処理方法
JP4106862B2 (ja) 2000-10-25 2008-06-25 信越半導体株式会社 シリコンウェーハの製造方法
US6897084B2 (en) * 2001-04-11 2005-05-24 Memc Electronic Materials, Inc. Control of oxygen precipitate formation in high resistivity CZ silicon
WO2002086960A1 (en) * 2001-04-20 2002-10-31 Memc Electronic Materials, Inc. Method for the preparation of a silicon wafer having stabilized oxygen precipitates
FR2827078B1 (fr) * 2001-07-04 2005-02-04 Soitec Silicon On Insulator Procede de diminution de rugosite de surface
US7883628B2 (en) * 2001-07-04 2011-02-08 S.O.I.Tec Silicon On Insulator Technologies Method of reducing the surface roughness of a semiconductor wafer
US7749910B2 (en) * 2001-07-04 2010-07-06 S.O.I.Tec Silicon On Insulator Technologies Method of reducing the surface roughness of a semiconductor wafer
JP4567251B2 (ja) * 2001-09-14 2010-10-20 シルトロニック・ジャパン株式会社 シリコン半導体基板およびその製造方法
US6955718B2 (en) * 2003-07-08 2005-10-18 Memc Electronic Materials, Inc. Process for preparing a stabilized ideal oxygen precipitating silicon wafer
JP2005051040A (ja) * 2003-07-29 2005-02-24 Matsushita Electric Ind Co Ltd 半導体装置の製造方法及び半導体基板
KR100531552B1 (ko) * 2003-09-05 2005-11-28 주식회사 하이닉스반도체 실리콘 웨이퍼 및 그 제조방법
US7485928B2 (en) * 2005-11-09 2009-02-03 Memc Electronic Materials, Inc. Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
US20090004458A1 (en) * 2007-06-29 2009-01-01 Memc Electronic Materials, Inc. Diffusion Control in Heavily Doped Substrates
US20090004426A1 (en) * 2007-06-29 2009-01-01 Memc Electronic Materials, Inc. Suppression of Oxygen Precipitation in Heavily Doped Single Crystal Silicon Substrates
JP2009177194A (ja) * 2009-03-19 2009-08-06 Sumco Corp シリコンウェーハの製造方法、シリコンウェーハ
EP3653761B1 (en) * 2016-12-28 2024-02-28 Sunedison Semiconductor Limited Silicon wafers with intrinsic gettering and gate oxide integrity yield

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JPS5680139A (en) * 1979-12-05 1981-07-01 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
JPS56158431A (en) * 1980-05-13 1981-12-07 Meidensha Electric Mfg Co Ltd Forming of oxidized film of semiconductor element for electric power
JPS5787119A (en) * 1980-11-19 1982-05-31 Toshiba Corp Manufacture of semiconductor device
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JPH0697664B2 (ja) * 1984-05-11 1994-11-30 住友電気工業株式会社 化合物半導体のアニ−ル法
US4622082A (en) * 1984-06-25 1986-11-11 Monsanto Company Conditioned semiconductor substrates
US4868133A (en) * 1988-02-11 1989-09-19 Dns Electronic Materials, Inc. Semiconductor wafer fabrication with improved control of internal gettering sites using RTA
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US5228927A (en) * 1988-03-25 1993-07-20 Shin-Etsu Handotai Company Limited Method for heat-treating gallium arsenide monocrystals
US5096839A (en) * 1989-09-20 1992-03-17 Kabushiki Kaisha Toshiba Silicon wafer with defined interstitial oxygen concentration

Also Published As

Publication number Publication date
FI932024A (fi) 1993-06-29
MY110258A (en) 1998-03-31
IT9048481A1 (it) 1992-05-15
JPH06504878A (ja) 1994-06-02
KR100247464B1 (ko) 2000-03-15
ATE176084T1 (de) 1999-02-15
WO1992009101A1 (en) 1992-05-29
US5403406A (en) 1995-04-04
DE69130802T2 (de) 1999-08-19
AU9033591A (en) 1992-06-11
IT1242014B (it) 1994-02-02
TW205110B (xx) 1993-05-01
IL99979A0 (en) 1992-08-18
EP0557415B1 (en) 1999-01-20
SK47093A3 (en) 1993-08-11
FI932024A0 (fi) 1993-05-05
DE69130802D1 (de) 1999-03-04
CZ84993A3 (en) 1993-11-17
IT9048481A0 (it) 1990-11-15
SG64901A1 (en) 1999-05-25
JP3412636B2 (ja) 2003-06-03
IL99979A (en) 1995-07-31
JP2003243402A (ja) 2003-08-29
EP0557415A1 (en) 1993-09-01

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