WO2021175222A1 - 一种半导体器件、制造方法及其应用 - Google Patents

一种半导体器件、制造方法及其应用 Download PDF

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WO2021175222A1
WO2021175222A1 PCT/CN2021/078736 CN2021078736W WO2021175222A1 WO 2021175222 A1 WO2021175222 A1 WO 2021175222A1 CN 2021078736 W CN2021078736 W CN 2021078736W WO 2021175222 A1 WO2021175222 A1 WO 2021175222A1
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substrate
trench
layer
semiconductor layer
semiconductor
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PCT/CN2021/078736
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English (en)
French (fr)
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黎子兰
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广东致能科技有限公司
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Priority to JP2022549769A priority Critical patent/JP7497446B2/ja
Priority to KR1020227030710A priority patent/KR20220136421A/ko
Priority to US17/788,030 priority patent/US20230047052A1/en
Priority to EP21764555.5A priority patent/EP4068387A4/en
Publication of WO2021175222A1 publication Critical patent/WO2021175222A1/zh

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Definitions

  • the present disclosure relates to the field of semiconductor devices, and more specifically, to a group III nitride semiconductor device, manufacturing method and application thereof.
  • Group III nitride semiconductor is an important new semiconductor material, which mainly includes AlN, GaN, InN and compounds of these materials such as AlGaN, InGaN, AlInGaN, etc. Taking advantage of the direct band gap, wide band gap, and high breakdown electric field strength of the III-nitride semiconductor, through optimized design of device structure and process, III-nitride semiconductor has great prospects in the field of power semiconductors.
  • High electron mobility and high hole mobility transistors are an important device for the application of group III nitride semiconductors. It is hoped to develop high electron mobility and high hole mobility with high withstand voltage, high power and low on-resistance performance. Transistor.
  • the existing high electron mobility and high hole mobility transistor structure designs are not sufficiently integrated per unit area, and the existing high electron mobility and high hole mobility transistors are mostly normally-on devices, which is not good for energy saving .
  • the present disclosure provides a novel semiconductor device structure and manufacturing method thereof.
  • a method of manufacturing a semiconductor device including:
  • Step 1 Provide a substrate, the substrate having a first surface
  • Step 2 forming a first insulating layer on the first surface of the substrate, the first insulating layer having a first surface parallel to the first surface of the substrate;
  • Step 3 Etch the first insulating layer and part of the substrate to form a plurality of first stepped structures and second stepped structures arranged vertically and spaced apart; the first surface of the plurality of first stepped structures and the The lower part of the second surface of the second stepped structure is respectively constituted by the second surface and the third surface of the substrate, and a plurality of the first surface of the first stepped structure and the second surface of the second stepped structure The upper part is respectively constituted by the second surface and the third surface of the first insulating layer;
  • Step 4 forming a second insulating layer on the third surface of the first step structure and the second step structure;
  • Step 5 A single crystal nucleation layer is formed on the second surface of the first stepped structure composed of the third surface of the substrate, and the second stepped structure of the second stepped structure is formed by the second surface of the substrate.
  • a single crystal nucleation layer is formed on the first surface formed by the surface;
  • Step 6 Taking the single crystal nucleation layer as the nucleation center, the first semiconductor layer is epitaxially grown from the side.
  • a method of manufacturing a semiconductor device including:
  • Step 1 Provide a substrate, the substrate having a first surface
  • Step 2 forming a first insulating layer on the first surface of the substrate, the first insulating layer having a first surface parallel to the first surface of the substrate;
  • Step 3 Etch the first insulating layer and part of the substrate to form a plurality of vertical and spaced first trenches and second trenches;
  • the lower part of the first surface and the lower part of the second surface are respectively constituted by the second surface and the third surface of the substrate, and the upper part of the first surface and the second surface of a plurality of the first grooves and the second grooves Respectively constituted by the second surface and the third surface of the first insulating layer;
  • Step 4 forming a second insulating layer on the third surface of the first trench and the second trench;
  • Step 5 A single crystal nucleation layer is formed on the second surface of the first trench formed by the third surface of the substrate, and the second surface of the substrate is formed in the second trench. A single crystal nucleation layer is formed on the first surface formed by the two surfaces;
  • Step 6 Taking the single crystal nucleation layer as the nucleation center, the first semiconductor layer is epitaxially grown from the side.
  • the second surface and the third surface of the substrate have a hexagonal symmetrical lattice structure.
  • the second surface and the third surface of the substrate are selected from the group consisting of Si (111) plane, Al2O3 (0001) plane, SiC (0001) plane, SiC (000-1) plane, GaN (0001) plane of GaN or (000-1) plane of GaN.
  • a single crystal nucleation layer is formed on a portion of the second surface of the first trench or the first stepped structure formed by the third surface of the substrate, and A single crystal nucleation layer is formed on a part of the second trench or the first surface of the second step structure formed by the second surface of the substrate.
  • step 5 can be replaced with step 5', in which step 5'takes the single crystal nucleation layer as a nucleation center, and epitaxially grows a first semiconductor layer in the trench side The first sub-layer of the first sub-layer, and then the first sub-layer as the core, the growth of the third doped semiconductor layer, and then the second sub-layer of the first semiconductor layer is continued to grow, the third semiconductor The layer is N-type doped or P-type doped.
  • a buffer layer is deposited on the nucleation layer.
  • the first and second trenches or the first and second stepped structures are formed, it further includes coplanar deposition to form a sacrificial layer, and the sacrificial layer and the first insulating layer have High etching selection ratio, and then dry etching to retain the sacrificial layer on the first surface and the second surface of the first trench and the second trench.
  • the sacrificial layer is used to form a second insulating layer on the third surface of the first and second trenches or the first and second stepped structures, and then the sacrificial layer is removed .
  • a fourth insulating layer is respectively formed on the first surface and the second surface of the first and second trenches or the first and second stepped structures.
  • the first insulating layer at the portion between the first and second trenches or the first and second stepped structures is exposed through a photolithography pattern, and the exposed first insulating layer is etched to remove the exposed first insulating layer.
  • a trench or the fourth insulating layer on the second surface of the first stepped structure and the fourth insulating layer on the first surface of the second trench or the second stepped structure, thereby exposing the substrate in the first trench The third surface and the second surface of the substrate in the second trench.
  • the nucleation layer on all the insulating layers needs to be separately removed; Growing without growing the nucleation layer on all the insulating layers.
  • the growth of the first semiconductor layer includes growth in a direction perpendicular to the first surface of the substrate, when the growth of the first semiconductor layer in a direction perpendicular to the first surface of the substrate exceeds the growth of the trench Or when the height of the step structure is high, the excess portion of the first semiconductor layer is removed by planarization or etching technology.
  • the growth of the first sublayer and the second sublayer of the first semiconductor layer and the growth of the third semiconductor layer include growth in a direction perpendicular to the first surface of the substrate.
  • the growth of the first sublayer, the second sublayer, and the third semiconductor layer of a semiconductor layer in the direction perpendicular to the first surface of the substrate exceeds the height of the trench or the step structure, through planarization or The etching technique removes the excess part or keeps the excess part.
  • a photolithography pattern is formed to expose a region between the adjacent first trench and the second trench, and the first insulating layer and part of the substrate in the region are etched , Exposing the first surface of the first semiconductor layer having the spontaneous and piezoelectric polarization effect and the opposite second surface having the spontaneous and piezoelectric polarization effect.
  • a photolithography pattern is formed to expose a partial area between the adjacent first trench and the second trench, and to expose the first semiconductor layer with spontaneous and piezoelectric polarization effects.
  • One side or second side; the first insulating layer, part of the substrate in the region, and the first side or the second side exposed by the first semiconductor layer are etched, exposing the first The second surface of the semiconductor layer or the first surface opposite thereto.
  • a photolithography pattern is formed to expose a part of the area between the adjacent first trench and the second trench, and the first insulating layer and part of the substrate are etched to expose
  • the first semiconductor layer has a first surface or a second surface with spontaneous and piezoelectric polarization effects, and the second surface or the first surface opposite to it is still covered by the substrate and the first insulating layer .
  • a third insulating layer is formed on the etched substrate, and then the third insulating layer on the first semiconductor layer is removed.
  • a second semiconductor layer is formed on the exposed first semiconductor layer, so that a two-dimensional electron gas and/or A two-dimensional hole gas is formed at the interface of the second surface of the first semiconductor layer adjacent to the second semiconductor layer.
  • a plurality of alternate stacks of the first semiconductor layer and the second semiconductor layer are continuously formed on the second semiconductor.
  • a dielectric layer is deposited, the dielectric layer is lithographically etched, and then metal is deposited so as to form along the length direction of the trench on the first side or the second side of the first semiconductor layer.
  • a fourth electrode is formed on the second surface or the first surface of the first semiconductor layer opposite to the first electrode, the second electrode, and the third electrode.
  • the three semiconductor layers are connected.
  • the nucleation layer is at a position corresponding to the first electrode, a position corresponding to the third electrode, or a position corresponding to the second electrode and the third electrode set up.
  • a current blocking layer may also be formed in a direction perpendicular to the first surface or the second surface of the trench.
  • corresponding doping is performed in the area corresponding to the first electrode and the area corresponding to the third electrode of the first semiconductor layer to form the corresponding first electrode area and the third electrode area.
  • the doping of the first electrode and the third electrode region is N-type doping; when the HHMT device is formed, the doping of the second electrode and the third electrode region is For P-type doping.
  • the doping of the first electrode region and the third electrode region is performed simultaneously with the doping of the third semiconductor layer, or the doping of the first electrode region and the doping of the third electrode region And the doping of the third semiconductor layer is performed sequentially.
  • a semiconductor device including:
  • a substrate the substrate having a first surface
  • the lower part of the first surface and the second surface of the first groove and the second groove are respectively formed by the second surface and the third surface of the substrate, and the first groove and the second groove
  • the upper part of the first surface and the second surface is composed of the second surface and the third surface of the first insulating layer;
  • a single crystal nucleation layer formed on the second surface of the first trench composed of the third surface of the substrate, and in the second trench composed of the second surface of the substrate A single crystal nucleation layer formed on the first surface of the structure;
  • the first semiconductor layer is epitaxially grown with the single crystal nucleation layer as the nucleation center.
  • the single crystal nucleation layer formed on a part of the second surface of the first trench the single crystal nucleation layer formed on a part of the first surface of the second trench Nuclear layer.
  • the first semiconductor layer is divided into a first sublayer and a second sublayer of the first semiconductor layer along the length of the trench, and the first sublayer and the second sublayer are in the first sublayer and the second sublayer.
  • a doped third semiconductor layer is also arranged between the layers.
  • the second surface and the third surface of the substrate have a hexagonal symmetrical lattice structure.
  • the second surface and the third surface of the substrate are selected from the group consisting of Si(111), Al2O3 (0001) plane, SiC (0001) plane, SiC (000-1) plane, GaN (0001) plane 0001) plane or (000-1) plane of GaN.
  • a second insulating layer is formed on the third surfaces of the first and second trenches.
  • a fourth insulating layer is respectively formed on the first surface of the first trench and on the second surface of the second trench.
  • the first semiconductor layer is flush with the first insulating layer or the first semiconductor layer has a portion protruding from the first insulating layer.
  • first insulating layer, the second insulating layer and the fourth insulating layer are silicon dioxide layers.
  • a semiconductor device including:
  • a substrate the substrate having a first surface
  • a plurality of first trenches and second trenches arranged in the substrate perpendicular to the first surface of the substrate and arranged at intervals;
  • a second insulating layer formed on the third surface of the plurality of the first trenches and the second trenches;
  • a single crystal nucleation layer formed on the second surface in the first trench and on the first surface in the second trench,
  • the first semiconductor layer has a first surface and a second surface parallel to the trench and perpendicular to the substrate.
  • the first surface with spontaneous polarization effect and piezoelectric polarization effect and the second surface opposite to it;
  • a second semiconductor layer is formed overlying the first semiconductor layer, and the forbidden band width of the second semiconductor layer is greater than the forbidden band width of the first semiconductor layer, so that the first surface of the first semiconductor and the Two-dimensional electron gas and two-dimensional hole gas are respectively formed on the second surface.
  • a substrate the substrate having a fourth surface
  • a third insulating layer formed on the fourth surface of the substrate
  • a plurality of first trenches and second trenches arranged in the substrate perpendicular to the fourth surface of the substrate and arranged at intervals;
  • a second insulating layer formed on the third surface of the plurality of the first trenches and the second trenches;
  • the single crystal nucleation layer formed on the second surface in the first trench and on the first surface in the second trench, and on the first surface and the first surface in the first trench A fourth insulating layer formed on the second surface in the second trench;
  • the first surface of the first surface and the second surface of the second trench, and the first surface perpendicular to the fourth surface of the substrate and protruding from the fourth surface of the substrate with spontaneous polarization effect and piezoelectric polarization effect One side and the second side opposite to it;
  • a second semiconductor layer is formed overlying the first semiconductor layer, and the forbidden band width of the second semiconductor layer is greater than the forbidden band width of the first semiconductor layer, so that the first surface of the first semiconductor and the Two-dimensional electron gas and two-dimensional hole gas are respectively formed on the second surface.
  • a substrate having a first surface and a fifth surface parallel to the first surface but lower than the first surface;
  • a third insulating layer formed on the first surface and the fifth surface of the substrate
  • a plurality of first trenches and second trenches arranged in the substrate perpendicular to the first surface of the substrate and arranged at intervals;
  • a second insulating layer formed on the third surface of the first trench and the second trench;
  • the single crystal nucleation layer formed on the second surface in the first trench and the first surface in the second trench, the first surface in the first trench and the second surface A fourth insulating layer respectively formed on the second surface in the trench;
  • the first semiconductor layer in the first trench and the second trench, and the first semiconductor layer protrudes from the fifth surface of the substrate, and the first semiconductor layer has a shape parallel to the first semiconductor layer.
  • a first surface with a spontaneous polarization effect and a piezoelectric polarization effect extending upwards from the first surface of a trench and the second surface of the second trench and perpendicular to the fifth surface of the substrate;
  • a second semiconductor layer is formed to cover the first surface of the first semiconductor layer, and the forbidden band width of the second semiconductor layer is greater than the forbidden band width of the first semiconductor layer.
  • a two-dimensional electron gas is formed on the first surface of the semiconductor.
  • a substrate having a first surface and a sixth surface parallel to the first surface but lower than the first surface;
  • a plurality of first trenches and second trenches arranged in the substrate perpendicular to the first surface of the substrate and arranged at intervals;
  • a second insulating layer formed on the third surface of the first trench and the second trench;
  • the single crystal nucleation layer formed on the second surface in the first trench and the first surface in the second trench is formed on the first surface in the first trench and the A fourth insulating layer respectively formed on the second surface in the second trench;
  • the first semiconductor layer in the first trench and the second trench, and the first semiconductor layer protrudes from the sixth surface of the substrate, and the first semiconductor layer has a shape parallel to the first semiconductor layer.
  • a second semiconductor layer is formed to cover the first surface of the first semiconductor layer, and the forbidden band width of the second semiconductor layer is higher than the forbidden band width of the first semiconductor layer.
  • Two-dimensional hole gas is formed on the second surface of the semiconductor.
  • the first semiconductor layer is divided into a first sublayer of the first semiconductor layer and a second sublayer of the second semiconductor layer in a direction along the length of the trench;
  • a third semiconductor layer is also arranged between the first sub-layer and the second sub-layer.
  • first surface and the second surface of the trench have a hexagonal symmetrical lattice structure.
  • the second surface and the third surface of the substrate are selected from the group consisting of Si (111) plane, Al2O3 (0001) plane, SiC (0001) plane, SiC (000-1) plane, GaN (0001) plane or (000-1) plane of GaN.
  • the third semiconductor layer is a P-type buried layer or an N-type buried layer.
  • a first electrode, a second electrode, and a third electrode are respectively formed on the third insulating layer along the first surface/second surface side of the first semiconductor in the longitudinal direction of the trench.
  • the first electrode, the second electrode and the third electrode are respectively connected to the second semiconductor layer; or the first electrode and the third electrode are connected to the first semiconductor, and the second electrode Connected to the second semiconductor.
  • the projection of the third semiconductor layer on the first surface/second surface of the first semiconductor layer falls on the second electrode on the first surface/second surface of the first semiconductor layer Within the scope of the projection or partially overlap with it.
  • first electrode, the second electrode and the third electrode are separated by a dielectric layer.
  • the A fourth electrode is formed on the three insulating layers, and the fourth electrode is connected to the third semiconductor layer.
  • the doping concentration of the third semiconductor layer is sufficient to deplete 95%-100% of the two-dimensional electrons in at least a part of the area overlapping the projection area of the second electrode without device bias.
  • Gas/two-dimensional cavitation gas is used to deplete 95%-100% of the two-dimensional electrons in at least a part of the area overlapping the projection area of the second electrode without device bias.
  • the nucleation layer is formed at a position corresponding to the first electrode, a position corresponding to the third electrode, or a position corresponding to the second electrode and the third electrode ⁇ Settings.
  • a current blocking layer is formed in a direction perpendicular to the first surface or the second surface of the trench.
  • the region of the first semiconductor layer corresponding to the first electrode and the region corresponding to the third electrode have corresponding doping to form corresponding first electrode regions and third electrode regions.
  • the doping of the first electrode and the third electrode region is N-type doping; when the HHMT device is formed, the doping of the second electrode and the third electrode region is For P-type doping.
  • an electronic device is provided.
  • the electronic device is a power supply device, a mobile phone, or a power amplifier in a communication system.
  • FIGS. 1-10 are schematic diagrams of a semiconductor device structure and a manufacturing method thereof according to an embodiment
  • FIGS. 11-14 are schematic diagrams of alternative semiconductor device structures and manufacturing methods thereof.
  • 15-17 are schematic diagrams of alternative semiconductor device structures and manufacturing methods thereof.
  • 19-21 is a schematic diagram of an optional semiconductor device structure and manufacturing method thereof.
  • 22-24 are schematic diagrams of alternative semiconductor device structures and manufacturing methods thereof.
  • 25-28 are schematic diagrams of alternative semiconductor device structures and manufacturing methods thereof.
  • FIG. 29 is a schematic diagram of an alternative method of manufacturing a semiconductor device.
  • FIG. 30 is a schematic diagram of an alternative method of manufacturing a semiconductor device.
  • the semiconductor device of the present disclosure is a compound semiconductor device containing a nitride semiconductor material, also referred to as a nitride semiconductor device, wherein the nitride semiconductor device is a group III nitride semiconductor device.
  • the III-nitride semiconductor device includes a transistor using Wurtzite III-nitride semiconductor material.
  • the transistor is a GaN transistor containing a GaN semiconductor material.
  • the GaN transistor is a normally closed transistor GaN-HEMT and/or GaN-HHMT.
  • FIGS. 1-10 A semiconductor device and a manufacturing method thereof according to an embodiment will be described with reference to FIGS. 1-10.
  • the semiconductor device includes a substrate 100.
  • the material of the substrate 100 can be selected according to actual needs. The present disclosure does not limit the specific material of the substrate 100, as long as the substrate material can meet Any substrate material with a hexagonal symmetry lattice structure on the side surface of the vertical trench formed perpendicular to the surface thereof can be used.
  • the material of the substrate 100 may be Si, Al2O3, SiC, GaN, etc. Since the silicon substrate has the advantages of low price and strong workability, the Si substrate is taken as an example for further description in this disclosure. .
  • the single crystal silicon substrate may be a silicon substrate using a (110) or (112) plane.
  • a substrate 100 is provided, and the substrate has a first surface 1001; a first insulating layer 101 is formed on the first surface 1001 of the substrate 100.
  • the first insulating layer 101 is thermally oxidized or For the SiO2 layer formed by vapor deposition, for example, the thickness of the first insulating layer 101 is about 0.5 micrometers. It should be noted that the numerical range in the present disclosure is only an example and not a limitation of the present disclosure.
  • the first insulating layer 101 has a first surface 1011 parallel to the first surface 1001 of the substrate.
  • the trenches include first trenches 102 and second trenches 102' arranged at intervals.
  • the dimensions of the groove and the second groove are the same.
  • the depth of the first trench and the second trench is about 5 microns.
  • the lower part of the first surface 1021 and the second surface 1022 of each groove are respectively constituted by the second surface 1002 and the third surface 1003 exposed by the substrate, wherein the second surface 1002 and the third surface 1003 of the substrate have hexagonal symmetry.
  • Lattice structure such as Si(111) plane.
  • the second surface and the third surface of the substrate can also be Al2O3 (0001) plane, SiC (0001) plane, or SiC (000-1) plane, GaN (0001) plane, or GaN (000- 1) Noodles and so on.
  • the upper part of the first surface 1021 and the second surface 1022 of each trench are respectively constituted by the second surface 1012 and the third surface 1013 of the first insulating layer 101.
  • a second insulating layer 103 is formed on the third surface 1023 of the trench.
  • the second insulating layer 103 may be a silicon dioxide layer formed by oxidation.
  • its thickness is About 500nm.
  • a fourth insulating layer 105 is formed on the first surface 1021 and the second surface 1022 of the trench.
  • the thickness of the fourth insulating layer is about 100 nm.
  • the interaction between the silicon substrate and the Ga-containing precursor is more conducive to improving the selectivity of the external delay.
  • part of the fourth insulating layer 105 on the second surface of the first trench and on the first surface of the second trench is removed, and the first trench of the substrate 100 exposed in the first trench is removed.
  • a single crystal nucleation layer 106 is formed on the third surface 1003 and the second surface 1002 of the substrate 100 exposed in the second trench.
  • the single crystal nucleation layer is an ALN layer
  • the growth direction of the ALN crystal is the ⁇ 0001> direction
  • the surface thereof is the (0001) plane.
  • the position where the single crystal nucleation layer is located corresponds to the formation position of the first electrode (source) of the subsequent device. Since the subsequent device structure takes the first electrode (source) as the reference point, the semiconductor device The structure can exhibit a symmetrical structure, and the voltage of the first electrode region (source region) is very low, so it is insensitive to crystal quality, thereby minimizing the influence of poor crystal quality in the nucleation region.
  • a first semiconductor layer 201 is selectively grown with the nucleation layer 106 as the core.
  • the first semiconductor layer 201 may be nitride, for example, intrinsic GaN (i-GaN) or unintentional Doped GaN layer. Due to the existence of the trench 102, the first semiconductor layer 201 starts to grow from the nucleation layer along the trench 102, where the growth includes growth along the first direction of the trench and also includes the second direction perpendicular to the trench. The first semiconductor layer 201 can also be grown outside the trench, and the first semiconductor layer 201 outside the trench can be removed by planarization or etching technology.
  • the first semiconductor layer can grow very flat during lateral epitaxial growth, and the vertical surface of the semiconductor device composed of it as a functional layer can be formed very flat with the help of the trench. Therefore, it is easy to achieve a higher aspect ratio. More specifically, when the first semiconductor layer 201 is used as a vertical channel, a higher channel density per unit area can be achieved, thereby reducing the resistance of the device and improving the performance of the device.
  • FIGS. 1-10 in which FIGS. 1, 2, 6, and 10 are cross-sectional views, and FIGS. 3-5 and 7-9 are top views.
  • a substrate 100 is provided.
  • the substrate may be a silicon substrate with a (110) or (112) plane.
  • a first insulating layer 101 is formed on the first surface 1001 of the substrate 100.
  • the first insulating layer 101 is a SiO2 layer formed by thermal oxidation or vapor deposition.
  • the thickness of the first insulating layer 101 is about 0.5 micrometers.
  • Step 2 As shown in FIG. 2, lithography is performed on the first insulating layer 101 at intervals to expose part of the inside of the first insulating layer 101, and then the first insulating layer 101 and the substrate below it are etched at the lithographic position 100.
  • Vertical trenches are formed.
  • the trenches include first trenches 102 and second trenches 102' arranged at intervals.
  • the two side surfaces of each trench, that is, the lower part of the first surface 1021 and the second surface 1022 are respectively constituted by the second surface 1002 and the third surface 1003 exposed by the etched substrate.
  • the second surface 1002 and the third surface 1003 of the substrate have a hexagonal symmetrical lattice structure, such as a Si(111) plane.
  • the second surface and the third surface of the substrate may also be Al2O3 (0001) plane, SiC (0001) plane, SiC (000-1) plane, GaN (0001) plane, GaN (000-1) plane, or the like.
  • Step 3 As shown in FIG. 3, on the basis of the structure formed in Step 2, a sacrificial layer 104 is formed by coplanar deposition.
  • the sacrificial layer 104 is a silicon nitride layer with a thickness of about 100 nanometers. It can be understood that the choice of the first insulating layer and the sacrificial layer only needs to have a high etching selection ratio between the two. For example, when the sacrificial layer is etched, the etchant basically does not etch the first insulating layer. Or its etching is extremely slow.
  • Step 4 As shown in FIG. 4, dry etching is performed to remove the sacrificial layer 104 on the first surface 1011 of the first insulating layer 101 and the sacrificial layer 104 on the third surface 1023 of the trench 102102', leaving the trench The first surface 1021 of 102 (102') and the first sacrificial layer 104 on the second surface 1022.
  • Step 5 As shown in FIG. 5, through an oxidation process, a second insulating layer 103 (silicon dioxide layer) is formed on the third surface 1023 of each trench.
  • the protection of a sacrificial layer 104 is not oxidized, and the insulating layer can avoid the incompatibility between gallium atoms and the silicon substrate during the subsequent growth of nitride semiconductor, and avoid the phenomenon of melt-back.
  • the second insulating layer can also effectively block the leakage current between the nitride semiconductor and the silicon substrate, and reduce the parasitic capacitance caused by the silicon substrate.
  • Step 6 As shown in FIG. 6, using the etching selection ratio of the first sacrificial layer 104 and the silicon dioxide layer, the first sacrificial layer on the first surface and the second surface of each trench is removed by selective wet etching 104.
  • Step 7 As shown in FIG. 7, through an oxidation process, a thinner fourth insulating layer 105 (silicon dioxide layer) is formed on the first surface and the second surface of the trench 102, respectively.
  • the thickness of the fourth insulating layer is equal to
  • the thicknesses of the first and second insulating layers are set to be different, so that when the fourth insulating layer is subsequently removed, there are still enough thick first and second insulating layers to protect the substrate.
  • These insulating layers can avoid the incompatibility of gallium atoms with the silicon substrate during the subsequent growth of nitride semiconductors, and avoid the phenomenon of melt-back, which is essential for the production of gallium nitride-based semiconductor devices on the silicon substrate. of.
  • Step 8 As shown in FIG. 8, a photoresist is applied, and a photolithography pattern is formed between the first trench and the second trench to expose the first insulating layer between the first trench and the second trench 101. It can be understood that the photolithography pattern can expose all the first insulating layer 101 between the first trench and the second trench.
  • Step 9 As shown in FIG. 9, remove the exposed fourth insulating layer 105 on the second surface of the first trench and on the first surface of the second trench, because the thickness of the first insulating layer is much larger than that of the The thickness of the fourth insulating layer. Therefore, in the process of removing part of the fourth insulating layer, the exposed part of the first insulating layer is only etched to a small thickness and will not be completely removed. Then the photoresist is removed, so that the A portion of the third surface 1003 of the substrate 100 is exposed in the first trench and a portion of the second surface 1002 of the substrate 100 is exposed in the second trench.
  • Step 10 As shown in FIG. 9, due to the melt-back effect between the silicon substrate and gallium, GaN cannot be directly deposited on the silicon substrate. It is usually necessary to deposit an AlN nucleation layer first, and then form the subsequent nitride semiconductor structure on this basis. Therefore, a single crystal AlN nucleation layer is respectively formed on the third surface 1003 of the substrate 100 in the exposed first trench and on the second surface 1002 of the substrate 100 in the exposed second trench. 106.
  • the growth direction of the single crystal AlN crystal is ⁇ 0001>, and the surface is the (0001) plane.
  • the selectivity of AlN is very low, and it is easy to generate polycrystalline or amorphous AlN on the insulating layer under normal process conditions, which is unfavorable for forming the desired structure. Therefore, it is necessary to separately remove AlN on the silicon dioxide layer after the nucleation layer is formed. Or, when the AlN nucleation layer is grown, a chlorine-containing gas is introduced to ensure that it grows only on the silicon substrate and not on the silicon dioxide layer.
  • the nucleation layer may also be GaN. At this time, it is easier to achieve nucleation only on the exposed substrate surface through process adjustment.
  • Step 11 As shown in FIG. 10, the first semiconductor layer 201 is then grown outwards with the nucleation layer 106 as the core side. Due to the existence of the trench 102, the first semiconductor layer 201 starts from the nucleation layer along the trench 102
  • the start side is epitaxial growth, where the growth includes growth along the first direction of the trench and also includes growth in the second direction perpendicular to the trench.
  • the first semiconductor layer 201 can also grow outside the trench and be planarized. Or etching technology removes the first semiconductor layer 201 outside the trench.
  • the side epitaxy can effectively improve the quality of the nitride semiconductor crystal in the side epitaxial region, thereby improving the electrical performance of the device.
  • Removal of the first semiconductor layer outside the trench can make the device in a constrained state during the formation process, which is conducive to the formation of a specific structure and size, helps to form a device with a higher aspect ratio, and provides in addition to growth. In addition to the adjustment of process parameters, it is a means to achieve a higher aspect ratio device. Since the growth of the first semiconductor in the trench is restricted by the first surface and the second surface of the trench, the growth process of the first semiconductor layer avoids The situation that the growth plane cannot be kept completely vertical or the growth plane is not on the same plane, as well as the situation that multiple and complicated growth planes may appear, facilitates the control of the device and the improvement of the electrical performance. It can be understood that the growth of the first semiconductor layer 201 outside the trench may not be removed, and a portion protruding from the trench may be formed.
  • a buffer layer can also be formed by deposition.
  • the structure of the first trench and the second trench can also be replaced with the corresponding first step structure and second step structure, and then a nucleation layer is formed on one sidewall of each step structure, and the substrate An insulating layer is formed on the first surface of the first surface and the third surface of the step parallel to the first surface of the substrate, and then the corresponding buffer layer and the first semiconductor layer 201 are epitaxially grown with the nucleation layer as the core. Refer to the previous manufacturing method for this, and will not repeat it.
  • FIGS. 11-14 are top views.
  • the first insulating layer 101 and the substrate 100 outside the first semiconductor layer are etched, and the first insulating layer 101 and part of the substrate 100 are removed, so that the first semiconductor layer 201 is protruding and etched
  • the fourth surface 1004 of the back substrate 100 The first surface 2013 of the first semiconductor layer 201 having the spontaneous polarization effect and the piezoelectric polarization effect and the second surface 2014 having the spontaneous polarization effect and the piezoelectric polarization effect opposite thereto, when the first semiconductor layer is GaN
  • the first face 2013 is the (0001) face
  • the second face 2014 is the (000-1) face.
  • a third insulating layer 107 is formed on the etched substrate 100 to isolate the exposed silicon substrate.
  • the third insulating layer may be a silicon dioxide layer.
  • a second semiconductor layer 202 is formed to cover the first semiconductor layer 201.
  • the second semiconductor layer may be an AlN layer or an AlGaN layer, and then two semiconductor layers are formed on the first surface 2013 and the second surface 2014 of the first semiconductor layer. Two-dimensional electron gas 2DEG and two-dimensional hole gas 2DHG.
  • a first electrode 401, a second electrode 402, and a third electrode 403 are respectively formed on the second semiconductor layer 202 in a direction along the length of the trench.
  • the first electrode is a source
  • the second electrode is a gate
  • the third electrode is a drain. It is also possible to form the first electrode and the third electrode on the first semiconductor layer 201 along the direction of the two-dimensional electron gas transport.
  • the first electrode to the third electrode are all formed on the surface of the third insulating layer of the substrate 100, so that while the structure of the semiconductor device has a vertical channel, the arrangement of the electrodes is particularly suitable for the planarization process, which is beneficial to improve The integration density of semiconductor devices.
  • the manufacturing method for manufacturing the semiconductor device is exemplarily described below.
  • the above-mentioned manufacturing method may further include the following steps.
  • Step 12 As shown in FIG. 11, a photolithography pattern is formed to expose the entire area between the adjacent first trench and the second trench from above, and the first insulating layer 101 and part of the substrate 100 in the etched area The material is such that the first semiconductor layer covering the fourth insulating layer in the trench 102 protrudes from the fourth surface 1004 of the etched substrate.
  • Step 13 As shown in FIG. 12, a third insulating layer 107 is formed on the fourth surface 1004 of the etched substrate 100.
  • the third insulating layer may be a silicon dioxide layer formed by oxidation, and then The fourth insulating layer covering the first semiconductor layer 201 is removed, thereby exposing the first surface 2013 of the first semiconductor layer 201 which has the spontaneous polarization effect and the piezoelectric effect and the opposite side 2013 which has the spontaneous polarization effect and the piezoelectric effect.
  • Step 14 As shown in FIG. 13, a second semiconductor layer 202 is formed overlying the first semiconductor layer 201.
  • the second semiconductor layer may be an AlN layer or an AlGaN layer.
  • Two-dimensional electron gas 2DEG and two-dimensional hole gas 2DHG are respectively formed on the surface 2014.
  • Step 15 As shown in Figure 14, a dielectric layer is deposited, the first dielectric layer is lithographically etched, and then metal is deposited thereon, so as to be on the first semiconductor layer 201 along the two-dimensional electron gas transmission direction.
  • a first electrode and a third electrode are respectively formed on the surface, and a second electrode is formed on the second semiconductor layer 202 along the two-dimensional electron gas transmission direction, wherein the second electrode is located in the middle of the first electrode and the third electrode.
  • the first electrode is a source
  • the second electrode is a gate
  • the third electrode is a drain.
  • the first to third electrodes are all formed on the second semiconductor layer 202 along the two-dimensional electron gas transport direction.
  • FIGS. 15-17 are top views.
  • a first sub-layer 2011 of a first semiconductor, a third semiconductor 203 and a second sub-layer 2012 of the first semiconductor are formed in the trench along the direction of the first surface and the second surface of the channel, The first sub-layer, the third semiconductor 203 and the second sub-layer completely fill the trench so that the layers are parallel to and coplanar with the first surface of the first semiconductor.
  • the third semiconductor layer has P-type doping or N-type doping.
  • the P-type doping is P-type GaN
  • the N-type doping is N-type GaN.
  • the doping concentration is 1E17-5E19/cm3, more preferably 1E+18/cm3-5E+19/cm3.
  • the P-type GaN layer can deplete the two-dimensional electron gas on the first side of the first semiconductor layer; the N-type GaN layer can deplete the two-dimensional hole gas on the second side of the first semiconductor layer, so that the device has a constant Closed state; the specific choice of P-type doping or N-type doping depends on the specific type of subsequent devices. For HEMT devices, choose P-type doping, and for HHMT devices, choose N-type doping. . It is understandable that the doping can be gradual. The rest of the structural features are the same as the above-mentioned embodiments, and will not be repeated here.
  • the projection of the third semiconductor on the first surface of the first semiconductor on the first semiconductor falls within the range of the projection of the second electrode in this direction, or partially overlaps the projection of the second electrode in this direction.
  • the doping concentration and size parameters of the third semiconductor layer can be set according to the device parameters, as long as it can deplete 95%-100% of the two-dimensional electron gas or two-dimensional hole gas, two-dimensional charge carriers The higher the gas concentration, the corresponding doping concentration can be increased accordingly.
  • the manufacturing method for the optional semiconductor device is specifically described below.
  • Step 11' As shown in FIGS. 15-17, after the nucleation layer 106 is formed, the first sub-layer 2011 of the first semiconductor is selectively grown with the nucleation layer 106 as the core. Due to the existence of the trench 102, the first sub-layer 2011 is The sub-layer 2011 starts from the nucleation layer and grows epitaxially along the starting side of the trench 102, wherein the growth includes growth along the first surface or the second surface of the trench in the first direction, and the third surface perpendicular to the trench. Growth. Then, with the first sub-layer 2011 as the core, a doped third semiconductor layer 203 is grown.
  • the growth of the third semiconductor layer 203 also includes growth along the first surface or the second surface of the trench in the first direction, and also includes Growth in the second direction perpendicular to the first or second surface of the trench, and growth perpendicular to the third surface of the trench.
  • the third semiconductor layer 203 is located within the projection range of the gate in the projection direction of the subsequent device, or partially overlaps the projection of the gate in this direction.
  • the second sublayer 2012 of the first semiconductor layer is continued to grow.
  • the second sublayer of the first semiconductor layer may also be an intrinsic GaN layer or an unintentionally doped GaN layer.
  • the growth direction of the second sublayer 2012 of the first semiconductor layer is the same as the growth direction of the first sublayer or the third semiconductor layer.
  • the coplanar structure can make the device in a constrained state during the formation process, is conducive to the formation of a specific structure and size, helps to form a device with a higher aspect ratio, and provides an implementation in addition to the adjustment of growth process parameters Since the growth of the first semiconductor and the third semiconductor in the trench is restricted by the first surface and the second surface of the trench, the growth process of the first semiconductor layer and the third semiconductor avoids Keep it completely vertical or the growth surface is not on the same plane, and avoid the possibility of multiple and complicated growth surfaces, so as to facilitate the control of the device and the improvement of electrical performance.
  • part of the first sub-layer, the third semiconductor layer and the second sub-layer may also be located outside the trench.
  • FIG. 18 is shown as a top view.
  • a fourth electrode 404 is formed on the first semiconductor layer 201 in the direction of the two-dimensional hole gas transport, that is, in the direction away from the two-dimensional electron gas transport.
  • the fourth electrode may be a body electrode for contact with the third semiconductor layer, so as to better control the threshold voltage. It is understandable that the fourth electrode may also be formed on the fourth surface of the substrate. The location and method for forming the fourth electrode are not specifically limited here, as long as it can contact the third electrode.
  • one side of the first semiconductor layer is etched to remove the first insulating layer 101 and part of the substrate 100 so that the substrate has a first surface and a fifth surface that is lower than and parallel to the first surface.
  • the first surface 2013 of the first semiconductor layer 201 having the spontaneous polarization effect and the piezoelectric polarization effect is exposed.
  • the first semiconductor layer is GaN
  • the first surface 2013 is the (0001) surface.
  • the second surface 2014 opposite to the first surface 2013 with spontaneous polarization effect and piezoelectric polarization effect is still covered by the substrate and the first insulating layer, and the second surface 2014 is the (000-1) surface of GaN .
  • a third insulating layer 107 is formed on the etched substrate 100 to isolate the exposed silicon substrate.
  • the third insulating layer may be a silicon dioxide layer.
  • a second semiconductor layer 202 is formed on the first surface 2013 of the first semiconductor layer 201.
  • the second semiconductor layer is an AlN layer or an AlGaN layer, thereby forming a two-dimensional electron gas 2DEG on the first surface 2013 of the first semiconductor layer.
  • the first semiconductor layer and the second layer may form a plurality of alternate stacked structures to form a HEMT device with a multi-channel structure of a plurality of two-dimensional electron gas 2DEGs.
  • Step 12' as shown in FIG. 19, a photolithography pattern is formed to expose the area on the first surface 2013 side of the first semiconductor layer, and the first insulating layer 101 and part of the substrate 100 in the area are etched to expose the first semiconductor layer
  • the second surface 2014 opposite to the first surface 2013, which has the spontaneous polarization effect and the piezoelectric polarization effect, is still surrounded by the fourth insulating layer, the substrate, and the first insulating layer.
  • a third insulating layer 107' is formed on the etched substrate 100.
  • the third insulating layer may be a silicon dioxide layer formed by oxidation.
  • the fourth insulating layer covering the first surface 2013 of the first semiconductor layer 201 is removed.
  • a second semiconductor layer 202 is formed by chemical deposition on the first surface 2013 of the first semiconductor layer 201.
  • the second semiconductor layer may be an AlN layer or an AlGaN layer, so that the A two-dimensional electron gas 2DEG is formed on the first surface 2013 of the device.
  • the substrate has a first surface and a sixth surface that is lower than and parallel to the first surface .
  • the second surface 2014 of the first semiconductor layer 201 having the spontaneous polarization effect and the piezoelectric polarization effect is exposed.
  • the first semiconductor layer is GaN
  • the second surface 2014 is the (000-1) surface.
  • the first surface 2013 opposite to the first surface 2013, which has the spontaneous polarization effect and the piezoelectric polarization effect is still covered by the substrate and the first insulating layer, and the first surface 2013 is the (0001) surface of GaN.
  • a third insulating layer 107 is formed on the etched substrate 100 to isolate the exposed silicon substrate.
  • the third insulating layer may be a silicon dioxide layer formed by oxidation.
  • a second semiconductor layer 202 is formed to cover the second surface 2014 of the first semiconductor layer 201.
  • the second semiconductor layer is an AlN layer or an AlGaN layer, thereby forming a two-dimensional hole gas on the first surface 2013 of the first semiconductor layer. 2DHG.
  • the first semiconductor layer and the second semiconductor layer may form a plurality of alternate stacked structures, thereby forming an HHMT device having a plurality of two-dimensional hole gas 2DHG channel structures.
  • Step 12' form a photolithography pattern to expose the area on the second surface 2014 side of the first semiconductor layer, and etch the material of the first insulating layer 101 and part of the substrate 100 in the area to expose the first semiconductor layer.
  • the layer 201 has a fourth insulating layer on the second surface 2014 side of the spontaneous polarization effect and the piezoelectric polarization effect.
  • the second surface 2011 with spontaneous polarization effect and piezoelectric polarization effect opposite to the second surface 2014 is still surrounded by the fourth insulating layer, the substrate and the first insulating layer.
  • a third insulating layer 107' is formed on the etched substrate 100.
  • the third insulating layer may be a silicon dioxide layer formed by oxidation.
  • the fourth insulating layer covering the second surface 2014 of the first semiconductor layer 201 is removed.
  • Step 14' cover the second surface 2014 of the first semiconductor layer 201 to form a second semiconductor layer 202 by chemical deposition.
  • the second semiconductor layer may be an AlN layer or an AlGaN layer, so that the first semiconductor layer Two-dimensional cavitation gas 2DHG is formed on the second surface 2014 of the layer.
  • it can also be changed to form a photolithographic pattern, exposing all areas between adjacent first trenches and second trenches from above, and etch the first insulating layer in this area.
  • Layer 101 and part of the substrate 100 so that the first semiconductor layer covering the fourth insulating layer in the trench 102 protrudes from the fourth surface of the etched substrate, and then only the first surface of the first semiconductor layer/
  • the area on the second surface side is further etched to expose the fifth surface or the sixth surface of the substrate.
  • the position of the single crystal nucleation layer corresponds to the formation position of the third electrode (drain) of the subsequent device.
  • a current blocking layer may be added to the single crystal nucleation layer.
  • the current blocking layer may be heavily doped C or Fe elements, and the doping range of C or Fe may be 1E17-1E20/cm3.
  • the position of the single crystal nucleation layer may also be set in the area between the second electrode and the third electrode.
  • the above technical problem can be overcome by separating the location of the nucleation layer from the location of the subsequent drain electrode area by a certain distance.
  • the regions of the corresponding first and second trenches may be exposed by photolithography.
  • the current blocking layer can be formed by performing corresponding doping during epitaxial growth with a single crystal nucleation layer as the core.
  • doping is performed in the first electrode region (source region) and the third electrode region (drain region) to reduce contact resistance. It is understandable that when forming the HEMT device, the doping type of the source region and the drain region is N-type; when forming the HHMT device, the doping type of the source region and the drain region is P-type .
  • the second semiconductor layer can be removed so that the first electrode and/or the third electrode are in physical contact with the first semiconductor layer, and form an ohmic contact with the two-dimensional electron carrier gas (2DEG).
  • 2DEG two-dimensional electron carrier gas
  • the first electrode (and/or the third electrode) is in physical contact with the first semiconductor layer, and is in physical contact with the second semiconductor layer.
  • the two-dimensional hole carrier gas (2DHG) forms an ohmic contact, due to the existence of the doped first electrode and the third electrode area, through the design of the process and structure, this method of directly making physical contact with the first semiconductor layer , which is more conducive to reducing ohmic contact resistance.
  • the case where the nucleation layer corresponds to the source region is taken as an example to illustrate the doping of the source region and the drain region.
  • the case where the nucleation layer corresponds to the drain region, or the case where the nucleation layer is located between the gate and the drain region is similar to the case where the nucleation layer corresponds to the source region, and will not be repeated here.
  • FIG. 25 after the nucleation layer is formed, during the growth of the first semiconductor layer 201 with the nucleation layer as the core, corresponding P-type or N-type doping is performed in the source region.
  • the intrinsic (undoped) first semiconductor layer or the unintentionally doped Doped first semiconductor layer grow the doped source region.
  • the intrinsic first semiconductor layer or the unintentionally doped first semiconductor layer is epitaxially grown to form the channel region. It can be understood that the channel region corresponding to the second electrode can be selectively doped to form the third semiconductor layer.
  • corresponding P-type or N-type doping may be performed in the drain region.
  • the doping of the drain region and the source region can be performed simultaneously with the doping of the third semiconductor layer, and it can also be the doping of the drain region, the doping of the source region and the third semiconductor layer. The doping is carried out successively.
  • a power supply device includes any one of the above-mentioned semiconductor devices.
  • the power supply device includes a primary circuit,
  • a mobile phone includes any one of the above-mentioned semiconductor devices.
  • the mobile phone includes a display screen, a charging unit, etc., wherein the charging unit includes any of the above-mentioned semiconductor devices.
  • An amplifier which can be used in power amplifiers in the fields of mobile phone base stations, optical communication systems, and the like.
  • the power amplifier can include any of the above-mentioned semiconductor devices.
  • the semiconductor device can reduce gate leakage current, has high threshold voltage, high power, and high reliability, and can achieve low on-resistance and constant device performance.
  • the off state can provide a stable threshold voltage, so that the semiconductor device has good switching characteristics.
  • the solution of the present disclosure can also help to achieve one of the following effects: it is easy to achieve a higher aspect ratio; it can achieve a higher channel density per unit area; it is suitable for a planarization process and is beneficial to improve semiconductor devices
  • the integration density of the semiconductor device; the structure and preparation process of the semiconductor device are relatively simple, which can effectively reduce the production cost.
  • the present disclosure provides a novel semiconductor device structure and manufacturing method thereof, which has simple process, low cost, high aspect ratio, can achieve higher channel density per unit area, and has high withstand voltage, high power and High-performance energy-saving semiconductor devices such as low on-resistance.

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Abstract

本公开内容提供一种半导体器件及其制作方法，所述器件包括一衬底、在所述衬底上的第一绝缘层、形成在所述衬底上的多个沟槽、所述沟槽的一侧壁上具有的成核层、以及通过所述成核层沿着所述沟槽形成的第一半导体层。本公开内容有助于实现如下效果之一：能实现较高的高宽比、更高的集成密度，降低导通电阻，提高阈值电压，实现常关状态，提供高功率、高可靠性、适合平面化工艺、制备方法简单、降低成本的半导体器件。

Description

一种半导体器件、制造方法及其应用
相关申请的交叉引用
本公开要求于2020年3月5日提交中国专利局的申请号为202010149409.5、名称为“一种半导体器件、制造方法及其应用”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开内容涉及半导体器件领域，更具体而言，涉及一种III族氮化物半导体器件、制造方法及其应用。
背景技术
III族氮化物半导体是一种重要的新型半导体材料，主要包括AlN、GaN、InN及这些材料的化合物如AlGaN、InGaN、AlInGaN等。利用所述III族氮化物半导体具有的直接带隙、宽禁带、高击穿电场强度等优点，通过器件结构与工艺的优化设计，III族氮化物半导体在功率半导体领域拥有巨大前景。高电子迁移率和高空穴迁移率晶体管是应用III族氮化物半导体的一个重要器件，希望开发具有高耐受电压、高功率和低导通电阻等高性能的高电子迁移率和高空穴迁移率晶体管。
现有的高电子迁移率和高空穴迁移率晶体管结构设计，单位面积上的集成度不够高，以及现有的高电子迁移率和高空穴迁移率晶体管多为常开型器件，对节约能源不利。
发明内容
鉴于此，本公开提供一种新颖的半导体器件结构及其制造方法。
在下文中将给出关于本公开内容的简要概述，以便提供关于本公开内容某些方面的基本理解。应当理解，此概述并不是关于本公开内容的穷举性概述。它并不是意图确定本公开内容的关键或重要部分，也不是意图限定本公开内容的范围。其目的仅仅是以简化的形式给出某些概念，以此作为稍后论述的更详细描述的前序。
根据本公开内容的一方面，提供一种半导体器件的制造方法，包括：
步骤1：提供一衬底，所述衬底具有第一表面；
步骤2：在所述衬底的第一表面上形成第一绝缘层，所述第一绝缘层具有与所述衬底的第一表面平行的第一表面；
步骤3：刻蚀所述第一绝缘层和部分所述衬底，形成多个垂直且间隔排列的第一台阶结构和第二台阶结构；多个所述第一台阶结构的第一表面和所述第二台阶结构的第二表面的下部分别由所述衬底的第二表面和第三表面构成，多个所述第一台阶结构的第一表面和所述第二台阶结构的第二表面的上部分别由所述第一绝缘层的第二表面和第三表面构成；
步骤4：在所述第一台阶结构和所述第二台阶结构的第三表面上形成第二绝缘层；
步骤5：在所述第一台阶结构的由所述衬底的第三表面构成的第二表面上形成单晶成核层，且在所述第二台阶结构的由所述衬底的第二表面构成的第一表面上形成单晶成核层；
步骤6：以所述单晶成核层为成核中心，侧向外延生长第一半导体层。
根据本公开内容的另一方面，提供一种半导体器件的制造方法，包括：
步骤1：提供一衬底，所述衬底具有第一表面；
步骤2：在所述衬底的第一表面上形成第一绝缘层，所述第一绝缘层具有与所述衬底的第一表面平行的第一表面；
步骤3：刻蚀所述第一绝缘层和部分所述衬底，形成多个垂直且间隔排列的第一沟槽和第二沟槽；多个所述第一沟槽和第二沟槽的第一表面和第二表面的下部分别由所述衬底的第二表面和第三表面构成，多个所述第一沟槽和所述第二沟槽的第一表面和第二表面的上部分别由所述第一绝缘层的第二表面和第三表面构成；
步骤4：在所述第一沟槽和所述第二沟槽的第三表面上形成第二绝缘层；
步骤5：在所述第一沟槽的由所述衬底的第三表面构成的第二表面上形成单晶成核层，且在所述第二沟槽中的由所述衬底的第二表面构成的第一表面上形成单晶成核层；
步骤6：以所述单晶成核层为成核中心，侧向外延生长第一半导体层。
可选地，其中所述衬底的第二表面和第三表面具有六角对称的晶格结构。
可选地，其中所述衬底的第二表面和第三表面选自Si的(111)面、Al2O3的(0001)面、SiC的(0001)面、SiC的(000-1)面、GaN的(0001)面或GaN的(000-1)面。
可选地，其中步骤5中，在所述第一沟槽或所述第一台阶结构的由所述衬底的第三表面构成的第二表面的一部分上形成单晶成核层，且在所述第二沟槽或所述第二台阶结构的由所述衬底的第二表面构成的第一表面的一部分上形成单晶成核层。
可选地，其中所述步骤5可替代成步骤5’，在所述步骤5’中以所述单晶成核层为成核中心，在所述沟槽中侧向外延生长第一半导体层的第一子层，然后再以所述第一子层为核心，进行掺杂的第三半导体层的生长，然后再继续生长所述第一半导体层的第二子层，所述第三半导体层是N-型掺杂或P-型掺杂。
可选地，其中在所述步骤5中，在生长所述第一半导体层之前，在所述成核层上沉积一缓冲层。
可选地，其中在所述第一和第二沟槽或所述第一和第二台阶结构形成后，还包括共面沉积形成一牺牲层，所述牺牲层与所述第一绝缘层具有高刻蚀选择比，然后通过干法刻蚀保留所述第一沟槽和第二沟槽的所述第一表面和第二表面上的所述牺牲层。
可选地，其中利用所述牺牲层，在所述第一和第二沟槽或所述第一和第二台阶结构的第三表面上形成一第二绝缘层，然后再去除所述牺牲层。
可选地，在所述第一和第二沟槽或所述第一和第二台阶结构的第一表面和第二表面上分别形成一第四绝缘层。
可选地，通过光刻图形以暴露所述第一、第二沟槽或所述第一和第二台阶结构之间部分的所述第一绝缘层，刻蚀以去除暴露出的所述第一沟槽或第一台阶结构第二表面上和所述第二沟槽或第二台阶结构第一表面上的所述第四绝缘层，从而露出所述第一沟槽中所述衬底的第三表面和所述第二沟槽中所述衬底的第二表面。
可选地，其中在形成单晶成核层后需要另行去除所述所有绝缘层上的成核层；或者，在形成成核层时，通入含氯的气体从而仅在所述衬底上生长而不在所述所有绝缘层上生长所述成核层。
可选地，其中所述第一半导体层的生长包括垂直所述衬底第一表面方向的生长，当所述第一半导体层在垂直所述衬底第一表面方向的生长超过所述沟槽或所述台阶结构的高度时，通过平坦化或蚀刻技术去除超出部分的所述第一半导体层。
可选地，其中所述第一半导体层的第一子层和第二子层的生长，以及所述第三半导体层的生长包括垂直所述衬底第一表面方向的生长，当所述第一半导体层的第一子层、第二子层和所述第三半导体层在垂直所述衬底第一表面方向的生长超过所述沟槽或所述台阶结构的高度时，通过平坦化或蚀刻技术去除超出部分或者保留所述超出部分。
可选地，形成光刻图形，露出相邻的所述第一沟槽和所述第二沟槽之间的区域，刻蚀所述区域的所述第一绝缘层和部分的所述衬底，露出所述第一半导体层具有自发和压电极化效应的第一面和与其相对的具有自发和压电极化效应的第二面。
可选地，形成光刻图形，露出相邻的所述第一沟槽和所述第二沟槽之间的部分区域，以及露出所述第一半导体层具有自发和压电极化效应的第一面或第二面；刻蚀所述区域的所述第一绝缘层、部分所述衬底，以及所述第一半导体层露出的所述第一面或第二面，露出所述第一半导体层的所述第二面或与其相对的所述第一面。
可选地，形成光刻图案，露出相邻的所述第一沟槽和所述第二沟槽之间的部分区域，刻蚀所述第一绝缘层和部分的所述衬底，暴露出所述第一半导体层具有自发和压电极化效应的第一面或第二面，而与其相对的所述第二面或第一面仍被所述衬底和所述第一绝缘层掩盖。
可选地，在刻蚀后的所述衬底上形成第三绝缘层，然后去除所述第一半导体层上的所述第三绝缘层。
可选地，在暴露出的所述第一半导体层上形成第二半导体层，从而使得与第二半导体层邻接的所述第一半导体层的第一面界面处形成二维电子气和/或与第二半导体层邻接的所述第一半导体层的第二面界面处形成二维空穴气。
可选地，在所述第二半导体上继续形成多个所述第一半导体层和第二半导体层交替的叠层。
可选地，沉积介质层，对所述介质层进行光刻刻蚀，再沉积金属，从而在所述第一半导体层的第一面或第二面侧沿着所述沟槽的长度方向形成第一电极、第二电极和第三电极，其中所述第二电极与所述第二半导体层接触，所述第一电极和第二电极与所述第二半导体层或所述第一半导体层接触。
可选地，在与所述第一电极、第二电极和第三电极相对的所述第一半导体层的第二面或第一面上形成第四电极，所述第四电极与所述第三半导体层相连接。
可选地，其中所述成核层在对应于所述第一电极的位置、对应于所述第三电极的位置或者在对应于所述第二电极和所述第三电极之间的位置处设置。
可选地，其中所述成核层设置在对应于所述第三电极的位置时，还可以在垂直所述沟槽第一面或第二面的方向上形成电流阻挡层。
可选地，其中在所述第一半导体层对应第一电极的区域和对应第三电极的区域进行相应的掺杂，形成相应的第一电极区域和第三电极区域。
可选地，其中当形成HEMT器件时，所述第一电极和第三电极区域的掺杂为N-型掺杂；当形成HHMT器件时，所述第二电极和第三电极区域的掺杂为P-型掺杂。
可选地，其中所述第一电极区域和第三电极区域的掺杂与所述第三半导体层的掺杂同时进行，或者所述第一电极区域的掺杂、第三电极区域的掺杂和所述第三半导体层的掺杂先后进行。
根据本公开内容的一方面，提供一种半导体器件，其包括：
一衬底，所述衬底具有第一表面；
在所述衬底的第一表面上形成的第一绝缘层，所述第一绝缘层具有与所述衬底的第一表面平行的第一表面；
多个垂直于衬底第一表面且间隔排列的第一沟槽和第二沟槽；
所述第一沟槽和所述第二沟槽的第一表面和第二表面的下部分别由所述衬底的第二表面和第三表面构成，所述第一沟槽和第二沟槽的第一表面和第二表面的上部由所述第一绝缘层的第二表面和第三表面构成；
在所述第一沟槽的由所述衬底的第三表面构成的第二表面上形成的单晶成核层，以及在所述第二沟槽中的由所述衬底的第二表面构成的第一表面上形成的单晶成核层；
以所述单晶成核层为成核中心，侧向外延生长的第一半导体层。
可选地，其中在所述第一沟槽的第二表面的一部分上形成的所述单晶成核层，在所述第二沟槽的第一表面的一部分上形成的所述单晶成核层。
可选地，其中所述第一半导体层在沿着所述沟槽的长度方向上分为第一半导体层的第一子层和第二子层，在所述第一子层和第二子层之间还设置有掺杂的第三半导体层。
可选地，其中所述衬底的第二表面和第三表面具有六角对称的晶格结构。
可选地，其中所述衬底的第二表面和第三表面选自Si(111)、Al2O3的(0001)面、SiC的(0001)面、SiC的(000-1)面、GaN的(0001)面或GaN的(000-1)面。
可选地，在所述第一和第二沟槽的第三表面上形成的第二绝缘层。
可选地，在所述第一沟槽的第一表面上和所述第二沟槽的第二表面上分别形成有一第四绝缘层。
可选地，其中所述第一半导体层与所述第一绝缘层平齐或者所述第一半导体层具有突出所述第一绝缘层的部分。
可选地，其中所述第一绝缘层、第二绝缘层和第四绝缘层是二氧化硅层。
根据本公开内容的一方面，提供一种半导体器件，其包括：
一衬底，所述衬底具有第一表面；
在所述衬底中形成的多个垂直于所述衬底的第一表面且间隔排列的第一沟槽和第二沟槽；
在多个所述第一沟槽和第二沟槽的第三表面上形成的第二绝缘层；
在所述第一沟槽中的第二表面上和所述第二沟槽中的第一表面上形成的单晶成核层，
以所述单晶成核层为成核中心生长的第一半导体层，所述第一半导体层具有平行于所述沟槽的第一表面和第二表面且垂直于所述衬底的第一表面的具有自发极化效应和压电极化效应的第一面和与其相对的第二面；
在所述第一半导体层上覆盖形成的第二半导体层，所述第二半导体层的禁带宽度大于所述第一半导体层的禁带宽度，从而在所述第一半导体的第一面和第二面上分别形成了二维电子气和二维空穴气。
根据本公开内容的一方面，提供：
一衬底，所述衬底具有第四表面；
在所述衬底的第四表面上形成的第三绝缘层；
在所述衬底中形成的多个垂直于所述衬底的第四表面且间隔排列的第一沟槽和第二沟槽；
在多个所述第一沟槽和所述第二沟槽的第三表面上形成的第二绝缘层；
在所述第一沟槽中的第二表面上和所述第二沟槽中的第一表面上形成的单晶成核层，以及在所述第一沟槽中的第一表面上和所述第二沟槽中的第二表面上形成的第四绝缘层；
在所述第一沟槽和第二沟槽中的第一半导体层，且所述第一半导体层突出所述衬底的第四表面，所述第一半导体层具有平行于所述第沟槽的第一表面和所述第二沟槽的第二表面及垂直于所述衬底的第四表面且突出所述衬底的第四表面的具有自发极化效应和压电极化效应的第一面和与其相对的第二面；
在所述第一半导体层上覆盖形成的第二半导体层，所述第二半导体层的禁带宽度大于所述第一半导体层的禁带宽度，从而在所述第一半导体的第一面和第二面上分别形成二维电子气和二维空穴气。
根据本公开内容的一方面，提供：
一衬底，所述衬底具有第一表面，以及与所述第一表面平行但低于所述第一表面的第五表面；
在所述衬底的第一表面和第五表面上形成的第三绝缘层；
在所述衬底中形成的多个垂直于所述衬底的第一表面且间隔排列的第一沟槽和第二沟槽；
在所述第一沟槽和所述第二沟槽的第三表面上形成的第二绝缘层；
在所述第一沟槽中的第二表面和所述第二沟槽中的第一表面上形成的单晶成核层，在所述第一沟槽中的第一表面和所述第二沟槽中的第二表面上分别形成的第四绝缘层，；
在所述第一沟槽和所述第二沟槽中的第一半导体层，且所述第一半导体层突出所述衬底的第五表面，所述第一半导体层具有平行于所述第一沟槽的第一表面和所述第二沟槽的第二表面且垂直于所述衬底的第五表面向上延伸的具有自发极化效应和压电极化效应的第一面；
在所述第一半导体层的所述第一面上覆盖形成的第二半导体层，所述第二半导体层的禁带宽度大于所述第一半导体层的禁带宽度，从而在所述第一半导体的第一面上形成二维电子气。
根据本公开内容的一方面，提供：
一衬底，所述衬底具有第一表面，以及与所述第一表面平行但低于所述第一表面的第六表面；
在所述衬底的第一表面和第六表面上形成的第三绝缘层；
在所述衬底中形成的多个垂直于所述衬底的第一表面且间隔排列的第一沟槽和第二沟槽；
在所述第一沟槽和第二沟槽的第三表面上形成的第二绝缘层；
在所述第一沟槽中的第二表面上和所述第二沟槽中的第一表面上形成的单晶成核层，在所述第一沟槽中的第一表面上和所述第二沟槽中的第二表面上分别形成的第四绝缘层；
在所述第一沟槽和所述第二沟槽中的第一半导体层，且所述第一半导体层突出所述衬底的第六表面，所述第一半导体层具有平行于所述第一沟槽的第二表面和所述第二沟槽的第一表面且垂直所述衬底的第六表面向上延伸的具有自发极化效应和压电极化效应的第二面；
在所述第一半导体层的所述第一面上覆盖形成第二半导体层，所述第二半导体层的禁带宽度高于所述第一半导体层的禁带宽度，从而在所述第一半导体的第二面上形成了二维空穴气。
可选地，其中在所述第一半导体层沿着所述沟槽长度的的方向上分为所述第一半导体层的第一子层和所述第二半导体层的第二子层；在所述第一子层和第二子层之间还设置有一第三半导体层。
可选地，其中所述沟槽的第一表面和第二表面具有六角对称的晶格结构。
可选地，其中所述衬底的第二表面和第三表面选自Si(111)面、Al2O3的(0001)面、SiC的(0001) 面、SiC的(000-1)面、GaN的(0001)面或GaN的(000-1)面。
可选地，其中所述第三半导体层是P-型掩埋层或N-型掩埋层。
可选地，其中沿着所述沟槽长度方向上的所述第一半导体的第一面/第二面侧，在所述第三绝缘层上分别形成第一电极、第二电极和第三电极，所述第一电极、第二电极和第三电极分别连接在所述第二半导体层上；或者所述第一电极、第三电极连接在所述第一半导体上，所述第二电极连接在所述第二半导体上。
可选地，其中所述第三半导体层在所述第一半导体层第一面/第二面上的投影落在所述第二电极在所述第一半导体层第一面/第二面上投影的范围内或与其有部分重叠。
可选地，其中所述第一电极、第二电极和第三电极之间用介质层隔离。
可选地，其中在于所述第一电极、第二电极和第三电极所在的所述第一半导体的第二面/第一面侧相对的第一面/第二面侧，在所述第三绝缘层上形成第四电极，所述第四电极连接在所述第三半导体层上。
可选地，其中所述第三半导体层的掺杂浓度，以在无器件偏压的情况下，足以耗尽与第二电极投影区域重叠处至少部分区域的95％-100％的二维电子气/二维空穴气。
可选地，其中所述成核层形成在对应于所述第一电极的位置、对应于所述第三电极的位置或者在对应于所述第二电极和所述第三电极之间的位置处设置。
可选地，其中所述成核层设置在对应于所述第三电极的位置时，在垂直所述沟槽第一面或第二面的方向上形成电流阻挡层。
可选地，其中所述第一半导体层对应第一电极的区域和对应第三电极的区域具有相应的掺杂，形成相应的第一电极区域和第三电极区域。
可选地，其中当形成HEMT器件时，所述第一电极和第三电极区域的掺杂为N-型掺杂；当形成HHMT器件时，所述第二电极和第三电极区域的掺杂为P-型掺杂。
根据本公开内容的另一方面，提供了一种电子装置。
可选地，所述电子装置是电源装置、手机、或通信系统中的功率放大器。
附图说明
下面，参照附图说明本公开的具体内容，这将有助于更加容易地理解本公开的目的、特点和优点。附图只是为了示出本公开内容的原理。在附图中不必依照比例绘制出单元的尺寸和相对位置。在附图中：
图1-10为根据一种实施方式的半导体器件结构及其制造方法的示意图；
图11-14为可选的半导体器件结构及其制造方法的示意图；
图15-17为可选的半导体器件结构及其制造方法的示意图；
图18为可选的半导体器件结构及其制造方法的示意图；
图19-21为可选的半导体器件结构及其制造方法的示意图；
图22-24为可选的半导体器件结构及其制造方法的示意图；
图25-28为可选的半导体器件结构及其制造方法的示意图；
图29为可选的半导体器件的制造方法的示意图。
图30为可选的半导体器件的制造方法的示意图。
具体实施方式
在下文中，将结合附图对本公开内容的示例性公开内容进行描述。为了清楚和简明起见，在说明书中并未描述实现本公开内容的所有特征。然而，应该了解，在实现本公开内容的过程中可以做出很多能够实施本公开内容的方式，以便实现开发人员的具体目标，并且这些方式可能会随着本公开内容的不同而有所改变。
在此，还需要说明的是，为了避免因不必要的细节而使本公开内容变得复杂，在附图中仅仅示出了与根据本公开内容的方案密切相关的器件结构，而省略了一些细节。
应理解的是，本公开内容并不会由于如下参照附图的描述而只限于所描述的实施形式。本文中，在可行的情况下，不同实施方式之间的特征可替换或组合、或在一个实施方式中可省略一个或多个特征。
具体地，本公开内容的半导体器件为包含氮化物半导体材料的化合物半导体器件，也称为氮化物半导体器件，其中，氮化物半导体器件是III族氮化物半导体器件。进一步的，III族氮化物半导体器件包括使用纤锌矿(Wurtzite)III族氮化物半导体材料的晶体管。更进一步的，晶体管是包含GaN半导体材料的GaN晶体管。特别的，GaN晶体管是常闭的晶体管GaN-HEMT和/或GaN-HHMT。
参照图1-图10来描述根据一种实施方式的半导体器件及其制备方法。
如图1-10所示，该半导体器件包括衬底100，衬底100的材质可以根据实际需要选取，本公开并不限制衬底100的具体材料，只要衬底材料为能够满足在其表面上形成的垂直于其表面的垂直沟槽的侧表面具有六角对称性的晶格结构的衬底材料皆可。示例性地，衬底100的材料可为Si、Al2O3、SiC、GaN等，由于硅衬底具有价格便宜、可加工性强等优点，所以在本公开中以Si衬底为例进行进一步的说明。
示例性地，单晶硅衬底可以是采用(110)或(112)面的硅衬底。如图1所示，提供一衬底100，衬底具有第一表面1001；在衬底100的第一表面1001上形成第一绝缘层101，示例性地，第一绝缘层101为热氧化或气相沉积形成的SiO2层，示例性地，第一绝缘层101的厚度约为0.5微米，应注意，本公开中的数值范围等仅作为示例而非对本公开的限制。第一绝缘层101具有平行于衬底第一表面1001的第一表面1011。刻蚀部分第一绝缘层101和其下方的衬底100，形成多个垂直的沟槽，具体而言，沟槽包括间隔排列的第一沟槽102和第二沟槽102’，第一沟槽和第二沟槽的尺寸相同。示例性地，第一沟槽和第二沟槽的深度约为5微米。各沟槽的第一表面1021和第二表面1022的下部分别由衬底暴露出的第二表面1002和第三表面1003构成，其中衬底的第二表面1002和第三表面1003具有六角对称的晶格结构，例如Si(111)面。可以理解的是，衬底的第二表面和第三表面还可以是Al2O3(0001)面、SiC(0001)面、或SiC(000-1)面、GaN(0001)面、或GaN(000-1)面等。各沟槽的第一表面1021和第二表面1022的上部分别由第一绝缘层101的第二表面1012和第三表面1013构成。如图5、6所示，在沟槽的第三表面1023上形成第二绝缘层103，示例性地，第二绝缘层103可以为氧化形成的二氧化硅层，示例性地，其厚度为约500nm。如图7所示，在沟槽的第一表面1021和第二表面1022上形成第四绝缘层105，示例性地，第四绝缘层的厚度为100nm左右，该第四绝缘层可避免在外延时，硅衬底与含Ga的前驱体的相互作用，同时更有利于提高外延时的选择性。进一步的，如图8、9去除第一沟槽的第二表面上的和第二沟槽的第一表面上的部分第四绝缘层105、在第一沟槽中暴露的衬底100的第三表面1003和在第二沟槽中暴露的衬底100的第二表面1002上形成单晶成核层106。示例性地，单晶成核层是ALN层，ALN晶体的生长方向是<0001>方向，其表面是(0001)面。示例性地，单晶成核层所在的位置与后续器件的第一电极(源极)的形成位置对应，由于后续形成的器件结构在以第一电极(源极)作为参照点时，半导体器件结构能够呈现出对称的结构，且第一电极区域(源极区域)的电压很低，因此，对晶体质量不敏感，从而将成核区域的晶体质量差的影响降低到最小。然后，如图10所示，以成核层106为核心选择性生长第一半导体层201，第一半导体层201可为氮化物，示例性地，如本征GaN(i-GaN)或非故意掺杂GaN层。由于沟槽102的存在，第一半导体层201从成核层开始沿着沟槽102开始生长，其中的生长包括沿着沟槽的第一方向的生长，也包括垂直于沟槽的第二方向的生长，第一半导体层201还可以在沟槽外生长，并通过平坦化或蚀刻技术去除沟槽外的第一半导体层201。
由于沟槽102的限制，使得第一半导体层在横向外延生长时可以生长的非常平直，进而由其作为功能层而构成的半导体器件的垂直表面可以借助于沟槽而形成得非常平直，因此容易实现较高的高宽比。更具体的，当第一半导体层201被用作垂直沟道时，可以使得在单位面积上实现更高的沟道密度，从而降低了器件的电阻，提升了器件的性能。
现参照图1-10来详细描述用于制造该半导体器件的制造方法，其中所示图1、2、6、10为剖视图，图3-5，7-9为俯视图。
步骤1：如图1所示，提供一衬底100，衬底可以是采用(110)或(112)面的硅衬底。在衬底100的第一表面1001上形成第一绝缘层101，示例性地，第一绝缘层101为热氧化或气相沉积形成的SiO2层。示例性地，第一绝缘层101的厚度约为0.5微米。
步骤2：如图2所示，在第一绝缘层101上间隔地进行光刻以露出第一绝缘层101的部分内部，接着在光刻位置刻蚀第一绝缘层101和其下方的衬底100，形成垂直的沟槽，沟槽包括间隔排列的第一沟 槽102和第二沟槽102’。各沟槽的两个侧表面即第一表面1021和第二表面1022的下部分别由经刻蚀后的衬底暴露出的第二表面1002和第三表面1003构成。衬底的第二表面1002和第三表面1003具有六角对称的晶格结构，例如Si(111)面。衬底的第二表面和第三表面还可以是Al2O3(0001)面、SiC(0001)面、SiC(000-1)面、GaN(0001)面或GaN(000-1)面等。
步骤3：如图3所示，在步骤2形成的结构的基础上，共面沉积形成牺牲层104，示例性地，牺牲层104是氮化硅层，其厚度约为100纳米。可以理解的是，第一绝缘层和牺牲层的选择，以其二者之间具有高蚀刻选择比即可，例如在刻蚀牺牲层时，刻蚀剂基本上不对第一绝缘层进行蚀刻，或对其蚀刻极其缓慢。
步骤4：如图4所示，进行干法刻蚀，去除第一绝缘层101的第一表面1011上的牺牲层104和沟槽102102’的第三表面1023上的牺牲层104，保留沟槽102(102’)的第一表面1021和第二表面1022上的第一牺牲层104。
步骤5：如图5所示，通过氧化工艺，在各沟槽的第三表面1023上形成第二绝缘层103(二氧化硅层)，沟槽的第一表面和第二表面由于保留的第一牺牲层104的保护没有被氧化，绝缘层可以避免在后续生长氮化物半导体时镓原子与硅衬底的不兼容，避免出现回熔(melt-back)现象。同时，该第二绝缘层还可以有效阻绝氮化物半导体与硅衬底之间的漏电流，并降低硅衬底所带来的寄生电容。
步骤6：如图6所示，利用第一牺牲层104和二氧化硅层的刻蚀选择比，通过选择性湿法刻蚀去除各沟槽的第一表面和第二表面的第一牺牲层104。
步骤7：如图7所示，通过氧化工艺，在沟槽102的第一表面和第二表面上分别形成较薄的第四绝缘层105(二氧化硅层)，第四绝缘层的厚度与第一、第二绝缘层的厚度设置地不同，以满足在后续去除第四绝缘层时候，仍然还有足够厚的第一和第二绝缘层以保护衬底。这些绝缘层可以避免在后续生长氮化物半导体时镓原子与硅衬底的不兼容，避免出现回熔(melt-back)现象，这对于硅衬底上制作氮化镓基半导体器件是必不可少的。
步骤8：如图8所示，涂敷光刻胶，在第一沟槽和第二沟槽之间形成光刻图形以暴露第一沟槽和第二沟槽之间部分的第一绝缘层101。可以理解的是，光刻图形可以暴露出第一沟槽和第二沟槽之间全部的第一绝缘层101。
步骤9：如图9所示，去除暴露出的第一沟槽的第二表面上的和第二沟槽的第一表面上的第四绝缘层105，由于第一绝缘层的厚度远大于第四绝缘层的厚度，因此，在去除部分第四第绝缘层的过程中，暴露的第一绝缘层部分仅被蚀刻很少的厚度并不会被完全去除，然后去除光刻胶，从而使得在第一沟槽中暴露出部分衬底100的第三表面1003和在第二沟槽中暴露出部分衬底100的第二表面1002。
步骤10：如图9所示，由于硅衬底与镓之间的回熔(melt-back)效果，硅衬底上不能直接沉积GaN。通常需要先沉积AlN的成核层，再在此基础上形成后续的氮化物半导体结构。因此，在暴露出的第一沟槽中的衬底100的第三表面1003上，以及在暴露出的第二沟槽中的衬底100的第二表面1002上分别形成单晶AlN成核层106，单晶AlN晶体的生长方向是<0001>，表面是(0001)面。需要指出的是，AlN的选择性很低，在通常的工艺条件下容易在绝缘层上也生成多晶或非晶的AlN，这对形成所需的结构是不利的。因此，需要在形成了成核层后另行去除二氧化硅层上的AlN。或者在生长AlN成核层时引入含氯气体以保证仅在硅衬底上生长而不在二氧化硅层生长。
可以理解的是，如果采用其他衬底例如Al2O3，则成核层也可以是GaN。此时通过工艺调节可以较容易实现仅在暴露的衬底表面成核。
步骤11：如图10所示，然后以成核层106为核心侧向外生长第一半导体层201，由于沟槽的102的存在，第一半导体层201从成核层开始沿着沟槽102开始侧向外延生长，其中生长包括沿着沟槽的第一方向的生长，也包括垂直于沟槽的第二方向的生长，第一半导体层201还可以在沟槽外生长，并通过平坦化或蚀刻技术去除沟槽外的第一半导体层201。侧向外延可以有效提升侧向外延区域的氮化物半导体晶体质量，进而提升器件的电学性能。去除沟槽外的第一半导体层，可以使得器件在形成过程中处于受约束的状态，有利于形成特定的结构和尺寸，有助于形成具有较高的高宽比的器件，提供了除生长工艺参数调整外的实现较高的高宽比器件的手段，而由于第一半导体在沟槽中的生长受到沟槽的第一表面和第二表面的限制，第一半导体层的生长过程避免了不能保持完全垂直或者生长面不在同一平面的情况， 以及可能出现多个、复杂的生长面的情况，方便实现对器件的控制与电学性能的提升。可以理解的是，第一半导体层201在沟槽外的生长也可以不必去除，而形成突出沟槽的部分。
可以理解的是，在生长第一半导体层之前，还可以先沉积形成一缓冲层。
可选地，第一沟槽和第二沟槽的结构也可以替换成相应的第一台阶结构和第二台阶结构，进而在各台阶结构的一侧壁上形成成核层，并在衬底的第一表面和平行衬底第一表面的台阶第三表面上形成一绝缘层，然后以成核层为核心进行相应的缓冲层、第一半导体层201的外延生长。对此参照前面的制造方法，不再赘述。
参照图11-14来描述可选的半导体器件和制造方法，图11-14为俯视图。
在上述内容的基础上，对第一半导体层外侧的第一绝缘层101及衬底100进行刻蚀，去除第一绝缘层101以及部分的衬底100，使得第一半导体层201凸出刻蚀后的衬底100的第四表面1004。第一半导体层201的具有自发极化效应和压电极化效应的第一面2013和与其相对的具有自发极化效应和压电极化效应的第二面2014，当第一半导体层为GaN时，第一面2013为(0001)面，第二面2014为(000-1)面。在刻蚀后的衬底100上形成第三绝缘层107，以隔离暴露的硅衬底。示例性地，第三绝缘层可以为二氧化硅层。然后以覆盖第一半导体层201的方式形成第二半导体层202，第二半导体层可以是AlN层或AlGaN层，进而在第一半导体层的第一面2013和第二面2014上分别形成了二维电子气2DEG和二维空穴气2DHG。
然后，在沿着沟槽长度的方向上在第二半导体层202上分别形成第一电极401、第二电极402和第三电极403。可选地，第一电极为源极，第二电极为栅极，第三电极为漏极。也可以使第一电极和第三电极沿着二维电子气传输的方向形成在第一半导体层201上。
其中第一电极至第三电极都形成在衬底100的第三绝缘层的表面上，使得半导体器件的结构在具有垂直沟道的同时，电极的设置特别的适合于平面化工艺，有利于提高半导体器件的集成密度。
下面示例性描述用于制造该半导体器件的制造方法。上述的制造方法还可以包括如下步骤。
步骤12：如图11所示，形成光刻图形，从上面露出相邻第一沟槽和第二沟槽之间的全部区域，刻蚀区域中第一绝缘层101和部分的衬底100的材料，使得沟槽102中的覆盖着第四绝缘层的第一半导体层突出于刻蚀后的衬底的第四表面1004。
步骤13：如图12所示，在刻蚀后的衬底100的第四表面1004上形成一第三绝缘层107，示例性地，第三绝缘层可以为氧化形成的二氧化硅层，然后去除覆盖着第一半导体层201的上的第四绝缘层，从而露出第一半导体层201的具有自发极化效应和压电效应的第一面2013和与其相对的具有自发极化效应和压电极化效应的第二面2014。
步骤14：如图13所示，在第一半导体层201上覆盖形成第二半导体层202，第二半导体层可以是AlN层或AlGaN层，进而在第一半导体层的第一面2013和第二面2014上分别形成了二维电子气2DEG和二维空穴气2DHG。
可以理解的是，还可以在第二半导体层上继续覆盖多个第一半导体层和第二半导体层交替的叠层结构，进而形成由多个二维电子气2DEG和二维空穴气2DHG构成的多沟道结构。
步骤15：如图14所示，沉积一介质层，对第一介质层进行光刻刻蚀，然后在其上沉积金属，从而沿着二维电子气传输方向在第一半导体层201的第一面处分别形成第一电极、第三电极以及沿着二维电子气传输方向在第二半导体层202上形成第二电极，其中第二电极位于第一电极和第三电极的中间。可选地，第一电极为源极，第二电极为栅极，第三电极为漏极。可选地，第一至第三电极都形成在沿着二维电子气传输方向的第二半导体层202上。
参照图15-17来描述可选的半导体器件及其制造方法，所示图15-17为俯视图。
可选地，在沟槽内沿着沟道的第一表面和第二表面的方向形成有第一半导体的第一子层2011、第三半导体203和第一半导体的第二子层2012层，第一子层、第三半导体203和第二子层完全填满沟槽使得各层平行于第一半导体的第一表面且共面。可以理解的是，第三半导体层中具有P-型掺杂或者N-型掺杂，示例性地，P-型掺杂是P-型GaN，N-型掺杂是N-型GaN，示例性地，掺杂浓度为1E17-5E19/cm3， 更优的为1E+18/cm3-5E+19/cm3。P-型GaN层可以耗尽第一半导体层的第一面的二维电子气；N-型GaN层可以耗尽第一半导体层的第二面的二维空穴气，从而使器件具有常闭状态；具体选择是进行P-型掺杂还是N-型掺杂视后续器件的具体类型而定，对于HEMT器件则选择进行P-型掺杂，对于HHMT器件则选择进行N-型掺杂。可以理解的是，掺杂可以是渐变的。其余的结构特征与上述实施方式相同，在此不再赘述。第三半导体在第一半导体在第一半导体的第一面的投影落在第二电极在该方向上的投影的范围内，或与第二电极在该方向上的投影有部分的重叠。第三半导体层的如其掺杂浓度、尺寸参数等可以根据器件参数来设置，只要能够耗尽其中95％-100％的二维电子气或二维空穴气即可，二维电荷载流子气的浓度越高，相应的掺杂浓度可以随之提高。
下面具体描述用于可选的半导体器件的制造方法。
步骤11’：如图15-17所示，在形成成核层106后，以成核层106为核心选择性生长第一半导体的第一子层2011，由于沟槽的102的存在，第一子层2011从成核层开始沿着沟槽102开始侧向外延生长，其中生长包括沿着沟槽的第一表面或第二表面的第一方向的生长，以及垂直于沟槽的第三表面的生长。然后以第一子层2011为核心，生长掺杂的第三半导体层203，第三半导体层203的生长同样包括沿着沟槽的第一表面或第二表面的第一方向的生长，也包括垂直于沟槽的第一表面或第二表面的第二方向的生长，以及垂直于沟槽的第三表面的生长。第三半导体层203位于后续器件的投影方向上的栅极的投影范围内，或与栅极在该方向上的投影有部分的重叠即可。
然后，以第三半导体层203为核心，继续生长第一半导体层的第二子层2012，第一半导体层的第二子层也可以是本征GaN层或非故意掺杂GaN层。第一半导体层的第二子层2012的生长方向与第一子层或第三半导体层的生长方向相同。最后通过平坦化或蚀刻技术去除垂直于沟槽的第三表面生长且位于沟槽外的第一子层、第三半导体和第二子层的部分，从而使得第一子层、第三半导体层和第二子层都位于沟槽内，形成具有共面的结构。共面结构，可以使得器件在形成过程中处于受约束的状态，有利于形成特定的结构和尺寸，有助于形成具有较高的高宽比的器件，提供了除生长工艺参数调整外的实现高宽比器件的手段，而由于第一半导体和第三半导体在沟槽中的生长受到沟槽的第一表面和第二表面的限制，第一半导体层和第三半导体的生长过程避免了不能保持完全垂直或者生长面不在同一平面的情况，且避免为可能出现多个、复杂的生长面的情况，方便实现对器件的控制与电学性能的提升。
当然可以理解的是，也可以使第一子层、第三半导体层和第二子层一部分位于沟槽外。
参照图18来描述可选的半导体器件及其制作方法，所示图18为俯视图。
可选地，在上述内容的基础上，在沿着二维空穴气传输的方向上亦即在沿着背离二维电子气传输的方向上，在第一半导体层201上形成第四电极404。第四电极可为体电极，用于与第三半导体层相接触，从而能更好的控制阈值电压。可以理解的是，第四电极也可以在衬底的第四表面上形成，这里对第四电极的形成位置和方法不做具体限定，只要其能与第三电极形成接触即可。
可选地，对第一半导体层的一侧进行刻蚀，去除第一绝缘层101以及部分衬底100，使得衬底具有第一表面和一低于且平行于第一表面的第五表面。暴露第一半导体层201的具有自发极化效应和压电极化效应的第一面2013，当第一半导体层为GaN时，第一面2013为(0001)面。此时，与第一面2013相对的具有自发极化效应和压电极化效应第二面2014则仍被衬底和第一绝缘层掩盖，第二面2014为GaN的(000-1)面。在刻蚀后的衬底100上形成一第三绝缘层107以隔离暴露的硅衬底，示例性地，第三绝缘层可以为二氧化硅层。然后在第一半导体层201的第一面2013上形成第二半导体层202，第二半导体层是AlN层或AlGaN层，从而在第一半导体层的第一面2013上形成了二维电子气2DEG。可以理解的是，第一半导体层和第二层可以形成多个交替的层叠结构从而形成具有多个二维电子气2DEG的多沟道结构的HEMT器件。
现将参照图19-21并结合前述制造方法来示例性描述用于制造该半导体器件的制造方法。
步骤12’，如图19所示，形成光刻图形，露出第一半导体层第一面2013侧的区域，刻蚀该区域中第一绝缘层101和部分的衬底100，暴露第一半导体层201的具有自发极化效应和压电极化效应的第一面侧的第四绝缘层。与第一面2013相对的具有自发极化效应和压电极化效应的第二面2014仍被第四绝 缘层、衬底和第一绝缘层包围。
步骤13’，如图20所示，在刻蚀后的衬底100上形成一第三绝缘层107’，示例性地，第三绝缘层可以为通过氧化形成的二氧化硅层。在通过第三绝缘层隔离暴露的硅衬底的情况下，去除覆盖在第一半导体层201第一面2013上的第四绝缘层。
步骤14’，如图21所示，在第一半导体层201的第一面2013上化学沉积形成第二半导体层202，第二半导体层可以是AlN层或AlGaN层，从而能够在第一半导体层的第一面2013上形成二维电子气2DEG。
可选地，仅对第一半导体层的一侧进行刻蚀，去除第一绝缘层101以及部分衬底100，使得衬底具有第一表面和一低于且平行于第一表面的第六表面。暴露第一半导体层201的具有自发极化效应和压电极化效应的第二面2014，当第一半导体层为GaN时，第二面2014为(000-1)面。此时，与第一面2013相对的具有自发极化效应和压电极化效应的第一面2013仍被衬底和第一绝缘层掩盖，第一面2013为GaN的(0001)面。在刻蚀后的衬底100上形成一第三绝缘层107以隔离暴露的硅衬底，示例性地，第三绝缘层可以为通过氧化形成的二氧化硅层。然后在第一半导体层201的第二面2014上覆盖形成第二半导体层202，第二半导体层是AlN层或AlGaN层，从而在第一半导体层的第一面2013上形成二维空穴气2DHG。可以理解的是，第一半导体层和第二半导体层可以形成多个交替的层叠结构，从而形成具有多个二维空穴气2DHG沟道结构的HHMT器件。
现将参照图22-24结合前述制造方法来示例性描述用于制造该半导体器件的制造方法。
步骤12’，如图22所示，形成光刻图形，露出第一半导体层第二面2014侧的区域，刻蚀该区域中第一绝缘层101和部分衬底100的材料，暴露第一半导体层201具有自发极化效应和压电极化效应的第二面2014侧的第四绝缘层。与第二面2014相对的具有自发极化效应和压电极化效应第二面2011仍被第四绝缘层、衬底和第一绝缘层包围。
步骤13’，如图23所示，在刻蚀后的衬底100上形成一第三绝缘层107’，示例性地，第三绝缘层可以为通过氧化形成的二氧化硅层。在通过该第三绝缘层隔离暴露的硅衬底的情况下，去除覆盖在第一半导体层201的第二面2014上的第四绝缘层。
步骤14’，如图24所示，在第一半导体层201的第二面2014上覆盖通过化学沉积形成第二半导体层202，第二半导体层可以是AlN层或AlGaN层，从而在第一半导体层的第二面2014上形成二维空穴气2DHG。
可以理解的是，在一些实施方式中，还可以变化成形成光刻图形的方式，从上面露出相邻第一沟槽和第二沟槽之间的全部区域，刻蚀该区域中第一绝缘层101和部分的衬底100，使得沟槽102中的覆盖着第四绝缘层的第一半导体层突出于刻蚀后的衬底的第四表面，然后仅对第一半导体层第一面/第二面侧的区域进行进一步的蚀刻，露出衬底的第五表面或第六表面，其具体方法可参照前述内容，在此不再赘述。
可选地，单晶成核层所在的位置与后续器件的第三电极(漏极)的形成位置对应，此时，为避免有成核区域的晶体质量较差以及漏电流较大等问题，可以在单晶成核层上加入电流阻挡层，电流阻挡层，例如可以是重掺杂的C或Fe元素的，C或Fe的掺杂范围可以为1E17-1E20/cm3。
可选地，单晶成核层的位置还可以设置在第二电极和第三电极之间的区域。示例性地，可以通过使成核层所在的位置与后续漏电极区域所在的位置隔开一定的距离来克服上述技术问题。
可选地，对于设置单晶成核层的区域，可以通过光刻来暴露相应的第一和第二沟槽的区域。
电流阻挡层可以在以单晶成核层为核心进行外延生长时，通过进行相应的掺杂来形成。
可选地，在第一电极区域(源极区域)和第三电极区域(漏极区域)进行掺杂以降低接触电阻。可以理解的是，当形成HEMT器件的时候，源极区域和漏极区域的掺杂类型是N-型；当形成HHMT器件的时候，源极区域和漏极区域的掺杂类型是P-型。
可选地，在HEMT器件中，可去除第二半导体层使第一电极和/或第三电极与第一半导体层物理接 触，并与二维电子载流子气(2DEG)形成欧姆接触，由于掺杂后的第一电极区域和第三电极区域的存在，通过工艺和结构的设计，这种直接与第一半导体层物理接触的方式，更有利于降低欧姆接触电阻。
可选地，在HHMT器件中，由于P-型欧姆接触更加难于形成，因此，当去除第二半导体层使第一电极(和/或第三电极)与第一半导体层物理接触，并与二维空穴载流子气(2DHG)形成欧姆接触时，由于掺杂后的第一电极和第三电极区域的存在，通过工艺和结构的设计，这种直接与第一半导体层物理接触的方式，更有利于降低欧姆接触电阻。
现将参照图25-28结合前述制造方法来示例性描述用于制造该半导体器件的制造方法。
以成核层与源极区域对应的情况为例来说明源极区域和漏极区域的掺杂。成核层与漏极区域对应的情况、或者成核层位于栅极和漏极区域之间的情况与成核层与源极区域对应的情况类似，在此不再赘述。如图25所示，在形成成核层后，在以成核层为核心进行第一半导体层201的生长过程中，在源极区域进行相应的P-型或N-型掺杂。
可选地，在以成核层为核心进行第一半导体层201的生长过程中，在进行相应的掺杂之前，先生长本征的(非掺杂的)第一半导体层，或非故意掺杂的第一半导体层，而后再进行掺杂的源极区域的生长。
接着，如图26-27所示，在掺杂的源极区域形成后，再继续进行本征的第一半导体层，或非故意掺杂的第一半导体层的外延生长形成沟道区域。可以理解的是，在第二电极对应的沟道区域可以选择进行相应的掺杂形成第三半导体层。
然后，如图28所示，可以在后一步的外延生长第一半导体层的过程中，在漏极区域进行相应的P-型或N-型掺杂。
可以理解的是，可以是其中漏极区域和源极区域的掺杂与第三半导体层的掺杂同时进行，还可以是漏极区域的掺杂、源极区域的掺杂和第三半导体层的掺杂先后进行。
一种电源装置，包括上述的半导体器件的任一种。电源装置包括有一次电路、
二次电路和变压器等，其中一次电路和二次电路中均具有开关元件，其中，开关元件采用上述的半导体器件的任一种。
一种手机，包括上述的半导体器件的任一种。手机包括显示屏，充电单元等，其中，充电单元包括上述的半导体器件的任一种。
一种放大器，放大器可以用于移动电话基站、光通信系统等领域中的功率放大器，所述功率放大器可以包括上述的半导体器件的任一种。
本公开内容的方案至少能有助于实现如下效果之一：所述半导体器件能够减小栅极漏电流，具有高阈值电压、高功率、高可靠性，能够实现低导通电阻和器件的常关状态，能够提供稳定的阈值电压，从而使得半导体器件具有良好的开关特性。
本公开内容的方案还能有助于实现如下效果之一：容易实现较高的高宽比；可以在单位面积上可以实现更高的沟道密度；适合于平面化工艺，有利于提升半导体器件的集成密度；所述半导体器件的结构和制备工艺较为简单，能有效降低生产成本。
以上结合具体的实施方式对本公开内容进行了描述，但本领域技术人员应该清楚，这些描述都是示例性地，并不是对本公开内容的保护范围的限制。本领域技术人员可以根据本公开内容的精神和原理对本公开内容做出各种变型和修改，这些变型和修改也在本公开内容的范围内。
工业实用性
本公开提供一种新颖的半导体器件结构及其制造方法，工艺简单、成本低廉，具有较高高宽比，可在单位面积上实现更高的沟道密度，具有高耐受电压、高功率和低导通电阻等高性能的节能的半导体器件。

Claims (18)

  1. 一种半导体器件的制造方法，包括：
    步骤1：提供一衬底，所述衬底具有第一表面；
    步骤2：在所述衬底的第一表面上形成第一绝缘层，所述第一绝缘层具有与所述衬底的第一表面平行的第一表面；
    步骤3：刻蚀所述第一绝缘层和部分所述衬底，形成多个垂直且间隔排列的第一台阶结构和第二台阶结构；多个所述第一台阶结构的第一表面和所述第二台阶结构的第二表面的下部分别由所述衬底的第二表面和第三表面构成，多个所述第一台阶结构的第一表面和所述第二台阶结构的第二表面的上部分别由所述第一绝缘层的第二表面和第三表面构成；
    步骤4：在所述第一台阶结构和所述第二台阶结构的第三表面上形成第二绝缘层；
    步骤5：在所述第一台阶结构的由所述衬底的第三表面构成的第二表面上形成单晶成核层，且在所述第二台阶结构的由所述衬底的第二表面构成的第一表面上形成单晶成核层；
    步骤6：以所述单晶成核层为成核中心，侧向外延生长第一半导体层。
  2. 一种半导体器件的制造方法，包括：
    步骤1：提供一衬底，所述衬底具有第一表面；
    步骤2：在所述衬底的第一表面上形成第一绝缘层，所述第一绝缘层具有与所述衬底的第一表面平行的第一表面；
    步骤3：刻蚀所述第一绝缘层和部分所述衬底，形成多个垂直且间隔排列的第一沟槽和第二沟槽；多个所述第一沟槽和第二沟槽的第一表面和第二表面的下部分别由所述衬底的第二表面和第三表面构成，多个所述第一沟槽和所述第二沟槽的第一表面和第二表面的上部分别由所述第一绝缘层的第二表面和第三表面构成；
    步骤4：在所述第一沟槽和所述第二沟槽的第三表面上形成第二绝缘层；
    步骤5：在所述第一沟槽的由所述衬底的第三表面构成的第二表面上形成单晶成核层，且在所述第二沟槽中的由所述衬底的第二表面构成的第一表面上形成单晶成核层；
    步骤6：以所述单晶成核层为成核中心，侧向外延生长第一半导体层。
  3. 如权利要求1所述的方法，其中，所述衬底的第二表面和第三表面具有六角对称的晶格结构。
  4. 如权利要求2所述的方法，其中，所述衬底的第二表面和第三表面具有六角对称的晶格结构。
  5. 如权利要求3所述的方法，其中，在步骤5中，在所述第一台阶结构的由所述衬底的第三表面构成的第二表面的一部分上形成一单晶成核层，且在所述第二台阶结构的由所述衬底的第二表面构成的第一表面的一部分上形成一单晶成核层。
  6. 如权利要求4所述的方法，其中，在步骤5中，在所述第一沟槽的由所述衬底的第三表面构成的第二表面的一部分上形成一单晶成核层，且在所述第二沟槽的由所述衬底的第二表面构成的第一表面的一部分上形成一单晶成核层。
  7. 如权利要求6所述的方法，其中，所述步骤5可替代成步骤5’，在所述步骤5’中，以所述单晶成核层为成核中心，在所述第一沟槽及第二沟槽中侧向外延生长第一半导体层的第一子层，然后再以所述第一子层为核心，进行掺杂的第三半导体层的生长，然后再继续生长所述第一半导体层的第二子层，所述第三半导体层是N-型掺杂或P-型掺杂。
  8. 一种半导体器件，其包括：
    一衬底，所述衬底具有第一表面；
    在所述衬底的第一表面上形成的第一绝缘层，所述第一绝缘层具有与所述衬底的第一表面平行的第一表面；
    多个垂直于衬底第一表面且间隔排列的第一沟槽和第二沟槽；
    所述第一沟槽和所述第二沟槽的第一表面和第二表面的下部分别由所述衬底的第二表面和第 三表面构成，所述第一沟槽和第二沟槽的第一表面和第二表面的上部由所述第一绝缘层的第二表面和第三表面构成；
    在所述第一沟槽的由所述衬底的第三表面构成的第二表面上形成的单晶成核层，以及在所述第二沟槽中的由所述衬底的第二表面构成的第一表面上形成的单晶成核层；
    以所述单晶成核层为成核中心，侧向外延生长的第一半导体层。
  9. 根据权利要求8所述的半导体器件，其中，在所述第一沟槽的第二表面的一部分上形成的所述单晶成核层，在所述第二沟槽的第一表面的一部分上形成的所述单晶成核层。
  10. 根据权利要求8或9所述的半导体器件，其中，所述第一半导体层在沿着所述沟槽的长度方向上分为第一半导体层的第一子层和第二子层，在所述第一子层和第二子层之间还设置有掺杂的第三半导体层。
  11. 根据权利要求8～10中任一项所述的半导体器件，其中，所述衬底的第二表面和第三表面具有六角对称的晶格结构。
  12. 一种半导体器件，其包括：
    一衬底，所述衬底具有第一表面；
    在所述衬底中形成的多个垂直于所述衬底的第一表面且间隔排列的第一沟槽和第二沟槽；
    在多个所述第一沟槽和第二沟槽的第三表面上形成的第二绝缘层；
    在所述第一沟槽中的第二表面上和所述第二沟槽中的第一表面上形成的单晶成核层，
    以所述单晶成核层为成核中心生长的第一半导体层，所述第一半导体层具有平行于所述沟槽的第一表面和第二表面且垂直于所述衬底的第一表面的具有自发极化效应和压电极化效应的第一面和与其相对的第二面；
    在所述第一半导体层上覆盖形成的第二半导体层，所述第二半导体层的禁带宽度大于所述第一半导体层的禁带宽度，从而在所述第一半导体的第一面和第二面上分别形成有二维电子气和二维空穴气。
  13. 一种半导体器件，其包括：
    一衬底，所述衬底具有第四表面；
    在所述衬底的第四表面上形成的第三绝缘层；
    在所述衬底中形成的多个垂直于所述衬底的第四表面且间隔排列的第一沟槽和第二沟槽；
    在多个所述第一沟槽和所述第二沟槽的第三表面上形成的第二绝缘层；
    在所述第一沟槽中的第二表面上和所述第二沟槽中的第一表面上形成的单晶成核层，以及在所述第一沟槽中的第一表面上和所述第二沟槽中的第二表面上形成的第四绝缘层；
    在所述第一沟槽和第二沟槽中的第一半导体层，且所述第一半导体层突出所述衬底的第四表面，所述第一半导体层具有平行于所述第一沟槽的第一表面和所述第二沟槽的第二表面及垂直于所述衬底的第四表面且突出所述衬底的第四表面的具有自发极化效应和压电极化效应的第一面和与其相对的第二面；
    在所述第一半导体层上覆盖形成的第二半导体层，所述第二半导体层的禁带宽度大于所述第一半导体层的禁带宽度，从而在所述第一半导体的第一面和第二面上分别形成二维电子气和二维空穴气。
  14. 一种半导体器件，其包括：
    一衬底，所述衬底具有第一表面，以及与所述第一表面平行但低于所述第一表面的第五表面；
    在所述衬底的第一表面和第五表面上形成的第三绝缘层；
    在所述衬底中形成的多个垂直于所述衬底的第一表面且间隔排列的第一沟槽和第二沟槽；
    在所述第一沟槽和所述第二沟槽的第三表面上形成的第二绝缘层；
    在所述第一沟槽中的第二表面和所述第二沟槽中的第一表面上形成的单晶成核层，在所述第一沟槽中的第一表面和所述第二沟槽中的第二表面上分别形成的第四绝缘层；
    在所述第一沟槽和所述第二沟槽中的第一半导体层，且所述第一半导体层突出所述衬底的第五表面，所述第一半导体层具有平行于所述第一沟槽的第一表面和所述第二沟槽的第二表面且垂 直于所述衬底的第五表面向上延伸的具有自发电极化效应和压电极化效应的第一面；
    在所述第一半导体层的所述第一面上覆盖形成的第二半导体层，所述第二半导体层的禁带宽度大于所述第一半导体层的禁带宽度，从而在所述第一半导体的第一面上形成二维电子气。
  15. 一种半导体器件，其包括：
    一衬底，所述衬底具有第一表面，以及与所述第一表面平行但低于所述第一表面的第六表面；
    在所述衬底的第一表面和第六表面上形成的第三绝缘层；
    在所述衬底中形成的多个垂直于所述衬底的第一表面且间隔排列的第一沟槽和第二沟槽；
    在所述第一沟槽和第二沟槽的第三表面上形成的第二绝缘层；
    在所述第一沟槽中的第二表面上和所述第二沟槽中的第一表面上形成的单晶成核层，在所述第一沟槽中的第一表面上和所述第二沟槽中的第二表面上分别形成的第四绝缘层；
    在所述第一沟槽和所述第二沟槽中的第一半导体层，且所述第一半导体层突出所述衬底的第六表面，所述第一半导体层具有平行于所述第一沟槽的第二表面和所述第二沟槽的第一表面且垂直于所述衬底的第六表面向上延伸的具有自发极化效应和压电极化效应的第二面；
    在所述第一半导体层的所述第一面上覆盖形成第二半导体层，所述第二半导体层的禁带宽度高于所述第一半导体层的禁带宽度，从而在所述第一半导体的第二面上形成了二维空穴气。
  16. 一种电源装置，包括有一次电路、二次电路和变压器，其中，所述一次电路和所述二次电路中均具有开关元件，所述开关元件采用包括权利要求8-11中任一项所述的半导体器件。
  17. 一种手机，其中，手机的充电单元包括权利要求8-11中任一项所述的半导体器件。
  18. 一种功率放大器，包括包括权利要求8-11中任一项所述的半导体器件。
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