WO2021218371A1 - 一种iii族氮化物半导体集成电路结构、制造方法及其应用 - Google Patents

一种iii族氮化物半导体集成电路结构、制造方法及其应用 Download PDF

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WO2021218371A1
WO2021218371A1 PCT/CN2021/078955 CN2021078955W WO2021218371A1 WO 2021218371 A1 WO2021218371 A1 WO 2021218371A1 CN 2021078955 W CN2021078955 W CN 2021078955W WO 2021218371 A1 WO2021218371 A1 WO 2021218371A1
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nitride semiconductor
conductivity type
transistor
carrier gas
dimensional carrier
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PCT/CN2021/078955
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English (en)
French (fr)
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黎子兰
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广东致能科技有限公司
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Priority to JP2022530180A priority Critical patent/JP7450719B2/ja
Priority to US17/436,011 priority patent/US20230044911A1/en
Priority to KR1020227016401A priority patent/KR20220082892A/ko
Priority to EP21759229.4A priority patent/EP3933920A4/en
Publication of WO2021218371A1 publication Critical patent/WO2021218371A1/zh

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    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Definitions

  • the present disclosure relates to the field of semiconductor integrated circuits, and more specifically, to a III-nitride semiconductor integrated circuit structure, manufacturing method and application thereof.
  • III-nitride semiconductors have become a research hotspot in the semiconductor industry due to their excellent performance such as high critical breakdown electric field, high electron saturation rate, high thermal conductivity, and strong radiation resistance.
  • III-nitride semiconductors and devices have shined in the fields of radio frequency/microwave, mobile communications and semiconductor lighting, and power integrated circuit design.
  • III-nitride semiconductor discrete devices exhibit unprecedented switching speeds and operating frequencies, in actual circuit applications, the parasitic inductance between chips will severely limit the switching speed of III-nitride semiconductor discrete devices.
  • An effective method to reduce parasitic inductance is to research and develop integrated circuits using III-nitride semiconductors.
  • CMOS complementary Metal Oxide Semiconductor
  • III-nitride semiconductor heterojunction has a strong polarization effect, there is a higher concentration of two-dimensional carrier gas at the interface of the heterojunction.
  • the high-mobility transistor made by using this two-dimensional carrier gas is usually Normally open.
  • normally-off transistors are usually required. Therefore, the realization of high-performance enhanced high-mobility transistors with high withstand voltage, high power and low on-resistance has always been one of the key concerns of the industry.
  • the present disclosure provides a complementary III-nitride semiconductor integrated circuit structure and a manufacturing method thereof.
  • the present application provides an integrated circuit structure including:
  • At least one first transistor includes:
  • a first nitride semiconductor structure with a first polarization junction which has a first conductivity type two-dimensional carrier gas
  • a first gate electrode disposed on the first nitride semiconductor structure
  • a first source electrode and a first drain electrode which are oppositely distributed on both sides of the first gate electrode, and are gas-coupled with the first conductivity type two-dimensional carrier;
  • At least one second transistor includes:
  • a second nitride semiconductor structure with a second polarization junction which has a two-dimensional carrier gas of the second conductivity type
  • a second gate electrode disposed on the second nitride semiconductor structure
  • a second source electrode and a second drain electrode which are oppositely distributed on both sides of the second gate electrode, and are gas-electrically coupled to the two-dimensional carrier of the second conductivity type;
  • first polarization junction and the second polarization junction have different crystal orientations
  • the conductivity types of the two-dimensional carrier gas of the first conductivity type and the two-dimensional carrier gas of the second conductivity type are different;
  • the two-dimensional carrier gas of the first conductivity type and the two-dimensional carrier gas of the second conductivity type respectively form a carrier in a direction parallel to the first polarization junction and the second polarization junction.
  • Current sub-channel Current sub-channel.
  • the first nitride semiconductor structure and the second nitride semiconductor structure are epitaxially grown on the same substrate.
  • the first polarization junction and the second polarization junction respectively have vertical interfaces.
  • the crystal orientation of the first polarization junction of the first nitride semiconductor structure is ⁇ 0001>, and the surface thereof is a (0001) plane.
  • the crystal orientation of the second polarization junction of the second nitride semiconductor structure is The surface is (0001 -) plane.
  • the substrate is silicon, sapphire, silicon carbide or gallium nitride.
  • the first conductivity type two-dimensional carrier gas is a two-dimensional electron gas.
  • the two-dimensional carrier gas of the second conductivity type is two-dimensional hole gas.
  • the first nitride semiconductor structure further includes a first doped structure electrically coupled with the first conductivity type two-dimensional carrier gas.
  • the second nitride semiconductor structure further includes a second doped structure electrically coupled with the second conductivity type two-dimensional carrier gas.
  • the first doped structure includes at least one doped region of the second conductivity type, which at least partially overlaps with the first gate electrode in the crystal projection direction.
  • the first doped structure further includes a plurality of doped regions of the first conductivity type electrically coupled with the first source electrode and the first drain electrode.
  • the second doped structure includes at least one doped region of the first conductivity type, which at least partially overlaps the second gate electrode in the direction of the crystal projection.
  • the second doped structure further includes a plurality of second conductivity type doped regions electrically coupled with the second source electrode and the second drain electrode.
  • the first transistor implements a normally-off type through a doped region of the second conductivity type that at least partially overlaps the first gate electrode in the direction of the crystal projection.
  • the second transistor realizes a normally-off type through a doped region of the first conductivity type that at least partially overlaps the second gate electrode in the direction of the crystal projection.
  • the first nitride semiconductor structure further includes a stacked structure of a first region of the first nitride semiconductor layer and a second nitride semiconductor layer, wherein the first nitride semiconductor layer and the second nitride semiconductor layer The forbidden band of the nitride semiconductor layer is different, and the carrier channel is formed at the interface between the first region of the first nitride semiconductor layer and the second nitride semiconductor layer.
  • the second nitride semiconductor structure further includes a stacked structure of a second region of the first nitride semiconductor layer and a second nitride semiconductor layer, wherein the first nitride semiconductor layer and the second nitride semiconductor layer The forbidden band of the nitride semiconductor layer is different, and the carrier channel is formed at the interface between the second region of the first nitride semiconductor layer and the second nitride semiconductor layer.
  • the first transistor and the second transistor are complementary and connected in series, wherein the first gate electrode and the second gate electrode are connected together as an input terminal, and the first source electrode or Any one of the second source electrode is coupled to ground or an external negative power source V SS , any one of the second source electrode or the first source electrode is coupled to an external positive power source V DD , and the first drain electrode is connected to the first The two drain electrodes are connected together as an output terminal.
  • At least two of the first transistors are connected in series or in parallel as a first unit, and at least two of the second transistors are connected in parallel or in series as a second unit, wherein the series connection in the first unit Or the parallel connection corresponds to the parallel connection or the series connection in the second unit, and the first unit and the second unit are connected in series and used as an output terminal, and the first unit in the first unit
  • the transistor and the second transistor in the second unit are complementary paired, and the first gate electrode and the second gate electrode of the complementary paired transistors are connected together as input terminals, respectively.
  • any one of the first source electrodes is coupled to ground or an external negative power supply V SS , and any one of the first drain electrodes serves as an output
  • the terminal is coupled with the second unit, and the remaining first source electrodes and the first drain electrodes are sequentially connected in series.
  • the first source electrode is connected together to couple the external positive power supply V DD
  • the first drain electrode is connected together as the output terminal and the second transistor One unit coupling.
  • the first source electrodes are connected together to be coupled to ground or an external negative power supply V SS , and the first drain electrodes are connected together as an output The end is coupled with the second unit.
  • any one of the first source electrodes is coupled to an external positive power source V DD
  • any one of the first drain electrodes serves as an output terminal and The first unit is coupled, and the remaining first source electrodes are sequentially connected in series with the remaining first drain electrodes.
  • the first transistor in the first unit can be connected in any number of series or parallel connections, and the first transistor in the second unit is complementary to the first transistor in the first unit.
  • the second transistors may be connected in parallel or in series in a corresponding number.
  • the integrated circuit structure further includes a nucleation layer.
  • the source electrode/drain electrode in the series connection or the parallel connection may be coupled to ground or an external negative power supply V SS .
  • the source electrode/drain electrode in the series connection or the parallel connection may be coupled to an external positive power supply V DD .
  • it further includes a first body electrode, which is electrically connected to the second conductivity type doped region.
  • it further includes a second body electrode, which is electrically connected to the first conductivity type doped region.
  • an electronic device is provided.
  • the present application provides a method for manufacturing an integrated circuit structure, including the following steps:
  • At least one first transistor is formed, which includes:
  • At least one second transistor is formed, which includes:
  • first nitride semiconductor structure and the second nitride semiconductor structure are formed at the same time;
  • first polarization junction and the second polarization junction have different crystal orientations, and the polarization junctions respectively have vertical interfaces;
  • the conductivity types of the two-dimensional carrier gas of the first conductivity type and the two-dimensional carrier gas of the second conductivity type are different;
  • the two-dimensional carrier gas of the first conductivity type and the two-dimensional carrier gas of the second conductivity type respectively form a carrier in a direction parallel to the first polarization junction and the second polarization junction.
  • Current sub-channel Current sub-channel.
  • the step of forming at least one first transistor further includes:
  • a first source electrode and a first drain electrode are formed respectively, which are oppositely distributed on both sides of the first gate electrode, and are gas-coupled with the first conductivity type two-dimensional carrier gas.
  • the step of forming at least one second transistor further includes:
  • a second source electrode and a second drain electrode are formed respectively, which are oppositely distributed on both sides of the second gate electrode and are electrically coupled with the second conductivity type two-dimensional carrier gas.
  • a substrate is provided, and the first nitride semiconductor structure and the second nitride semiconductor structure are formed on the substrate.
  • the first nitride semiconductor structure and the second nitride semiconductor structure respectively include different regions of the first nitride semiconductor layer and a stacked structure of the second nitride semiconductor layer.
  • the step of forming the first nitride semiconductor structure and the second nitride semiconductor structure on the substrate further includes:
  • first trenches Forming a plurality of first trenches on the substrate, and epitaxially grow the first nitride semiconductor layer on the sidewalls of the first trenches to fill the first trenches;
  • a second nitride semiconductor layer is epitaxially grown on the side surfaces of different regions of the first nitride semiconductor layer, respectively.
  • the step of forming the transistor further includes:
  • one or more first gate electrodes, first source electrodes, and first drain electrodes are formed on the first nitride semiconductor structure and the second nitride semiconductor structure, and one or more A second gate electrode, a second source electrode, and a second drain electrode.
  • the first polarization junction of the first nitride semiconductor structure is formed in a crystal orientation ⁇ 0001> direction, which has a (0001) crystal plane.
  • the substrate is silicon, sapphire, silicon carbide or gallium nitride.
  • the first conductivity type two-dimensional carrier gas is a two-dimensional electron gas
  • the second conductivity type two-dimensional carrier gas is a two-dimensional hole gas
  • the step of forming the first nitride semiconductor structure with a polarized junction further includes:
  • a first doped structure is formed, and the first doped structure is electrically coupled with the first conductivity type two-dimensional carrier gas.
  • the step of forming a second nitride semiconductor structure having a polarized junction further includes:
  • a second doped structure is formed, and the second doped structure is electrically coupled with the second conductivity type two-dimensional carrier gas.
  • the first doped structure includes at least one doped region of the second conductivity type, which at least partially overlaps with the first gate electrode in the crystal projection direction.
  • the first doped structure further includes a plurality of doped regions of the first conductivity type electrically coupled with the first source electrode and the first drain electrode.
  • the second doped structure includes at least one doped region of the first conductivity type, which at least partially overlaps the second gate electrode in the direction of the crystal projection.
  • the second doped structure further includes a plurality of second conductivity type doped regions electrically coupled with the second source electrode and the second drain electrode.
  • a first body electrode is further formed, which is electrically connected to the second conductivity type doped region.
  • a second body electrode is further formed, which is electrically connected to the first conductivity type doped region.
  • the two-dimensional carrier gas between the first transistors and/or between the second transistors is further removed, and an insulating medium is filled.
  • the step of forming the first nitride semiconductor structure with a polarized junction further includes:
  • the forbidden bands of the first nitride semiconductor layer and the second nitride semiconductor layer are different, and the carrier channel is formed in the first region of the first nitride semiconductor layer and the second region of the second nitride semiconductor layer. On the interface of the nitride semiconductor layer.
  • the step of forming a second nitride semiconductor structure having a polarized junction further includes:
  • the forbidden bands of the first nitride semiconductor layer and the second nitride semiconductor layer are different, and the carrier channel is formed in the second region of the first nitride semiconductor layer and the second region of the second nitride semiconductor layer. On the interface of the nitride semiconductor layer.
  • a III-nitride semiconductor integrated circuit structure including:
  • At least one first transistor includes:
  • a first nitride semiconductor structure with a first polarization junction which has a first conductivity type two-dimensional carrier gas
  • a first gate electrode disposed on the first nitride semiconductor structure
  • a first source electrode and a first drain electrode which are oppositely distributed on both sides of the first gate electrode, and are gas-coupled with the first conductivity type two-dimensional carrier;
  • At least one second transistor includes:
  • a second nitride semiconductor structure with a second polarization junction which has a two-dimensional carrier gas of the second conductivity type
  • a second gate electrode disposed on the second nitride semiconductor structure
  • a second source electrode and a second drain electrode which are oppositely distributed on both sides of the second gate electrode, and are gas-electrically coupled to the two-dimensional carrier of the second conductivity type;
  • first polarization junction and the second polarization junction have different crystal orientations
  • the conductivity types of the two-dimensional carrier gas of the first conductivity type and the two-dimensional carrier gas of the second conductivity type are different;
  • the two-dimensional carrier gas of the first conductivity type and the two-dimensional carrier gas of the second conductivity type respectively form a carrier in a direction parallel to the first polarization junction and the second polarization junction.
  • Current sub-channel Current sub-channel.
  • FIG. 1 is a schematic diagram of circuit symbols of a high electron mobility transistor and a high hole mobility transistor
  • FIG. 2 is a plan view and A-A cross-sectional view of a III-nitride semiconductor integrated circuit structure 10;
  • FIG. 3 is a plan view and an A-A cross-sectional view of an optional III-nitride semiconductor integrated circuit structure 10';
  • Figure 4 is a schematic diagram of an optional inverter circuit structure with additional electrical connections and circuit elements
  • FIG. 5 is a schematic diagram of an optional NAND gate circuit structure with additional electrical connections and circuit elements
  • Figure 6 is a schematic diagram of an optional NOR circuit structure with additional electrical connections and circuit elements
  • Figure 7 is a schematic diagram of an optional complex CMOS circuit structure with additional electrical connections and circuit elements
  • 8-40 is a schematic diagram of a manufacturing method of a nitride integrated circuit structure.
  • Fig. 41 is a schematic block diagram of a manufacturing method of a nitride integrated circuit structure.
  • the integrated circuit structure of the present disclosure is a complementary integrated circuit based on a group III nitride semiconductor, and includes: at least one first transistor and at least one second transistor.
  • the first transistor includes: a first nitride semiconductor structure with a first polarization junction, which has a first conductivity type two-dimensional carrier gas; a first gate electrode, which is disposed on the first nitride semiconductor structure; The first source electrode and the first drain electrode are oppositely distributed on both sides of the first gate electrode, and are gas-coupled with the first conductivity type two-dimensional carrier.
  • the second transistor includes: a second nitride semiconductor structure with a second polarization junction, which has a two-dimensional carrier gas of the second conductivity type; a second gate electrode, which is disposed on the second nitride semiconductor structure; The second source electrode and the second drain electrode are oppositely distributed on both sides of the second gate electrode, and are gas-electrically coupled with the second conductivity type two-dimensional carrier.
  • the first polarization junction and the second polarization junction have different crystal orientations; the conductivity types of the two-dimensional carrier gas of the first conductivity type and the two-dimensional carrier gas of the second conductivity type are different ; The first conductivity type two-dimensional carrier gas and the second conductivity type two-dimensional carrier gas respectively form a current carrier in a direction parallel to the first polarization junction and the second polarization junction Sub-channel.
  • the integrated circuit structure of the present disclosure can be widely used in electronic devices with analog and/or digital integrated circuits such as inverters, amplifiers, inverters, NAND gates, NOR gates, etc., to realize operation, amplification, transmission, Conversion/conversion, logic and other functions.
  • analog and/or digital integrated circuits such as inverters, amplifiers, inverters, NAND gates, NOR gates, etc.
  • FIGS. 1-7 illustrates the circuit symbols of the High Electron Mobility Transistor (HEMT) and the High Hole Mobility Transistor (HHMT).
  • the HEMT 100 includes a first source electrode 101, a first drain electrode 103, a first gate electrode 102, and a first body electrode 104. Between the first source electrode 101 and the first drain electrode 103 is a two-dimensional electron gas (Two- Dimensional Electron Gas (2DEG) channel 105, and solid spheres represent electrons.
  • the HHMT 200 includes a second source electrode 201, a second drain electrode 203, a second gate electrode 202, and a second body electrode 204.
  • Two-dimensional hole gas (Two -Dimensional Hole Gas, 2DHG) channel 205 hollow spheres represent holes.
  • the first gate electrode 102 and the second gate electrode 202 control the on and off of the conduction channels of the HEMT 100 and HHMT 200, respectively, and the first body electrode 104 and the second body electrode 204 control the threshold voltages of the HEMT 100 and HHMT 200, respectively.
  • HEMT100 can be used as the first transistor
  • HHMT200 can be used as the second transistor, and vice versa.
  • FIG. 2 shows a plan view and an A-A cross-sectional view of an integrated circuit structure 10 of a III-nitride semiconductor.
  • the integrated circuit structure 10 includes a nucleation layer 121, a first nitride semiconductor layer 122, a second nitride semiconductor layer 123 and a plurality of electrodes 101, 102, 103, 104, 201, 202, 203, 204.
  • the integrated circuit structure 10 includes at least one of the first conductivity type (for example, N-channel or N-type) formed in or on the first region 124 of the first nitride semiconductor layer 122
  • the integrated circuit structure 10 can be regarded as a complementary integrated circuit. Furthermore, since the base layer on which the transistors 100 and 200 are formed is the first nitride semiconductor layer 122, the integrated circuit structure 10 may be referred to as a complementary nitride integrated circuit structure in the present disclosure.
  • the nucleation layer 121 may be an AlN layer.
  • the first nitride semiconductor layer 122 may be formed of GaN without dopants.
  • the first nitride semiconductor layer 122 may also include one or more nitride semiconductor sub-layers, which may be formed of GaN, InN, AlN, AlGaN, InAlN, InGaN, AlGaInN or other suitable alloy materials.
  • the first nitride semiconductor layer 122 may have a thickness in the range of 1 micrometer to 10 micrometers. Alternatively, the first nitride semiconductor layer 122 may be thicker or thinner.
  • the numerical range described in the present disclosure is only an example and not a limitation of the present disclosure.
  • the first region 124 of the first nitride semiconductor layer 122 is a region away from the nucleation layer 121
  • the second region 125 of the first nitride semiconductor layer 122 is a region opposite or adjacent to the nucleation layer 121.
  • the surface of the first region 124 and second region 125 are different crystal faces, for example, the former is the (0001) plane, which is (0001 -) plane.
  • the crystal orientations of the first region 124 and the second region 125 of the first nitride semiconductor layer 122 are different, for example, the former is the ⁇ 0001> crystal orientation, and the latter is Crystal orientation, the ⁇ 0001> crystal orientation and The crystal directions are opposite to each other.
  • the first nitride semiconductor layer 122 may be epitaxially formed on another substrate 120.
  • the substrate 120 may be a silicon substrate, a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, or the like.
  • the substrate that can be used to achieve the epitaxial growth of the first nitride semiconductor layer 122 can be formed of a material selected from silicon, sapphire, silicon carbide, gallium nitride, or any other suitable material.
  • the first nitride semiconductor layer 122 itself may include the substrate 120.
  • first nitride semiconductor layer used in the present disclosure may refer to a gallium nitride substrate or a nitride semiconductor layer grown on a substrate.
  • first nitride semiconductor layer 122 may be appropriately doped, which will be discussed in further detail later.
  • the second nitride semiconductor layer 123 is formed on the first nitride semiconductor layer 122 and forms a stacked structure with the first region 124 and the second region 125 of the first nitride semiconductor layer 122, respectively.
  • the second nitride semiconductor layer 123 is a barrier layer or a carrier supply layer, and may be formed of, for example, an alloy from a group III nitride.
  • the second nitride semiconductor layer 123 may include one or more nitride semiconductor sublayers, and may be formed of AlGaN, InAlN, InGaN, AlN or other suitable alloy materials.
  • the second nitride semiconductor layer 123 may be formed of an AlGaN alloy having an atomic percentage of aluminum in the range of about 20% to 30%. Alternatively, the percentage of aluminum can be lower or higher.
  • the first nitride semiconductor layer 122 has a first band gap
  • the second nitride semiconductor layer 123 has a second band gap, which is larger than the first band gap.
  • the first nitride semiconductor layer 122 such as a GaN layer may have a band gap of about 3.4 eV
  • the second nitride semiconductor layer 123 such as an AlGaN layer may have a band gap of about 4.0 eV.
  • the band gap of the second nitride semiconductor layer 123 may be higher or lower. In any case, the band gaps of the first nitride semiconductor layer 122 and the second nitride semiconductor layer 123 are different from each other.
  • first region 124 of the first nitride semiconductor layer 122 and the second nitride semiconductor layer 123 have a first polarization junction 126 at the contact interface to form a first nitride semiconductor structure;
  • the second region 125 and the second nitride semiconductor layer 123 have a second polarization junction 127 at the contact interface to form a second nitride semiconductor structure.
  • the first nitride semiconductor structure includes a stacked structure of the first region 124 of the first nitride semiconductor layer 122 and the second nitride semiconductor layer 123, and the stacked structure may be a stacked structure of multiple sub-layers;
  • the second nitride semiconductor structure includes a stacked structure of the second region 125 of the first nitride semiconductor layer 122 and the second nitride semiconductor layer 123, and the stacked structure may be a stacked structure of multiple sub-layers.
  • the stacked structure may be, for example, a stacked structure of the first sublayer/second sublayer of the first nitride semiconductor layer 122 and the first sublayer/second sublayer of the second nitride semiconductor layer 123.
  • the first nitride semiconductor structure and the second nitride semiconductor structure are formed simultaneously or separately.
  • the first nitride semiconductor layer 122 and the second nitride semiconductor layer 123 lack inversion symmetry, they are aligned with the ⁇ 0001> crystal orientation or Crystal orientation perpendicular to the crystal plane (0001) plane and the (0001 -) plane is a polar plane, the polarization is formed in the transitional region between the contact junction, respectively.
  • the first polarization junction 126 and the second polarization junction 127 have different crystal orientations, for example, the former is the ⁇ 0001> crystal orientation, and the latter is Crystal orientation, and the first polarization junction 126 and the second polarization junction 127 have a vertical interface.
  • the former is the ⁇ 0001> crystal orientation
  • the latter is Crystal orientation
  • the first polarization junction 126 and the second polarization junction 127 have a vertical interface.
  • there is a strong positive polarization charge at the vertical interface of the first polarization junction 126 and a strong negative polarization charge at the vertical interface of the second polarization junction 127.
  • first conductivity type two-dimensional carrier gas and the second conductivity type two-dimensional carrier gas are formed in directions parallel to the first polarization junction 126 and the second polarization junction 127, respectively. Carrier channel.
  • the two-dimensional electron gas is located in a region corresponding to the conductive channel 105 of the first transistor 100, and provides a current flowing between the first source electrode 101 and the first drain electrode 103 of the first transistor 100;
  • the hole gas is located in a region corresponding to the conductive channel 205 of the second transistor 200 and provides a current flowing between the second source electrode 201 and the second drain electrode 203 of the second transistor 200.
  • the aforementioned plurality of electrodes 101, 102, 103, 104, 201, 202, 203, 204 are respectively disposed on the first nitride semiconductor structure and the second nitride semiconductor structure.
  • the first source electrode 101 and the first drain electrode 103 are oppositely distributed on both sides of the first gate electrode 102, and are gas-coupled with the first conductivity type two-dimensional carrier gas to form at least one first transistor 100.
  • the second source electrode 201 and the second drain electrode 203 are oppositely distributed on both sides of the second gate electrode 202, and are gas-coupled with two-dimensional carriers of the second conductivity type to form at least one second transistor 200.
  • the first transistor 100 further includes a first body electrode 104, which is disposed on the side surface of the first nitride semiconductor structure opposite to the first gate electrode 102;
  • the second transistor 200 further includes a second body electrode 204, which Opposite to the second gate electrode 202, it is disposed on the side surface of the second nitride semiconductor structure.
  • the first nitride semiconductor layer 122 further includes at least one doped region 150 of the second conductivity type (for example, P-type), which at least partially overlaps with the first gate electrode 102 in the ⁇ 0001> crystal orientation projection direction , And electrically coupled with the two-dimensional carrier gas of the first conductivity type, thereby substantially depleting the two-dimensional carrier gas of the one conductivity type to realize the first transistor 100 as a normally-off type.
  • the first body electrode 104 may also be electrically connected to the doped region 150 of the second conductivity type (for example, P-type).
  • the first nitride semiconductor layer 122 further includes at least one doped region 140 of the first conductivity type (for example, N-type), which is in contact with the second gate electrode 202
  • the crystal orientation projection direction at least partially overlaps and is electrically coupled with the second conductivity type two-dimensional carrier gas, thereby substantially depleting the two conductivity type two-dimensional carrier gas to realize the second transistor 200 as a normally-off type.
  • the second body electrode 204 can also be electrically connected to the doped region 140 of the first conductivity type (for example, N-type).
  • the first nitride semiconductor layer 122 may include at least one doped region 150 of the second conductivity type (for example, P-type) and a doped region 140 of the first conductivity type (for example, N-type) at the same time, which are respectively
  • the two-dimensional carrier gas near the first gate electrode 102 and the second gate electrode 202 is substantially depleted, so that the first transistor 100 and the second transistor 200 are normally off at the same time.
  • FIG. 3 shows a plan view and a cross-sectional view along the AA direction of another integrated circuit structure 10' of a group III nitride semiconductor.
  • a plurality of first conductivity types may be alternately formed in the first nitride semiconductor layer 122 ( Doped regions 140 of the second conductivity type (eg P-type) and a plurality of doped regions 150 of the second conductivity type (eg P-type).
  • the doped region 150 of the second conductivity type (for example, P-type) at least partially overlaps the first gate electrode 102 in the ⁇ 0001> crystal orientation projection direction, and substantially depletes the first gate electrode 102
  • the nearby two-dimensional carrier gas of the first conductivity type, and the doped regions 140 of the first conductivity type (for example, N-type) are electrically coupled with the first source electrode 101 and the first drain electrode 103, respectively.
  • the doped region 140 of the first conductivity type (for example, N-type) is in the The crystal orientation projection direction at least partially overlaps the second gate electrode 202, and substantially depletes the second conductivity type two-dimensional carrier gas near the second gate electrode 102, and the doping of the second conductivity type (for example, P-type)
  • the region 150 is electrically coupled with the second source electrode 201 and the second drain electrode 203, respectively.
  • FIGS. 4-7 exemplarily show various circuits using the complementary integrated circuit structure of FIG. 2, it should be understood that the various circuit implementations of FIGS. 4-7 may also use the complementary integrated circuit structure of FIG. 3.
  • FIG. 4 illustrates an inverter circuit structure with additional electrical connections and circuit elements.
  • the inverter circuit structure 400 includes a first transistor 100 and a second transistor 200, and the first transistor and the second transistor are connected in series.
  • the first transistor 100 and the second transistor 200 have the shape of FIG. 2 or FIG. 3 Circuit configuration.
  • the first transistor 100 is a HEMT
  • the second transistor 200 is a HHMT
  • the first gate electrode 102 and the second gate electrode 202 are connected together as an input terminal V in
  • the first source electrode 101 is coupled to ground or an external negative terminal.
  • the power supply V SS , the second source electrode 201 is coupled to the external positive power supply V DD , and the first drain electrode 103 and the second drain electrode 203 are connected together as an output terminal.
  • FIG. 5 illustrates the NAND circuit structure with additional electrical connections and circuit elements.
  • the NAND gate circuit structure 500 includes at least two first transistors 100 and at least two second transistors 200, and the first transistor 100 and the second transistor 200 have the circuit structure of FIG. 2 or FIG. 3.
  • the first transistor 100 is a HEMT
  • the second transistor 200 is a HHMT.
  • At least two first transistors 100 are connected in series as the first unit 501
  • at least two second transistors 200 are connected in parallel as the second unit 502
  • the connection terminal of the first unit 501 and the second unit 502 connected in series is used as the output terminal Vout.
  • first transistor 100 of the first unit and the second transistor 200 of the second unit are complementary paired, and the gate electrodes 102 and 202 of the two complementary paired transistors are connected together as input terminals A and B, respectively. More specifically, a plurality of first transistors 100 in the first unit are sequentially connected in series, one of the first source electrodes 101 is coupled to ground or an external negative power supply V SS , and one first drain electrode 103 is used as the output terminal Vout of the first unit 501 It is electrically coupled with the second unit 502.
  • the multiple second transistors 200 in the second unit 502 are connected in parallel, wherein multiple second drain electrodes 203 are connected together as the output terminal Vout to electrically couple with the first unit 501, and multiple second source electrodes 201 are connected together to couple externally. Positive power supply V DD .
  • FIG. 6 illustrates the NOR circuit structure with additional electrical connections and circuit elements.
  • the NOR circuit structure 600 includes at least two first transistors 100 and at least two second transistors 200, and the first transistor 100 and the second transistor 200 have the circuit structure of FIG. 2 or FIG. 3.
  • the first transistor 100 is a HEMT
  • the second transistor 200 is a HHMT.
  • At least two first transistors 100 are connected in parallel as the first unit 601, at least two second transistors 200 are connected in series as the second unit 602, and the connection terminal of the first unit 601 and the second unit 602 connected in series is used as the output terminal Vout.
  • first transistor 100 of the first unit 601 and the second transistor 200 of the second unit 602 are complementary paired, and the gate electrodes 102 and 202 of the two complementary paired transistors are connected together as input terminals A and B, respectively. More specifically, a plurality of first transistors 100 in the first unit 601 are connected in parallel, wherein a plurality of first source electrodes 101 are connected together to be coupled to ground or an external negative power supply V SS , and a plurality of first drain electrodes 103 are connected together as The output terminal Vout of the first unit 601 is electrically coupled with the second unit 602.
  • the plurality of second transistors 200 in the second cell 601 are sequentially connected in series, one of the first source electrode 101 is coupled to the external positive power supply V DD , and one first drain electrode 103 serves as the output terminal Vout of the second cell 602 and the first cell 601 Electrical coupling.
  • Figure 7 illustrates a complex CMOS circuit structure with additional electrical connections and circuit elements.
  • the complex CMOS circuit structure 700 includes at least two first transistors 100 and at least two second transistors 200, and the first transistor 100 and the second transistor 200 have the circuit structure of FIG. 2 or FIG. 3.
  • the first transistor 100 is a HEMT
  • the second transistor 200 is a HHMT.
  • a plurality of first transistors 100 are connected in series or in parallel in any number and serve as the first unit 701.
  • the plurality of second transistors 200 are complementary paired with the plurality of first transistors 100 in the first unit 701, and any number of corresponding parallel connections or series connections are performed, and they serve as the second unit 702.
  • the connection end of the first unit 701 and the second unit 702 connected in series is used as the output end Vout.
  • the gate electrodes 102 and 202 of the aforementioned two complementary paired transistors are connected together as input terminals A, B, C, and D, respectively.
  • first transistors 100 in the first unit 701 which are respectively denoted as first transistors 100 11 , 100 12 , 100 13 , and 100 14
  • second transistors 200 are denoted as second transistors 200 11 , 200 12 , 200 13 , and 200 14, respectively .
  • the two first transistors 100 11 and 100 12 in the first unit 701 are connected in parallel, and are connected in series with another first transistor 100 13 to form a series unit, which is then connected in parallel with the last first transistor 100 14, which
  • the first source electrodes 101 are connected together to be coupled to the ground or an external negative power supply V SS , and the first drain electrodes 103 thereof are connected together as the output terminal V out to be electrically coupled to the second unit 702.
  • two second transistors 200 11 and 200 12 are connected in series to form a series unit, and then connected in parallel with another second transistor 200 13 to form a parallel unit.
  • the second source electrode 201 is connected together to couple an external positive power supply. V DD, then the unit is connected in parallel with the last second in series transistor 20014, a second drain electrode 203 20014 701 electrically coupled as the output terminal V out of the second unit and the first unit.
  • first transistor 100 and the second transistor 200 are shown as being directly adjacent to each other, the two may be spatially separated from each other (although still on the same first nitride semiconductor layer 122), with any number of intervening Devices, and/or one or more isolation structures may exist between the transistors 100 and 200.
  • the isolation structure may include an isolation trench and an isolation dielectric filling the trench.
  • various nitride integrated circuit structures 10 can be implemented in electronic devices including various other types of circuits.
  • Such circuits include, but are not limited to, AC-to-DC converters (rectifiers), DC-to-DC converters, DC-to-AC inverters, AC-to-AC converters, amplifiers, and various other types of circuits. Therefore, the examples given above are not meant to be limiting.
  • the nitride integrated circuit structure 10 may also include any combination of additional active and/or passive devices, including at least one first transistor 100 (for example, HEMT) and at least one second transistor 200 (for example, HHMT), diodes, resistors, and capacitors. , Inductance, etc., any combination of these, together with the conductive interconnections between various devices, can realize functions such as operation, amplification, transmission, conversion, and logic.
  • additional active and/or passive devices including at least one first transistor 100 (for example, HEMT) and at least one second transistor 200 (for example, HHMT), diodes, resistors, and capacitors. , Inductance, etc., any combination of these, together with the conductive interconnections between various devices, can realize functions such as operation, amplification, transmission, conversion, and logic.
  • HEMT and HHMT need to be formed on a substrate. It is preferable to realize both HEMT and HHMT. Of course, HEMT and HHMT can also be realized separately, and by forming trenches containing doped structures.
  • the channel structure realizes a normally-off transistor. Of course, in principle, it can also be realized by a doped nitride semiconductor gate electrode outside the channel structure. In this disclosure, the formation of a channel structure containing a doped structure is mainly described.
  • a substrate 120 is provided, and the substrate may be a silicon substrate with a (110) or (112) plane.
  • the substrate 120 may be a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, or the like.
  • a first insulating layer 802 is formed on the first surface 801 of the substrate 120.
  • the first insulating layer 802 is a SiO 2 layer formed by thermal oxidation or vapor deposition.
  • the thickness of the first insulating layer 802 is about 0.5 microns.
  • a photoresist layer is formed on the first insulating layer 802, and an opening that can expose the first insulating layer 802 underneath is formed on the photoresist layer.
  • the first insulating layer 802 and the substrate 120 below it are etched to form a plurality of vertical
  • the first trenches 803 are arranged at intervals, and the sidewalls of the first trenches have a hexagonal symmetrical lattice structure, such as a Si(111) plane.
  • a sacrificial layer 804 is formed by coplanar deposition.
  • the sacrificial layer 804 is a silicon nitride layer with a thickness of about 100 nanometers. It is understandable that the choice of the first insulating layer 802 and the sacrificial layer 804 only needs to have a high etching selection ratio between the two. For example, when the sacrificial layer 804 is etched, the etchant is When the sacrificial layer 804 is etched, the first insulating layer 802 is basically not etched, or it is etched very slowly.
  • dry etching is performed to remove the sacrificial layer 804 on the surface of the first insulating layer 802 and the sacrificial layer 804 on the bottom of the first trench 803, leaving the first Side surfaces of the trench 803, such as the first sacrificial layer 804 on the first side surface 805 and the second side surface 806.
  • a second insulating layer 807 (silicon dioxide layer) is formed on the bottom surface of the trench through an oxidation process, and the side surfaces of the first trench 803, such as the first side surface 805 and the first side surface 805
  • the two side surfaces 806 are not oxidized due to the remaining protection of the first sacrificial layer 804, and the second insulating layer 807 can avoid the incompatibility between gallium atoms and the silicon substrate during the subsequent growth of nitride semiconductors, and avoid melting back (melt-back) phenomenon.
  • the second insulating layer 807 can also effectively block the leakage current between the nitride semiconductor and the silicon substrate, and reduce the parasitic capacitance caused by the silicon substrate.
  • a thin third insulating layer 808 (silicon dioxide layer) is formed on the first and second side surfaces 805, 806 of the first trench 803, respectively.
  • the thickness of the layer 808 is set to be different from the thickness of the first and second insulating layers.
  • the thickness of the third insulating layer 808 satisfies that when the third insulating layer 808 is subsequently removed, there are still enough thick first and second insulating layers to protect the substrate.
  • a photoresist 809 is coated on the foregoing structure, and a photolithography pattern is formed between the first trenches 803 to expose the first trenches through an exposure and development process well known to those skilled in the art. 803 between the third insulating layer 808 and the first insulating layer 802.
  • parts of the third insulating layer 808 and the first insulating layer 802 on the side surfaces of the plurality of first trenches 803 that are exposed are removed.
  • the thickness is much greater than the thickness of the third insulating layer 808. Therefore, in the process of removing part of the third insulating layer 808, the exposed part of the first insulating layer 802 is only etched to a small thickness and will not be etched. Completely removed. Then, the remaining photoresist 809 is removed, so that a part of the side surfaces 805 and 806 of the substrate 120 are exposed in the first trench 803.
  • GaN cannot be directly deposited on the silicon substrate. It is usually necessary to deposit an AlN nucleation layer first, and then form the subsequent nitride semiconductor structure on this basis. Therefore, a single crystal AlN nucleation layer 121 is respectively formed on the exposed side surfaces 805 and 806 of the first trench 803, the growth direction of the single crystal AlN crystal is ⁇ 0001>, and the surface is the (0001) plane. . It should be pointed out that the selectivity of AlN is very low, and it is easy to generate polycrystalline or amorphous AlN on the insulating layer under normal process conditions, which is unfavorable for forming the desired structure. Therefore, it is necessary to separately remove AlN on the silicon dioxide layer after the nucleation layer is formed. Or, when the AlN nucleation layer is grown, a chlorine-containing gas is introduced to ensure that it grows only on the silicon substrate and not on the silicon dioxide layer.
  • the nucleation layer may also be GaN. At this time, it is easier to achieve nucleation only on the exposed substrate surface through process adjustment.
  • the first nitride layer semiconductor 122 is then grown outwards with the nucleation layer 121 as the core side. Due to the existence of the first trench 803, the first nitride semiconductor layer 122 is separated from the nucleation layer Start to grow epitaxially along the starting side of the first trench 803, the growth direction is ⁇ 0001>, and the ⁇ 0001> crystal direction is The crystal directions are opposite to each other.
  • the first nitride semiconductor layer 122 may also be grown outside the trench, and the first nitride semiconductor layer 122 outside the first trench 803 may be removed by planarization or etching technology.
  • the side epitaxy can effectively improve the quality of the nitride semiconductor crystal in the side epitaxial region, thereby improving the electrical performance of the device.
  • the first nitride semiconductor layer 122 outside the trench is removed. It can be understood that the growth of the first nitride semiconductor layer 122 outside the first trench 803 may not be removed, and a portion protruding from the first trench 803 may be formed.
  • the first nitride semiconductor layer 122 may be formed of GaN without dopants.
  • the first nitride semiconductor layer 122 may also include one or more nitride semiconductor sublayers, which may be formed of GaN, InN, AlN, AlGaN, InAlN, InGaN, AlGaInN or other suitable alloy materials.
  • the first nitride semiconductor layer 122 may have a thickness in the range of 1.0 micrometer to 10 micrometers. Alternatively, the first nitride semiconductor layer 122 may be thicker or thinner. It should be noted that the numerical range described in the present disclosure is only an example and not a limitation of the present disclosure.
  • a buffer layer may be deposited first, or of course, the buffer layer may not be formed.
  • At least one doped region 150 of the second conductivity type (for example, P-type) can also be formed on the first nitride semiconductor layer 122, which is in the projection direction of the ⁇ 0001> crystal direction with the first gate electrode 102. At least partially overlapped, and electrically coupled with the first conductivity type two-dimensional carrier gas, thereby substantially depleting the first conductivity type two-dimensional carrier gas, so that the first transistor 100 is normally off.
  • the doping concentration, size parameters, etc. of the doped region 150 of the second conductivity type can be set by device parameters, so as to substantially deplete the two-dimensional carrier gas of the first conductivity type, that is, to deplete 95%-100%.
  • the first conductivity type two-dimensional carrier gas The higher the concentration of the two-dimensional carrier gas of the first conductivity type, the higher the corresponding doping concentration.
  • At least one doped region 140 of the first conductivity type can also be formed in the first nitride semiconductor layer 122, which is in the ⁇ 0001(-)> crystal orientation with the aforementioned second gate electrode 202.
  • the projection direction at least partially overlaps, and is electrically coupled with the second conductivity type two-dimensional carrier gas, thereby substantially depleting the second conductivity type two-dimensional carrier gas to realize the second transistor 200 as a normally-off type.
  • the doping concentration and size parameters of the doped region 140 of the first conductivity type can be set by device parameters, so as to substantially deplete the two-dimensional carrier gas of the second conductivity type, that is, to deplete the two-dimensional carrier gas of the second conductivity type. Exhaust 95%-100% of the second conductivity type two-dimensional carrier gas. The higher the concentration of the second conductivity type two-dimensional carrier gas, the corresponding doping concentration can be increased accordingly.
  • At least one doped region 150 of the second conductivity type (e.g., P-type) and doped region 140 of the first conductivity type (e.g., N-type) can also be simultaneously formed on the first nitride semiconductor layer 122. It basically depletes the two-dimensional carrier gas near the first gate electrode 102 and the second gate electrode 202 respectively, so as to realize that the first transistor 100 and the second transistor 200 are normally off at the same time.
  • the silicon substrate 120 between the first nitride semiconductor layers 122 is etched to remove the first insulating layer 802 and part of the silicon substrate 120 to form a plurality of second ⁇ 810 ⁇ Groove 810.
  • a third insulating layer 808 may be preserved on the outer surface of the first nitride semiconductor layer 122 in addition to the nucleation layer.
  • the third insulating layer 808 can be removed, thereby exposing ⁇ 0001> and the first nitride semiconductor layer 122
  • the side surface 180 of the first nitride semiconductor layer 122 in the ⁇ 0001> direction is the first region 124 of the first nitride semiconductor layer 122, and the side surface 180 of the first nitride semiconductor layer 122
  • the side surface 190 in the direction is the second region 125 of the first nitride semiconductor layer 122.
  • the third insulating layer 808 may also be retained first and removed in a later step, which will not be repeated here.
  • a fourth insulating layer 811 is formed on the etched substrate 120 to fill the second trench 810, and is planarized to isolate the exposed silicon substrate.
  • the four insulating layer 811 may be a silicon dioxide layer for example.
  • a portion of the fourth insulating layer 811 on the bottom and sidewalls of the second trench 810 is etched away to expose a portion of the first region 124 of the first nitride semiconductor layer 122 And the second area 125.
  • a second nitride semiconductor layer 123 is then formed on the exposed first region 124 and the second region 125 of the first nitride semiconductor layer 122, and the first nitride semiconductor layer 122 is The region 124 and the second region 125 respectively form a laminated structure.
  • the second nitride semiconductor layer 123 is a barrier layer or a carrier supply layer, and may include one or more nitride semiconductor sublayers.
  • the second nitride semiconductor layer 123 may be formed of AlGaN, InAlN, InGaN, AlN or other suitable alloy materials.
  • the second nitride semiconductor layer 123 may be formed of an AlGaN alloy having an atomic percentage of aluminum in the range of about 20% to 30%. Alternatively, the percentage of aluminum can be lower or higher.
  • the first nitride semiconductor layer 122 has a first band gap
  • the second nitride semiconductor layer 123 has a second band gap
  • the second band gap is larger than the first band gap.
  • the first nitride semiconductor layer 122 such as a GaN layer may have a band gap of about 3.4 eV
  • the second nitride semiconductor layer 123 such as an AlGaN layer may have a band gap of about 4.0 eV.
  • the band gap of the second nitride semiconductor layer 123 may be higher or lower. In any case, the band gaps of the first nitride semiconductor layer 122 and the second nitride semiconductor layer 123 are different from each other.
  • the first nitride semiconductor layer 122 and the second nitride semiconductor layer 123 lack inversion symmetry, they are aligned with the ⁇ 0001> crystal orientation or Crystal orientation perpendicular to the crystal plane (0001) plane and the (0001 -) plane is a polar plane, the polarization is formed in the transitional region between the contact junction, respectively.
  • the first region 124 of the first nitride semiconductor layer 122 and the second nitride semiconductor layer 123 have a first polarization junction 126 at the contact interface to form a first nitride semiconductor structure;
  • the second region 125 and the second nitride semiconductor layer 123 have a second polarization junction 127 at the contact interface to form a second nitride semiconductor structure.
  • the first nitride semiconductor structure includes a stacked structure of the first region 124 of the first nitride semiconductor layer 122 and the second nitride semiconductor layer 123, and the stacked structure may be a stacked structure of multiple sub-layers.
  • the second nitride semiconductor structure includes a stacked structure of the second region 125 of the first nitride semiconductor layer 122 and the second nitride semiconductor layer 123, and the stacked structure may be a stacked structure of multiple sub-layers.
  • the stacked structure may be, for example, a stacked structure of the first sublayer/second sublayer of the first nitride semiconductor layer 122 and the first sublayer/second sublayer of the second nitride semiconductor layer 123.
  • the first nitride semiconductor structure and the second nitride semiconductor structure are formed at the same time.
  • the first polarization junction 126 and the second polarization junction 127 have different crystal orientations, for example, the former is a ⁇ 0001> crystal orientation, and the latter is Crystal orientation, and the first polarization junction 126 and the second polarization junction 127 have a vertical interface.
  • the first conductivity type two-dimensional carrier gas and the second conductivity type two-dimensional carrier gas respectively form a carrier channel in a direction parallel to the first polarization junction 126 and the second polarization junction 127.
  • a fifth insulating layer 812 is formed on the foregoing structure to fill the second trench 810, and the fifth insulating layer 812 is lithographically etched to form a source electrode, a drain electrode, and a gate electrode window.
  • the fifth insulating layer 812 is lithographically etched to form a source electrode, a drain electrode, and a gate electrode window.
  • FIG. 2 using techniques known to those skilled in the art, such as electron beam evaporation technology, evaporate four layers of Ti, Al, Ti, and TiN in the source electrode window, the drain electrode window, and the gate electrode window.
  • the thickness may be 20 nm, 130nm, 25nm, 70nm, and after stripping and annealing, an ohmic electrode in ohmic contact with the two-dimensional carrier gas and a gate electrode insulated or in Schottky contact with the second nitride semiconductor layer 123 are formed. That is, the source electrodes 101 and 201, the drain electrodes 103 and 203, and the gate electrodes 102 and 202 of the HEMT100 and HHMT200 are formed. Specifically, the first source electrode 101 and the first drain electrode 103 are oppositely distributed on both sides of the first gate electrode 102, and are gas-coupled with the first conductivity type two-dimensional carrier gas to form at least one first transistor 100. The second source electrode 201 and the second drain electrode 203 are oppositely distributed on both sides of the second gate electrode 202, and are gas-coupled with two-dimensional carriers of the second conductivity type to form at least one second transistor 200.
  • body electrodes 104 and 204 can be formed on the aforementioned structure, which are respectively connected with the doped region 150 of the second conductivity type (for example, P-type) and the The doped regions 140 of the first conductivity type (for example, N-type) are electrically connected.
  • the first transistor 100 further includes a first body electrode 104, which is disposed on the side surface of the first nitride semiconductor structure opposite to the first gate electrode 102;
  • the second transistor 200 further includes a second body electrode 204, which is disposed on the side surface of the second nitride semiconductor structure opposite to the second gate electrode 202.
  • an oxidation process may be used to form a sixth insulating layer 811' instead of the fourth insulating layer 811 to isolate the silicon substrate 120 in the second trench.
  • the structure obtained after etching a part of the silicon substrate, as shown in FIG. 20, is introduced as a basis, and it is renumbered as FIG. 26.
  • the following only introduces the structure or method that is different from the foregoing content, and the content with the same structure and method will not be described in detail.
  • the structure shown in FIG. 26 is oxidized, and a sixth insulating layer 811' is formed on the side surfaces of the silicon substrate 120 and the first nitride semiconductor layer 122 exposed by the second trench 810. . Since the nitride semiconductor is not easily oxidized, the sixth insulating layer 811' formed on the surface of the first nitride semiconductor layer 122 is relatively thin.
  • the sixth insulating layer 811' surrounding the side surface of the first nitride semiconductor layer 122 is removed to expose a portion of the first region 124 and the second region 125 of the first nitride semiconductor layer 122.
  • the third insulating layer 808 on the side surface of the first nitride semiconductor layer 122 may also be retained in the process of forming the structure of FIG. 20(26).
  • the third insulating layer can protect the side surface of the first nitride semiconductor layer 122 during the oxidation process shown in FIG. 27 and be removed in the subsequent step shown in FIG. 28.
  • a second nitride semiconductor layer 123 is formed on the exposed first region 124 and the second region 125 of the first nitride semiconductor layer 122, and the first nitride semiconductor layer 122 is The region 124 and the second region 125 respectively form a laminated structure.
  • the material of the second nitride semiconductor layer 123 is the same as the foregoing embodiment.
  • the stacked structure may be, for example, a stacked structure of the first sublayer/second sublayer of the first nitride semiconductor layer 122 and the first sublayer/second sublayer of the second nitride semiconductor layer 123.
  • the first nitride semiconductor structure and the second nitride semiconductor structure are formed at the same time.
  • a source electrode, a drain electrode, and a gate electrode window are formed on the aforementioned structure.
  • electron beam evaporation technology evaporates four layers of Ti, Al, Ti, and TiN on the source electrode window and the drain electrode window.
  • an ohmic electrode in ohmic contact with the two-dimensional carrier gas is formed, and TiN metal is evaporated in the gate electrode window to form an insulating or Schottky-contact gate electrode with the second nitride semiconductor layer 123, that is, forming The source electrodes 101 and 201, the drain electrodes 103 and 203, and the gate electrodes 102 and 202 of the HEMT100 and HHMT200.
  • These electrode structures can also be formed by etching.
  • body electrodes 104 and 204 can also be formed on the aforementioned structure, which are respectively connected to the doped region 150 of the second conductivity type (for example, P-type) and the first conductivity type.
  • Type (for example, N-type) doped regions 140 are electrically connected.
  • the two-dimensional carrier gas between different transistors namely 2DEG and 2DHG
  • the two-dimensional carrier gas between different transistors is removed to prevent electrical connection between different transistors due to 2DEG and 2DHG.
  • a technique known in the art such as inductively coupled plasma etching (ie, ICP etching)
  • trenches are formed between different transistors, and the seventh insulating medium 812 is filled to form a trench isolation structure.
  • FIG. 33 the description is based on the structure of FIG. 18 formed by the foregoing method, and is renumbered as FIG. 33.
  • the first nitride semiconductor layer 122 is grown outwardly with the nucleation layer 121 as the core side. Due to the existence of the first trench 803, the first nitride semiconductor layer 122 is grown from The nucleation layer starts to grow epitaxially along the starting side of the first trench 803, the first nitride semiconductor layer 122 may also grow outside the trench, and the first trench is removed by planarization or etching techniques. The first nitride semiconductor layer 122 outside the trench 803.
  • the material of the first nitride layer semiconductor 122 is the same as the aforementioned structure.
  • a plurality of doped regions 140 of the first conductivity type (for example, N-type) and a plurality of second conductivity are alternately formed in the first nitride semiconductor layer 122.
  • Type (for example, P-type) doped region 150 is alternately formed in the first nitride semiconductor layer 122.
  • the silicon substrate 120 between the first nitride semiconductor layers 122 is etched to remove the first insulating layer 802 and part of the silicon substrate 120 to form a second trench 810, thereby exposing ⁇ 0001> and ⁇ 0001> of the first nitride semiconductor layer 122
  • the side surface 180 of the first nitride semiconductor layer 122 in the ⁇ 0001> direction is the first region 124 of the first nitride semiconductor layer 122, and the side surface 180 of the first nitride semiconductor layer 122
  • the side surface 190 in the direction is the second region 125 of the first nitride semiconductor layer 122.
  • a fourth insulating layer 811 is formed on the etched substrate 120 to fill the second trench 810, and is planarized to isolate the exposed silicon substrate.
  • the four insulating layer 811 may be a silicon dioxide layer for example.
  • a portion of the fourth insulating layer 811 on the bottom and sidewalls of the second trench 810 is etched away to expose a portion of the first region 124 of the first nitride semiconductor layer 122 And the second area 125.
  • a second nitride semiconductor layer 123 is then formed on the exposed first region 124 and the second region 125 of the first nitride semiconductor layer 122, and the first nitride semiconductor layer 122 is The region 124 and the second region 125 respectively form a laminated structure.
  • the material of the second nitride semiconductor layer 123 is the same as the material of the aforementioned structure.
  • the stacked structure may be, for example, a stacked structure of the first sublayer/second sublayer of the first nitride semiconductor layer 122 and the first sublayer/second sublayer of the second nitride semiconductor layer 123.
  • the first nitride semiconductor structure and the second nitride semiconductor structure are formed at the same time.
  • a fifth insulating layer 812 is formed on the aforementioned structure to fill the second trench 810, and the fifth insulating layer 812 is photoetched to form a source electrode, a drain electrode, and a gate electrode. window.
  • electron beam evaporation technology evaporates the four layers of Ti, Al, Ti, and TiN in the source electrode window and the drain electrode window.
  • the thickness can be 20nm, 130nm, 25nm, 70nm, and the After annealing, an ohmic electrode in ohmic contact with the two-dimensional carrier gas is formed, and a gate electrode insulated or in Schottky contact with the second nitride semiconductor layer 123 is formed in the gate electrode window, that is, the HEMT 100 is formed. And the source electrode 101/201, drain electrode 103/203, and gate electrode 102/202 of HHMT200. These electrode structures can also be formed by etching.
  • the first source electrode 101 and the first drain electrode 103 are oppositely distributed on both sides of the first gate electrode 101, and are gas-coupled with the first conductivity type two-dimensional carrier gas to form at least one first transistor 100.
  • the doped region 150 of the second conductivity type for example, P-type
  • the doped region 140 of the first conductivity type for example, N-type
  • the second source electrode 201 and the second drain electrode 203 are oppositely distributed on both sides of the second gate electrode 202, and are gas-coupled with the second conductivity type two-dimensional carrier gas to form at least one second transistor 200.
  • the doped region 140 of the first conductivity type for example, N-type
  • the doped region 150 is electrically coupled with the second source electrode 201 and the second drain electrode 203, respectively.
  • body electrodes 104 and 204 can also be formed on the aforementioned structure, which are respectively connected with the doped region 150 of the second conductivity type (such as P-type) and the The doped regions 140 of the first conductivity type (for example, N-type) are electrically connected.
  • the first transistor 100 further includes a first body electrode 104, which is disposed on a side surface of the first nitride semiconductor structure opposite to the first gate electrode 102.
  • the second transistor 200 further includes a second body electrode 204, which is disposed on the side surface of the second nitride semiconductor structure opposite to the second gate electrode 202.
  • a trench isolation structure can be formed between different transistors.
  • the integrated circuit structure of the present disclosure is a complementary circuit of HEMT and HHMT based on III-nitride semiconductors, which can realize HEMT and HHMT on the same substrate.
  • Integrated, and HEMT and HHMT each have a polarization junction with a vertical interface.
  • the polarization junctions of the two have different crystal orientations.
  • the two-dimensional carrier gas forms a carrier channel in the direction parallel to the polarization junction, and By burying the doped region, the corresponding channel carriers are almost depleted.
  • the present disclosure utilizes the polarization characteristics of III-nitride semiconductors to creatively realize the generation of complementary two-dimensional carrier gas at the polarization junction interface of different crystal directions, so that the HEMT and HHMT of III-nitride semiconductors are on the same substrate. Integration to form a complementary integrated circuit structure. Compared with traditional silicon-based complementary circuits such as CMOS, the 2DEG and 2DHG of the integrated circuit structure of the present disclosure have advantages in terms of carrier mobility, on-current density, and switching speed, as well as on-resistance and parasitic inductance. Become lower, and the device is in the normally-off state, so as to achieve higher on-current density, higher integration, and lower energy consumption technical effects.
  • the integrated circuit structure of the present disclosure can be used as the core part of electronic equipment and widely used in analog or digital integration such as inverters, amplifiers, NAND gates, and NOR gates. In the circuit.
  • the manufacturing method of the integrated circuit structure of the present disclosure can achieve a higher channel density per unit area; it is suitable for a planarization process and is beneficial to improve the integration of transistors. Density; the process of the integrated circuit structure is relatively simple, which can effectively reduce production costs.
  • III-nitride semiconductor integrated circuit structure and manufacturing method provided by the present disclosure are simple in process, low in cost, achieve higher integration per unit area, and have high-performance complementary types such as high withstand voltage, high power, and low on-resistance.
  • Semiconductor integrated circuit structure is simple in process, low in cost, achieve higher integration per unit area, and have high-performance complementary types such as high withstand voltage, high power, and low on-resistance.

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Abstract

本公开提供一种III族氮化物半导体集成电路结构、制造方法及其应用。所述集成电路结构是基于III族氮化物半导体的HEMT与HHMT的互补型电路，能在同一个衬底上实现HEMT与HHMT的集成，且HEMT与HHMT分别具有垂直界面的极化结，两者的极化结的晶向不同，二维载流子气在平行于所述极化结方向上形成载流子沟道，并借助掩埋掺杂区域而几乎耗尽对应的沟道载流子。与传统的硅基CMOS相比，本公开的集成电路结构在载流子迁移率、导通电流密度、开关速度等方面都具有优势，能够实现低导通电阻、低的寄生电感和器件的常关状态，能达到更高的导通电流密度、更高的集成度和能耗小的技术效果。

Description

一种III族氮化物半导体集成电路结构、制造方法及其应用
相关申请的交叉引用
本公开要求于2020年4月29日提交中国专利局的申请号为202010361160.4、名称为“一种III族氮化物半导体集成电路结构、制造方法及其应用”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开内容涉及半导体集成电路领域，更具体而言，涉及一种III族氮化物半导体集成电路结构、制造方法及其应用。
背景技术
宽禁带半导体比如III族氮化物半导体因临界击穿电场高、电子饱和速率大、热导率高、抗辐射能力强等卓越性能，已成为半导体产业界的研究热点。近年来，III族氮化物半导体和器件在射频/微波、移动通信和半导体照明、功率集成电路设计等领域大放异彩。尽管III族氮化物半导体分立器件展现了前所未有的开关速度和工作频率，但在实际电路应用中，芯片间的寄生电感会严重限制III族氮化物半导体分立器件的开关速度。降低寄生电感的一种行之有效的方法是研究并开发利用III族氮化物半导体的集成电路。
实现III族氮化物半导体集成电路的关键在于突破利用III族氮化物半导体的互补型电路技术。以传统的硅基集成电路为例，其逻辑电路的基础结构是以互补型金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)构成的。CMOS是由P沟道MOS器件和N沟道MOS器件共同构成的互补型集成电路。对于III族氮化物半导体材料来说，基于二维电子气(Two-Dimensional Electron Gas，2DEG)的N沟道晶体管(High Electron Mobility Transistor，HEMT)发展较为成熟，而对于P型AlGaN/GaN结构的研究较少，具有很多挑战，比如如何克服源区、漏区的P型掺杂困难，实现P沟道器件和N沟道器件的单片集成等。因此，当前互补型高迁移率晶体管(Complementary High Mobility Transistor，CHMT)技术的难点在于研制P沟道晶体管(High Hole Mobility Transistor，HHMT)，即以异质材料界面处的二维空穴气(Two-Dimensional Hole Gas，2DHG)作为P沟道层来制作P沟道晶体管，并与N沟道晶体管实现单片集成。
另外，也仍存在其它技术难点需要攻克。由于III族氮化物半导体异质结具有强极化效应，在异质结界面处存在较高浓度的二维载流子气，使用这种二维载流子气制作的高迁移率晶体管通常是常开型的。然而，在实际电路应用中，为节省功率及控制方便，通常需要常关型的晶体管。因此，具有高耐受电压、高功率和低导通电阻等高性能的增强型高迁移率晶体管的实现一直是业界重点关注的问题之一。
发明内容
鉴于上述情况，本公开提供一种互补型的III族氮化物半导体集成电路结构及其制造方法。
在下文中将给出关于本公开内容的简要概述，以便提供关于本公开内容某些方面的基本理解。应当理解，此概述并不是关于本公开内容的穷举性概述。它并不是意图确定本公开内容的关键或重要部分，也不是意图限定本公开内容的范围。其目的仅仅是以简化的形式给出某些概念，以此作为稍后论述的更详细描述的前序。
根据本公开内容的一方面，本申请提供一种集成电路结构，包括：
至少一个第一晶体管，包括：
具有第一极化结的第一氮化物半导体结构，其具有第一导电类型二维载流子气；
第一栅电极，其设置在所述第一氮化物半导体结构上；
第一源电极和第一漏电极，其相对分布在所述第一栅电极的两侧，并与所述第一导电类型二维载流子气耦合；
至少一个第二晶体管，包括：
具有第二极化结的第二氮化物半导体结构，其具有第二导电类型二维载流子气；
第二栅电极，其设置在所述第二氮化物半导体结构上；
第二源电极和第二漏电极，其相对分布在第二栅电极的两侧，并与所述第二导电类型二维载流子气电耦合；
其中，所述第一极化结与所述第二极化结具有不同的晶向；
其中，所述第一导电类型二维载流子气与所述第二导电类型二维载流子气的导电类型不同；
其中，所述第一导电类型二维载流子气与所述第二导电类型二维载流子气分别在平行于所述第一极化结与所述第二极化结方向上形成载流子沟道。
可选地，所述第一氮化物半导体结构和第二氮化物半导体结构外延生长在相同的衬底上。
可选地，所述第一极化结和所述第二极化结分别具有垂直界面。
可选地，所述第一氮化物半导体结构的所述第一极化结的晶向是<0001>，其表面是(0001)面。
可选地，所述第二氮化物半导体结构的所述第二极化结的晶向是
Figure PCTCN2021078955-appb-000001
表面是(0001 -)面。
可选地，所述衬底是硅、蓝宝石、碳化硅或氮化镓。
可选地，所述第一导电类型二维载流子气是二维电子气。
可选地，所述第二导电类型二维载流子气是二维空穴气。
可选地，所述第一氮化物半导体结构进一步包括第一掺杂结构，该第一掺杂结构与所述第一导电类型二维载流子气电耦合。
可选地，所述第二氮化物半导体结构进一步包括第二掺杂结构，该第二掺杂结构与所述第二导电类型二维载流子气电耦合。
可选地，所述第一掺杂结构包括至少一个第二导电类型掺杂区域，其与所述第一栅电极在所述晶向投影方向上至少部分重叠。
可选地，所述第一掺杂结构进一步包括多个第一导电类型掺杂区域，其与所述第一源电极和所述第一漏电极电耦合。
可选地，所述第二掺杂结构包括至少一个第一导电类型掺杂区域，其与所述第二栅电极在所述晶向投影方向上至少部分重叠。
可选地，所述第二掺杂结构进一步包括多个第二导电类型掺杂区域，其与所述第二源电极和所述第二漏电极电耦合。
可选地，所述第一晶体管通过在所述晶向投影方向上与所述第一栅电极至少部分重叠的第二导电类型掺杂区域实现常关型。
可选地，所述第二晶体管通过在所述晶向投影方向上与所述第二栅电极至少部分重叠的第一导电类型掺杂区域实现常关型。
可选地，所述第一氮化物半导体结构进一步包括第一氮化物半导体层的第一区域和第二氮化物半导体层的叠层结构，其中所述第一氮化物半导体层和所述第二氮化物半导体层的禁带宽带不同，所述载流子沟道形成在所述第一氮化物半导体层的第一区域和所述第二氮化物半导体层的界面上。
可选地，所述第二氮化物半导体结构进一步包括第一氮化物半导体层的第二区域和第二氮化物半导体层的叠层结构，其中所述第一氮化物半导体层和所述第二氮化物半导体层的禁带宽带不同，所述载流子沟道形成在所述第一氮化物半导体层的第二区域和所述第二氮化物半导体层的界面上。
可选地，所述第一晶体管与所述第二晶体管是互补型且串联连接，其中所述第一栅电极与所述第二栅电极连接在一起作为输入端，所述第一源电极或所述第二源电极任一个耦合接地或外部负电源V SS，所述第二源电极或所述第一源电极任一个耦合到外部正电源V DD，所述第一漏电极与所述第二漏电极连接在一起作为输出端。
可选地，至少两个所述第一晶体管串联连接或并联连接作为第一单元，至少两个所述第二晶体管并联连接或串联连接作为第二单元，其中所述第一单元中的串联连接或并联连接与第二单元中的并联连接或串联连接是对应的，并且所述第一单元与所述第二单元串联连接在一起并作为输出端，所述第一单元中的所述第一晶体管与所述第二单元中的所述第二晶体管是互补配对的，且互补配对的晶体管的所述第 一栅电极与所述第二栅电极连接在一起分别作为输入端。
可选地，所述第一单元中的至少两个第一晶体管串联连接时，所述第一源电极的任一个耦合接地或外部负电源V SS，所述第一漏电极的任一个作为输出端与第二单元耦合，其余的所述第一源电极与所述第一漏电极依次串联连接。
可选地，述第二单元中的至少两个第二晶体管并联连接时，所述第一源电极连接在一起耦合外部正电源V DD，所述第一漏电极连接在一起作为输出端与第一单元耦合。
可选地，所述第一单元中的至少两个第一晶体管并联连接时，所述第一源电极连接在一起耦合接地或外部负电源V SS，所述第一漏电极连接在一起作为输出端与第二单元耦合。
可选地，所述第二单元中的至少两个第二晶体管串联连接时，所述第一源电极的任一个耦合外部正电源V DD，所述第一漏电极的任一个作为输出端与第一单元耦合，其余所述第一源电极与其余所述第一漏电极依次串联连接。
可选地，所述第一单元中的所述第一晶体管可以进行任意数量的串联连接或并联连接，所述第二单元中的与所述第一单元中的所述第一晶体管互补配对的所述第二晶体管可以进行对应数量的并联连接或串联连接。
可选地，所述的集成电路结构还包括成核层。
可选地，所述串联连接或并联连接中的所述源电极/漏电极可以耦合接地或外部负电源V SS。
可选地，所述串联连接或并联连接中的所述源电极/漏电极可以耦合外部正电源V DD。
可选地，还包括第一体电极，其与所述第二导电类型掺杂区域电连接。
可选地，还包括第二体电极，其与所述第一导电类型掺杂区域电连接。
根据本公开内容的另一方面，提供了一种电子装置。
根据本公开内容的另一方面，本申请提供一种集成电路结构制造方法，包括以下步骤：
形成至少一个第一晶体管，其包括：
形成具有第一极化结的第一氮化物半导体结构，其具有第一导电类型二维载流子气；
形成至少一个第二晶体管，其包括：
形成具有第二极化结的第二氮化物半导体结构，其具有第二导电类型二维载流子气；
其中，所述第一氮化物半导体结构和所述第二氮化物半导体结构是同时形成的；
其中，所述第一极化结与所述第二极化结具有不同的晶向，且所述极化结分别具有垂直界面；
其中，所述第一导电类型二维载流子气与所述第二导电类型二维载流子气的导电类型不同；
其中，所述第一导电类型二维载流子气与所述第二导电类型二维载流子气分别在平行于所述第一极化结与所述第二极化结方向上形成载流子沟道。
可选地，形成至少一个第一晶体管的步骤进一步包括：
形成第一栅电极，其设置在所述第一氮化物半导体结构上；
分别形成第一源电极和第一漏电极，其相对分布在所述第一栅电极的两侧，并与所述第一导电类型二维载流子气耦合。
可选地，形成至少一个第二晶体管的步骤进一步包括：
形成第二栅电极，其设置在所述第二氮化物半导体结构上；
分别形成第二源电极和第二漏电极，其相对分布在第二栅电极的两侧，并与所述第二导电类型二维载流子气电耦合。
可选地，提供一衬底，在所述衬底上形成所述第一氮化物半导体结构和第二氮化物半导体结构。
可选地，所述第一氮化物半导体结构和第二氮化物半导体结构分别包括第一氮化物半导体层的不同区域和第二氮化物半导体层的叠层结构。
可选地，在所述衬底上形成所述第一氮化物半导体结构和第二氮化物半导体结构的步骤进一步包括：
在衬底上形成多个第一沟槽，在所述第一沟槽侧壁上侧向外延生长所述第一氮化物半导体层以填充所述第一沟槽；
去除所述第一氮化物半导体层之间的部分衬底以形成多个第二沟槽；
在所述第二沟槽内分别在所述第一氮化物半导体层不同区域的侧面外延生长第二氮化物半导体层。
可选地，形成所述晶体管的步骤进一步包括：
在所述第二沟槽内分别在所述第一氮化物半导体结构和第二氮化物半导体结构上形成一个或多个第一栅电极、第一源电极和第一漏电极，以及一个或多个第二栅电极、第二源电极和第二漏电极。
可选地，在晶向<0001>方向上形成所述第一氮化物半导体结构的所述第一极化结，其具有(0001)晶面。
可选地，在晶向
Figure PCTCN2021078955-appb-000002
方向上形成所述第二氮化物半导体结构的所述第二极化结，其具有(0001 -)晶面。
可选地，所述衬底是硅、蓝宝石、碳化硅或氮化镓。
可选地，所述第一导电类型二维载流子气是二维电子气，所述第二导电类型二维载流子气是二维空穴气。
可选地，形成具有极化结的第一氮化物半导体结构的步骤进一步包括：
形成第一掺杂结构，该第一掺杂结构与所述第一导电类型二维载流子气电耦合。
可选地，形成具有极化结的第二氮化物半导体结构的步骤进一步包括：
形成第二掺杂结构，该第二掺杂结构与所述第二导电类型二维载流子气电耦合。
可选地，所述第一掺杂结构包括至少一个第二导电类型掺杂区域，其与所述第一栅电极在所述晶向投影方向上至少部分重叠。
可选地，所述第一掺杂结构进一步包括多个第一导电类型掺杂区域，其与所述第一源电极和所述第一漏电极电耦合。
可选地，所述第二掺杂结构包括至少一个第一导电类型掺杂区域，其与所述第二栅电极在所述晶向投影方向上至少部分重叠。
可选地，所述第二掺杂结构进一步包括多个第二导电类型掺杂区域，其与所述第二源电极和所述第二漏电极电耦合。
可选地，进一步形成第一体电极，其与所述第二导电类型掺杂区域电连接。
可选地，进一步形成第二体电极，其与所述第一导电类型掺杂区域电连接。
可选地，进一步去除所述第一晶体管之间和/或所述第二晶体管之间的所述二维载流子气，并填充绝缘介质。
可选地，形成具有极化结的第一氮化物半导体结构的步骤进一步包括：
形成第一氮化物半导体层的第一区域和第二氮化物半导体层的叠层结构；
其中所述第一氮化物半导体层和所述第二氮化物半导体层的禁带宽带不同，所述载流子沟道形成在所述第一氮化物半导体层的第一区域和所述第二氮化物半导体层的界面上。
可选地，形成具有极化结的第二氮化物半导体结构的步骤进一步包括：
形成第一氮化物半导体层的第二区域和第二氮化物半导体层的叠层结构；
其中所述第一氮化物半导体层和所述第二氮化物半导体层的禁带宽带不同，所述载流子沟道形成在所述第一氮化物半导体层的第二区域和所述第二氮化物半导体层的界面上。
一种III族氮化物半导体集成电路结构，包括：
至少一个第一晶体管，包括：
具有第一极化结的第一氮化物半导体结构，其具有第一导电类型二维载流子气；
第一栅电极，其设置在所述第一氮化物半导体结构上；
第一源电极和第一漏电极，其相对分布在所述第一栅电极的两侧，并与所述第一导电类型二维载流子气耦合；
至少一个第二晶体管，包括：
具有第二极化结的第二氮化物半导体结构，其具有第二导电类型二维载流子气；
第二栅电极，其设置在所述第二氮化物半导体结构上；
第二源电极和第二漏电极，其相对分布在第二栅电极的两侧，并与所述第二导电类型二维载流子气电耦合；
其中，所述第一极化结与所述第二极化结具有不同的晶向；
其中，所述第一导电类型二维载流子气与所述第二导电类型二维载流子气的导电类型不同；
其中，所述第一导电类型二维载流子气与所述第二导电类型二维载流子气分别在平行于所述 第一极化结与所述第二极化结方向上形成载流子沟道。
附图说明
参照附图下面说明本公开内容的具体内容，这将有助于更加容易地理解本公开内容的以上和其他目的、特点和优点。附图只是为了示出本公开内容的原理。在附图中不必依照比例绘制出单元的尺寸和相对位置。在附图中：
图1是一种高电子迁移率晶体管及高空穴迁移率晶体管的电路符号的示意图；
图2是一种III族氮化物半导体的集成电路结构10的平面图和A-A向剖视图；
图3是可选的III族氮化物半导体的集成电路结构10′的平面图和A-A向剖视图；
图4是可选的具有附加电连接和电路元件的反相器电路结构的示意图；
图5是可选的具有附加电连接和电路元件的与非门电路结构的示意图；
图6是可选的具有附加电连接和电路元件的或非门电路结构的示意图；
图7是可选的具有附加电连接和电路元件的复杂CMOS电路结构的示意图；
图8-40是一种氮化物集成电路结构的制造方法的示意图。
图41是一种氮化物集成电路结构的制造方法的示意性框图。
具体实施方式
在下文中将结合附图对本公开内容的示例性公开内容进行描述。为了清楚和简明起见，在说明书中并未描述实现本公开内容的所有特征。在此，还需要说明的是，为了避免因不必要的细节而模糊了本公开内容，在附图中仅仅示出了与根据本公开内容的方案密切相关的器件结构，而省略了与本公开内容关系不大的其他细节。在附图中，同样的附图标记贯穿不同的附图指示相应的部分。同时，在本公开的描述中，术语“第一”、“第二”等仅用于区分描述，而不能理解为指示或暗示相对重要性，也不暗示序列或顺序。
应理解的是，本公开内容并不会由于如下参照附图的描述而只限于所描述的实施形式。本文中，词语“示例性”、“一种”和“可选地”等相近含义的用语意指用作例子、实例或说明。本文中，所描述的任何可作为“示例”的例子或实施例不一定被解释为比其它实施例优先或有利。在可行的情况下，不同实施方案之间的特征可替换或借用、以及在一个实施方案中可省略一个或多个特征。
具体地，如图41所示，本公开内容的集成电路结构是基于III族氮化物半导体的互补型集成电路，包括：至少一个第一晶体管和至少一个第二晶体管。第一晶体管包括：具有第一极化结的第一氮化物半导体结构，其具有第一导电类型二维载流子气；第一栅电极，其设置在所述第一氮化物半导体结构上；第一源电极和第一漏电极，其相对分布在所述第一栅电极的两侧，并与所述第一导电类型二维载流子气耦合。第二晶体管包括：具有第二极化结的第二氮化物半导体结构，其具有第二导电类型二维载流子气；第二栅电极，其设置在所述第二氮化物半导体结构上；第二源电极和第二漏电极，其相对分布在第二栅电极的两侧，并与所述第二导电类型二维载流子气电耦合。所述第一极化结与所述第二极化结具有不同的晶向；所述第一导电类型二维载流子气与所述第二导电类型二维载流子气的导电类型不同；所述第一导电类型二维载流子气与所述第二导电类型二维载流子气分别在平行于所述第一极化结与所述第二极化结方向上形成载流子沟道。
本公开内容的集成电路结构可广泛用于具有反相器、放大器、逆变器、与非门、或非门等模拟和/或数字集成电路的电子设备中，以实现运算、放大、传输、变换/转换、逻辑等功能。
参照图1-图7来描述根据本公开的一种集成电路结构。图1示意的是高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)及高空穴迁移率晶体管(High Hole Mobility Transistor，HHMT)的电路符号。HEMT 100包括第一源电极101、第一漏电极103、第一栅电极102和第一体电极104，其中在第一源电极101和第一漏电极103之间是二维电子气(Two-Dimensional Electron Gas，2DEG)沟道105，实心圆球代表电子。HHMT 200包括第二源电极201、第二漏电极203、第二栅电极202和第二体电极204，其中在第二源电极201和第二漏电极203之间是二维空穴气(Two-Dimensional Hole Gas，2DHG)沟道205，空心圆球代表空穴。第一栅电极102和第二栅电极202分别控制HEMT 100和HHMT 200导 电沟道的导通和关断，第一体电极104和第二体电极204分别控制HEMT100和HHMT200的阈值电压。在本公开中，HEMT100可作为第一晶体管，HHMT200可作为第二晶体管，反之亦可。
图2示出了一种III族氮化物半导体的集成电路结构10的平面图和A-A向剖视图。根据附图2，集成电路结构10包括成核层121、第一氮化物半导体层122、第二氮化物半导体层123和多个电极101、102、103、104、201、202、203、204。正如下面将要更详细描述的，集成电路结构10包括形成在第一氮化物半导体层122的第一区域124内或其上的第一导电类型(例如N-沟道或N-类型)的至少一个第一晶体管100，以及形成在第一氮化物半导体层122的第二区域125内或其上的第二导电类型(例如P-沟道或P-类型)的至少一个第二晶体管200。由于晶体管100、200在相同半导体层(即第一氮化物半导体层122)上形成，所以集成电路结构10和晶体管100、200都被认为是单片集成的。此外，由于晶体管100、200是不同导电类型，所以集成电路结构10可被认为是互补型集成电路。再者，由于在其上形成晶体管100、200的基层是第一氮化物半导体层122，所以集成电路结构10在本公开中可被称为互补型氮化物集成电路结构。
示例性的，成核层121可以是AlN层。可选地，也可没有成核层。第一氮化物半导体层122可由无掺杂剂的GaN形成。可选地，第一氮化物半导体层122也可包括一个或多个氮化物半导体子层，可由选自于GaN、InN、AlN、AlGaN、InAlN、InGaN、AlGaInN或其它合适的合金材料形成。第一氮化物半导体层122可以具有1微米至10微米范围内的厚度。可选地，第一氮化物半导体层122可以更厚或更薄。应注意，本公开中所述的数值范围仅作为示例而非对本公开的限制。另外，第一氮化物半导体层122的第一区域124是远离成核层121的区域，第一氮化物半导体层122的第二区域125是与成核层121相对或相邻的区域。所述第一区域124和所述第二区域125的表面是不同的晶面，例如前者是(0001)面，后者是(0001 -)面。换句话说，第一氮化物半导体层122的第一区域124与第二区域125的晶向不同，例如前者是<0001>晶向，后者是
Figure PCTCN2021078955-appb-000003
晶向，所述<0001>晶向与
Figure PCTCN2021078955-appb-000004
晶向互为反方向。
为了增强氮化物集成电路结构10的机械稳定性，可使第一氮化物半导体层122外延在另一个衬底120上。衬底120可为硅衬底、蓝宝石衬底、碳化硅衬底或氮化镓衬底等等。换句话说，可被用于实现第一氮化物半导体层122的外延生长的衬底可以由选自与硅、蓝宝石、碳化硅、氮化镓或任何其它合适的材料来形成。可选地，第一氮化物半导体层122本身可包括衬底120。因此，本公开所用的术语“第一氮化物半导体层”可以指氮化镓衬底或生长在衬底上的氮化物半导体层。可选地，为调谐阈值电压或实现常关型特性，或为了实现欧姆接触，可对第一氮化物半导体层122进行适当掺杂，后面会进一步详细论述。
第二氮化物半导体层123形成在第一氮化物半导体层122上，与第一氮化物半导体层122的第一区域124和第二区域125分别形成叠层结构。第二氮化物半导体层123是势垒层，或是载流子供给层，例如可由从III族氮化物的合金形成。可选地，第二氮化物半导体层123可包括一个或多个氮化物半导体子层，可由AlGaN、InAlN、InGaN、AlN或其它合适的合金材料形成。第二氮化物半导体层123可由具有在大约20％至30％范围内的铝原子百分比的AlGaN合金形成。可选地，铝的百分比可更低或更高。
第一氮化物半导体层122具有第一带隙，并且第二氮化物半导体层123具有第二带隙，第二带隙大于第一带隙。第一氮化物半导体层122例如GaN层可以具有大约3.4eV的带隙，第二氮化物半导体层123例如AlGaN层可以具有大约4.0eV的带隙。可选地，第二氮化物半导体层123的带隙可更高或更低。在任何情况下，第一氮化物半导体层122和第二氮化物半导体层123的带隙彼此不同。由此，第一氮化物半导体层122的第一区域124与第二氮化物半导体层123在接触界面具有第一极化结126，形成第一氮化物半导体结构；第一氮化物半导体层122的第二区域125与第二氮化物半导体层123在接触界面具有第二极化结127，形成第二氮化物半导体结构。换句话说，第一氮化物半导体结构包括第一氮化物半导体层122的第一区域124与第二氮化物半导体层123的叠层结构，该叠层结构可以是多个子层的叠层结构；第二氮化物半导体结构包括第一氮化物半导体层122的第二区域125与第二氮化物半导体层123的叠层结构，该叠层结构可以是多个子层的叠层结构。可选地，叠层结构例如可以是第一氮化物半导体层122的第一子层/第二子层和第二氮化物半导体层123的第一子层/第二子层的叠层结构。所述第一氮化物半导体结构和所述第二氮化物半导体结构是同时或分别形成的。由于自发极化和压电极化效应的存在，并且第一氮化物半导体层122和第二氮化物半导体层123缺乏反转对称性，因此与<0001>晶向或
Figure PCTCN2021078955-appb-000005
晶向垂直的晶面(0001)面和(0001 -)面是极性面，在两者接触的过渡区域分别形成极化结。
继续参照图2，第一极化结126及第二极化结127具有不同的晶向，例如前者是<0001>晶向，后者是
Figure PCTCN2021078955-appb-000006
晶向，并且，第一极化结126和第二极化结127具有垂直界面。相对应的，在第一极化结126的垂直界面处有很强的极化正电荷，在第二极化结127的垂直界面处有很强的极化负电荷，由此，因这些极化正电荷或负电荷的存在，会分别吸引并导致界面处二维电子气(例如可称为第一导电类型或第二导电类型)与二维空穴气(相对应地，例如可称为第二导电类型或第一导电类型)的生成。正如在下文将要更详细描述的，第一导电类型二维载流子气与第二导电类型二维载流子气分别在平行于第一极化结126与第二极化结127方向上形成载流子沟道。其中，二维电子气位于与第一晶体管100的导电沟道105相对应的区域中，并提供在第一晶体管100的第一源电极101、第一漏电极103之间流动的电流；二维空穴气位于与第二晶体管200的导电沟道205相对应的区域中，并提供在第二晶体管200的第二源电极201、第二漏电极203之间流动的电流。
继续参照图2，前述多个电极101、102、103、104、201、202、203、204分别设置在第一氮化物半导体结构和第二氮化物半导体结构上。第一源电极101、第一漏电极103相对分布在第一栅电极102的两侧，并与第一导电类型二维载流子气耦合，构成至少一个第一晶体管100。第二源电极201、第二漏电极203相对分布在第二栅电极202的两侧，并与第二导电类型二维载流子气耦合，构成至少一个第二晶体管200。可选地，第一晶体管100还包括第一体电极104，其与第一栅电极102相对设置在第一氮化物半导体结构的侧表面上；第二晶体管200还包括第二体电极204，其与第二栅电极202相对设置在第二氮化物半导体结构的侧表面上。
可选地，第一氮化物半导体层122还包括至少一个第二导电类型(例如P-类型)的掺杂区域150，其与第一栅电极102在<0001>晶向投影方向上至少部分重叠，并与第一导电类型二维载流子气电耦合，从而基本耗尽该一导电类型二维载流子气以实现第一晶体管100为常关型。为控制第一晶体管100的阈值电压，还可设置第一体电极104与该第二导电类型(例如P-类型)的掺杂区域150电连接。可选地，第一氮化物半导体层122还包括至少一个第一导电类型(例如N-类型)的掺杂区域140，其与第二栅电极202在
Figure PCTCN2021078955-appb-000007
晶向投影方向上至少部分重叠，并与第二导电类型二维载流子气电耦合，从而基本耗尽该二导电类型二维载流子气以实现第二晶体管200为常关型。为控制第二晶体管200的阈值电压，还可设置第二体电极204与该第一导电类型(例如N-类型)的掺杂区域140电连接。可选地，第一氮化物半导体层122可同时包括至少一个第二导电类型(例如P-类型)的掺杂区域150和第一导电类型(例如N-类型)的掺杂区域140，其分别基本耗尽第一栅电极102和第二栅电极202附近的二维载流子气，以同时实现第一晶体管100和第二晶体管200为常关型。
图3示出了另一种III族氮化物半导体的集成电路结构10′的平面图和A-A向剖视图，可选地，还可以在第一氮化物半导体层122中交替形成多个第一导电类型(例如N-类型)的掺杂区域140和多个第二导电类型(例如P-类型)的掺杂区域150。在第一晶体管100中，第二导电类型(例如P-类型)的掺杂区域150在<0001>晶向投影方向上至少部分与第一栅电极102重叠，并基本耗尽第一栅电极102附近的第一导电类型二维载流子气，第一导电类型(例如N-类型)的掺杂区域140分别与第一源电极101和第一漏电极103电耦合。在第二晶体管200中，第一导电类型(例如N-类型)的掺杂区域140在
Figure PCTCN2021078955-appb-000008
晶向投影方向上至少部分与第二栅电极202重叠，并基本耗尽第二栅电极102附近的第二导电类型二维载流子气，第二导电类型(例如P-类型)的掺杂区域150分别与第二源电极201和第二漏电极203电耦合。
下面结合图4-7讨论各种附加电路元件可电耦合于第一晶体管100和第二晶体管200以形成各种类型的电气电路。虽然图4-7示例性示出了利用图2的互补集成电路结构的各种电路，但是应了解，图4-7的各种电路实施还可以是利用图3的互补集成电路结构。
图4示例出了具有附加电连接和电路元件的反相器电路结构。反相器电路结构400包括一个第一晶体管100和一个第二晶体管200，并且第一晶体管与所述第二晶体管是串联连接，该第一晶体管100和第二晶体管200具有图2或图3的电路结构。可选地，第一晶体管100是HEMT，第二晶体管200是HHMT，其中，第一栅电极102与第二栅电极202连接在一起作为输入端V in，第一源电极101耦合接地或外部负电源V SS，所述第二源电极201耦合到外部正电源V DD，第一漏电极103与第二漏电极203 连接在一起作为输出端。
图5示例出了具有附加电连接和电路元件的与非门电路结构。与非门电路结构500包括至少两个第一晶体管100和至少两个第二晶体管200，该第一晶体管100和第二晶体管200具有图2或图3的电路结构。可选地，第一晶体管100是HEMT，第二晶体管200是HHMT。至少两个第一晶体管100串联连接作为第一单元501，至少两个第二晶体管200并联连接作为第二单元502，并且第一单元501与第二单元502串联连接在一起的连接端作为输出端Vout。另外，第一单元的第一晶体管100与第二单元的第二晶体管200是互补配对的，互补配对的两个晶体管的栅电极102、202连接在一起分别作为输入端A、B。更具体的，第一单元中的多个第一晶体管100依次串联连接，其中一个第一源电极101耦合接地或外部负电源V SS，一个第一漏电极103作为第一单元501的输出端Vout与第二单元502电耦合。第二单元502中的多个第二晶体管200并联连接，其中多个第二漏电极203连接在一起作为输出端Vout与第一单元电501耦合，多个第二源电极201连接在一起耦合外部正电源V DD。
图6示例出了具有附加电连接和电路元件的或非门电路结构。或非门电路结构600包括至少两个第一晶体管100和至少两个第二晶体管200，该第一晶体管100和第二晶体管200具有图2或图3的电路结构。可选地，第一晶体管100是HEMT，第二晶体管200是HHMT。至少两个第一晶体管100并联连接作为第一单元601，至少两个第二晶体管200串联连接作为第二单元602，并且第一单元601与第二单元602串联连接在一起的连接端作为输出端Vout。另外，第一单元601的第一晶体管100与第二单元602的第二晶体管200是互补配对的，互补配对的两个晶体管的栅电极102、202连接在一起分别作为输入端A、B。更具体的，第一单元601中的多个第一晶体管100并联连接，其中多个第一源电极101连接在一起耦合接地或外部负电源V SS，多个第一漏电极103连接在一起作为第一单元601的输出端Vout与第二单元602电耦合。第二单元601中的多个第二晶体管200依次串联连接，其中一个第一源电极101耦合外部正电源V DD，一个第一漏电极103作为第二单元602的输出端Vout与第一单元601电耦合。
图7示例出了具有附加电连接和电路元件的复杂CMOS电路结构。复杂CMOS电路结构700包括至少两个第一晶体管100和至少两个第二晶体管200，该第一晶体管100和第二晶体管200具有图2或图3的电路结构。可选地，第一晶体管100是HEMT，第二晶体管200是HHMT。多个第一晶体管100进行任意数量的串联连接或并联连接并作为第一单元701。多个第二晶体管200与第一单元701中的多个第一晶体管100互补配对，并进行任意数量的对应的并联连接或串联连接，且作为第二单元702。第一单元701与第二单元702串联连接在一起的连接端作为输出端Vout。另外，前述互补配对的两个晶体管的栅电极102、202连接在一起分别作为输入端A、B、C、D。更具体的，第一单元701中有4个第一晶体管100，分别记为第一晶体管100 11、100 12、100 13、100 14，第二单元702中有4个与之互补配对的第二晶体管200，分别记为第二晶体管200 11、200 12、200 13、200 14。第一单元701中的两个第一晶体管100 11、100 12并联连接，并与另一第一晶体管100 13串联连接形成串联单元，该串联单元再与最后一个第一晶体管100 14并联连接，其第一源电极101连接在一起耦合接地或外部负电源V SS，其第一漏电极103连接在一起作为输出端V out与第二单元702电耦合。第二单元702中两个第二晶体管200 11、200 12串联连接形成串联单元，再与另一第二晶体管200 13并联连接形成一并联单元，其第二源电极201连接在一起耦合外部正电源V DD，该并联单元再与最后一个第二晶体管200 14串联连接，200 14的第二漏电极203作为第二单元的输出端V out与第一单元701电耦合。
此外，虽然第一晶体管100和第二晶体管200被示为彼此直接相邻，但是两者可以在空间上彼此分离(虽然仍然在相同的第一氮化物半导体层122上)，其中任何数目的插入器件，和/或一种或多种隔离结构可存在于晶体管100、200之间。例如，如图32所示，隔离结构可以包括隔离沟槽及填入沟槽的隔离介质。
除了可以实现各种互补氮化物集成电路结构10的电路的上述例子，各种氮化物集成电路结构10可以被实现在包括各种其它类型电路的电子设备中。这种电路包括但并不限于AC至DC转换器(整流器)、DC至DC转换器、DC至AC逆变器、AC至AC转换器、放大器以及各种其它类型的电路。因此，上述给出的例子并不意在限制性的。
氮化物集成电路结构10还可以包括附加有源和/或无源器件的任何组合，包括至少一个第一晶体管100(例如HEMT)和至少一个第二晶体管200(例如HHMT)、二极管、电阻、电容、电感等等，这些 连同各种器件之间的导电互连的任何组合，能够实现运算、放大、传输、转换、逻辑等功能。
以下参照图8-40来详细描述用于制造上述氮化物集成电路结构10的制造方法。为实现前述互补型氮化物集成电路结构10，需要在一衬底上形成HEMT和HHMT，优选的是同时实现HEMT和HHMT，当然也可分别实现HEMT和HHMT，并通过形成含掺杂结构的沟道结构而实现常关型晶体管。当然，从原理上说，也可由沟道结构外的掺杂氮化物半导体栅电极实现。在本公开中，主要就形成含掺杂结构的沟道结构进行说明。另外，从原理上说，要同时实现HEMT和HHMT，可以有三种工艺路线：无限制生长得到的垂直沟道，水平沟槽限制生长得到的垂直沟道，垂直沟槽限制生长得到的垂直沟道。但是由于水平沟槽限制可以获得最高的集成密度并且工艺相对简单，所以，在本公开中只以这种情况说明。
如图8-9所示，提供一衬底120，所述衬底可以是采用(110)或(112)面的硅衬底。可选地，衬底120可为蓝宝石衬底、碳化硅衬底或氮化镓衬底等等。在所述衬底120第一表面801上形成第一绝缘层802，示例性的，所述第一绝缘层802为热氧化或气相沉积形成的SiO 2层。示例性地，所述第一绝缘层802的厚度约为0.5微米。第一绝缘层802上形成有光刻胶层，光刻胶层上形成有可露出下方的第一绝缘层802的开口。
如图10所示，在所述第一绝缘层802上的光刻胶层上形成的开口处，刻蚀所述第一绝缘层802和其下方的所述衬底120，形成垂直的多个第一沟槽803，所述第一沟槽803是间隔排列，所述第一沟槽的侧壁具有六角对称的晶格结构，例如Si(111)面。
如图11所示，在前述形成的结构基础上，共面沉积形成牺牲层804，示例性地，所述牺牲层804是氮化硅层，其厚度约为100纳米。可以理解的是，所述第一绝缘层802和牺牲层804的选择，以其二者之间具有高蚀刻选择比即可，例如在刻蚀所述牺牲层804时，刻蚀剂对所述牺牲层804的进行刻蚀时，基本上不对第一绝缘层802进行蚀刻，或对其蚀刻极其缓慢。
如图12所示，进行干法刻蚀，去除所述第一绝缘层802表面上的所述牺牲层804和所述第一沟槽803底部上的所述牺牲层804，保留所述第一沟槽803侧表面，比如第一侧表面805和第二侧表面806上的所述第一牺牲层804。
如图13所示，通过氧化工艺，在所述沟槽的底面上形成第二绝缘层807(二氧化硅层)，所述第一沟槽803的侧表面，比如第一侧表面805和第二侧表面806由于保留的所述第一牺牲层804的保护没有被氧化，所述第二绝缘层807可以避免在后续生长氮化物半导体时镓原子与硅衬底的不兼容，避免出现回熔(melt-back)现象。同时，该第二绝缘层807还可以有效阻绝氮化物半导体与硅衬底之间的漏电流，并降低硅衬底所带来的寄生电容。
如图14所示，通过选择性湿法腐蚀，利用所述第一牺牲层804和所述第二绝缘层807的刻蚀选择比，去除所述第一沟槽803侧表面，比如第一和第二侧表面805、806上的所述第一牺牲层804。
如图15所示，通过氧化工艺，在所述第一沟槽803的第一和第二侧表面805、806上分别形成较薄的第三绝缘层808(二氧化硅层)，第三绝缘层808的厚度设置为与第一、第二绝缘层的厚度的不同。第三绝缘层808的厚度满足在后续去除所述第三绝缘层808时候，仍然还有足够厚的第一和第二绝缘层以保护所述衬底即可。这些绝缘层可以避免在后续生长氮化物半导体时镓原子与硅衬底的不兼容，避免出现回熔(melt-back)现象，对于硅衬底上制作氮化物半导体器件是必不可少的。
如图16所示，在前述结构上涂敷光刻胶809，通过本领域技术人员熟知的曝光显影工艺，在所述第一沟槽803之间形成光刻图形以暴露所述第一沟槽803之间的部分所述第三绝缘层808和所述第一绝缘层802。
如图17所示，去除暴露出的所述多个第一沟槽803的侧表面上的部分所述第三绝缘层808和所述第一绝缘层802，由于所述第一绝缘层802的厚度远大于所述第三绝缘层808的厚度，因此，在去除部分所述第三绝缘层808的过程中，所述暴露的第一绝缘层802部分仅被蚀刻很少的厚度并不会被完全去除。然后去除剩下的所述光刻胶809，从而使得在所述第一沟槽803中暴露出所述衬底120的一部分侧表面805、806。
如图18所示，由于硅衬底与镓之间的回熔(melt-back)效果，硅衬底上不能直接沉积GaN。通常需要先沉积AlN的成核层，再在此基础上形成后续的氮化物半导体结构。因此，在暴露出的所述第一沟槽803侧表面805、806上分别形成单晶AlN成核层121，所述单晶AlN晶体的生长方向是<0001>，其 表面是(0001)面。需要指出的是，AlN的选择性很低，在通常的工艺条件下容易在绝缘层上也生成多晶或非晶的AlN，这对形成所需的结构是不利的。因此，需要在形成了成核层后另行去除二氧化硅层上的AlN。或者在生长AlN成核层时引入含氯气体以保证仅在所述硅衬底上生长而不在所述二氧化硅层生长。
可以理解的是，如果采用其他衬底例如Al 2O 3，则成核层也可以是GaN。此时通过工艺调节可以较容易实现仅在暴露的衬底表面成核。
如图19所示，然后以成核层121为核心侧向外生长第一氮化物层半导体122，由于所述第一沟槽803的存在，所述第一氮化物半导体层122从成核层开始沿着所述第一沟槽803开始侧向外延生长，生长方向为<0001>，所述<0001>晶向与
Figure PCTCN2021078955-appb-000009
晶向互为反方向。所述第一氮化物半导体层122还可以在所述沟槽外生长，通过平坦化或蚀刻技术去除所述第一沟槽803外的第一氮化物半导体层122。侧向外延可以有效提升侧向外延区域的氮化物半导体晶体质量，进而提升器件的电学性能。去除所述沟槽外的第一氮化物半导体层122。可以理解的是，所述第一氮化物半导体层122在所述第一沟槽803外的生长也可以不必去除，而形成突出所述第一沟槽803的部分。
根据本实施例，第一氮化物半导体层122可由无掺杂剂的GaN形成。可选地，第一氮化物半导体层122也可包括一个或多个氮化物半导体子层，可由GaN、InN、AlN、AlGaN、InAlN、InGaN、AlGaInN或其它合适的合金材料形成。第一氮化物半导体层122可以具有1.0微米至10微米范围内的厚度。可选地，第一氮化物半导体层122可以更厚或更薄。应注意，本公开中所述的数值范围仅作为示例而非对本公开的限制。
可以理解的是，在生长所述第一氮化物半导体层之前，还可以先沉积形成一缓冲层，当然也可以不形成缓冲层。
可选地，还可在第一氮化物半导体层122形成至少一个第二导电类型(例如P-类型)的掺杂区域150，其与前述第一栅电极102在<0001>晶向投影方向上至少部分重叠，并与第一导电类型二维载流子气电耦合，从而基本耗尽该第一导电类型二维载流子气，以实现第一晶体管100为常关型。所述第二导电类型的掺杂区域150的掺杂浓度、尺寸参数等可以通过器件参数设置，以满足基本耗尽第一导电类型二维载流子气，也即耗尽95％-100％的第一导电类型二维载流子气。第一导电类型二维载流子气的浓度越高，相应的掺杂浓度可以随之提高。
可选地，还可在第一氮化物半导体层122形成至少一个第一导电类型(例如N-类型)的掺杂区域140，其与前述第二栅电极202在<0001(—)>晶向投影方向上至少部分重叠，并与第二导电类型二维载流子气电耦合，从而基本耗尽该第二导电类型二维载流子气以实现第二晶体管200为常关型。所述第一导电类型(例如N-类型)的掺杂区域140的掺杂浓度、尺寸参数等可以通过器件参数设置，以满足基本耗尽第二导电类型二维载流子气，也即耗尽95％-100％的第二导电类型二维载流子气。第二导电类型二维载流子气的浓度越高，相应的掺杂浓度可以随之提高。
可选地，还可在第一氮化物半导体层122同时形成至少一个第二导电类型(例如P-类型)的掺杂区域150和第一导电类型(例如N-类型)的掺杂区域140，其分别基本耗尽第一栅电极102和第二栅电极202附近的二维载流子气，以同时实现第一晶体管100和第二晶体管200为常关型。
如图20所示，对所述第一氮化物半导体层122之间的硅衬底120进行刻蚀，去除所述第一绝缘层802以及部分的所述硅衬底120，形成多个第二沟槽810。在对硅衬底120进行刻蚀后，第一氮化物半导体层122除成核层外侧表面还可能保存有第三绝缘层808。在此可以去除该第三绝缘层808，由此暴露了所述第一氮化物半导体层122的<0001>和
Figure PCTCN2021078955-appb-000010
方向上的侧表面180、190，其对应晶面分别为(0001)面和(0001 -)面。换句话说，第一氮化物半导体层122的<0001>方向上的侧表面180为所述第一氮化物半导体层122的第一区域124，第一氮化物半导体层122的
Figure PCTCN2021078955-appb-000011
方向上的侧表面190为所述第一氮化物半导体层122的第二区域125。可选地，也可以先保留第三绝缘层808并在较后的步骤中去除，在此不再赘述。
如图21所示，在所述刻蚀后的衬底120上形成第四绝缘层811以填充所述第二沟槽810，并平坦化，以隔离暴露的所述硅衬底，所述第四绝缘层811示例性的可以为二氧化硅层。
如图22所示，刻蚀掉所述第二沟槽810内的底部及侧壁上的部分所述第四绝缘层811，以暴露部分 所述第一氮化物半导体层122的第一区域124和第二区域125。
如图23所示，然后在暴露的所述第一氮化物半导体层122的第一区域124和第二区域125上形成第二氮化物半导体层123，与第一氮化物半导体层122的第一区域124和第二区域125分别形成叠层结构。可选地，第二氮化物半导体层123是势垒层，或是载流子供给层，可包括一个或多个氮化物半导体子层。第二氮化物半导体层123，可由AlGaN、InAlN、InGaN、AlN或其它合适的合金材料形成。第二氮化物半导体层123可由具有在大约20％至30％范围内的铝原子百分比的AlGaN合金形成。可选地，铝的百分比可更低或更高。
可选地，第一氮化物半导体层122具有第一带隙，并且第二氮化物半导体层123具有第二带隙，第二带隙大于第一带隙。第一氮化物半导体层122例如GaN层可以具有大约3.4eV的带隙，第二氮化物半导体层123例如AlGaN层可以具有大约4.0eV的带隙。可选地，第二氮化物半导体层123的带隙可更高或更低。在任何情况下，第一氮化物半导体层122和第二氮化物半导体层123的带隙彼此不同。
由于自发极化和压电极化效应的存在，并且第一氮化物半导体层122和第二氮化物半导体层123缺乏反转对称性，因此与<0001>晶向或
Figure PCTCN2021078955-appb-000012
晶向垂直的晶面(0001)面和(0001 -)面是极性面，在两者接触的过渡区域分别形成极化结。因此，第一氮化物半导体层122的第一区域124与第二氮化物半导体层123在接触界面具有第一极化结126，形成第一氮化物半导体结构；第一氮化物半导体层122的第二区域125与第二氮化物半导体层123在接触界面具有第二极化结127，形成第二氮化物半导体结构。换句话说，第一氮化物半导体结构包括第一氮化物半导体层122的第一区域124与第二氮化物半导体层123的叠层结构，该叠层结构可以是多个子层的叠层结构。第二氮化物半导体结构包括第一氮化物半导体层122的第二区域125与第二氮化物半导体层123的叠层结构，该叠层结构可以是多个子层的叠层结构。可选地，叠层结构例如可以是第一氮化物半导体层122的第一子层/第二子层和第二氮化物半导体层123的第一子层/第二子层的叠层结构。所述第一氮化物半导体结构和所述第二氮化物半导体结构是同时形成的。
可选地，所述第一极化结126及第二极化结127具有不同的晶向，例如前者是<0001>晶向，后者是
Figure PCTCN2021078955-appb-000013
晶向，并且，第一极化结126和第二极化结127具有垂直界面。第一导电类型二维载流子气与第二导电类型二维载流子气分别在平行于第一极化结126与第二极化结127方向上形成载流子沟道。
如图24所示，在前述结构上形成第五绝缘层812以填充所述第二沟槽810，并光刻所述第五绝缘层812形成源电极、漏电极以及栅电极窗口。如图2所示，采用本领域技术人员公知的技术，例如电子束蒸发技术在源电极窗口、漏电极窗口以及栅电极窗口蒸发Ti、Al、Ti、TiN四层金属，例如厚度可为20nm、130nm、25nm、70nm，并通过剥离、退火后，形成与二维载流子气欧姆接触的欧姆电极，以及与所述第二氮化物半导体层123绝缘或成肖特基接触的栅电极，也即形成所述HEMT100和HHMT200的源电极101、201，漏电极103、203，以及栅电极102、202。具体地，第一源电极101、第一漏电极103相对分布在第一栅电极102的两侧，并与第一导电类型二维载流子气耦合，构成至少一个第一晶体管100。第二源电极201、第二漏电极203相对分布在第二栅电极202的两侧，并与第二导电类型二维载流子气耦合，构成至少一个第二晶体管200。
如图25、图3所示，为控制晶体管的阈值电压，还可在前述结构上形成体电极104、204，其分别与该第二导电类型(例如P-类型)的掺杂区域150以及该第一导电类型(例如N-类型)的掺杂区域140电连接。具体地，可选地，第一晶体管100还包括第一体电极104，其与第一栅电极102相对设置在第一氮化物半导体结构的侧表面上；第二晶体管200还包括第二体电极204，其与第二栅电极202相对设置在第二氮化物半导体结构的侧表面上。
可选地，可以采用氧化工艺形成第六绝缘层811’替代第四绝缘层811对上述第二沟槽中的硅衬底120进行隔离。具体地，以刻蚀部分硅衬底后得到的结构，如图20所示的结构为基础介绍，对其重新编号为图26。以下仅介绍与前述内容不同的结构或方法，具有相同结构及方法的内容就不再详细介绍。
如图27所示，对图26所示的结构进行氧化，在所述第二沟槽810暴露的硅衬底120及所述第一氮化物半导体层122的侧面上形成第六绝缘层811’。由于氮化物半导体不容易被氧化，所以在第一氮化物半导体层122表面形成的第六绝缘层811’相对较薄。
如图28所示，去除环绕所述第一氮化物半导体层122侧面上的第六绝缘层811’，以暴露部分所述 第一氮化物半导体层122的第一区域124和第二区域125。也可以在形成图20(26)结构的过程中先保留第一氮化物半导体层122侧面上的第三绝缘层808。该第三绝缘层可以保护在图27所示的氧化过程中保护第一氮化物半导体层122侧面并在以后的图28所示步骤中被去除。
如图29所示，然后在暴露的所述第一氮化物半导体层122的第一区域124和第二区域125上形成第二氮化物半导体层123，与第一氮化物半导体层122的第一区域124和第二区域125分别形成叠层结构。可选地，第二氮化物半导体层123的材质与前述实施例相同。可选地，叠层结构例如可以是第一氮化物半导体层122的第一子层/第二子层和第二氮化物半导体层123的第一子层/第二子层的叠层结构。所述第一氮化物半导体结构和所述第二氮化物半导体结构是同时形成的。
如图30、图2所示，在前述结构上形成源电极、漏电极以及栅电极窗口。采用本领域技术人员公知的技术，例如电子束蒸发技术在源电极窗口、漏电极窗口蒸发Ti、Al、Ti、TiN四层金属，例如厚度可为20nm、130nm、25nm、70nm，并通过剥离、退火后，形成与二维载流子气欧姆接触的欧姆电极，以及在栅电极窗口蒸发TiN金属以与所述第二氮化物半导体层123形成绝缘或肖特基接触的栅电极，也即形成所述HEMT100和HHMT200的源电极101、201，漏电极103、203，以及栅电极102、202。也可以采用刻蚀的办法形成这些电极结构。
如图31所示，为控制晶体管的阈值电压，还可在前述结构上形成体电极104、204，其分别与该第二导电类型(例如P-类型)的掺杂区域150以及该第一导电类型(例如N-类型)的掺杂区域140电连接。
如图32所示，去除不同晶体管间的二维载流子气，即2DEG和2DHG，以防止不同晶体管间由于2DEG和2DHG造成的电连接。具体地，利用本领域技术公知的技术，例如感应耦合等离子刻蚀(即ICP刻蚀)，在不同晶体管间形成沟槽，并填充第七绝缘介质812形成沟槽隔离结构。
下面，对形成第一氮化物半导体121的掺杂结构进行说明。以下仅介绍与前述结构不同的结构或方法，具有相同结构及方法的内容就不再详细介绍。
如图33所示，以前述方法形成的图18的结构为基础进行说明，重新编号为图33。
可选地，如图34所示，以成核层121为核心侧向外生长第一氮化物层半导体122，由于所述第一沟槽803的存在，所述第一氮化物半导体层122从成核层开始沿着所述第一沟槽803开始侧向外延生长，所述第一氮化物半导体层122还可以在所述沟槽外生长，通过平坦化或蚀刻技术去除所述第一沟槽803外的第一氮化物半导体层122。可选地，第一氮化物层半导体122的材质与前述结构相同。
与前述结构不同的是，在侧向外延时，在所述第一氮化物半导体层122中交替形成多个第一导电类型(例如N-类型)的掺杂区域140和多个第二导电类型(例如P-类型)的掺杂区域150。
如图35所示，对所述第一氮化物半导体层122之间的硅衬底120进行刻蚀，去除所述第一绝缘层802以及部分的所述硅衬底120，形成第二沟槽810，由此暴露了所述第一氮化物半导体层122的<0001>和
Figure PCTCN2021078955-appb-000014
方向上的侧表面180、190，其对应晶面分别为(0001)面和(0001 -)面。换句话说，第一氮化物半导体层122的<0001>方向上的侧表面180为所述第一氮化物半导体层122的第一区域124，第一氮化物半导体层122的
Figure PCTCN2021078955-appb-000015
方向上的侧表面190为所述第一氮化物半导体层122的第二区域125。
如图36所示，在所述刻蚀后的衬底120上形成第四绝缘层811以填充所述第二沟槽810，并平坦化，以隔离暴露的所述硅衬底，所述第四绝缘层811示例性的可以为二氧化硅层。
如图37所示，刻蚀掉所述第二沟槽810内的底部及侧壁上的部分所述第四绝缘层811，以暴露部分所述第一氮化物半导体层122的第一区域124和第二区域125。
如图38所示，然后在暴露的所述第一氮化物半导体层122的第一区域124和第二区域125上形成第二氮化物半导体层123，与第一氮化物半导体层122的第一区域124和第二区域125分别形成叠层结构。可选地，第二氮化物半导体层123的材质与前述结构的材质相同。可选地，叠层结构例如可以是第一氮化物半导体层122的第一子层/第二子层和第二氮化物半导体层123的第一子层/第二子层的叠层结构。所述第一氮化物半导体结构和所述第二氮化物半导体结构是同时形成的。
如图39、图2、3所示，在前述结构上形成第五绝缘层812以填充所述第二沟槽810，并光刻所述第五绝缘层812形成源电极、漏电极以及栅电极窗口。采用本领域技术人员公知的技术，例如电子束蒸发技术在源电极窗口、漏电极窗口蒸发Ti、Al、Ti、TiN四层金属，例如厚度可为20nm、130nm、25nm、 70nm，并通过剥离、退火后，形成与二维载流子气欧姆接触的欧姆电极，以及在栅电极窗口形成与所述第二氮化物半导体层123绝缘或成肖特基接触的栅电极，也即形成所述HEMT100和HHMT200的源电极101/201，漏电极103/203，以及栅电极102/202。也可以采用刻蚀的办法形成这些电极结构。
具体地，第一源电极101、第一漏电极103相对分布在第一栅电极101的两侧，并与第一导电类型二维载流子气耦合，构成至少一个第一晶体管100。其中，在第一晶体管100中，第二导电类型(例如P-类型)的掺杂区域150在<0001>晶向投影方向上至少部分与第一栅电极102重叠，并基本耗尽第一栅电极102附近的第一导电类型二维载流子气，第一导电类型(例如N-类型)的掺杂区域140分别与第一源电极101和第一漏电极103电耦合。另外，第二源电极201、第二漏电极203相对分布在第二栅电极202的两侧，并与第二导电类型二维载流子气耦合，构成至少一个第二晶体管200。其中，在第二晶体管200中，第一导电类型(例如N-类型)的掺杂区域140在
Figure PCTCN2021078955-appb-000016
晶向投影方向上至少部分与第二栅电极202重叠，并基本耗尽第二栅电极102附近的第二导电类型二维载流子气，第二导电类型(例如P-类型)的掺杂区域150分别与第二源电极201和第二漏电极203电耦合。
如图40、图3所示，为控制晶体管的阈值电压，还可在前述结构上形成体电极104、204，其分别与该第二导电类型(例如P-类型)的掺杂区域150以及该第一导电类型(例如N-类型)的掺杂区域140电连接。具体地，可选地，第一晶体管100还包括第一体电极104，其与第一栅电极102相对设置在第一氮化物半导体结构的侧表面上。第二晶体管200还包括第二体电极204，其与第二栅电极202相对设置在第二氮化物半导体结构的侧表面上。
可选的，为去除不同晶体管间的二维载流子气，即2DEG和2DHG，以防止不同晶体管间由于2DEG和2DHG造成的电连接。可在不同晶体管间形成沟槽隔离结构。
本公开内容的方案至少能有助于实现如下效果之一：本公开的集成电路结构是基于III族氮化物半导体的HEMT与HHMT的互补型电路，能在同一个衬底上实现HEMT与HHMT的集成，且HEMT与HHMT分别具有垂直界面的极化结，两者的极化结的晶向不同，二维载流子气在平行于所述极化结方向上形成载流子沟道，并借助掩埋掺杂区域而几乎耗尽对应的沟道载流子。本公开利用III族氮化物半导体的极化特性，创造性地实现不同晶向上的极化结界面产生互补型的二维载流子气，使III族氮化物半导体的HEMT与HHMT在一个衬底上集成，形成互补型的集成电路结构。与传统的硅基互补型电路如CMOS相比，本公开的集成电路结构的2DEG与2DHG在载流子迁移率、导通电流密度、开关速度等方面都具有优势，并且导通电阻、寄生电感变低，且器件为常关状态，从而能达到更高的导通电流密度、更高的集成度、能耗小的技术效果。
本公开内容的方案至少能有助于实现如下效果之一：本公开的集成电路结构可作为电子设备的核心部分广泛用于反相器、放大器、与非门、或非门等模拟或数字集成电路中。
本公开内容的方案还能有助于实现如下效果之一：本公开的集成电路结构的制造方法可以在单位面积上实现更高的沟道密度；适合于平面化工艺，有利于提升晶体管的集成密度；所述集成电路结构的工艺较为简单，能有效减低生产成本。
上述描述是指被“连接”或“耦合”在一起的元素或节点或特征。正如本公开所使用的，除非另有明确说明，“连接”意指一个元素被直接联接到(或直接互通)另一个元素，并且不一定是机械地连接。同样，除非另有明确说明，“耦合”意指一个元素被直接或非直接联接到(直接或非直接互通)另一个元素，并且不一定是机械地耦合。因此，虽然附图中所示的示意图描述了一个示例性元素布置，但是在描述的主题的实施例中可提出附加中间元素、器件、特征、或组件。
虽然在上述详细说明中已经提出了至少一个示例性实施例，但是应当认识到还存在大量的变化。而且本领域技术人员应该清楚，这些描述都是示例性的，并不是对本公开内容的保护范围的限制。本领域技术人员可以根据本公开内容的精神和原理对本公开内容做出各种变型和修改，这些变型和修改也在本公开内容的范围内。
工业实用性
本公开提供的III族氮化物半导体集成电路结构、制造方法工艺简单、成本低廉、在单位面积上实现更高集成度，具有高耐受电压、高功率和低导通电阻等高性能的互补型半导体集成电路结构。

Claims (19)

  1. 一种集成电路结构，包括：
    至少一个第一晶体管，包括：
    具有第一极化结的第一氮化物半导体结构，其具有第一导电类型二维载流子气；
    第一栅电极，其设置在所述第一氮化物半导体结构上；
    第一源电极和第一漏电极，其相对分布在所述第一栅电极的两侧，并与所述第一导电类型二维载流子气耦合；
    至少一个第二晶体管，包括：
    具有第二极化结的第二氮化物半导体结构，其具有第二导电类型二维载流子气；
    第二栅电极，其设置在所述第二氮化物半导体结构上；
    第二源电极和第二漏电极，其相对分布在第二栅电极的两侧，并与所述第二导电类型二维载流子气电耦合；
    其中，所述第一极化结与所述第二极化结具有不同的晶向；
    其中，所述第一导电类型二维载流子气与所述第二导电类型二维载流子气的导电类型不同；
    其中，所述第一导电类型二维载流子气与所述第二导电类型二维载流子气分别在平行于所述第一极化结与所述第二极化结方向上形成载流子沟道。
  2. 如权利要求1所述的集成电路结构，其特征在于，所述第一氮化物半导体结构和第二氮化物半导体结构外延生长在相同的衬底上。
  3. 如权利要求2所述的集成电路结构，其特征在于，所述第一极化结和所述第二极化结分别具有垂直界面。
  4. 如权利要求1-3中任一项所述的集成电路结构，其特征在于，所述第一晶体管与所述第二晶体管是互补型且串联连接，其中所述第一栅电极与所述第二栅电极连接在一起作为输入端，所述第一源电极或所述第二源电极耦合接地或外部负电源V SS，所述第二源电极或所述第一源电极耦合到外部正电源V DD，所述第一漏电极与所述第二漏电极连接在一起作为输出端。
  5. 如权利要求1-3中任一项所述的集成电路结构，其特征在于，至少两个所述第一晶体管串联连接或并联连接作为第一单元，至少两个所述第二晶体管并联连接或串联连接作为第二单元，其中所述第一单元中的串联连接或并联连接与第二单元中的并联连接或串联连接是对应的，并且所述第一单元与所述第二单元串联连接在一起并以所述第一单元与所述第二单元串联的连接端作为输出端，所述第一单元中的所述第一晶体管与所述第二单元中的所述第二晶体管是互补配对的，且互补配对的晶体管的所述第一栅电极与所述第二栅电极连接在一起分别作为输入端。
  6. 如权利要求5所述的集成电路结构，其特征在于，所述第一单元中的所述第一晶体管可以进行任意数量的串联连接或并联连接，所述第二单元中的与所述第一单元中的所述第一晶体管互补配对的所述第二晶体管可以进行对应数量的并联连接或串联连接。
  7. 如权利要求1～6中中任一项所述的集成电路结构，其特征在于，还包括成核层。
  8. 如权利要求1～7中中任一项所述的集成电路结构，其特征在于，所述第一氮化物半导体结构进一步包括第一掺杂结构，该第一掺杂结构与所述第一导电类型二维载流子气电耦合。
  9. 如权利要求8所述的集成电路结构，其特征在于，所述第二氮化物半导体结构进一步包括第二掺杂结构，该第二掺杂结构与所述第二导电类型二维载流子气电耦合。
  10. 如权利要求9所述的集成电路结构，其特征在于，所述第一掺杂结构包括至少一个第二导电类型掺杂区域，其与所述第一栅电极在所述晶向投影方向上至少部分重叠。
  11. 如权利要求10所述的集成电路结构，其特征在于，所述第二掺杂结构包括至少一个第一导电类型掺杂区域，其与所述第二栅电极在所述晶向投影方向上至少部分重叠。
  12. 一种电子设备，包括如权利要求1-11中任一项所述的集成电路结构。
  13. 一种集成电路结构制造方法，包括以下步骤：
    形成至少一个第一晶体管，其包括：
    形成具有第一极化结的第一氮化物半导体结构，其具有第一导电类型二维载流子气；
    形成至少一个第二晶体管，其包括：
    形成具有第二极化结的第二氮化物半导体结构，其具有第二导电类型二维载流子气；
    其中，所述第一氮化物半导体结构和所述第二氮化物半导体结构是同时形成的；
    其中，所述第一极化结与所述第二极化结具有不同的晶向，且所述极化结分别具有垂直界面；
    其中，所述第一导电类型二维载流子气与所述第二导电类型二维载流子气的导电类型不同；
    其中，所述第一导电类型二维载流子气与所述第二导电类型二维载流子气分别在平行于所述第一极化结与所述第二极化结方向上形成载流子沟道。
  14. 如权利要求13所述的方法，其特征在于，形成至少一个第一晶体管的步骤进一步包括：
    形成第一栅电极，其设置在所述第一氮化物半导体结构上；
    形成第一源电极和第一漏电极，其相对分布在所述第一栅电极的两侧，并与所述第一导电类型二维载流子气耦合。
  15. 如权利要求14所述的方法，其特征在于，形成至少一个第二晶体管的步骤进一步包括：
    形成第二栅电极，其设置在所述第二氮化物半导体结构上；
    形成第二源电极和第二漏电极，其相对分布在第二栅电极的两侧，并与所述第二导电类型二维载流子气电耦合。
  16. 如权利要求15所述的方法，其特征在于，形成具有第一极化结的第一氮化物半导体结构的步骤进一步包括：
    形成第一掺杂结构，该第一掺杂结构与所述第一导电类型二维载流子气电耦合。
  17. 如权利要求16所述的方法，其特征在于，形成具有第二极化结的第二氮化物半导体结构的步骤进一步包括：
    形成第二掺杂结构，该第二掺杂结构与所述第二导电类型二维载流子气电耦合。
  18. 如权利要求17所述的方法，其特征在于，所述第一掺杂结构包括至少一个第二导电类型掺杂区域，其与所述第一栅电极在所述晶向投影方向上至少部分重叠。
  19. 如权利要求18所述的方法，其特征在于，所述第二掺杂结构包括至少一个第一导电类型掺杂区域，其与所述第二栅电极在所述晶向投影方向上至少部分重叠。
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