WO2021208624A1 - 一种空穴沟道半导体晶体管、制造方法及其应用 - Google Patents

一种空穴沟道半导体晶体管、制造方法及其应用 Download PDF

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WO2021208624A1
WO2021208624A1 PCT/CN2021/078960 CN2021078960W WO2021208624A1 WO 2021208624 A1 WO2021208624 A1 WO 2021208624A1 CN 2021078960 W CN2021078960 W CN 2021078960W WO 2021208624 A1 WO2021208624 A1 WO 2021208624A1
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layer
channel
channel layer
substrate
planar
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PCT/CN2021/078960
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English (en)
French (fr)
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黎子兰
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广东致能科技有限公司
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Priority claimed from CN202010288958.0A external-priority patent/CN111816702A/zh
Application filed by 广东致能科技有限公司 filed Critical 广东致能科技有限公司
Priority to PCT/CN2021/078960 priority Critical patent/WO2021208624A1/zh
Priority to EP21786315.8A priority patent/EP3944337A4/en
Priority to KR1020227015501A priority patent/KR20220078677A/ko
Priority to US17/594,846 priority patent/US20220384633A1/en
Priority to JP2022528141A priority patent/JP7397982B2/ja
Publication of WO2021208624A1 publication Critical patent/WO2021208624A1/zh

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Definitions

  • the present disclosure relates to the field of semiconductors, and more specifically, to a hole-channel group III nitride semiconductor transistor, a manufacturing method and applications thereof.
  • Group III nitride semiconductor is an important new semiconductor material, which mainly includes AlN, GaN, InN and compounds of these materials such as AlGaN, InGaN, AlInGaN, etc. Taking advantage of the direct band gap, wide band gap, and high breakdown electric field strength of the III-nitride semiconductors, through optimized design of device structure and process, III-nitride semiconductors have great prospects in the fields of power semiconductors and wireless communications. . Although the possibility of realizing hole-channel group III nitride transistors has been explored, so far, it is still difficult to manufacture this type of transistor.
  • the existing III-nitride semiconductor transistors are designed as lateral devices, and the integration per unit area is not high enough.
  • the existing III-nitride semiconductor device transistors are normally-on devices, which is very unfavorable for energy saving.
  • the present disclosure provides a novel hole-channel group III nitride transistor structure and a manufacturing method thereof, aiming to overcome the above-mentioned drawbacks.
  • a method for manufacturing a non-planar hole channel semiconductor transistor including:
  • a substrate is provided, and a stepped structure is etched on its upper surface.
  • the stepped structure has a substantially parallel first surface and a second surface, and a vertical surface respectively connecting the first surface and the second surface, and The lattice on the vertical surface has hexagonal symmetry;
  • a non-planar channel layer is epitaxially grown on the side perpendicular to the second surface;
  • a barrier layer is formed on the channel layer, thereby simultaneously forming two-dimensional hole gas and immovable background negative charges at the interface of the barrier layer and the channel layer; and/or the two-dimensional Electron gas and immobile positive background charge.
  • the substrate is selected from Al2O3, 4H-SiC, (110) silicon or (112) silicon.
  • the vertical surface is selected from the (0001) plane of Al2O3, the (0001) plane of 4H-SiC or the (111) plane of silicon.
  • a first insulating layer is formed on the other surface of the substrate except the vertical surface.
  • the method for forming the first insulating layer includes coplanar deposition of SiN on the substrate, and a vertical orientation etching technique to retain only the SiN on the vertical surface, and then deposit SiN on other surfaces except the vertical surface.
  • a silicon dioxide layer is formed on the surface, and the SiN on the sidewall is removed by wet etching, leaving the silicon dioxide layer on the other surface.
  • the method further includes forming a nucleation layer at the vertical surface, the nucleation layer is formed on a part of the vertical surface; or the nucleation layer is formed on the entire surface of the vertical surface.
  • the polycrystalline or amorphous layer formed by the nucleation layer material is removed or remains on the first insulating layer.
  • the substrate when it is a silicon substrate, it must have the nucleation layer.
  • the method further includes using the nucleation layer as the core, and laterally growing a buffer layer epitaxially.
  • the method further includes using the nucleation layer or the buffer layer as a core, and laterally growing a first channel layer epitaxially.
  • the method further includes growing an N-type buried layer epitaxially with the first channel layer as the core.
  • the buried layer consumes 95-100% of the two-dimensional cavitation gas.
  • a body diode can be formed by combining the N-type buried layer and the two-dimensional hole gas.
  • the method further includes using the first channel layer or the buried layer as a core, and continuing to epitaxially grow a second channel layer.
  • the materials of the first channel layer and the second channel layer are the same or different.
  • the second channel layer is GaN or the first channel layer is P-type GaN, and the second channel layer is GaN .
  • it further includes removing the barrier layer covering the ⁇ 0001> direction of the first channel layer.
  • a fourth insulating layer is formed in the ⁇ 0001> direction of the first channel layer.
  • the first channel layer is P-type GaN
  • the first channel layer and the N-type buried layer form a PN structure.
  • the method further includes depositing and forming a third channel layer before depositing the barrier layer.
  • the third channel layer is unintentionally doped or intrinsic GaN; or GaN or InGaN with a lower doping concentration.
  • it also includes a source electrode, a drain electrode, and a gate electrode forming a transistor.
  • the source electrode and the drain electrode are in physical contact with the channel layer of the transistor, and are in ohmic contact with the two-dimensional hole gas; or the source electrode and the drain electrode are in contact with the potential
  • the barrier layer makes physical contact to form an ohmic contact.
  • the gate electrode and the barrier layer form a Schottky contact or form an insulating contact.
  • the insulating contact is to form a gate insulating layer on the barrier layer at a position corresponding to the gate electrode.
  • the method for forming the gate insulating layer is to grow the gate insulating layer in-situ after the barrier layer is formed by the MOCVD method; or the gate insulating layer is in-situ with the potential
  • the barrier layer is grown separately in different growth equipment.
  • drain electrode, the gate electrode and the source electrode are sequentially arranged in a direction substantially perpendicular to the first surface of the substrate, and the positions of the source electrode and the drain electrode can be interchanged.
  • it further includes forming a body electrode connected to the buried layer.
  • the body electrode is formed by physical contact with the buried layer.
  • the body electrode is formed by ohmic contact with the two-dimensional electron gas, and the body electrode is electrically connected to the buried layer by the two-dimensional electron gas.
  • the body electrode depletes all or part of the two-dimensional electron gas between the second and third electrodes, leaving only the background positive charge, thereby partially canceling the original
  • the electric field generated by the negative background charge in the 2DHG makes the electric field distribution more uniform.
  • the method further comprises forming the drain electrode is formed by a first metal layer on a first surface of the substrate, the barrier layer of the isotropic etch removes the transistor (0001 -) plane A small amount of the deposited first metal layer.
  • the method for forming the gate further includes coplanar depositing and forming a second insulating layer on the first metal layer, and the height of the second insulating layer exposes the barrier layer or the gate insulating layer. layer, and then forming a second metal layer on the second insulating layer, removing the isotropic etching barrier layer (0001 -) of the transistor of the second surface of the small amount of metal deposited layer.
  • the method for forming the source electrode further forms a third insulating layer by coplanar deposition on the second metal layer, and then forms a third metal layer on the third insulating layer, and then uses photolithography to form a third insulating layer.
  • the source electrode is formed by etching.
  • a non-planar hole channel semiconductor transistor including:
  • the stepped structure has a first surface and a second surface that are substantially parallel, and a vertical surface connecting the first surface and the second surface respectively, and the crystal of the vertical surface
  • the lattice has hexagonal symmetry
  • a non-planar channel layer grown epitaxially with the vertical surface as the core and limited by the second surface, perpendicular to the second surface;
  • the barrier layer is formed on the channel layer, thereby simultaneously forming the two-dimensional hole gas and/or the two-dimensional electron gas at the interface of the barrier layer and the channel layer.
  • the substrate is selected from Al2O3, intrinsic GaN, 4H-SiC, and (110) silicon or (112) silicon.
  • the vertical surface is selected from the group consisting of the (0001) plane of Al2O3, the (0001) plane of 4H-SiC and the (111) plane of silicon.
  • a first insulating layer is provided on the other surface of the substrate except the vertical surface.
  • nucleation layer on the vertical surface of the substrate.
  • a polycrystalline or amorphous layer formed of the nucleation layer material on the first insulating layer.
  • the buffer layer there is a buffer layer outside the nucleation layer, and the buffer layer has a single-layer or multi-layer structure.
  • N-type buried layer on the first channel layer, and the N-type buried layer and the two-dimensional hole gas form a body diode structure.
  • the materials of the first channel layer and the second channel layer are the same or different.
  • the first channel layer is N-type GaN or P-type GaN
  • the second channel layer is GaN
  • the third channel layer is unintentionally doped or intrinsic GaN, or is InGaN, or the third channel layer is GaN with a lower doping concentration.
  • the first channel layer is P-type GaN
  • the first channel layer and the buried layer form a body diode structure.
  • a source electrode, a drain electrode and a gate electrode are also provided therein.
  • the source electrode/drain electrode is in physical contact with the channel layer of the transistor and is in ohmic contact with the two-dimensional hole gas; or the source electrode/drain electrode is in contact with the potential
  • the barrier layer makes physical contact to form an ohmic contact.
  • the gate electrode and the barrier layer form a Schottky contact or form an insulating contact.
  • the insulating contact includes a gate insulating layer between the gate electrode and the barrier layer.
  • drain electrode, the gate electrode and the source electrode are sequentially arranged in a direction substantially perpendicular to the first surface of the substrate, and the positions of the source electrode and the drain electrode can be interchanged.
  • the body electrode is electrically connected to the buried layer.
  • the buried layer and the two-dimensional hole gas are stabilized while stabilizing the threshold voltage.
  • the formed body diode conducts a current that is opposite to the direction of the channel current of the transistor; or through the connection of the body electrode, the first channel layer composed of the buried layer and the P-type GaN is realized Circuit application of the formed body diode.
  • the body electrode is physically connected to the buried layer, or the body electrode is in ohmic contact through the two-dimensional electron gas.
  • the first channel layer is P-type doped corresponding to the drain region
  • the second channel layer is P-type doped corresponding to the source region
  • a non-planar hole channel semiconductor device including:
  • the channel layer includes first and second channel layers
  • a barrier layer (130) is formed on the channel layer, thereby simultaneously forming a two-dimensional hole gas and/or the two-dimensional electron gas at the interface of the barrier layer (130) and the channel layer .
  • the substrate is selected from Al2O3, intrinsic GaN, 4H-SiC, and (110) silicon or (112) silicon.
  • first insulating layer on the upper surface of the substrate.
  • nucleation layer there is a nucleation layer on the substrate.
  • the buffer layer there is a buffer layer outside the nucleation layer, and the buffer layer has a single-layer or multi-layer structure.
  • first and second channel layers are stacked on top of each other in parallel with the upper surface of the substrate.
  • an N-type buried layer is sandwiched between the first and second channel layers.
  • the N-type buried layer and the two-dimensional hole gas form a body diode structure.
  • the materials of the first channel layer and the second channel layer are the same or different.
  • the first channel layer is N- or P-type GaN
  • the second channel layer is intrinsic GaN or N-type GaN.
  • the third channel layer is unintentionally doped GaN, InGaN or AlInGaN.
  • the first channel layer is P-type GaN
  • the first channel layer and the buried layer form a body diode structure.
  • it also has a source, a drain, and a gate.
  • the source/drain is in physical contact with the channel layer of the device, and is in ohmic contact with the two-dimensional hole gas; or the source/drain is in contact with the potential
  • the barrier layer makes physical contact to form an ohmic contact.
  • the gate and the barrier layer form a Schottky contact or form an insulating contact.
  • the insulating contact includes a gate dielectric layer between the gate and the barrier layer.
  • the source, gate and drain electrodes are sequentially arranged in a direction substantially perpendicular to the upper surface of the substrate; the positions of the source and drain can be interchanged.
  • the body electrode is electrically connected to the buried layer.
  • the body electrode is physically connected to the buried layer, or the body electrode is in ohmic contact through the two-dimensional electron gas.
  • a radio frequency device including the aforementioned transistor.
  • an electric power device including the aforementioned transistor.
  • 1-12 is a schematic diagram of a hole channel group III nitride transistor structure and a manufacturing method thereof;
  • 13-15 are schematic diagrams of an optional hole channel group III nitride transistor structure and a manufacturing method thereof;
  • 16-17 are schematic diagrams of an optional hole channel group III nitride transistor structure and a manufacturing method thereof;
  • 18 is a schematic diagram of an optional hole channel group III nitride transistor structure and a manufacturing method thereof;
  • 19-21 are schematic diagrams of an optional hole channel group III nitride transistor structure and a manufacturing method thereof;
  • 22-25 are schematic diagrams of an optional hole channel group III nitride transistor structure and a manufacturing method thereof;
  • 26-31 are schematic diagrams of an optional hole channel group III nitride transistor structure and a manufacturing method thereof;
  • 32-33 are schematic diagrams of an optional hole channel group III nitride transistor structure and a manufacturing method thereof;
  • FIG. 34 is a schematic diagram of an alternative method of manufacturing a hole channel group III nitride transistor.
  • Group III nitride semiconductors mainly have two crystal structures: Wurtzite and Zinc-blende. Because wurtzite has the advantages of stability and easier access to higher crystal quality, III-nitride semiconductors in practical applications usually have a wurtzite structure.
  • the III-nitride transistor structure in the present disclosure includes a III-nitride transistor using a wurtzite crystal structure.
  • the III-nitride transistor is a hole-channel III-nitride transistor; optionally, the hole-channel III-nitride transistor is a normally closed hole-channel nitride transistor; more optionally, The normally closed hole channel nitride transistor is a normally closed hole channel gallium nitride transistor.
  • a III-nitride transistor includes a substrate 100.
  • an independent substrate or bulk GaN material can be used. Since the preparation of GaN materials is very expensive, a feasible way is Make GaN epitaxially grow on a heterogeneous substrate and fabricate devices.
  • Heterogeneous substrate materials mainly include Al2O3 (sapphire), silicon and SiC. Among them, the (0001) plane of Al2O3, the (0001) plane of 4H-SiC, and the (111) plane of silicon all have a hexagonal symmetrical lattice structure, which is suitable as a substrate surface for heterogeneous growth, on which nitride semiconductors are formed. Nucleus and growth are conducive to obtaining higher quality GaN or AlN crystals.
  • the sapphire substrate has been widely used due to its low cost and the relatively matching lattice between the gallium nitride epitaxial layer and the sapphire substrate. If heat dissipation is taken into consideration, the use of silicon substrates to prepare GaN epitaxial layers is also increasing, but the use of silicon substrates requires consideration of leakage current and withstand voltage. This is carefully designed in the process flow of the present disclosure, which can avoid the influence of the silicon substrate material on the performance of the device, and it is obviously helpful to improve the withstand voltage and reduce the dark current.
  • the material of the heterogeneous substrate can be selected according to actual needs.
  • the present disclosure does not limit the specific material of the substrate, as long as the substrate material is able to meet the side of the vertical groove formed on the surface perpendicular to the surface. Any substrate material with a hexagonal symmetrical lattice structure on the surface can be used.
  • the substrate material can be Al2O3 (sapphire), 4H-SiC, silicon, and intrinsic GaN.
  • a stepped structure is formed on a substrate 100 by photolithography.
  • the stepped structure is composed of a first surface 1001 of the substrate 100, a second surface 1002 parallel to the first surface, and The vertical surface 1003 connecting the first surface 1001 and the second surface 1002 is constituted.
  • the vertical surface has hexagonal symmetry.
  • the step depth is about 5 microns.
  • the nucleation layer 101 is formed on the vertical surface, and the nucleation layer 101 may be formed on a part of the vertical surface or on the entire surface of the vertical surface.
  • semiconductor layers such as GaN cannot be grown directly on the substrate due to the reflow effect of Ga atoms.
  • structures such as AlN and GaN nucleation layers must be grown on the substrate to further grow the GaN epitaxial layer.
  • the GaN can directly nucleate and grow on Al2O3 (sapphire), SiC, or intrinsic GaN, but from the perspective of crystal quality control, the nucleation layer 101 can be introduced during the process.
  • the first channel layer 110 is grown epitaxially to the upper side perpendicular to the second surface, and then the second channel layer 120 is grown laterally epitaxially.
  • the materials of the first channel layer 110 and the second channel layer 120 may be the same or different.
  • the first channel layer is an N-type doped GaN layer
  • the second channel layer is a GaN layer
  • the first channel layer is a P-type doped GaN layer
  • the second channel layer is The doping concentration of the GaN layer is 1E17-1E20/cm3.
  • the substrate may not be etched into a step shape. For example, nucleation growth may be directly performed on the upper surface of the substrate to form the first and second channel layers.
  • the buffer layer 140 may have a single-layer or multi-layer structure.
  • the material of the buffer layer may be, for example, AlN, One or more of GaN, AlGaN, InGaN, AlInN and AlGaInN.
  • corresponding P-type doping is performed at a part of the region corresponding to the transistor forming the source electrode, and the first channel layer 110 is corresponding to the part of the transistor forming the drain electrode.
  • P-type doping can also be performed. P-type doping can effectively reduce the contact resistance of the corresponding area.
  • the P-type doping concentration can be 1E17-1E20/cm3.
  • the second channel layer 120 covering both sides in the direction of the first surface on the first channel layer is removed to expose the first channel layer.
  • a barrier layer 130 such as AlGaN, is formed on the first channel layer and the second channel layer.
  • the III-nitride semiconductor Since the channel layer and the barrier layer use a III-nitride semiconductor, the III-nitride semiconductor has polarity, so there may be fixed polarization charges on the surface of the polar semiconductor or at the interface of two different polar semiconductors. The existence of these fixed polarization charges can attract movable holes and electrons to form two-dimensional hole gas 2DHG and two-dimensional electron gas 2DEG. The generation of these two-dimensional hole gas 2DHG and two-dimensional electron gas 2DEG does not require an additional electric field, nor does it depend on the doping effect in the semiconductor. They are spontaneously generated. Because they do not need to be doped, the two-dimensional hole gas is scattered by ions. The effect is greatly reduced, so it has a higher mobility.
  • 2DHG is formed at the interface between the first and second channel layers in the ⁇ 0001 -> direction and the barrier layer. Or remove the second channel layer 120 covering the first channel layer in the ⁇ 0001 - > direction and the ⁇ 0001> direction to expose the first channel layer.
  • a barrier layer 130 such as AlGaN, is formed on the first channel layer and the second channel layer. Thereby, 2DHG is formed at the interface between the first and second channel layers in the ⁇ 0001 - > direction and the barrier layer, and at the same time, 2DHG is formed at the interface between the first and second channel layers in the ⁇ 0001> direction and the barrier layer. 2DEG is formed at the interface.
  • the source electrode 200, the drain electrode 210 and the gate electrode 220 of the transistor are formed.
  • the positions of the source electrode 200, the drain electrode 210 and the gate electrode 220 are not specifically limited.
  • the source electrode and the drain electrode can be connected to the channel layer (110/120) of the transistor.
  • Make physical contact and make ohmic contact with the two-dimensional hole carrier gas (2DHG), or the source electrode and the drain electrode can make physical contact with the barrier layer 130 directly.
  • the gate electrode 220 can form an insulating contact or Schottky contact with the barrier layer 130 on the barrier layer 130.
  • the insulating layer contact means that a gate insulating layer 300 is formed between the gate electrode and the barrier layer.
  • the layer can be silicon dioxide, high-K dielectric material, etc.
  • the gate insulating layer 300 can play a role of passivating the surface of the barrier layer, which is beneficial to reduce the gate leakage current of the transistor and use the transistor as a power electronic device.
  • the gate When the gate is directly fabricated on the barrier layer, it has a large gate leakage current. At this time, the barrier layer maintains a sufficiently high forbidden band width, and it also acts as a dielectric layer.
  • the transistors made in this way are mostly used as radio frequency (RF) device.
  • the source electrode 200, the drain electrode 210 and the gate electrode 220 may be arranged in a direction perpendicular to the first surface of the substrate 100.
  • the drain electrode 210 is closer to the first surface 1001 of the substrate 100. It can be understood that the source electrode can also be closer to the first surface 1001 of the substrate 100.
  • FIGS. 4-12 and FIG. 34 the manufacturing method for manufacturing the semiconductor device of this structure will be described in detail.
  • Step 1 as shown in FIG. 4, a substrate 100 is provided, a photolithography pattern is formed on the substrate 100, and then the upper surface is etched to form a stepped structure.
  • the etching depth is about 5 microns.
  • the stepped structure is composed of a first surface 1001 of the substrate 1001, a second surface 1002 parallel to the first surface 1001, and a vertical surface 1003 respectively connecting the first surface 1001 and the second surface 1002, wherein the vertical surface has a hexagonal symmetry
  • the lattice structure, the vertical surface with a hexagonal symmetrical lattice structure is easy for the nucleation and growth of nitride semiconductors, while other surfaces are not easy for the nucleation and growth of nitride semiconductors.
  • Step 2 As shown in FIG. 5, a nucleation layer 101 is formed on the vertical surface.
  • the nucleation layer 101 may be formed on a part of the vertical surface or on the entire surface of the vertical surface.
  • the material of the nucleation layer is, for example, GaN, ALN, etc.
  • GaN cannot be grown directly on the substrate due to the reflow effect of Ga atoms. It is usually necessary to grow structures such as a nucleation layer on the substrate to further grow the GaN epitaxial layer.
  • Step 3 As shown in FIG. 6, with the nucleation layer 101 as the core, and limited by the second surface 1002 of the substrate 100, it grows epitaxially upward along the vertical surface of the substrate and laterally along the second surface of the substrate.
  • the buffer layer 140 is then epitaxially grown on the first channel layer 110. It can be understood that the buffer layer is not necessary, so the first channel layer 110 can also be epitaxially grown with the nucleation layer as the core side as shown in FIG. 7.
  • Step 4 As shown in FIG. 8, the first channel layer 110 is used as the core, and then the second channel layer 120 is grown laterally epitaxially.
  • the materials of the first channel layer 110 and the second channel layer 120 may be the same or different.
  • N-type doping or P-type doping may be performed during the lateral epitaxial growth of the first channel layer. It is understandable that the subsequent drain is formed at the first channel layer as an example. If the subsequent source is formed at the first channel layer, the second channel layer will be epitaxially grown on the side. N-type doping or P-type doping.
  • corresponding P-type doping may be performed in the second channel layer 120 at a part of the region corresponding to the transistor forming the source electrode, and the region of the first channel layer 110 corresponding to the transistor forming the drain electrode. P-type doping can also be carried out. P-type doping can effectively reduce the contact resistance of the corresponding area.
  • Step 5 As shown in FIG. 9, remove the second channel layer 120 covering the first channel layer in the ⁇ 0001 - > direction, exposing the (0001 - ) surface of the first channel layer, and at the same time remove the covering on the The second channel layer 120 in the ⁇ 0001> direction on the first channel layer exposes the (0001) plane of the first channel layer. Then, as shown in FIG. 10, a barrier layer 130, such as AlGaN, is formed on the first channel layer and the second channel layer.
  • a barrier layer 130 such as AlGaN
  • 2DHG and immovable background negative charges are formed at the interface between the first and second channel layers in the ⁇ 0001 - > direction and the barrier layer; in the first and second channel layers in the ⁇ 0001> direction At the interface with the barrier layer, 2DEG and an immovable background positive charge are formed.
  • Step 6 As shown in FIG. 11, the source electrode 200, the drain electrode 210, and the gate electrode 220 of the transistor are formed.
  • the positions of the source electrode 200, the drain electrode 210 and the gate electrode 220 are not specifically limited.
  • the source electrode and the drain electrode can be the same as the transistor
  • the channel layer (110/120) is in physical contact and is in ohmic contact with the two-dimensional hole carrier gas (2DHG), or the source electrode and the drain electrode are directly in physical contact with the barrier layer 130.
  • the gate electrode 220 can form an insulating contact or a Schottky contact with the barrier layer 130 on the barrier layer 130.
  • the insulating layer contact refers to the formation of a gate insulating layer 300 between the gate electrode and the barrier layer. -situ) situ growth.
  • the formation method of the gate insulating layer 300 may also be grown separately in a growth equipment different from the barrier layer. However, it should be pointed out that the quality of the in-situ gate insulating layer is better. Therefore, it is preferable to choose the in-situ in-situ insulating layer.
  • the gate insulating layer can be silicon dioxide, SiN, high-K dielectric materials, etc.
  • the gate insulating layer 300 can passivate the surface of the barrier layer, which is beneficial to reduce the gate leakage current of the transistor and the application of the transistor in power electronics. . If the gate electrode is directly fabricated on the barrier layer, the transistor thus fabricated is more used in radio frequency (RF) devices because it has a larger gate leakage current than a transistor with a gate insulating layer.
  • RF radio frequency
  • the source electrode 200, the drain electrode 210, and the gate electrode 220 may be arranged in a direction perpendicular to the first surface of the substrate 100.
  • the drain electrode 210 is closer to the first surface 1001 of the substrate 100.
  • the gate electrode 220 is located between the drain electrode 210 and the source electrode 200.
  • the source and drain electrodes make physical contact with the channel layer of the transistor, which is beneficial to reduce Ohmic contact resistance.
  • the non-planar group III nitride transistor with irregular cross-section grown on the vertical surface can improve the integration of the device, can effectively reduce the gate leakage current, and the preparation process is simple, which can be carried out through the vertical surface.
  • the lateral extension method forms two-dimensional electron carrier gas while forming two-dimensional hole carrier gas, which can effectively improve the mobility of holes.
  • step 4 the AlN nucleation layer is used as the core, and limited by the second surface 1002 of the substrate 100, after the first channel layer 110 is grown laterally epitaxially, Before the second channel layer 120 is epitaxially grown, side epitaxial growth is performed to form an N-type buried layer.
  • the N-type buried layer is exemplarily an N-type GaN layer.
  • the second channel layer 120 is epitaxially grown with the buried layer as the core.
  • the doping concentration covering the N-type buried layer is exemplarily 1E17-5E19/cm3, and more preferably 1E+18/cm3-5E+19/cm3.
  • the N-type GaN layer can deplete the two-dimensional hole gas in the channel layer, thereby causing the device to have a normally-off state; it is understandable that the doping can be gradual and will not be repeated here.
  • the projection of the N-type buried layer in the ⁇ 0001 - > direction falls within the projection range of the gate electrode in this direction, or has a partial overlap range with the projection of the gate electrode in this direction.
  • the setting of the N-type buried layer such as its doping concentration, size parameters, etc. can be set by device parameters to satisfy 95%-100% of the two-dimensional hole gas above it. The higher the concentration of the two-dimensional hole gas, The corresponding doping concentration can be increased accordingly.
  • the second channel layer 120 and the buried layer in the ⁇ 0001 - > direction covering the first channel layer are removed, exposing the (0001 - ) surface of the first channel layer, and the covering is removed at the same time.
  • the second channel layer 120 and the buried layer in the ⁇ 0001> direction on the first channel layer expose the (0001) plane of the first channel layer.
  • the body diode structure is also realized at the same time.
  • the N-type GaN layer also forms a PN structure with 2DHG at the same time when the device can have a normally closed state, where 2DHG constitutes the "P" part of the PN structure.
  • the PN structure is integrated and manufactured in the transistor structure. This PN structure can be used for various circuit applications through the connection of subsequent electrodes, which enriches the design and functions of the circuit. Exemplarily, in circuit applications, the PN structure can conduct a current that is opposite to the current direction of the HHMT.
  • the body electrode can be etched by etching the barrier layer and the non-polar or semi-polar surface of the second channel layer to etch the through holes that reach the N-type buried layer, and then further fill the metal to form the body. Electrode 230.
  • the method for forming the body electrode can also completely remove or partially remove the barrier layer covering the first channel layer in the ⁇ 0001> direction to expose the N-type buried layer, and then to expose the N-type buried layer.
  • a body electrode 230 is formed on the N-type buried layer.
  • a PN structure is formed between the N-type buried layer and the first channel layer formed of P-type GaN, and the PN structure can be connected to both ends of the transistor in parallel by setting the voltage of the drain electrode and the body electrode.
  • the PN structure can conduct currents that are opposite to the current direction of the HHMT, which enriches the design and functions of the circuit.
  • the body electrode 230 is in contact with the two-dimensional electron gas phase. It is understandable that the body electrode 230 only needs to be in contact with the two-dimensional electron gas, and the specific position thereof is not further restricted.
  • the barrier layer on the (0001) plane is etched to expose the second channel layer on the (0001) plane, and then the body electrode 230 is formed on the second channel layer. Due to the spontaneous effect and the piezoelectric effect, A two-dimensional electron gas (2DEG) is formed at the interface between the first and second channel layers in the ⁇ 0001> direction and the barrier layer.
  • the body electrode is electrically connected to the N-type nitride semiconductor buried layer through the two-dimensional electron gas, and its potential is controlled.
  • the potential of the N-type semiconductor buried layer is floating, which is not conducive to stably controlling the threshold voltage of the device.
  • the two-dimensional electron gas formed spontaneously in the channel layer is used, and The two-dimensional electron gas is indirectly electrically connected with the N-type semiconductor buried layer to control the potential of the N-type buried layer, which in turn makes the arrangement of the body electrode more flexible.
  • the above-mentioned PN structure can also be applied in a circuit through the connection of the body electrode and the two-dimensional electron gas, so that the PN structure can conduct current in the reverse direction relative to the HHMT current, which enriches the design and functions of the circuit .
  • the two-dimensional electron gas Since there is still an immovable background positive charge in the channel layer when the two-dimensional electron gas is spontaneously formed, the two-dimensional electron gas attracted by the background positive charge.
  • the body electrode When the body electrode is at a negative high voltage during the turn-off of the device, the 2DHG is depleted, leaving the background negative charge.
  • the connection between the body electrode and the 2DEG will also be depleted due to the effect of the electric field.
  • Located between the gate and the drain All or part of the 2DEG and expose the background positive charge.
  • the positive background charge can partially offset the distribution of the electric field generated by the negative background charge and increase the voltage resistance of the device.
  • a third channel layer 160 is further formed before the barrier layer is formed on the first channel layer, the buried layer, and the second channel layer.
  • the manufacturing method may be: before the barrier layer is deposited in step 5, a third channel layer 160 is deposited first.
  • the third channel layer 160 may be unintentionally doped or intrinsic GaN. It is understandable that the third channel layer may also be GaN with a lower doping concentration. For example, the doping concentration is ⁇ 1E18/cm3, and the lower doping concentration can keep the channel well shut off. At the same time, it effectively reduces the scattering of doped atoms or ions to channel carriers. Or the third channel layer may also be InGaN.
  • the buried layer 150 When the buried layer 150 depletes 95-100% of the 2DHG at the corresponding channel, due to the effects of ion scattering, it will greatly increase the resistance of the transistor when it is turned on.
  • the arrangement of the third channel layer can significantly reduce the N-type semiconductor
  • the ion scattering effect of the buried layer can reduce the on-resistance of the transistor.
  • the decrease in electron mobility caused by ion scattering can be reduced by providing the third channel layer.
  • the first and second channel layers can be obtained by using materials with a lower band gap for the first and second channel layers. The gap between the channel layer and the barrier layer is larger.
  • the third channel layer is performed before the growth of the barrier layer, which makes little changes to the process flow.
  • an insulating layer 310 as shown in FIG. 22 is formed on other surfaces of the substrate except for the vertical surface 1003.
  • the insulating layer completely covers other surfaces.
  • the substrate when the substrate is a Si substrate, since the (111) plane of the Si substrate (1--1--1--) No difference in the surface properties, thus perpendicular to the surface of the substrate 1003 may be Si substrate (111) plane or (1--1--1--) plane.
  • the Si substrate may be a Si substrate with (110) or (112) plane.
  • the provision of the insulating layer can prevent Ga atoms from melting back to the Si substrate during growth.
  • the selective growth of nucleation layers, such as AlN is very difficult. That is to say, in addition to growing single crystal AlN on the vertical surface of silicon, amorphous or polycrystalline AlN is also prone to be formed on the insulating layer 400.
  • amorphous or polycrystalline AlN may have an adverse effect on the structure and function of the device. Therefore, the amorphous or polycrystalline part will be etched, or the corrosion gas containing Cl, such as Cl2 or HCL gas, will be introduced during growth.
  • the etching selection ratio between crystalline AlN and polycrystalline/amorphous AlN thereby removing the amorphous or polycrystalline AlN layer on the insulating layer 310, leaving the single-crystalline AlN layer on the vertical surface 1003. Since the nitride semiconductor containing Ga material is difficult to directly nucleate and grow on the insulating layer, the nitride semiconductor can be selectively grown only on the single crystal AlN layer formed on the vertical surface.
  • the polycrystalline or amorphous AlN layer is essentially an insulating layer, the nitride semiconductor containing Ga material is difficult to nucleate and grow on the polycrystalline or amorphous AlN layer, so the insulating layer can also be retained 310 on the polycrystalline or amorphous AlN layer.
  • the polycrystalline or amorphous AlN layer can also be removed.
  • the above-mentioned insulating layer may also be unnecessary. This is mainly because Ga atoms are compatible with Al2O3 or SiC, and there is no reflow phenomenon. Nitride semiconductors are easier to nucleate and grow on the vertical surface with a hexagonal symmetrical lattice structure, so that the vertical surface naturally has the ability of selective growth.
  • an insulating layer makes the process window for nucleation and growth on the vertical surface larger and more controllable. Therefore, when an Al2O3 or SiC substrate is used, an insulating layer 310 may also be formed on other surfaces except the vertical surface 1003.
  • An example of a method of forming an insulating layer 310 on surfaces other than the vertical surface 1003 is as follows.
  • a boss shape is formed by etching on the substrate.
  • the boss has two opposite vertical surfaces.
  • the vertical surface is the (111) plane of silicon.
  • SiN is grown on the vertical surface by using techniques such as LPCVD, and only the SiN on the sidewalls is retained by an etching technique with a vertical orientation.
  • SiO2 is grown through an oxidation process. Because the vertical surface is protected by SiN, there is no growth of SiO2, and a SiO2 layer is formed on the other surface of the silicon wafer.
  • the SiN on the vertical surface is etched away through a wet etching process such as hot phosphoric acid and most of the silicon dioxide on the other surfaces is retained.
  • the design of the insulating layer can effectively prevent the substrate material from affecting the performance of the device, which is beneficial to improve the withstand voltage and reduce the dark current.
  • the manufacturing method of the source electrode, the drain electrode and the gate electrode is exemplified as follows.
  • a thicker first metal layer 210 is formed on the first insulating layer formed on the first surface of the substrate by deposition and lift-off or deposition and laser positioning etching.
  • an insulating layer deposited on the outer, barrier layer of the transistor (0001 -) also have a small deposition surface, and then removing the barrier layer of the transistor (0001 -) by isotropic etching of the metal layer surface.
  • a second insulating layer 320 is formed by coplanar deposition on the first metal layer, and the growth thickness of the second insulating layer 320 is precisely controlled by CMP combined with etch-back or precisely controlled so that the height of the second insulating layer is set at the gate region of the transistor.
  • the barrier layer or the gate insulating layer at the gate region Expose the barrier layer or the gate insulating layer at the gate region. Then forming a first metal layer and a method similar to the second metal layer 220 is formed on the second insulating layer, the same, except the second metal layer deposited on the second insulating layer, the barrier layer of the transistor (0001 - ) will have a small deposition surface, and then removing the barrier layer of the transistor (0001 by isotropic etching - metal layer) surface. Then, continue coplanar deposition on the second metal layer to form a third insulating layer 330, and by etching back or precisely controlling the growth thickness of the third insulating layer, the height of the third insulating layer is set at the source region of the transistor.
  • a third metal layer 200 is formed on the third insulating layer, and then a source electrode is formed by photolithography.
  • a gate, a source, and a drain are formed between the two transistors at the same time.
  • the positions of the source electrode and the drain electrode can be exchanged, and the source electrode and the drain electrode can form an ohmic contact with the two-dimensional hole gas through steps such as annealing.
  • the gate electrode and the barrier layer form Schottky contact or are insulated and separated by the gate dielectric and the barrier layer.
  • the III-nitride semiconductor channel layer and barrier layer are grown on the above-mentioned specific surface of the above-mentioned substrate, such as GaN material or AlGaN material, when the surface is (0001) plane or (000-1) plane
  • a fourth insulating layer 340 is formed on the (0001) surface of the group III nitride semiconductor channel layer to protect the (0001) surface of the channel layer. It can be understood that the fourth insulating layer may extend to the non-polar surface of the group III nitride semiconductor channel layer parallel to the first and second surfaces of the substrate.
  • the existence of the two-dimensional electron gas 2DEG will respond to changes in the potential of the source, drain and gate, thereby increasing parasitic capacitance and leakage channels.
  • a radio frequency electronic device such as personal computers, mobile phones, digital cameras and other electronic equipment. It includes any of the above-mentioned transistors.
  • the power electronic device can be used in power amplifiers in the fields of mobile phone base stations, optical communication systems, etc., or can be a power supply device, and the power electronic device can include any of the above-mentioned transistors.
  • the hole-channel III-nitride transistor structure can reduce gate leakage current, has high threshold voltage, high power, and high reliability, and can achieve low conductivity.
  • the on-resistance and the normally-off state of the device can provide a stable threshold voltage, so that the hole-channel group III nitride transistor has good switching characteristics.
  • the solution of the present disclosure can also help to achieve one of the following effects: a higher channel density per unit area can be achieved; the integration density of the transistor is improved; the structure and preparation process of the transistor are relatively simple, which can effectively reduce the production cost .
  • the present disclosure provides a novel hole-channel group III nitride transistor structure and a manufacturing method thereof.
  • the process is simple, the cost is low, and higher channel density per unit area is realized, and it has high withstand voltage, high power and low power.
  • High-performance energy-saving normally closed hole-channel group III nitride transistors such as on-resistance.

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Abstract

本公开提供一种非平面空穴沟道晶体管及其制作方法，所述非平面空穴沟道晶体管具有一基片，所述基片表面具有包括垂直表面的台阶结构，以所述垂直表面为核心，侧向外延生长非平面沟道层，在所述沟道层上形成势垒层，从而同时在所述势垒层和所述沟道层的界面处形成二维空穴气和/或二维电子气。本公开内容提供具有工艺简单、成本低廉、在单位面积上实现更高的沟道密度，具有高耐受电压、高功率和低导通电阻等高性能、节能的常闭型空穴沟道III族氮化物晶体管。

Description

一种空穴沟道半导体晶体管、制造方法及其应用
相关申请的交叉引用
本公开要求于2020年4月13日提交中国专利局的申请号为202010288958.0、名称为“一种空穴沟道半导体晶体管、制造方法及其应用”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开内容涉及半导体领域，更具体而言，涉及一种空穴沟道III族氮化物半导体晶体管、制造方法及其应用。
背景技术
III族氮化物半导体是一种重要的新型半导体材料，主要包括AlN、GaN、InN及这些材料的化合物如AlGaN、InGaN、AlInGaN等。利用所述III族氮化物半导体具有的直接带隙、宽禁带、高击穿电场强度等优点，通过器件结构与工艺的优化设计，III族氮化物半导体在功率半导体和无线通信领域拥有巨大前景。目前虽然探索了实现空穴沟道III族氮化物晶体管的可能性，但迄今为止，制造这种类型的晶体管依然具有一定难度。
此外，现有的III族氮化物半导体晶体管的结构设计多为横向器件，单位面积上的集成度不够高。另外，现有的III族氮化物半导体器件晶体管为常开型器件，对节约能源很不利。
发明内容
鉴于此，本公开提供一种新颖的空穴沟道III族氮化物晶体管结构及其制造方法，旨在克服上述缺陷。
在下文中将给出关于本公开内容的简要概述，以便提供关于本公开内容某些方面的基本理解。应当理解，此概述并不是关于本公开内容的穷举性概述。它并不是意图确定本公开内容的关键或重要部分，也不是意图限定本公开内容的范围。其目的仅仅是以简化的形式给出某些概念，以此作为稍后论述的更详细描述的前序。
根据本公开内容的一方面，提供一种非平面空穴沟道半导体晶体管的制造方法，包括：
提供一基片，在其上表面刻蚀出台阶状结构，所述台阶状结构具有大致平行的第一表面和第二表面，以及分别连接第一表面和第二表面的垂直表面，且所述垂直表面的晶格具有六角对称性；
从所述垂直表面处为核心，受所述第二表面的限制，垂直所述第二表面侧向外延生长非平面沟道层；
在所述沟道层上形成势垒层，从而同时在所述势垒层和所述沟道层的界面处形成二维空穴气及不可移动的背景负电荷；和/或所述二维电子气及不可移动的背景正电荷。
可选地，其中所述基片选自Al2O3、4H-SiC、(110)面的硅或(112)面的硅。
可选地，其中所述垂直表面选自Al2O3的(0001)面，4H-SiC的(0001)面或硅的(111)面。
可选地，其中在所述基片的除所述垂直表面外的其他表面上形成第一绝缘层。
可选地，其中所述第一绝缘层形成的方法包括在所述基片上共面沉积SiN，通过垂直取向的蚀刻技术，仅保留所述垂直表面上的SiN，然后在除垂直表面以外的其他表面上形成二氧化硅层，进而通过湿法腐蚀去除侧壁上的SiN，保留所述其它表面上的二氧化硅层。
可选地，还包括在所述垂直表面处形成成核层，所述成核层形成在所述垂直表面的部分表面上；或所述成核层形成在所述垂直表面的全部表面上。
可选地，其中由所述成核层材料形成的多晶或非晶层去除或保留在所述第一绝缘层上。
可选地，其中当所述基片为硅基片时，必须具有所述成核层。
可选地，还包括以所述成核层为核心，侧向外延生长一缓冲层。
可选地，还包括以所述成核层或以所述缓冲层为核心，侧向外延生长第一沟道层。
可选地，还包括以所述第一沟道层为核心，侧向外延生长一N型掩埋层。
可选地，其中所述掩埋层能耗尽95-100％的二维空穴气。
可选地，其中能通过将所述N型掩埋层与所述二维空穴气构成体二极管。
可选地，还包括以所述第一沟道层或所述掩埋层为核心，继续侧向外延生长第二沟道层。
可选地，其中所述第一沟道层和第二沟道层的材料相同或不同。
可选地，其中所述第一沟道层为N-型GaN，所述第二沟道层为GaN或者所述第一沟道层为P-型GaN，所述第二沟道层为GaN。
可选地，还包括露出所述第一沟槽层的(0001 -)面；或同时露出所述第一沟道层的(0001)面和(0001 -)面。
可选地，其中还包括去除覆盖在所述第一沟道层<0001>方向的所述势垒层。
可选地，其中在所述第一沟道层<0001>方向上形成第四绝缘层。
可选地，其中当所述第一沟道层为P-型GaN时，所述第一沟道层与所述N型掩埋层形成PN结构。
可选地，还包括在沉积所述势垒层之前，沉积形成第三沟道层。
可选地，其中所述第三沟道层为非故意掺杂、或本征的GaN；或者为掺杂浓度较低的GaN或者InGaN。
可选地，还包括形成晶体管的源电极、漏电极和栅电极。
可选地，其中所述源电极和漏电极与所述晶体管的所述沟道层进行物理接触，并与所述二维空穴气欧姆接触；或者所述源电极和漏电极与所述势垒层进行物理接触，形成欧姆接触。
可选地，其中所述栅电极与所述势垒层形成肖特基接触或形成绝缘接触。
可选地，其中所述绝缘接触为在所述势垒层上对应于所述栅电极位置处形成一栅绝缘层。
可选地，其中所述栅绝缘层的形成方法是通过MOCVD法形成所述势垒层后，在线(in-situ)同位生长所述栅绝缘层；或者所述栅绝缘层在与所述势垒层不同的生长设备中另行生长。
可选地，其中所述漏极、栅极和源极在大致垂直所述基片的第一表面的方向上依序设置，所述源极和漏极的位置能互换。
可选地，还包括形成与所述掩埋层连接的体电极。
可选地，其中通过与所述掩埋层物理接触形成所述体电极。
可选地，其中通过与所述二维电子气欧姆接触形成所述体电极，进而通过所述二维电子气使得所述体电极与所述掩埋层电性连接。
可选地，其中所述体电极在所述器件被关闭时，耗尽第二和第三电极之间的全部或部分二维电子气，进而仅剩下所述背景正电荷，从而部分抵消原2DHG内所述背景负电荷产生的电场，使得所述电场分布更均匀。
可选地，其中所述漏极的形成方法进一步包括通过在所述基片第一表面上形成第一金属层，各项同性刻蚀去除所述晶体管的所述势垒层(0001 -)面上少量沉积的所述第一金属层。
可选地，其中所述栅极的形成方法进一步包括在所述第一金属层上共面沉积形成第二绝缘层，所述第二绝缘层的高度露出所述势垒层或所述栅绝缘层，然后再在所述第二绝缘层上形成第二金属层，各项同性刻蚀去除所述晶体管的所述势垒层(0001 -)面上少量沉积的所述第二金属层。
可选地，其中所述源极的形成方法进一步在所述第二金属层上共面沉积形成第三绝缘层，然后再在所述第三绝缘层上形成第三金属层，然后通过光刻蚀刻形成所述源极。
根据本公开内容的另一方面，提供一种非平面空穴沟道半导体晶体管，包括：
一基片，其上形成一台阶状结构，所述台阶状结构具有大致平行的第一表面和第二表面，以及分别连接第一表面和第二表面的垂直表面，且所述垂直表面的晶格具有六角对称性；
以所述垂直表面为核心，受所述第二表面的限制，垂直所述第二表面侧向外延生长的非平面沟道层；
在所述沟道层上形成所述势垒层，从而同时在所述势垒层和所述沟道层的界面处形成二维空穴气和/或所述二维电子气。
可选地，其中所述基片选自Al2O3、本征GaN、4H-SiC以及(110)面的硅或者(112)面的硅。
可选地，其中所述垂直表面选自Al2O3的(0001)面，4H-SiC的(0001)面以及硅的(111)面。
可选地，其中在所述基片的除所述垂直表面外的其他表面上具有第一绝缘层。
可选地，其中在所述基片的所述垂直表面上具有一成核层。
可选地，其中在所述第一绝缘层上具有所述成核层材料形成的多晶或非晶层。
可选地，其中在所述成核层外还具有一缓冲层，所述缓冲层具有单层或多层结构。
可选地，其中在所述成核层外具有第一沟道层。
可选地，其中在所述缓冲层外具有第一沟道层。
可选地，其中在所述第一沟道层上具有一N型掩埋层，所述N型掩埋层与所述二维空穴气形成体二极管结构。
可选地，其中还具有一第二沟道层。
可选地，其中所述第一沟道层和第二沟道层的材料相同或不同。
可选地，其中所述第一沟道层为N-型GaN或P-型GaN，所述第二沟道层为GaN。
可选地，其中还具有第三沟道层，所述第三沟道层为非故意掺杂或本征的GaN，或者为InGaN或者所述第三沟道层为掺杂浓度较低的GaN。
可选地，其中在所述第一沟道层<0001>方向上不具有所述势垒层。
可选地，其中在所述第一沟道层<0001>方向上具有第四绝缘层。
可选地，其中所述当所述第一沟道层为P型GaN时，所述第一沟道层与所述掩埋层形成体二极管结构。
可选地，其中还具有源电极、漏电极和栅电极。
可选地，其中所述源电极/漏电极与所述晶体管的所述沟道层进行物理接触，并与所述二维空穴气欧姆接触；或者所述源电极/漏电极与所述势垒层进行物理接触，形成欧姆接触。
可选地，其中所述栅电极与所述势垒层形成肖特基接触或形成绝缘接触。
可选地，其中绝缘接触是在所述栅电极和所述势垒层之间具有一栅绝缘层。
可选地，其中所述漏极、栅极和源极在大致垂直所述基片的第一表面的方向上依序设置，所述源极和漏极的位置能互换。
可选地，其中还具有一体电极，所述体电极与所述掩埋层电性连接，通过所述体电极的设置，在稳定阈值电压的同时使得所述掩埋层与所述二维空穴气形成的体二极管导通相对于所述晶体管沟道电流方向反向的电流；或者通过所述体电极的连接，实现所述掩埋层与所述P-型GaN构成的所述第一沟道层形成的体二极管的电路应用。
可选地，其中所述体电极与所述掩埋层物理连接，或者所述体电极通过所述二维电子气欧姆接触。
可选地，其中所述第一沟道层中对应于漏极区域进行P-型掺杂，所述第二沟道层中对应于源极区域进行P-型掺杂。
根据本公开内容的另一方面，提供一种非平面空穴沟道半导体器件，包括：
一基片，在垂直所述基片的上表面外延生长非平面的沟道层；
所述沟道层包括第一和第二沟道层；
在所述沟道层上形成势垒层(130)，从而同时在所述势垒层(130)和所述沟道层的界面处形成二维空穴气和/或所述二维电子气。
可选地，其中所述基片选自Al2O3、本征GaN、4H-SiC以及(110)面的硅或者(112)面的硅。
可选地，其中在所述基片的上表面上具有第一绝缘层。
可选地，其中在所述基片上具有一成核层。
可选地，其中在所述成核层外还具有一缓冲层，所述缓冲层具有单层或多层结构。
可选地，其中第一和第二沟道层平行所述衬底的上表面上下叠置。
可选地，其中所述第一和第二沟道层之间夹有N型掩埋层。
可选地，其中所述N型掩埋层与所述二维空穴气形成体二极管结构。
可选地，其中所述第一沟道层和所述第二沟道层的材料相同或不同。
可选地，其中所述第一沟道层为N-或P-型GaN，所述第二沟道层为本征GaN或N-型GaN。
可选地，其中还具有第三沟道层，所述第三沟道层为非故意掺杂的GaN，InGaN或AlInGaN。
可选地，其中在所述第一沟道层<0001>方向上不具有所述势垒层。
可选地，其中在所述第一沟道层<0001>方向上具有第四绝缘层。
可选地，其中当所述第一沟道层为P型GaN时，所述第一沟道层与所述掩埋层形成体二极管结构。
可选地，其中还具有源极、漏极和栅极。
可选地，其中所述源极/漏极与所述器件的所述沟道层进行物理接触，并与所述二维空穴气欧姆接触；或者所述源极/漏极与所述势垒层进行物理接触，形成欧姆接触。
可选地，其中所述栅极与所述势垒层形成肖特基接触或形成绝缘接触。
可选地，其中绝缘接触是在所述栅极和所述势垒层之间具有一栅介质层。
可选地，其中所述源、栅和漏电极在大致垂直所述基片的上表面的方向上依序设置；所述源和漏的位置能互换。
可选地，其中还具有一体电极，所述体电极与所述掩埋层电性连接。
可选地，其中所述体电极与所述掩埋层物理连接，或者所述体电极通过所述二维电子气欧姆接触。
根据本公开内容的另一方面，提供了一种射频器件，其包括如前所述的晶体管。
根据本公开内容的另一方面，提供了一种电力功率器件，其包括如前所述的晶体管。
附图说明
下面，参照附图说明本公开的具体内容，这将有助于更加容易地理解本公开的目的、特点和优点。附图只是为了示出本公开内容的原理。在附图中不必依照比例绘制出单元的尺寸和相对位置。在附图中：
图1-12为一种空穴沟道III族氮化物晶体管结构及其制造方法的示意图；
图13-15为可选的空穴沟道III族氮化物晶体管结构及其制造方法的示意图；
图16-17为可选的空穴沟道III族氮化物晶体管结构及其制造方法的示意图；
图18为可选的空穴沟道III族氮化物晶体管结构及其制造方法的示意图；
图19-21为可选的空穴沟道III族氮化物晶体管结构及其制造方法的示意图；
图22-25为可选的空穴沟道III族氮化物晶体管结构及其制造方法的示意图；
图26-31为可选的空穴沟道III族氮化物晶体管结构及其制造方法的示意图；
图32-33为可选的空穴沟道III族氮化物晶体管结构及其制造方法的示意图；
图34为可选的空穴沟道III族氮化物晶体管的制造方法的示意图。
具体实施方式
在下文中，将结合附图对本公开内容的示例性公开内容进行描述。为了清楚和简明起见，在说明书中并未描述实现本公开内容的所有特征。然而，应该了解，在实现本公开内容的过程中可以做出很多能够实施本公开内容的方式，以便实现开发人员的具体目标，并且这些方式可能会随着本公开内容的不同而有所改变。
在此，还需要说明的是，为了避免因不必要的细节而使本公开内容变得复杂，在附图中仅仅示出了与根据本公开内容的方案密切相关的器件结构，而省略了一些细节。
应理解的是，本公开内容并不会由于如下参照附图的描述而只限于所描述的实施形式。本公开内容中，在可行的情况下，不同实施方式之间的特征可替换或组合、或在一个实施方式中可省略一个或多个特征。
在以下具体实施方式中可参照附图，附图示出了本公开内容的一部分并示出了示例性实施方式。此外，将理解的是，在不脱离所请求保护的主题的范围的情况下，可以利用其它实施方式并可以做出结构和/或逻辑改变。还应当指出，方向和位置(例如，上、下、顶部、底部、等等)仅用于帮助对附图中的特征的描述，并非在限制性意义上仅采用以下具体实施方式。
如在本公开内容的说明书和所附权利要求书中所使用的术语，除非上下文另外明确指示，“一”、“一个”和“所述”也包括复数形式。还将理解的是，如本文中所使用的术语“和/或”指代并包括相关联的列出的项中的一个或多个的任何和所有可能的组合。
III族氮化物半导体主要有纤锌矿(Wurtzite)和闪锌矿(Zinc-blende)两种晶体结构。由于纤锌矿具有稳定及较容易获得较高晶体质量的优势，实际应用的III族氮化物半导体通常具有纤锌矿结构。
因此具体地，本公开中的III族氮化物晶体管结构包括使用纤锌矿(Wurtzite)晶体结构的III族氮 化物晶体管。可选地，III族氮化物晶体管为空穴沟道III族氮化物晶体管；可选地，空穴沟道III族氮化物晶体管是常闭的空穴沟道氮化物晶体管；更可选地，所述常闭的空穴沟道氮化物晶体管是常闭的空穴沟道氮化镓晶体管。
如图1-3所示，III族氮化物晶体管包括基片100，在氮化物晶体管中，可采用独立的衬底或块状的GaN材料，由于制备GaN材料非常昂贵，一种可行的方式是使GaN在异质基片上外延生长并制作器件。异质基片材料主要有Al2O3(蓝宝石)、硅以及SiC等。其中Al2O3的(0001)面、4H-SiC的(0001)面以及硅的(111)面等都具有六角对称的晶格结构，适于作为异质生长的基片面，氮化物半导体在其上成核与生长，有利于获得较高质量的GaN或AlN晶体。
另外，蓝宝石基片由于其成本低，以及氮化镓外延层与蓝宝石基片之间的晶格较为匹配，因此得到了大量的使用。若考虑到散热性，采用硅基片制备GaN外延层也越来越多，但采用硅基片需要考虑漏电流和耐压的问题。在本公开的工艺流程中对此进行了精心设计，能够避免硅基片材料对器件性能产生影响，对提高耐压和减小暗电流都有明显帮助。
综上，异质基片的材质可以根据实际需要选取，本公开内容并不限制基片的具体材料，只要基片材料为能够满足在其表面上形成的垂直于其表面的垂直沟槽的侧表面具有六角对称性的晶格结构的基片材料皆可。在本公开中基片材料可以为Al2O3(蓝宝石)，4H-SiC、硅以及本征GaN等。
在本公开中，如图1所示，在基片100上通过光刻蚀刻形成台阶状结构，台阶状结构由基片100的第一表面1001，与第一表面平行的第二表面1002以及分别连接着第一表面1001和第二表面1002的垂直表面1003构成，垂直表面具有六角对称性，示例性地，台阶状的阶差深度约为5微米。
在垂直表面上形成成核层101，成核层101可以形成在该垂直表面的部分表面上，或在垂直表面的全部表面上。对于硅材料而言，由于Ga原子回熔效应的影响，诸如GaN的半导体层不能直接在基片上生长，通常需要在基片上生长如AlN、GaN成核层等结构才能进一步生长GaN外延层。而GaN可以直接在Al2O3(蓝宝石)、SiC、或本征GaN上成核成长，但若从晶体控制质量的角度出发，可以在工艺过程中引入成核层101.
以成核层101为核心，受基片100的第二表面1002的限制，垂直于第二表面向上侧向外延生长第一沟道层110，然后继续侧向外延生长第二沟道层120。第一沟道层110和第二沟道层120的材料可以相同或不同。示例性地，第一沟道层为N-型掺杂的GaN层，第二沟道层为GaN层，或者第一沟道层为P-型掺杂的GaN层，第二沟道层为GaN层，其掺杂浓度为1E17-1E20/cm3。可以理解的是，基片也可不刻蚀成台阶状，例如可以直接在基片的上表面上进行成核生长以形成第一和第二沟道层。
可选地，如图2所示，在成核层和第一沟道层之间还可以具有缓冲层140，缓冲层140可以具有单层或多层结构，缓冲层的材料例如可以是AlN、GaN、AlGaN、InGaN、AlInN和AlGaInN中一种或多种。
可选地，第二沟道层120中在后续对应于晶体管形成源电极的部分区域处，进行相应的P-型掺杂，第一沟道层110中对应于晶体管形成漏电极的部分区域处也可以进行P-型掺杂。P-型掺杂可以有效地降低相应区域的接触电阻。P-型掺杂浓度可为1E17-1E20/cm3。
去除覆盖在第一沟道层上的第一表面的方向上的两侧的第二沟道层120，露出第一沟道层。在第一沟道层和第二沟道层上形成势垒层130，例如AlGaN。
由于沟道层和势垒层采用III族氮化物半导体，III族氮化物半导体具有极性，因此可以在极性半导体的表面或两种不同的极性半导体界面处存在固定极化电荷。这些固定极化电荷的存在可吸引可移动的空穴和电子从而形成二维空穴气2DHG和二维电子气2DEG。这些二维空穴气2DHG和二维电子气2DEG的产生不需要附加电场，也不依赖于半导体内的掺杂效应，是自发产生的，由于不必掺杂，二维空穴气受到的离子散射作用大大减少，因此具有较高的迁移率。
形成势垒层后，在<0001 ->方向的第一和第二沟道层内与势垒层交界的界面处形成2DHG。或者去除覆盖在第一沟道层上的<0001 ->方向和<0001>方向上的第二沟道层120，露出第一沟道层。在第一沟道层和第二沟道层上形成势垒层130，例如AlGaN。从而在<0001 ->方向的第一和第二沟道层内与势垒层交界的界面处形成2DHG，同时在＜0001＞方向的第一和第二沟道层内与势垒层交界的界面处形成2DEG。
形成晶体管的源电极200、漏电极210和栅电极220，源电极200、漏电极210和栅电极220的位置不做具体限定，源电极和漏电极可以与晶体管的沟道层(110/120)进行物理接触，并与二维空穴载流子气(2DHG)欧姆接触，或者源电极和漏电极直接与势垒层130进行物理接触。另外，栅电极220在势垒层130上与势垒层130能形成绝缘接触或者肖特基接触，其中绝缘层接触是指在栅电极和势垒层之间形成一栅绝缘层300，栅绝缘层可以是二氧化硅、高K介质材料等，栅绝缘层300可以起到对势垒层的表面钝化作用，有利于降低晶体管的栅漏电流以及将晶体管作为电力电子器件。
当栅极直接制作在势垒层上，则具有较大的栅漏电流，此时势垒层再保持足够高的禁带宽度时，也起到介质层的作用，如此制成的晶体管多作为射频(RF)器件。
示例性地，如图3所示，源电极200、漏电极210和栅电极220可以在垂直于基片100的第一表面的方向上排列。其中漏电极210更靠近基片100的第一表面1001。可以理解的是，源电极也可以更靠近基片100的第一表面1001。
现参照图4-12以及图34来详细描述用于制造该结构的半导体器件的制造方法。
步骤1，如图4所示，提供一基片100，在基片100上形成光刻图形，然后在其上表面蚀刻形成台阶状结构，示例性地，刻蚀的深度约为5微米。台阶状结构由基片100的第一表面1001、与第一表面1001平行的第二表面1002以及分别连接着第一表面1001和第二表面1002的垂直表面1003构成，其中垂直表面具有六角对称的晶格结构，具有六角对称晶格结构的垂直表面易于氮化物半导体的成核与生长，而其他表面则不易于氮化物半导体的成核与生长。
步骤2：如图5所示，在垂直表面上形成成核层101，成核层101可以形成在垂直表面的部分表面上，或形成在垂直表面的全部表面上。成核层材料，示例性地如GaN、ALN等。
对于硅材料而言，由于Ga原子回熔效应的影响，GaN不能直接在基片上生长，通常需要在基片上生长如成核层等结构才能进一步生长GaN外延层。
步骤3：如图6所示，以成核层101为核心，受基片100的第二表面1002的限制，沿着基片的垂直表面向上以及沿着基片的第二表面向侧面外延生长缓冲层140后再侧向外延生长第一沟道层110。可以理解的是，缓冲层非必须，因此也可以如图7所示以成核层为核心侧面外延生长第一沟道层110。
步骤4：如图8所示，以第一沟道层110为核心，然后继续侧向外延生长第二沟道层120。第一沟道层110和第二沟道层120的材料可以相同或不同。例如，可以在侧向外延生长第一沟道层的过程中进行N-型掺杂或P-型掺杂。可以理解的是，此处是以后续漏极形成在第一沟道层为例，如果后续源极形成在第一沟道层处，则在侧向外延生长第二沟道层的过程中进行N-型掺杂或P-型掺杂。
可选地，可以在第二沟道层120中在后续对应于晶体管形成源电极的部分区域处，进行相应的P-型掺杂，第一沟道层110中对应于晶体管形成漏电极的区域处也可以进行P-型掺杂。P-型掺杂可以有效地降低相应区域的接触电阻。
步骤5：如图9所示，去除覆盖在第一沟道层上的<0001 ->方向上的第二沟道层120，露出第一沟道层的(0001 -)面，同时去除覆盖在第一沟道层上的<0001>方向上的第二沟道层120，露出第一沟道层的(0001)面。然后如图10所示，在第一沟道层和第二沟道层上形成势垒层130，例如AlGaN。从而在<0001 ->方向的第一和第二沟道层内与势垒层交界的界面处形成2DHG以及不可移动的背景负电荷；在＜0001＞方向的第一和第二沟道层内与势垒层交界的界面处形成2DEG以及不可移动的背景正电荷。
步骤6：如图11所示，形成晶体管的源电极200、漏电极210和栅电极220，源电极200、漏电极210和栅电极220的位置不做具体限定，源电极和漏电极可以与晶体管的沟道层(110/120)进行物理接触，并与二维空穴载流子气(2DHG)欧姆接触，或者源电极和漏电极直接与势垒层130进行物理接触。另外，栅电极220在势垒层130上与势垒层130能形成绝缘接触或者肖特基接触。
如图12所示，其中绝缘层接触是指在栅电极和势垒层之间形成一栅绝缘层300，栅极绝缘层300的形成方法可以在MOCVD腔室内形成势垒层后，在线(in-situ)同位生长。栅极绝缘层300的形成方法也可以在与势垒层不同的生长设备中单独生长。但应当指出，在线同位生长栅极绝缘层的质量更好，因此，优选选择在线(in-situ)同位生长绝缘层。
栅绝缘层可以是二氧化硅、SiN、高K介质材料等，栅绝缘层300可以起到对势垒层的表面钝化作用，有利于降低晶体管的栅漏电流以及晶体管在电力电子方面的应用。如果栅电极直接制作在势垒层上， 如此制成的晶体管则更多应用在射频(RF)器件中，因为相对于具有栅绝缘层的晶体管而言，其具有较大的栅漏电流。
示例性地，源电极200、漏电极210和栅电极220可以在垂直于基片100的第一表面的方向上排列。其中漏电极210更靠近基片100的第一表面1001。栅电极220位于漏电极210与源电极200之间。
可选地，当第一和第二沟道层中的源极区域和漏极区域存在P-型掺杂的时候，源电极和漏电极与晶体管的沟道层进行物理接触，如此有利于降低欧姆接触电阻。
由此，通过垂直表面上生长出的具有不规则横截面的非平面型的III族氮化物晶体管，可以提高器件的集成度，能有效降低栅漏电流，且制备工艺简单，可以通过垂直表面进行侧向外延的方式在形成二维空穴载流子气的同时，形成了二维电子载流子气，能有效提高空穴的迁移率。
如图13所示，在第一沟道层和第二沟道层之间还具有一N型掩埋层。
其具体的制造方法如图14所示，在步骤4中以AlN成核层为核心，受基片100的第二表面1002的限制，侧向外延生长第一沟道层110后，在侧向外延生长第二沟道层120前，先进行侧向外延生长形成N型掩埋层，N型掩埋层示例性地为N型GaN层。然后以掩埋层为核心继续侧向外延生长第二沟道层120。覆盖在N型掩埋层掺杂浓度示例性地为1E17-5E19/cm3，更优的为1E+18/cm3-5E+19/cm3。N型GaN层可以耗尽沟道层中的二维空穴气，进而导致器件具有常闭状态；可以理解的是，掺杂可以是渐变的，在此不再赘述。可选地，N型埋层在<0001 ->方向的投影落在栅电极在该方向上的投影范围内，或与栅电极在该方向上的投影有部分的重叠范围。N型掩埋层的设置，如其掺杂浓度、尺寸参数等可以通过器件参数设置以满足耗尽其上方95％-100％的二维空穴气即可，二维空穴气的浓度越高，相应的掺杂浓度可以随之提高。
然后如图15所示，去除覆盖在第一沟道层上的<0001 ->方向上的第二沟道层120和掩埋层，露出第一沟道层的(0001 -)面，同时去除覆盖在第一沟道层上的<0001>方向上的第二沟道层120和掩埋层，露出第一沟道层的(0001)面。
可以理解的是，在形成N型GaN层与2DHG沟道的同时，也同时实现了体二极管的结构。
N型GaN层在导致器件可以具有常闭状态的情况下，还同时形成与2DHG的一种PN结构，其中2DHG构成了该PN结构中的“P”部分。PN结构整合制造在晶体管结构中，可以通过后续电极的连接将这种PN结构进行各种的电路应用，丰富了电路的设计和功能。示例性地，在电路应用中，PN结构可以导通相对于HHMT电流方向反向的电流。
可选地，还具有体电极230，体电极连接到N型掩埋层。示例性，如图16所示，体电极可以通过蚀刻势垒层、第二沟道层的非极性或半极性面刻蚀出到达N型掩埋层的通孔后再进一步填充金属形成体电极230。
可以理解的是，如图17所示，体电极的形成方法还可以完全去除或部分去除覆盖在第一沟道层上的<0001>方向上的势垒层露出N型掩埋层，进而在露出的N型掩埋层上形成体电极230。
需要说明的是，当不存在体电极230时，N型半导体掩埋层的电势是浮动的，不利于稳定的控制器件的阈值电压。
此外，由N型掩埋层与由P-型GaN形成的第一沟道层之间形成了PN结构，PN结构能通过漏电极和体电极的电压设置并联在晶体管的两端。在电路应用中，PN结构可以导通相对于HHMT电流方向反向的电流，丰富了电路的设计和功能。
可选地，如图18所示，还具有一体电极230，体电极230与二维电子气相接触。可以理解的是，体电极230与二维电子气接触即可，不对其具体位置进行进一步的限制。示例性地，通过刻蚀(0001)面的势垒层，露出(0001)面的第二沟道层，进而在第二沟道层上形成体电极230，由于基于自发效应和压电效应，在＜0001＞方向的第一和第二沟道层内与势垒层交界的界面处形成二维电子气(2DEG)。由此，体电极通过二维电子气与N型氮化物半导体掩埋层电连接并控制其电位。
应当指出的是，当不存在体电极230时，N型半导体掩埋层的电势是浮动的，不利于稳定的控制器 件的阈值电压，此时利用沟道层中自发形成的二维电子气，并通过二维电子气与N型半导体掩埋层间接电连接，控制N型掩埋层的电位，进而也使得体电极的设置更加灵活。可选地，上述的PN结构也可以通过这种体电极与二维电子气的连接方式应用在电路中，使得PN结构可以导通相对于HHMT电流方向反向的电流，丰富电路的设计和功能。
由于沟道层中在自发形成二维电子气时还存在不可移动的背景正电荷，背景正电荷吸引了的二维电子气。体电极在器件的关闭过程中由于漏极电极处于负高电压，2DHG被耗尽，剩下了背景负电荷，体电极与2DEG的连接由于电场作用也会耗尽位于栅极和漏极之间的全部或部分2DEG并露出背景正电荷。背景正电荷可部分抵消背景负电荷产生的电场的分布并增加器件的耐压能力。
可选地，如图19-21所示，在第一沟道层、掩埋层和第二沟道层上形成势垒层之前，还形成一第三沟道层160。如图所示，其制作方法可以是，在上述步骤5中淀积形成势垒层前，先沉积形成一第三沟道层160。第三沟道层160可为非故意掺杂或本征的GaN。可以理解的是，第三沟道层也可以是掺杂浓度较低的GaN，示例性地，掺杂浓度<1E18/cm3，该较低的掺杂浓度可以在保持对沟道良好关断的同时有效降低掺杂原子或离子对沟道载流子的散射。或者第三沟道层也可以是InGaN。
当掩埋层150在耗尽对应沟道处95-100％的2DHG的同时，由于离子散射等作用，会大幅升高晶体管导通时的电阻，第三沟道层的设置可以显著降低N型半导体掩埋层所带来的离子散射作用，从而可以降低晶体管导通电阻。此外，通过设置通过第三沟道层可以减少离子散射导致的电子迁移率的下降，另外，通过使第一和第二沟道层采用更低禁带宽度的材料可以获得第一和第二沟道层与势垒层更大的禁带宽度差异。另外，第三沟道层在势垒层生长前进行，对工艺流程的改变小。
可选地，在基片除垂直表面1003外的其他表面上形成有如图22所示的一绝缘层310。可选地，绝缘层全部覆盖其他表面。
应当指出的是，当基片为Si基片时，由于Si基片的(111)面与(1 -1 -1 -)面没有性质差异，因此基片的垂直表面1003可以是Si基片的(111)面或(1 -1 -1 -)面。Si基片可以是采用(110)或(112)面的Si基片。通过绝缘层的设置可以防止生长时Ga原子对Si基片的回熔作用。此外由于成核层，例如AlN的选区生长是很困难的，也就是说除了在硅的垂直表面上生长形成单晶AlN外，在绝缘层400上也容易生成非晶或多晶的AlN。这些非晶或多晶的AlN对器件的结构和功能可能具有不良影响，因此会通过蚀刻非晶或多晶部分，或者生长时引入含Cl的腐蚀气体，例如Cl2或HCL气体，利用气体对单晶AlN和多晶/非晶AlN之间的蚀刻选择比，从而去除绝缘层310上的非晶或多晶AlN层，保留垂直表面1003上的单晶AlN层。由于含有Ga材料的氮化物半导体难于在绝缘层上直接成核生长，从而可以使得该氮化物半导体只在垂直表面形成的单晶AlN层上实现选择性生长。
可以理解的是，由于多晶或非晶的AlN层本质上也是一种绝缘层，含有Ga材料的氮化物半导体难于在多晶或非晶的AlN层上成核生长，因此也可以保留绝缘层310上的多晶或非晶的AlN层。可选地，还可以将多晶或非晶的AlN层去除。
可以理解的是，当采用Al2O3或SiC基片时，上述绝缘层也可以不需要。这主要是因为Ga原子与Al2O3或SiC是兼容的，没有回熔现象。氮化物半导体在具有六角对称晶格结构的垂直表面上更容易成核与生长，从而垂直表面自然具有选区生长的能力。
进一步可以理解的是，在采用Al2O3或SiC基片时，具有绝缘层则使得垂直表面上的成核与生长的工艺窗口更大更可控。因此，在采用Al2O3或SiC基片时，也可以为在除垂直表面1003外的其他表面上形成有一绝缘层310。
除垂直表面1003外的其他表面上形成有一绝缘层310的方法示例性如下。
如图23-25所示，在基片上蚀刻形成一凸台形状，凸台具有相对的两个垂直表面，示例性地，当基片为硅时，垂直表面为硅的(111)面。然后在垂直表面上通过使用LPCVD等技术生长SiN，通过具有垂直取向的刻蚀技术，仅保留在侧壁的SiN。然后通过氧化工艺生长SiO2，垂直表面由于有SiN的保护，因此没有SiO2的生长，而在硅片的其他表面上形成了一SiO2层。接着，在利用SiN和SiO2的刻蚀选择比，通过热磷酸等湿法蚀刻工艺，刻蚀掉垂直表面的SiN而保留其他表面上的大部分二氧化硅。
绝缘层的设计能有效避免基片材料对器件性能产生影响，有利于提高耐压和减小暗电流。
参照图26-31，源极、漏极和栅极的制作方法示例性说明如下。
在形成HHMT晶体管后，通过沉积及剥离或沉积及激光定位刻蚀等方法在基片第一表面上形成的第一绝缘层上形成较厚的第一金属层210，第一金属层除了在第一绝缘层上沉积外，在晶体管势垒层的(0001 -)面上也会有少量沉积，然后通过各项同性刻蚀去除晶体管势垒层的(0001 -)面上的金属层。然后在第一金属层上共面沉积形成第二绝缘层320，通过CMP结合回刻或精确控制第二绝缘层320的生长厚度，使得第二绝缘层的高度设置在晶体管的栅极区域处，露出栅极区域处的势垒层或栅绝缘层。然后与第一金属层形成方法类似的，在第二绝缘层上形成第二金属层220，同样的，第二金属层除了在第二绝缘层上沉积外，在晶体管势垒层的(0001 -)面上也会有少量沉积，然后通过各向同性腐蚀去除晶体管势垒层的(0001 -)面上的金属层。接着，继续在第二金属层上共面沉积形成一第三绝缘层330，通过回刻或精确控制第三绝缘层的生长厚度，使得第三绝缘层的高度设置在晶体管的源极区域处，露出源极区域处的势垒层或第二沟道层。然后类似的，在第三绝缘层上形成第三金属层200，，然后通过光刻刻蚀形成源电极。从而如图所示，同时在两个晶体管之间形成栅极、源极和漏极。
可以理解的是，源极和漏极的位置可以互相交换，源极和漏极可以通过退火等步骤与二维空穴气形成欧姆接触。栅电极与势垒层形成肖特基接触或者被栅介质与势垒层绝缘隔开。
如前所述，上述基片的上述特定面上生长有III族氮化物半导体沟道层和势垒层，例如GaN材料或AlGaN材料，当其表面是(0001)面或(000-1)面时，都具有镓极性或氮极性，即具有<0001>或<0001 ->取向。从而能在<0001 ->方向的沟道层内靠近沟道层和势垒层界面处有2DHG，在＜0001＞方向的沟道层内靠近沟道层和势垒层的界面处有2DEG。
可选地，如图32所示，去除在了＜0001＞方向上的势垒层，从而无法再在＜0001＞方向上形成二维电子气2DEG。或者如图33所示，在III族氮化物半导体沟道层的(0001)面上形成第四绝缘层340以保护沟道层的(0001)面。可以理解的是，第四绝缘层可以延伸到III族氮化物半导体沟道层的平行于基片第一和第二表面的非极性面上。
二维电子气2DEG的存在，会对源极、漏极和栅极的电势变化产生响应，从而增加寄生电容和漏电通道。
一种射频电子器件，例如个人计算机，手机，数码相机等其它电子设备。包括上述的晶体管中的任一种。
一种电力电子器件，电力电子器可以用于移动电话基站、光通信系统等领域中的功率放大器，或者可以是一种电源器件，电力电子器件可以包括上述的晶体管的任一种。
本公开内容的方案至少能有助于实现如下效果之一：空穴沟道III族氮化物晶体管结构能够减小栅极漏电流，具有高阈值电压、高功率、高可靠性，能够实现低导通电阻和器件的常关状态，能够提供稳定的阈值电压，从而使得空穴沟道III族氮化物晶体管具有良好的开关特性。
本公开内容的方案还能有助于实现如下效果之一：可以在单位面积上实现更高的沟道密度；提升了晶体管的集成密度；晶体管的结构和制备工艺较为简单，能有效减低生产成本。
以上结合具体的实施方式对本公开内容进行了描述，但本领域技术人员应该清楚，这些描述都是示例性地，并不是对本公开内容的保护范围的限制。本领域技术人员可以根据本公开内容的精神和原理对本公开内容做出各种变型和修改，这些变型和修改也在本公开内容的范围内。
工业实用性
本公开提供一种新颖的空穴沟道III族氮化物晶体管结构及其制造方法，工艺简单、成本低廉、在单位面积上实现更高的沟道密度，具有高耐受电压、高功率和低导通电阻等高性能的节能的常闭型空穴沟道III族氮化物晶体管。

Claims (15)

  1. 一种非平面空穴沟道半导体晶体管的制造方法，包括：
    提供基片，在其上表面刻蚀出台阶状结构，所述台阶状结构具有大致平行的第一表面和第二表面，以及分别连接第一表面和第二表面的垂直表面，且所述垂直表面的晶格具有六角对称性；
    以所述垂直表面处为核心，受所述第二表面的限制，垂直于所述第二表面侧向外延生长非平面沟道层；
    在所述沟道层上形成势垒层，从而同时在所述势垒层和所述沟道层的界面处形成二维空穴气及不可移动的背景负电荷；和/或所述二维电子气及不可移动的背景正电荷。
  2. 如权利要求1所述的方法，还包括在所述垂直表面处形成成核层，所述成核层形成在所述垂直表面的部分表面上；或所述成核层形成在所述垂直表面的全部表面上。
  3. 如权利要求2所述的方法，还包括以所述成核层为核心，侧向外延生长第一沟道层。
  4. 如权利要求3所述的方法，还包括以所述第一沟道层为核心，侧向外延生长N型掩埋层。
  5. 如权利要求4的所述的方法，还包括以所述第一沟道层或所述掩埋层为核心，继续侧向外延生长第二沟道层。
  6. 一种非平面空穴沟道半导体晶体管，包括：
    基片，其上形成为台阶状结构，所述台阶状结构具有大致平行的第一表面和第二表面，以及分别连接第一表面和第二表面的垂直表面，且所述垂直表面的晶格具有六角对称性；
    以所述垂直表面为核心，受所述第二表面的限制，垂直于所述第二表面侧向外延生长的非平面沟道层；
    在所述沟道层上形成有势垒层，从而同时在所述势垒层和所述沟道层的界面处形成二维空穴气和/或所述二维电子气。
  7. 如权利要求6所述的非平面空穴沟道半导体晶体管，其中，在所述基片的除所述垂直表面外的其他表面上具有第一绝缘层。
  8. 如权利要求6或7所述的非平面空穴沟道半导体晶体管，其中，在所述基片的所述垂直表面上具有成核层。
  9. 如权利要求8所述的非平面空穴沟道半导体晶体管，其中，在所述成核层外还具有缓冲层，所述缓冲层具有单层或多层结构。
  10. 一种非平面空穴沟道半导体器件，包括：
    基片，在垂直于所述基片的上表面外延生长有非平面的沟道层；
    所述沟道层包括第一沟道层和第二沟道层；
    在所述沟道层上形成有势垒层(130)，从而同时在所述势垒层(130)和所述沟道层的界面处形成二维空穴气和/或所述二维电子气。
  11. 如权利要求10所述的非平面空穴沟道半导体器件，其中，还具有第三沟道层，所述第三沟道层为非故意掺杂或本征的GaN，或者为InGaN或者所述第三沟道层为掺杂浓度较低的GaN。
  12. 一种射频器件，其包括权利要求6-9中任一项所述的非平面空穴沟道半导体晶体管。
  13. 一种射频器件，其包括权利要求10或11所述的非平面空穴沟道半导体器件。
  14. 一种电力功率器件，其包括权利要求6-9中任一项所述的非平面空穴沟道半导体晶体管。
  15. 一种电力功率器件，其包括权利要求10或11所述的非平面空穴沟道半导体器件。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116072531B (zh) * 2023-03-07 2023-08-22 徐州致能半导体有限公司 一种在半导体功能区侧面制作电极的方法
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130207078A1 (en) * 2012-01-18 2013-08-15 Kopin Corporation InGaN-Based Double Heterostructure Field Effect Transistor and Method of Forming the Same
CN104269433A (zh) * 2014-09-05 2015-01-07 电子科技大学 具有复合沟道层的氮化镓基增强型异质结场效应晶体管
US20170154987A1 (en) * 2015-11-27 2017-06-01 Huga Optotech Inc. Normally-off high electron mobility transistors and fabrication methods thereof
US20170222047A1 (en) * 2016-01-07 2017-08-03 Lawrence Livermore National Security, Llc Three dimensional vertically structured electronic devices
CN108831922A (zh) * 2018-06-05 2018-11-16 大连芯冠科技有限公司 具有GaAs和GaN复合沟道的GaN HEMT器件及制备方法
CN109524460A (zh) * 2017-09-19 2019-03-26 世界先进积体电路股份有限公司 高空穴移动率晶体管
CN110224019A (zh) * 2019-04-12 2019-09-10 广东致能科技有限公司 一种半导体器件及其制造方法
CN110634867A (zh) * 2019-09-10 2019-12-31 英诺赛科（珠海）科技有限公司 半导体装置及其制造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2765611A3 (en) * 2013-02-12 2014-12-03 Seoul Semiconductor Co., Ltd. Vertical gallium nitride transistors and methods of fabricating the same

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130207078A1 (en) * 2012-01-18 2013-08-15 Kopin Corporation InGaN-Based Double Heterostructure Field Effect Transistor and Method of Forming the Same
CN104269433A (zh) * 2014-09-05 2015-01-07 电子科技大学 具有复合沟道层的氮化镓基增强型异质结场效应晶体管
US20170154987A1 (en) * 2015-11-27 2017-06-01 Huga Optotech Inc. Normally-off high electron mobility transistors and fabrication methods thereof
US20170222047A1 (en) * 2016-01-07 2017-08-03 Lawrence Livermore National Security, Llc Three dimensional vertically structured electronic devices
CN109524460A (zh) * 2017-09-19 2019-03-26 世界先进积体电路股份有限公司 高空穴移动率晶体管
CN108831922A (zh) * 2018-06-05 2018-11-16 大连芯冠科技有限公司 具有GaAs和GaN复合沟道的GaN HEMT器件及制备方法
CN110224019A (zh) * 2019-04-12 2019-09-10 广东致能科技有限公司 一种半导体器件及其制造方法
CN111816702A (zh) * 2019-04-12 2020-10-23 广东致能科技有限公司 一种空穴沟道半导体晶体管、制造方法及其应用
CN110634867A (zh) * 2019-09-10 2019-12-31 英诺赛科（珠海）科技有限公司 半导体装置及其制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3944337A4 *

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