WO2023178684A1 - 氮化镓场效应晶体管的结构和制备方法 - Google Patents

氮化镓场效应晶体管的结构和制备方法 Download PDF

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WO2023178684A1
WO2023178684A1 PCT/CN2022/083160 CN2022083160W WO2023178684A1 WO 2023178684 A1 WO2023178684 A1 WO 2023178684A1 CN 2022083160 W CN2022083160 W CN 2022083160W WO 2023178684 A1 WO2023178684 A1 WO 2023178684A1
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epitaxial
field effect
epitaxial structure
gallium nitride
effect transistor
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PCT/CN2022/083160
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English (en)
French (fr)
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鲁微
马俊彩
李水明
马平
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华为技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • Embodiments of the present application relate to the field of semiconductor technology, and in particular to a structure and preparation method of a gallium nitride field effect transistor.
  • GaN switching devices prepared from GaN as an intrinsic material have become a research and development direction.
  • GaN switching devices usually require CMOS (complementary metal oxide semiconductor, complementary metal oxide semiconductor) devices to drive.
  • the structure and preparation method of the gallium nitride field effect transistor provided in this application can improve the performance of the gallium nitride field effect transistor.
  • inventions of the present application provide a structure of a gallium nitride field effect transistor.
  • the structure of the gallium nitride field effect transistor includes: a substrate; a first epitaxial structure disposed on the substrate; A semiconductor layer on the first epitaxial structure, a groove is provided on the upper surface of the semiconductor layer, a first filling material is provided on the inner wall of the groove, and a second filling material is provided on the surface of the first filling material.
  • a first source structure, a first drain structure and a first gate structure are provided on the semiconductor layer, wherein the first source structure and the first drain structure are respectively provided on the Both sides of the first gate structure are isolated from each other, and the first gate structure is disposed on the second filling material.
  • the gallium nitride field effect transistor provided in the embodiment of the present application may be a p-channel transistor.
  • a first filling material is attached to the inner wall of the groove, and the first filling material separates the inner wall of the groove from the second filling material.
  • reducing the on-state resistance value of the gallium nitride field effect transistor is comparable to the existing technology of increasing the size of the p-channel transistor to increase the hole mobility of the p-channel device to increase the switching rate of the p-channel transistor.
  • embodiments of the present application reduce the turn-on and turn-off delays of the p-channel transistor by reducing the resistance of the conductive channel, and can increase the operating speed of the p-channel transistor while adopting a smaller size.
  • the p-channel transistor provided by the embodiment of the present application can be used in a complementary field effect transistor to improve the operating efficiency of the complementary field effect transistor.
  • the structure of the gallium nitride field effect transistor provided by the embodiments of the present application can improve the performance of the gallium nitride field effect transistor.
  • the gallium nitride field effect transistor is a complementary field effect transistor, and the first epitaxial structure, the semiconductor layer, the first source structure, the first drain The structure and the first gate structure form a p-channel transistor; the gallium nitride field-effect transistor further includes an n-channel transistor, and the n-channel transistor includes: a second epitaxial layer disposed on the substrate.
  • the first epitaxial structure and the second epitaxial structure are separated; a second source structure, a second drain structure and a second gate structure are provided on the second epitaxial structure, so The second source structure and the second drain are disposed on both sides of the second gate structure and isolated from each other; wherein the second gate structure includes a A semiconductor structure and a metal structure disposed on the semiconductor structure.
  • CMOS devices and GaN switching devices are placed on different chips, and long lead connections are required between the CMOS devices and GaN switching devices.
  • the industry has proposed to prepare CMOS devices and GaN switching devices on the same chip.
  • enhancement mode n-channel devices and depletion mode n-channel devices made of GaN materials are made into coupling structures to achieve complementary effects to drive GaN switching devices as CMOS devices.
  • CMOS devices formed by enhancement mode n-channel devices and depletion mode n-channel devices have higher static power consumption.
  • n-channel transistors and p-channel transistors respectively, it is possible to simultaneously prepare p-channel transistors on the same chip. and n-channel transistors, that is, complementary transistors are prepared on the same chip; thus, the length of the conductive lines used to connect the p-channel transistors and n-channel transistors can be reduced, thereby providing turn-on and turn-off of electronic devices speed.
  • the static power of the complementary field-effect transistor can be reduced compared to the complementary structure of enhancement-mode n-channel devices and depletion-mode n-channel devices in traditional technology. Consumption.
  • the first filling material is a metal oxide material.
  • the metal oxide material is nickel oxide.
  • the second filling material is one of aluminum oxide, aluminum nitride, silicon nitride and silicon oxide.
  • the first epitaxial structure includes a gallium nitride buffer layer disposed on the substrate.
  • the first epitaxial structure further includes an aluminum gallium nitride layer disposed on the gallium nitride buffer layer; the second epitaxial layer and the first epitaxial layer have the same Structure.
  • the material of the semiconductor layer is the same as the material of the semiconductor structure.
  • the first epitaxial structure and the second epitaxial structure are isolated from each other by a passivation layer, and the material of the passivation layer is silicon nitride or silicon oxide.
  • the first epitaxial structure and the second epitaxial structure are isolated by a high resistance region, and the high resistance region is formed by a high resistance region between the first epitaxial structure and the second epitaxial structure. It is formed by injecting nitrogen ions, helium ions or hydrogen ions into the epitaxial structure.
  • embodiments of the present application provide a method for manufacturing a gallium nitride field effect transistor.
  • the preparation method includes: providing a substrate; forming a first epitaxial structure on the substrate; A semiconductor layer is formed on the epitaxial structure, wherein a groove is provided on the upper surface of the semiconductor layer, a first filling material is provided on the inner wall of the groove, and a second filling material is provided on the surface of the first filling material; A first source structure, a first drain structure and a first gate structure are provided on the semiconductor layer, wherein the first source structure and the first drain structure are respectively provided on the first Both sides of the gate structure are isolated from each other, and the first gate structure is disposed on the second filling material.
  • the method further includes: forming a second epitaxial structure on the substrate, the first epitaxial structure and the second epitaxial structure being spaced apart; A second source structure, a second drain structure and a second gate structure are disposed on the two epitaxial structures, and the second source structure and the second drain are disposed on both sides of the second gate structure. , and are isolated from each other; wherein, the second gate structure includes a semiconductor structure disposed on the second epitaxial structure and a metal structure disposed on the semiconductor structure.
  • the first epitaxial structure and the second epitaxial structure are formed by depositing multiple semiconductor layers on a substrate and separating each of the multiple semiconductor layers. formed in two parts; wherein the first epitaxial structure includes a first part of each of the multi-layer semiconductor layers, and the second epitaxial structure includes a first part of each of the multi-layer semiconductor layers. Layer the second part of the semiconductor layer.
  • the first filling material is nickel oxide; the second filling material is one of aluminum oxide, aluminum nitride, silicon oxide and silicon nitride.
  • embodiments of the present application provide an inverter, which includes a p-channel transistor and an n-channel transistor as described in any of the above aspects; the source of the p-channel transistor is coupled to the power terminal, The source of the n-channel transistor is coupled to the ground; the gate of the p-channel transistor is coupled to the gate of the n-channel transistor for input signals; the drain of the p-channel transistor Coupled with the drain of the n-channel transistor for outputting an inverted signal.
  • Figure 1 is a schematic structural diagram of a complementary field effect transistor provided by an embodiment of the present application.
  • Figure 2A is a schematic diagram of the positional relationship between the metal oxide material 122 and the dielectric material 123 in the groove 121 provided by the embodiment of the present application;
  • Figure 2B is another schematic diagram of the positional relationship between the metal oxide material 122 and the dielectric material 123 in the groove 121 provided by the embodiment of the present application;
  • Figure 3 is a flow chart of a method for preparing the complementary field effect transistor shown in Figure 1 provided by an embodiment of the present application;
  • Figures 4A-4I are schematic structural diagrams of the complementary field effect transistor shown in Figure 1 during the preparation process
  • 5A to 5C are schematic diagrams of the circuit structure of a logic device formed using the complementary field effect crystal shown in FIG. 1 according to an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a complementary field effect transistor 100 provided by an embodiment of the present application.
  • a complementary field effect transistor 100 includes a substrate 10 , an epitaxial structure 11 disposed on the substrate 10 , and an epitaxial structure 21 disposed on the substrate 10 .
  • the epitaxial structure 11 and the epitaxial structure 21 are connected by The passivation layers 30 are separated from each other.
  • the epitaxial structure 11 and each film layer structure on the epitaxial structure 11 are used to form a p-channel transistor, and the epitaxial structure 21 and each film layer structure on the epitaxial structure 21 are used to form an n-channel transistor. It can be seen from FIG. 1 that p-channel transistors and n-channel transistors share the same substrate 10, so that p-channel transistors and n-channel transistors can be formed on the same chip.
  • the epitaxial structure 11 and the epitaxial structure 21 are separated by a passivation layer 30 .
  • a high-resistance region can also be formed between the epitaxial structure 11 and the epitaxial structure 21 .
  • the high-resistance region is formed by injecting nitrogen ions into the epitaxial structure between the epitaxial structure 11 and the epitaxial structure 21 . , helium ions or hydrogen ions.
  • the embodiment of the present application is described as an example in which the epitaxial structure 11 and the epitaxial structure 21 are separated by a passivation layer 30 , but this is not used to limit the solution.
  • a semiconductor layer 12 is provided on the epitaxial structure 11 .
  • the semiconductor layer 12 includes a surface S1 in contact with the epitaxial structure 11 and a surface S2 opposite the surface S1 .
  • a groove 121 is provided on the surface S2 of the semiconductor layer 12 , and a groove 121 is provided in the groove 121 .
  • a metal oxide material 122 which is a P-type dielectric material, including but not limited to: aluminum oxide such as NiO (nickel oxide), Cu 2 O (copper oxide), or SnO (tin oxide).
  • a dielectric material 123 is also provided in the groove 121.
  • the dielectric material 123 can be, for example, aluminum oxide (AlO), aluminum trioxide (Al 2 O 3 ), aluminum nitride (AlN), silicon nitride (SiN) or Silicon oxide (SiO), etc.
  • the metal oxide material 122 separates the inner surface of the semiconductor layer 12 from the dielectric material 123 .
  • the metal oxide material 122 can be coated on the inner wall of the groove 121, and the dielectric material 123 is deposited in the groove 121, as shown in FIG. 1 .
  • the metal oxide material 122 can be filled in the groove 121; when the metal oxide material 122 is filled in the groove 121, the surface of the metal oxide material 122 is also provided with grooves, and the metal oxide The grooves on the surface of the object material 122 are used to fill the dielectric material 123, as shown in Figure 2A.
  • the metal oxide material 122 may only be attached to the sidewalls of the groove 121 , and the rest of the groove 121 is filled with the dielectric material 123 .
  • the groove 121 and the material deposited in the groove 121 are used to form the conductive channel of the above-mentioned P-channel transistor.
  • the dielectric material 123 filled in the groove 121 can also be in the shape of a groove to be embedded in the metal structure 15 .
  • enhancement mode n-channel devices and depletion mode n-channel devices are made into coupling structures to achieve complementary effects.
  • CMOS devices formed by enhancement mode n-channel devices and depletion mode n-channel devices have higher static power consumption.
  • the industry has further proposed using p-channel devices made of GaN materials to couple with n-channel devices into complementary logic structures to improve static power consumption.
  • p-type GaN materials are difficult to dope and activate, and the hole mobility of the material is low.
  • the complementary field effect transistor adopts p-channel transistors and n-channel transistors.
  • the complementary field effect transistor Compared with the complementary structure achieved by enhancement-mode n-channel devices and depletion-mode n-channel devices in traditional technology, The static power consumption of the complementary field effect transistor can be reduced; in addition, the complementary field effect transistor provided by the embodiment of the present application can make the metal oxide material A parallel relationship is formed between the resistance introduced by 122 and the resistance introduced by the semiconductor layer 12, thereby reducing the resistance value of the conductive channel sidewall of the p-channel transistor, that is, reducing the open-state resistance value of the p-channel transistor, which is different from the existing In technology, the hole mobility of the p-channel device is increased by increasing the size of the p-channel transistor to increase the switching rate of the p-type transistor.
  • the resistance of the conductive channel is reduced by reducing the resistance of the p-channel device.
  • the turn-on and turn-off delays of the transistor can increase the operating speed of p-channel transistors while using smaller sizes. Thereby improving the working efficiency of the complementary field effect transistor.
  • the substrate 10 shown in FIG. 1 is usually formed of a semiconductor material.
  • the semiconductor material may include, but is not limited to, silicon (Si), gallium nitride (GaN), silicon carbide (SiC), sapphire (sapphire) or diamond (C), etc.
  • the epitaxial structure 11 may include at least one semiconductor layer, for example, it may include one semiconductor layer, two semiconductor layers, etc. The embodiments of this application are not specifically limited.
  • FIG. 1 schematically shows that the epitaxial structure 11 includes a semiconductor layer 111 , semiconductor layer 112 and semiconductor layer 113 are three semiconductor layers.
  • the semiconductor layer 111 is in contact with the substrate 10
  • the semiconductor layer 112 is disposed between the semiconductor layer 111 and the semiconductor layer 113
  • the semiconductor layer 113 is in contact with the semiconductor layer 12 .
  • the semiconductor layer 111 may also be called a buffer layer, and the material of the buffer layer may include one or more of ALN, ALGaN and GaN.
  • the material used in the substrate 10 and the semiconductor material used in the conductive channel region cannot be bonded well.
  • a metal structure 13 and a metal structure 14 are respectively provided on the surface S2 of the semiconductor layer 12 and on both sides of the groove 121 .
  • An ohmic contact is formed between the metal structure 13 and the surface S2 of the semiconductor layer 12 to lead out the source of the P-channel transistor.
  • An ohmic contact is formed between the metal structure 14 and the surface S2 of the semiconductor layer 12 to lead out the drain of the P-channel transistor. pole.
  • a metal structure 15 is provided on the dielectric material 123 deposited in the groove 121.
  • the metal structure 15 is used to form a gate electrode.
  • the metal structure 15 is a continuous structure.
  • the metal structure 15 includes a part embedded in the groove 121 and a part disposed in the groove 121.
  • the portion above the semiconductor layer 12 and the portion of the metal structure 15 embedded in the groove 121 are wrapped by the dielectric material 123 .
  • the portion of the metal structure 15 disposed above the semiconductor layer 12 covers the groove 121 in the orthographic projection of the semiconductor layer 12 .
  • the materials of the metal structure 13, the metal structure 14 and the metal structure 15 include but are not limited to: titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W), palladium (Pd), gold (Au), aluminum (Al), titanium nitride (TiN), or compounds thereof.
  • the number of semiconductor layers included in the epitaxial structure 21 and the material used for each semiconductor layer are the same as the semiconductor structure 22 .
  • FIG. 1 shows that the epitaxial structure 21 includes a semiconductor layer 211 and a semiconductor layer 212 . There are three semiconductor layers including the semiconductor layer 213. For the materials used in each semiconductor layer, refer to the relevant descriptions in the epitaxial structure 11 and will not be described again.
  • a metal structure 22, a metal structure 23 and a semiconductor structure 24 are provided on the surface S3 of the epitaxial structure 21.
  • the metal structure 22 and the metal structure 23 are disposed on both sides of the semiconductor structure 24 .
  • the metal structure 22 and the semiconductor structure 24 and the semiconductor structure 24 and the metal structure 22 are separated by the passivation layer 30 .
  • An ohmic contact is formed between the metal structure 22 and the surface S3 of the epitaxial structure 21 to lead out the drain of the n-channel transistor.
  • An ohmic contact is formed between the metal structure 23 and the surface S3 of the epitaxial structure 21 to lead out the source of the n-channel transistor.
  • a metal structure 25 is provided on the semiconductor structure 24, and a Schottky contact or an ohmic contact is formed between the metal structure 25 and the semiconductor structure 24 to lead out the gate of the n-channel transistor.
  • the material of the semiconductor structure 24 is the same as the material of the semiconductor layer 12 , for example, it is formed of GaN crystal doped with magnesium element.
  • the materials of the metal structure 22, the metal structure 23 and the metal structure 24 may be the same, for example, may include but are not limited to: titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W), palladium (Pd), gold ( Au), aluminum (Al), titanium nitride (TiN), or compounds thereof.
  • each film layer structure in the p-channel transistor and the exposed surfaces of each film layer structure in the n-channel transistor are covered and wrapped by the passivation layer 30 .
  • the material of the passivation layer 30 may be silicon nitride (SiN), for example.
  • the electrodes of the p-channel transistor and the electrodes of the n-channel transistor can be connected through wires, thereby forming a p-channel transistor and an n-channel transistor on the GaN substrate.
  • Complementary field effect transistors are used, and the formed logic device is specifically referred to Figures 5A to 5C.
  • Figure 1 schematically shows the connection between the drain of the p-channel transistor and the drain of the n-channel transistor; in other possible implementations, the source of the p-channel transistor
  • the terminal can also be connected to the source of an n-channel transistor.
  • An embodiment of the present application also provides an electronic device, which includes a complementary field effect transistor.
  • the complementary field effect transistor may be, for example, the complementary field effect transistor 100 as shown in FIG. 1 .
  • the electronic device may be an unpackaged bare chip or an electronic device.
  • the complementary field effect transistor is an electronic device, the bare chip of the complementary field effect transistor shown in the embodiment of the present application can be packaged in a tube casing.
  • the shell may include but is not limited to a plastic shell, a metal shell (such as a gold shell, a nickel shell), etc., and each electrode of the complementary field effect transistor is led out from the outer surface of the shell.
  • the electronic device may also be an integrated circuit product.
  • the integrated circuit product may also include other circuits, so that the complementary field effect transistor shown in the embodiment of the present application is Type field effect transistors cooperate with other circuits to achieve various circuit functions.
  • embodiments of the present application also provide a method of manufacturing a complementary field effect transistor.
  • the following takes the structure of the complementary field effect transistor produced as shown in Figure 1 as an example.
  • the process 300 shown in FIG. 3 describes in detail the process flow of manufacturing a complementary field effect transistor.
  • the process flow 300 includes the following steps:
  • Step 301 Provide a substrate 10, and form an epitaxial structure 101 on the substrate 10.
  • the substrate 10 may be a semiconductor material, and the semiconductor material may include but is not limited to: silicon (Si), gallium nitride (GaN), silicon carbide (SiC), sapphire (sapphire) or diamond (C), etc.
  • the first semiconductor material, the second semiconductor material and the third semiconductor material are sequentially epitaxially grown on the substrate 10 to form the epitaxial structure 101.
  • the first semiconductor material may be, for example, one or more of ALN, ALGaN, and GaN; the second semiconductor material may be, for example, GaN; and the third semiconductor material may be, for example, AlGaN.
  • Step 302 Form the semiconductor layer 102 on the epitaxial structure 101.
  • a GaN layer doped with magnesium may be epitaxially grown on the epitaxial structure 101 .
  • the resulting structure after this step is shown in Figure 4A.
  • Step 303 Etch the epitaxial structure 101 to form the epitaxial structure 11 and the epitaxial structure 21 isolated from each other.
  • various processes such as dry etching or wet etching can be used to etch the epitaxial structure 101 to form two semiconductor structures that are separated from each other.
  • the epitaxial structure 11 and the film structure thereon are used to form a p-channel transistor, and the epitaxial structure 21 and the film structure thereon are used to form an n-channel transistor.
  • the semiconductor layer 102 on the epitaxial structure 101 is also etched into two parts: the semiconductor layer 1021 and the semiconductor layer 1022 that are separated from each other.
  • the second semiconductor material and the third semiconductor material are etched through, but the first semiconductor material is not etched through, and the etching is carried out until the inside of the semiconductor layer formed by the first semiconductor material is retained.
  • Preset thickness of the contact side of the substrate 10 is shown in Figure 4B.
  • the above step 303 can also be replaced with the following step: using an ion implantation process to implant ions into the middle region of the epitaxial structure 101 to form a high resistance region.
  • the ions may include but are not limited to : Nitrogen ions, helium ions or hydrogen ions.
  • the two sides of the high resistance region where ions are not implanted are epitaxial structure 11 and epitaxial structure 21 respectively. Therefore, the epitaxial structure 11 and the epitaxial structure 21 are isolated by the high resistance region.
  • Step 304 Etch the semiconductor layer 1022 to form the semiconductor structure 24.
  • a patterned mask layer may be coated on the surface of the semiconductor layer 1022 first.
  • the mask layer may be, for example, one or a combination of photoresist, dielectric layer and metal. Therefore, some areas of the semiconductor layer 1022 are covered by the mask layer, and some areas are exposed. Then, the semiconductor layer 1022 is etched through the mask layer. In the semiconductor layer 1022 , the portion not covered by the mask layer is etched away, and the portion covered by the mask layer remains. The remaining portion is the semiconductor structure 24 . In this step, parts on both sides of the upper surface of the epitaxial structure 21 are exposed. After this step, the resulting structure is shown in Figure 4C.
  • Step 305 Form a metal structure 22 and a metal structure 23 respectively on the upper surface S3 of the epitaxial structure 21 and on both sides of the semiconductor structure 24.
  • metal materials may be deposited on the exposed areas on both sides of the upper surface S3 of the epitaxial structure 21 to form the metal structure 22 and the metal structure 23 respectively.
  • the metal material may include, for example, but is not limited to: titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W), palladium (Pd), gold (Au), aluminum (Al), titanium nitride (TiN) ), or its compounds.
  • a high-temperature annealing process is used to achieve ohmic contact between the metal structure 22 and the epitaxial structure 21, and between the metal structure 23 and the epitaxial structure 21, respectively, to form the drain and source of the n-channel transistor.
  • the resulting structure is shown in Figure 4D.
  • Step 306 Form the metal structure 13 and the metal structure 14 respectively on the upper surface S2 of the epitaxial structure 11 and in the area close to the side.
  • metal materials may be deposited on areas on both sides of the upper surface S2 of the epitaxial structure 21 to form the metal structure 22 and the metal structure 23 .
  • the metal material may include, for example, but is not limited to: titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W), palladium (Pd), gold (Au), aluminum (Al), titanium nitride (TiN) ), or its compounds.
  • a high-temperature annealing process is used to realize ohmic contact between the metal structure 22 and the epitaxial structure 21, and between the metal structure 23 and the epitaxial structure 21, respectively, to form the drain and source of the p-channel transistor.
  • the resulting structure is shown in Figure 4E.
  • Step 307 Etch the area between the surface S2 of the semiconductor layer 12, the metal structure 13 and the metal structure 14 to form a groove 121.
  • a patterned mask layer may be coated on the surface of the semiconductor layer 12 first.
  • the mask layer may be, for example, one or a combination of photoresist, dielectric layer and metal. Therefore, some areas of the semiconductor layer 12 are covered by the mask layer, and some areas are exposed. Then, the semiconductor layer 12 is etched through the mask layer. In the semiconductor layer 12 , the portion not covered by the mask layer is etched away, and the portion covered by the mask layer remains, thereby forming a groove 121 . After this step, the resulting structure is shown in Figure 4F.
  • Step 308 Form metal oxide material 122 in groove 121.
  • the metal oxide material 122 may be NiO, for example.
  • This step may further include the following steps: step 3081, deposit NiO in the groove 121.
  • NiO can be deposited in the groove 121 in various ways.
  • a NiO film can be sputtered on the inner wall of the groove 121 through a magnetron sputtering process by controlling the ratio of oxygen and argon.
  • NiO can be deposited in the groove 121 through a pulsed laser deposition (PLD) process by controlling the ratio of oxygen and argon.
  • PLD pulsed laser deposition
  • Lifting or etching processes may be used to remove excess NiO outside the groove 121 and in the groove 121 .
  • an isotropic dry etching process can be used to etch away the NiO at the bottom of the groove 121 , leaving only the NiO attached to the side walls of the groove 121 .
  • the resulting structure after this step is shown in Figure 4G.
  • Step 309 Deposit dielectric material 123 in the groove 121 in the area where the metal oxide material 122 is not provided.
  • various deposition processes such as atomic layer deposition (ALD) or plasma enhanced chemical vapor deposition (PECVD) can be used to deposit the dielectric material 123 in the groove 121 .
  • the dielectric material 123 may include, for example, but is not limited to: aluminum oxide, aluminum nitride, silicon nitride, silicon oxide, etc.
  • etching or other processes are used to remove the dielectric material outside the groove 121 and part of the dielectric material 123 on the surface of the groove, thereby forming a groove on the surface of the dielectric material 123 .
  • the structure formed after this step is shown in Figure 4H.
  • Step 310 deposit metal material on the dielectric material 123 deposited in the groove 121 and on the semiconductor structure 24 respectively to form the metal structure 15 and the metal structure 25.
  • a metal material can first be deposited on the dielectric material 123 deposited in the groove 121, and a metal material can be deposited on the semiconductor structure 24 to form the metal structure 15 and the metal structure 25; and then processes such as evaporation and annealing are used. , so that the dielectric material 123 and the metal structure 15 are in contact with each other to form a gate electrode, and a Schottky contact or an ohmic contact is formed between the semiconductor structure 24 and the metal structure 25 to form a gate electrode.
  • the metal structure 15 includes a portion embedded in the groove 121 and a portion disposed on the semiconductor layer 12 .
  • the portion of the metal structure 15 embedded in the groove 121 is wrapped by a dielectric material 123 .
  • the metal materials may include, but are not limited to: Ti, Ni, Pt, W, Pd, Au, Al, TiN and other metals or compounds.
  • the structure formed after this step is shown in Figure 4I.
  • Step 311 In the structure shown in FIG. 4I, a passivation layer 30 is formed on each surface away from the substrate to protect each electrode and each semiconductor layer.
  • the passivation layer may be made of SiN, for example.
  • the gap between the epitaxial structure 11 and the epitaxial structure 21 is also filled with SiN to isolate the epitaxial structure 11 and the epitaxial structure 21 and to protect the epitaxial structure 11 and the epitaxial structure 21 .
  • a P-channel transistor and an N-channel transistor are formed on the same substrate.
  • Step 312 Open holes in the passivation layer 30 to lead out each electrode to realize the connection between the electrode of the P-channel transistor and the electrode of the N-channel transistor, thereby forming the complementary field effect transistor 100.
  • the method of preparing the complementary field effect transistor 100 shown in FIG. 3 is schematic, and in other possible scenarios, it may include more or fewer steps than in FIG. 3 .
  • the etching of the semiconductor layer 1022 shown in step 304 to form the semiconductor structure 24 and the etching of the surface S2 of the semiconductor layer 12 to form the groove 121 shown in step 307 can be prepared through the same process; and then For example, in step 305, the metal structure 22 and the metal structure 23 are respectively formed on the upper surface S3 of the epitaxial structure 21, and in step 306, the metal structure 13 and the metal structure 14 are respectively formed on the upper surface S2 of the epitaxial structure 11, you can use Prepared in the same process.
  • an embodiment of the present application also provides a logic device, which is prepared by the complementary field effect transistor 100 as shown in FIG. 1 .
  • the logic device may be, for example, an inverter, a NAND gate, or a NOR gate. Specifically, refer to FIGS. 5A to 5C.
  • FIG. 5A is a schematic structural diagram of an inverter provided by an embodiment of the present application.
  • the gate of the p-channel transistor p1 and the gate of the n-channel transistor n1 in the complementary field effect transistor 100 are connected through wires to serve as the signal input terminal Vin; the drain of the p-channel transistor p1
  • the drain of the n-channel transistor n1 is connected through a lead as the signal output terminal Vout;
  • the source of the p-channel transistor is connected to the power supply terminal Vdd through a lead;
  • the source of the n-channel transistor is connected to the common ground Gnd through a lead, so that
  • the inverter shown in Fig. 5A is formed.
  • FIG. 5B is a schematic structural diagram of a NAND gate provided by an embodiment of the present application.
  • the NAND gate shown in FIG. 5B can be fabricated from two complementary field effect transistors 100 as shown in FIG. 1 .
  • the source of the p-channel transistor p1 and the source of the p-channel transistor p2 are connected to the power terminal Vdd through a lead; the gate of the p-channel transistor p1 and the gate of the n-channel transistor n1 are connected through a lead.
  • the gate of the p-channel transistor p2 and the gate of the n-channel transistor n2 are connected through a wire, as the signal input terminal Vi2; the drain of the p-channel transistor p1 and the drain of the p-channel transistor p2 and the drain of the n-channel transistor n1 are connected by a wire, serving as the signal output terminal Vout; the source of the n-channel transistor n1 and the drain of the n-channel transistor n2 are connected by a wire, and the source of the n-channel transistor n2 is connected with the drain of the n-channel transistor n2.
  • the common ground Gnd is connected through a lead.
  • the p-channel transistor p1 and the n-channel transistor n1 are one of the complementary field effect transistors 100; the p-channel transistor p2 and the n-channel transistor n2 are the other complementary field effect transistor 100.
  • FIG. 5C is a schematic structural diagram of a NOR gate provided by an embodiment of the present application.
  • the NOR gate shown in FIG. 5C can be fabricated from two complementary field effect transistors 100 as shown in FIG. 1 .
  • the source of p-channel transistor p1 is connected to the power terminal Vdd through a lead;
  • the drain of p-channel transistor p1 is connected to the source of p-channel transistor p2;
  • the gate of p-channel transistor p1 is connected to the n-channel
  • the gate of the transistor n1 is connected through a lead and serves as the signal input terminal Vi1;
  • the gate of the p-channel transistor p2 and the gate of the n-channel transistor n2 are connected through a lead and serves as the signal input terminal Vi2;
  • the drain of the p-channel transistor p2 , the drain of n-channel transistor n1 and the drain of n-channel transistor n2 are connected through a lead as the signal output terminal Vout

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Abstract

本申请实施例提供了一种氮化镓场效应晶体管的结构和制备方法，该互补型场效应晶体管的结构包括：衬底；设置于衬底之上的第一外延结构；设置于第一外延结构之上的半导体层，半导体层的上表面设置有凹槽，凹槽的内壁设置有第一填充材料，第一填充材料的表面设置有第二填充材料；半导体层之上设置有第一源极结构、第一漏极结构和第一栅极结构，其中，第一源极结构和第一漏极结构分别设置于第一栅极结构的两侧、且互相隔离，第一栅极结构设置于第二填充材料之上，由此可以降氮化镓晶体管中导电沟道的电阻，以提高氮化镓晶体管的工作速度。

Description

氮化镓场效应晶体管的结构和制备方法 技术领域
本申请实施例涉及半导体技术领域，尤其涉及一种氮化镓场效应晶体管的结构和制备方法。
背景技术
随着通信、人工智能等技术的发展，大量的数据流动与转移的需求越来越大，对电子器件的要求越来越高。低功耗、高速率、小型化的电子器件成为发展方向。氮化镓(GaN)材料由于具有优越的电学性能(例如宽禁带和高电子迁移率)，使得由GaN作为本征材料制备的GaN开关器件成为研究和发展方向。GaN开关器件通常需要CMOS(complementary metal oxide semiconductor，互补金属氧化物半导体)器件来驱动。
如何提高用于驱动GaN开关器件的CMOS器件的性能，成为需要解决的问题。
发明内容
本申请提供的氮化镓场效应晶体管的结构和制备方法，可以提高氮化镓场效应晶体管的性能。
为达到上述目的，本申请采用如下技术方案：
第一方面，本申请实施例提供一种氮化镓场效应晶体管的结构，该氮化镓场效应晶体管的结构包括：衬底；设置于所述衬底之上的第一外延结构；设置于所述第一外延结构之上的半导体层，所述半导体层的上表面设置有凹槽，所述凹槽的内壁设置有第一填充材料，所述第一填充材料的表面设置有第二填充材料；所述半导体层之上设置有第一源极结构、第一漏极结构和第一栅极结构，其中，所述第一源极结构和所述第一漏极结构分别设置于所述第一栅极结构的两侧、且互相隔离，所述第一栅极结构设置于所述第二填充材料之上。
本申请实施例提供的氮化镓场效应晶体管，可以为p沟道晶体管。该p沟道晶体管中，第一填充材料贴附于所述凹槽的内壁，所述第一填充材料将所述凹槽的内壁与所述第二填充材料分隔开。通过在凹槽中设置第一填充材料，可以使得第一填充材料引入的电阻、与半导体层引入的电阻之间形成并联关系，从而可以降低p沟道晶体管的导电沟道侧壁的电阻值，也即降低氮化镓场效应晶体管开态电阻值，与现有技术中通过增大p沟道晶体管的尺寸来提高p沟道器件的空穴迁移率、以提高p沟道晶体管的开关速率相比，本申请实施例通过降低导电沟道的电阻来降低p沟道晶体管的导通和关断时延，可以在采用较小尺寸的情况下提高p沟道晶体管的工作速度。另外，本申请实施例提供的p沟道晶体管可以应用于互补型场效应晶体管中，以提高互补型场效应晶体管的工作效率。综上，本申请实施例提供的氮化镓场效应晶体管的结构，可以提高氮化镓场效应晶 体管的性能。
在一种可能的实现方式中，所述氮化镓场效应晶体管为互补型场效应晶体管，所述第一外延结构、所述半导体层、所述第一源极结构、所述第一漏极结构以及所述第一栅极结构形成p沟道晶体管；所述氮化镓场效应晶体管还包括n沟道晶体管，所述n沟道晶体管包括：设置于所述衬底之上的第二外延结构，所述第一外延结构和所述第二外延结构之间分隔开；所述第二外延结构之上设置有第二源极结构、第二漏极结构和第二栅极结构，所述第二源极结构和所述第二漏极设置于所述第二栅极结构两侧、且互相隔离；其中，所述第二栅极结构包括设置于所述第二外延结构之上的半导体结构以及设置于所述半导体结构之上的金属结构。
传统技术中，CMOS器件和GaN开关器件设置于不同的芯片上，CMOS器件和GaN开关器件之间需要较长的引线连接。为了缩短CMOS器件与GaN开关器件之间的互联引线，以降低引线引入的寄生电感和寄生电阻，业界提出在同一芯片上制备CMOS器件与GaN开关器件。在该种方式中，由GaN材料制备的增强型n沟道器件与耗尽型n沟道器件，被制作成耦合结构用于实现互补作用，以作为CMOS器件驱动GaN开关器件。然而，由增强型n沟道器件与耗尽型n沟道器件所形成的CMOS器件具有较高的静态功耗。
本申请实施例通过在同一衬底上形成相互分隔的第一外延结构和第二外延结构，以分别形成n沟道晶体管和p沟道晶体管，可以实现在同一芯片上同时制备出p沟道晶体管和n沟道晶体管，也即实现同一芯片上制备出互补晶体管；从而可以降低用于连接p沟道晶体管和n沟道晶体管之间的导电线路的长度，从而提供电子器件的导通和关断速度。另外，通过采用p沟道晶体管和n沟道晶体管，与传统技术中、由增强型n沟道器件与耗尽型n沟道器件实现互补结构相比，可以降低互补型场效应晶体管的静态功耗。
在一种可能的实现方式中，所述第一填充材料为金属氧化物材料。
在一种可能的实现方式中，所述金属氧化物材料为氧化镍。
在一种可能的实现方式中，所述第二填充材料为：氧化铝、氮化铝、氮化硅和氧化硅中的一项。
在一种可能的实现方式中，所述第一外延结构包括设置于所述衬底之上的氮化镓缓冲层。
在一种可能的实现方式中，所述第一外延结构还包括设置于所述氮化镓缓冲层之上的氮化镓铝层；所述第二外延层与所述第一外延层具有相同的结构。
在一种可能的实现方式中，所述半导体层的材料与所述半导体结构的材料相同。
在一种可能的实现方式中，所述第一外延结构和所述第二外延结构之间通过钝化层相互隔离，所述钝化层的材料为氮化硅或氧化硅。
在一种可能的实现方式中，所述第一外延结构和所述第二外延结构之间通过高阻区隔离，所述高阻区是通过在第一外延结构和第二外延结构之间的外延结构中、注入氮离子、氦离子或者氢离子所形成的。
第二方面，本申请实施例提供一种氮化镓场效应晶体管的制备方法，该制备方法包括：提供一衬底；在所述衬底之上的形成第一外延结构；在所述第一外延结构之上形成 半导体层，其中，所述半导体层的上表面设置有凹槽，所述凹槽的内壁设置有第一填充材料，所述第一填充材料的表面设置有第二填充材料；所述半导体层之上设置有第一源极结构、第一漏极结构和第一栅极结构，其中，所述第一源极结构和所述第一漏极结构分别设置于所述第一栅极结构的两侧、且互相隔离，所述第一栅极结构设置于所述第二填充材料之上。
在一种可能的实现方式中，所述方法还包括：在所述衬底之上形成第二外延结构，所述第一外延结构和所述第二外延结构之间分隔开；所述第二外延结构之上设置有第二源极结构、第二漏极结构和第二栅极结构，所述第二源极结构和所述第二漏极设置于所述第二栅极结构两侧、且互相隔离；其中，所述第二栅极结构包括设置于所述第二外延结构之上的半导体结构以及设置于所述半导体结构之上的金属结构。
在一种可能的实现方式中，所述第一外延结构和所述第二外延结构，是通过在衬底上沉积多层半导体层、将所述多层半导体层中的每一层半导体层分隔成两部分而形成的；其中，所述第一外延结构包括所述多层半导体层中的每一层半导体层的第一部分，所述第二外延结构包括所述多层半导体层中的每一层半导体层的第二部分。
在一种可能的实现方式中，所述第一填充材料为氧化镍；所述第二填充材料为氧化铝、氮化铝、氧化硅和氮化硅中的一项。
第三方面，本申请实施例提供一种反相器，该反相器包括如上任意方面所述的p沟道晶体管和n沟道晶体管；所述p沟道晶体管的源极与电源端耦合，所述n沟道晶体管的源极与地端耦合；所述p沟道晶体管的栅极与所述n沟道晶体管的栅极耦合，以用于输入信号；所述p沟道晶体管的漏极与所述n沟道晶体管的漏极耦合，以用于输出反相后的信号。
应当理解的是，本申请的第二方面-第三方面与本申请的第一方面的技术方案一致，各方面及对应的可行实施方式所取得的有益效果相似，不再赘述。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的互补型场效应晶体管的一个结构示意图；
图2A是本申请实施例提供的凹槽121中金属氧化物材料122和介质材料123之间的位置关系示意图；
图2B是本申请实施例提供的凹槽121中金属氧化物材料122和介质材料123之间的位置关系又一个示意图；
图3是本申请实施例提供的如图1所示的互补型场效应晶体管的制备方法流程图；
图4A-图4I是如图1所示的互补型场效应晶体管制备过程中的各结构示意图；
图5A-图5C是本申请实施例提供的采用图1所示的互补型场效应晶体形成的逻辑器件的电路结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本文所提及的"第一"、"第二"以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，"一个"或者"一"等类似词语也不表示数量限制，而是表示存在至少一个。
在本申请实施例中，“示例性的”或者“例如”等词用于表示例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或两个以上。
请参考图1，图1是本申请实施例提供的互补型场效应晶体管100的一个结构示意图。在图1中，互补型场效应晶体管100包括衬底10、设置于衬底10之上的外延结构11、设置于衬底10之上的外延结构21，外延结构11和外延结构21之间通过钝化层30互相分隔开来。外延结构11以及外延结构11之上的各膜层结构用于形成p沟道晶体管，外延结构21以及外延结构21之上的各膜层结构用于形成n沟道晶体管。从图1中可以看出，p沟道晶体管和n沟道晶体管共用同一个衬底10，从而p沟道晶体管和n沟道晶体管可以形成于同一个芯片上。
需要说明的是，图1所示的互补型场效应晶体管中，示出了外延结构11和外延结构21之间通过钝化层30分隔开。在一种可选的实现方式中，外延结构11和外延结构21之间也可以为高阻区，该高阻区是通过在外延结构11和外延结构21之间的外延结构中，注入氮离子、氦离子或者氢离子所形成的。本申请实施例中以外延结构11和外延结构21之间通过钝化层30分隔开为例进行描述，但不用于对方案的限定。
本申请实施例中，外延结构11之上设置有半导体层12。沿图1所示的方向Z，半导体层12包括与外延结构11相接触的表面S1、以及与表面S1相对的表面S2，半导体层12的表面S2上设置有凹槽121，凹槽121中设置有金属氧化物材料122，该金属氧化物材料为P型介质材料，包括但不限于：NiO(氧化镍)、Cu 2O(氧化铜)或者SnO(氧化锡)等氧化铝。此外，凹槽121中还设置有介质材料123，介质材料123例如可以为氧化铝(AlO)、三氧化二铝(Al 2O 3)、氮化铝(AlN)、氮化硅(SiN)或者氧化硅(SiO)等。其中，金属氧化物材料122将半导体层12的内表面与介质材料123之间分隔开来。一种可能的实现方式中，金属氧化物材料122可以涂布于凹槽121的内壁，介质材料123沉积于凹槽121中，如图1所示。一种可能的实现方式中，金属氧化物材料122可以填充于凹槽121中；当金属氧化物材料122填充于凹槽121中时，金属氧化物材料122的表面同样设置有凹槽，金属氧化物材料122表面的凹槽用于填充介质材料123，如图2A所示。一种可能的实现方式中，金属氧化物材料122可以仅贴附于凹槽121的 侧壁，凹槽121的其余部分被介质材料123填充。需要说明的是，凹槽121以及凹槽121中沉积的材料用于形成上述P沟道晶体管的导电沟道。需要说明的是，凹槽121所填充的介质材料123，也可以呈凹槽状，以嵌入金属结构15。
传统技术中，为了实现在同一芯片上制备CMOS器件与GaN开关器件，通常由GaN材料制备的增强型n沟道器件与耗尽型n沟道器件，被制作成耦合结构用于实现互补作用，以作为CMOS器件驱动GaN开关器件。然而，由增强型n沟道器件与耗尽型n沟道器件所形成的CMOS器件具有较高的静态功耗。由此，业界进一步提出采用由GaN材料制备的p沟道器件与n沟道器件耦合成为互补逻辑结构，以改善静态功耗。然而，p型GaN材料的掺杂和激活难度大，材料的空穴迁移率低。当采用GaN材料制备p沟道器件时，需要制备较大尺寸的p沟道器件以弥补空穴迁移率低的问题。这就导致所制备出的器件的尺寸较大，从而增大寄生电容，降低了器件的性能。本申请实施例提供的互补型场效应晶体管，通过采用p沟道晶体管和n沟道晶体管，与传统技术中、由增强型n沟道器件与耗尽型n沟道器件实现互补结构相比，可以降低互补型场效应晶体管的静态功耗；另外，本申请实施例提供的互补型场效应晶体管，通过在p型效应晶体管的凹槽121中设置金属氧化物材料122，可以使得金属氧化物材料122引入的电阻、与半导体层12引入的电阻之间形成并联关系，从而可以降低p沟道晶体管的导电沟道侧壁的电阻值，也即降低p沟道晶体管开态电阻值，与现有技术中通过增大p沟道晶体管的尺寸来提高p沟道器件的空穴迁移率、以提高p型晶体管的开关速率相比，本申请实施例通过降低导电沟道的电阻来降低p沟道晶体管的导通和关断时延，可以在采用较小尺寸的情况下提高p沟道晶体管的工作速度。从而提高互补型场效应晶体管的工作效率。
请继续参考图1，如图1所示的衬底10，通常采用半导体材料形成。该半导体材料可以包括但不限于：硅(Si)、氮化镓(GaN)、碳化硅(SiC)、蓝宝石(sapphire)或金刚石(C)等。外延结构11可以包括至少一层半导体层，例如可以包括一层半导体层、两层半导体层等，本申请实施例不做具体限定，图1中示意性的示出了外延结构11包括半导体层111、半导体层112和半导体层113三层半导体层。其中，半导体层111与衬底10接触，半导体层112设置于半导体层111和半导体层113之间，半导体层113与半导体层12接触。半导体层111也可以称为缓冲(buffer)层，该缓冲层的材料可以包括ALN、ALGaN和GaN中的一种或多种。通常，基于半导体的特性，例如应力、温度等，衬底10所采用的材料与导电沟道区域所采用的半导体材料无法较好的键合。通过设置外延结构11，利用外延结构11作为半导体层12与衬底10之间的过度，可以提高互补型场效应晶体管100的应力。
半导体层12的表面S2之上、凹槽121的两侧还分别设置有金属结构13和金属结构14。金属结构13与半导体层12的表面S2之间形成欧姆接触，以引出P沟道晶体管的源极，金属结构14与半导体层12的表面S2之间形成欧姆接触，以引出P沟道晶体管的漏极。此外，凹槽121所沉积的介质材料123之上还设置有金属结构15，金属结构15用于形成栅极，金属结构15为连续结构，金属结构15包括嵌入凹槽121中的部分以及设置于半导体层12之上的部分，金属结构15中嵌入凹槽121中的部分被介质材料123包裹，金属结构15设置于半导体层12之上的部分向半导体层12的正投影覆盖凹槽121。 金属结构13、金属结构14和金属结构15的材料，包括但不限于：钛(Ti)、镍(Ni)、铂(Pt)、钨(W)、钯(Pd)、金(Au)、铝(Al)、氮化钛(TiN)、或者其化合物。综上，衬底10、设置于衬底10之上的外延结构11、设置于外延结构11之上的半导体层12、半导体层12的凹槽121中填充的金属氧化物材料122、介质材料123、凹槽121之上的金属结构15、以及半导体层12的表面S2之上的金属结构13和金属结构14，形成p沟道晶体管。
在图1中，外延结构21所包括的半导体层的数目、以及每一层半导体层所采用的材料，与半导体结构22相同，图1中示出了外延结构21包括半导体层211、半导体层212和半导体层213三层半导体层，各半导体层所采用的材料参考外延结构11中的相关描述，不再赘述。外延结构21的表面S3之上设置有金属结构22、金属结构23和半导体结构24。金属结构22和金属结构23设置于半导体结构24的两侧，金属结构22和半导体结构24之间、以及半导体结构24和金属结构22之间，均由钝化层30分隔开来。金属结构22与外延结构21的表面S3之间形成欧姆接触，以引出n沟道晶体管的漏极，金属结构23与外延结构21的表面S3之间形成欧姆接触，以引出n沟道晶体管的源极，半导体结构24之上设置有金属结构25，金属结构25与半导体结构24之间形成肖特基接触或欧姆接触，以引出n沟道晶体管的栅极。其中，半导体结构24的材料与半导体层12的材料相同，例如为GaN晶体中掺杂镁元素形成的。金属结构22、金属结构23和金属结构24的材料可以相同，例如可以包括但不限于:钛(Ti)、镍(Ni)、铂(Pt)、钨(W)、钯(Pd)、金(Au)、铝(Al)、氮化钛(TiN)、或者其化合物。综上，衬底10、设置于衬底10之上的外延结构21、设置于外延结构21之上的金属结构22、金属结构23、半导体结构24以及设置于半导体结构24之上的金属结构25，形成n沟道晶体管。
另外，从图1中可以看出，p沟道晶体管中的各膜层结构暴露出的表面、以及n沟道晶体管中的各膜层结构暴露出的表面，均被钝化层30覆盖和包裹。其中，钝化层30的材料例如可以为氮化硅(SiN)。此外，基于所形成的逻辑结构的需要，可以将p沟道晶体管的电极与n沟道晶体管的电极之间通过引线连接，从而实现在GaN衬底上形成由p沟道晶体管和n沟道晶体管组成的互补场效应晶体管。其中，采用如图1所示的互补型场效应晶体管100，所形成的逻辑器件具体参考图5A～图5C。需要说明的是，图1中示意性的示出了p沟道晶体管的漏极与n沟道晶体管的漏极之间相连接的情况；在其他可能的实现方式中，p沟道晶体管的源极也可以与n沟道晶体管的源极连接。本申请实施例还提供一种电子设备，该电子设备包括互补型场效应晶体管，该互补型场效应晶体管例如可以为如图1所示的互补型场效应晶体管100。具体的，该电子设备可以为未经封装的裸芯片，还可以为电子器件。当互补型场效应晶体管为电子器件时，本申请实施例所示的互补型场效应晶体管的裸芯片，可以被封装于管壳内。该管壳可以包括但不限于塑封管壳、金属管壳(例如金壳、镍壳)等，在管壳的外表面引出互补型场效应晶体管的各电极。此外，电子设备也可以为集成电路产品，其中，该集成电路产品中除了包括本申请实施例所述的互补型场效应晶体管外，还可以包括其他电路，从而使得本申请实施例所示的互补型场效应晶体管与其他电路之间相互配合，以实现各种电路功能。
基于如上所述的互补型场效应晶体管的结构，本申请实施例还提供一种制作互补型场效应晶体管的方法，下面以所制作出的互补型场效应晶体管的结构如图1为例，结合图3所示的流程300，对制作互补型场效应晶体管的工艺流程进行详细描述。该工艺流程300包括如下步骤：
步骤301，提供一衬底10，在衬底10上形成外延结构101。
衬底10可以为半导体材料，该半导体材料具体可以包括但不限于：硅(Si)、氮化镓(GaN)、碳化硅(SiC)、蓝宝石(sapphire)或金刚石(C)等。
采用金属有机化合物化学气相沉淀(metal-organic chemical vapor deposition，MOCVD)工艺，在衬底10上依次外延生长第一半导体材料、第二半导体材料和第三半导体材料，以形成外延结构101。其中，第一半导体材料例如可以为ALN、ALGaN、GaN中的一种或几种；第二半导体材料例如可以为GaN；第三半导体材料例如可以为AlGaN。
步骤302，在外延结构101上形成半导体层102。该步骤中，可以在外延结构101上外延生长掺杂有镁元素的GaN层。该步骤之后所形成的结构如图4A所示。
步骤303，对外延结构101进行刻蚀，以形成相互隔离的外延结构11和外延结构21。
该步骤中，可以采用干刻或者湿刻等各种工艺，对外延结构101刻蚀，从而形成相互分离的两个半导体结构。其中，外延结构11与其之上的膜层结构用于形成p沟道晶体管，外延结构21与其之上的膜层结构用于形成n沟道晶体管。需要说明的是，该步骤中，外延结构101之上的半导体层102同样被刻蚀成相互分离的半导体层1021和半导体层1022两部分。本申请实施例中，对外延结构101刻蚀时，刻穿第二半导体材料和第三半导体材料，不刻穿第一半导体材料，刻蚀至第一半导体材料所形成的半导体层内部，保留与衬底10接触侧的预设厚度。该步骤之后所形成的结构如图4B所示。
此外，在一种可能的实现方式中，上述步骤303还可以被替换为如下步骤：采用离子注入工艺对外延结构101的中间区域进行离子注入，以形成高阻区，该离子可以包括但不限于：氮离子、氦离子或者氢离子。高阻区未注入离子的两侧分别为外延结构11和外延结构21。从而，外延结构11和外延结构21之间通过高阻区隔离。
步骤304，刻蚀半导体层1022，以形成半导体结构24。
该步骤中，可以首先在半导体层1022表面涂布图案化的掩膜(mask)层。该掩膜层例如可以为光刻胶、介质层和金属中的一种或几种的组合。从而，半导体层1022中一些区域被掩膜层覆盖，一些区域暴露出来。然后，通过掩膜层，对半导体层1022进行刻蚀。半导体层1022中，未被掩膜层覆盖的部分被刻蚀掉，被掩膜层覆盖的部分保留下来，该保留下来的部分即为半导体结构24。该步骤中，外延结构21的上表面两侧的部分被暴露出来。该步骤之后，所形成的结构如图4C所示。
步骤305，在外延结构21的上表面S3之上、半导体结构24的两侧，分别形成金属结构22和金属结构23。
该步骤中，可以在外延结构21上表面S3两侧暴露出的区域分别沉积金属材料，以形成金属结构22和金属结构23。该金属材料例如可以包括但不限于：钛(Ti)、镍(Ni)、铂(Pt)、钨(W)、钯(Pd)、金(Au)、铝(Al)、氮化钛(TiN)、或 者其化合物。然后，采用高温退火工艺，分别实现金属结构22与外延结构21之间的欧姆接触、以及金属结构23与外延结构21之间的欧姆接触，以形成n沟道晶体管的漏极和源极。该步骤之后，所形成的结构如图4D所示。
步骤306，在外延结构11的上表面S2上、靠近侧边的区域，分别形成金属结构13和金属结构14。
该步骤中，可以在外延结构21上表面S2两侧的区域分别沉积金属材料，以形成金属结构22和金属结构23。该金属材料例如可以包括但不限于：钛(Ti)、镍(Ni)、铂(Pt)、钨(W)、钯(Pd)、金(Au)、铝(Al)、氮化钛(TiN)、或者其化合物。然后，采用高温退火工艺，分别实现金属结构22与外延结构21之间的欧姆接触、以及金属结构23与外延结构21之间的欧姆接触，以形成p沟道晶体管的漏极和源极。该步骤之后，所形成的结构如图4E所示。
步骤307，对半导体层12的表面S2、金属结构13和金属结构14之间的区域进行刻蚀，以形成凹槽121。
该步骤中，可以首先在半导体层12表面涂布图案化的掩膜(mask)层。该掩膜层例如可以为光刻胶、介质层和金属中的一种或几种的组合。从而，半导体层12中一些区域被掩膜层覆盖，一些区域暴露出来。然后，通过掩膜层，对半导体层12进行刻蚀。半导体层12中，未被掩膜层覆盖的部分被刻蚀掉，被掩膜层覆盖的部分保留下来，从而形成凹槽121。该步骤之后，所形成的结构如图4F所示。
步骤308，在凹槽121内形成金属氧化物材料122。
金属氧化物材料122例如可以为NiO。该步骤又可以包括如下步骤：步骤3081，在凹槽121内沉积NiO。本申请实施例可以通过各种方式在凹槽121中沉积NiO。第一种可能的实现方式中，可以通过磁控溅射(sputter)工艺，通过控制氧气和氩气的比例，在凹槽121的内壁溅射NiO薄膜。在第二种可能的实现方式中，可以通过脉冲激光沉积(pulsed laser deposition，PLD)工艺，通过控制氧气和氩气的比例，在凹槽121内沉积NiO。步骤3082，去除掉凹槽121之外以及凹槽121中多余的NiO。可以采用剥离或者刻蚀等工艺，去除凹槽121之外以及凹槽121中多余的NiO。在一种可选的实现方式中，可以采用各项同性的干法刻蚀工艺，将凹槽121底部的NiO刻蚀掉，仅保留凹槽121侧壁上贴附的NiO。该步骤之后所形成的结构如图4G所示。
步骤309，在凹槽121内、未设置金属氧化物材料122的区域沉积介质材料123。
该步骤中，可以采用原子层沉积(ALD，atomic layer deposition)或者等离子体增强化学气相沉积(PECVD，plasma enhanced chemical vapor deposition)等各种沉积工艺，将介质材料123沉积于凹槽121中。其中，介质材料123例如可以包括但不限于：氧化铝、氮化铝、氮化硅、氧化硅等。然后，采用刻蚀等工艺去除凹槽121之外的介质材料以及凹槽表面的部分介质材料123，从而在介质材料123的表面形成凹槽。该步骤之后所形成的结构如图4H所示。
步骤310，分别在凹槽121中所沉积的介质材料123之上、以及半导体结构24之上，沉积金属材料，以形成金属结构15和金属结构25。该步骤中，可以首先在凹槽121中所沉积的介质材料123之上沉积金属材料，在半导体结构24之上沉积金属材料，以形成 金属结构15和金属结构25；然后采用蒸发和退火等工艺，使得介质材料123与金属结构15之间相互接触，以形成栅极，半导体结构24与金属结构25之间形成肖特基接触或欧姆接触，以形成栅极。金属结构15包括嵌入凹槽121中的部分以及设置于半导体层12之上的部分，金属结构15中嵌入凹槽121中的部分被介质材料123包裹。其中，金属材料可以包括但不限于：Ti、Ni、Pt、W、Pd、Au、Al、TiN等金属或化合物。该步骤之后所形成的结构如图4I所示。
步骤311，在如图4I所示的结构中、远离衬底的各表面形成钝化层30，以对各电极以及各半导体层进行保护。
钝化层的材料例如可以为SiN。其中，外延结构11和外延结构21之间的空隙中同样填充有SiN，以对外延结构11和外延结构21之间隔离，并且对外延结构11和外延结构21进行保护。
经过步骤301～步骤311，在同一衬底上形成P沟道晶体管和N沟道晶体管。
步骤312，对钝化层30开孔，以引出各电极，实现P沟道晶体管的电极与N沟道晶体管的电极之间的连接，从而形成互补场效应晶体管100。
需要说明的是，图3所示的制备互补场效应晶体管100的方法为示意性的，在其他可能的场景中，可以包括比图3更多或更少的步骤。例如，步骤304中所示的刻蚀半导体层1022以形成半导体结构24，和步骤307中所示的对半导体层12的表面S2进行刻蚀以形成凹槽121，可以通过同一工序制备出；再例如，步骤305中在外延结构21的上表面S3之上分别形成金属结构22和金属结构23，以及步骤306中在外延结构11的上表面S2上分别形成金属结构13和金属结构14，可以通过同一工序制备出。
基于如上任意实施例所述的互补型场效应晶体管，本申请实施例还提供一种逻辑器件，该逻辑器件由如图1所示的互补型场效应晶体管100制备而成。该逻辑器件例如可以为反相器、与非门或者或非门等。具体参考图5A～图5C。
图5A是本申请实施例提供的反相器的结构示意图。如图5A所示，将互补型场效应晶体管100中的p沟道晶体管p1的栅极与n沟道晶体管n1的栅极通过引线连接，作为信号输入端Vin；p沟道晶体管p1的漏极与n沟道晶体管n1的漏极通过引线相连，作为信号输出端Vout；p沟道晶体管的源极与电源端Vdd通过引线连接；n沟道晶体管的源极与公共地Gnd通过引线连接，从而形成图5A所示的反相器。
图5B是本申请实施例提供的与非门的结构示意图。图5B所示的与非门可以由两个如图1所示的互补型场效应晶体管100制备而成。具体的，p沟道晶体管p1的源极以及p沟道晶体管p2的源极，与电源端Vdd通过引线连接；p沟道晶体管p1的栅极与n沟道晶体管n1的栅极通过引线连接，作为信号输入端Vi1；p沟道晶体管p2的栅极与n沟道晶体管n2的栅极通过引线连接，作为信号输入端Vi2；p沟道晶体管p1的漏极、p沟道晶体管p2的漏极以及n沟道晶体管n1的漏极之间通过引线连接，作为信号输出端Vout；n道晶体管n1的源极与n沟道晶体管n2的漏极通过引线连接，n沟道晶体管n2的源极与公共地Gnd通过引线连接。其中，p沟道晶体管p1和n沟道晶体管n1为其中一互补型场效应晶体管100；p沟道晶体管p2和n沟道晶体管n2为另外一个互补型场效应晶体管100。
图5C是本申请实施例提供的或非门的结构示意图。图5C所示的或非门可以由两个如图1所示的互补型场效应晶体管100制备而成。具体的，p沟道晶体管p1的源极通过引线与电源端Vdd连接；p沟道晶体管p1的漏极与p沟道晶体管p2的源极连接；p沟道晶体管p1的栅极与n沟道晶体管n1的栅极通过引线连接，作为信号输入端Vi1；p沟道晶体管p2的栅极与n沟道晶体管n2的栅极通过引线连接，作为信号输入端Vi2；p沟道晶体管p2的漏极、n沟道晶体管n1的漏极以及n沟道晶体管n2的漏极之间通过引线连接，作为信号输出端Vout；n沟道晶体管n1的源极以及n沟道晶体管n2的源极，与公共地Gnd通过引线连接。其中，p沟道晶体管p1和n沟道晶体管n1为其中一互补型场效应晶体管100；p沟道晶体管p2和n沟道晶体管n2为另外一个互补型场效应晶体管100。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (14)

  1. 一种氮化镓场效应晶体管的结构，其特征在于，包括：
    衬底；
    设置于所述衬底之上的第一外延结构；
    设置于所述第一外延结构之上的半导体层，所述半导体层的上表面设置有凹槽，所述凹槽的内壁设置有第一填充材料，所述第一填充材料的表面设置有第二填充材料；
    所述半导体层之上设置有第一源极结构、第一漏极结构和第一栅极结构，其中，所述第一源极结构和所述第一漏极结构分别设置于所述第一栅极结构的两侧、且互相隔离，所述第一栅极结构设置于所述第二填充材料之上。
  2. 根据权利要求1所述的氮化镓场效应晶体管的结构，其特征在于，所述氮化镓场效应晶体管为互补型场效应晶体管，所述第一外延结构、所述半导体层、所述第一源极结构、所述第一漏极结构以及所述第一栅极结构形成p沟道晶体管；所述氮化镓场效应晶体管还包括n沟道晶体管，所述n沟道晶体管包括：
    设置于所述衬底之上的第二外延结构，所述第一外延结构和所述第二外延结构之间分隔开；
    所述第二外延结构之上设置有第二源极结构、第二漏极结构和第二栅极结构，所述第二源极结构和所述第二漏极设置于所述第二栅极结构两侧、且互相隔离；
    其中，所述第二栅极结构包括设置于所述第二外延结构之上的半导体结构以及设置于所述半导体结构之上的金属结构。
  3. 根据权利要求1或2所述的氮化镓场效应晶体管的结构，其特征在于，
    所述第一填充材料为金属氧化物材料；
    所述第二填充材料为氧化铝、氮化铝、氧化硅和氮化硅中的一项。
  4. 根据权利要求3所述的氮化镓场效应晶体管的结构，其特征在于，所述金属氧化物材料为氧化镍。
  5. 根据权利要求2所述的氮化镓场效应晶体管的结构，其特征在于，所述第一外延结构包括设置于所述衬底之上的氮化镓缓冲层。
  6. 根据权利要求5所述的氮化镓场效应晶体管的结构，其特征在于，所述第一外延结构还包括设置于所述氮化镓缓冲层之上的氮化镓铝层；
    所述第二外延层与所述第一外延层具有相同的结构。
  7. 根据权利要求2所述的氮化镓场效应晶体管的结构，其特征在于，所述半导体层的材料与所述半导体结构的材料相同。
  8. 根据权利要求2所述的氮化镓场效应晶体管的结构，其特征在于，所述第一外延结构和所述第二外延结构之间通过钝化层相互隔离，所述钝化层的材料为氮化硅。
  9. 根据权利要求2所述的氮化镓场效应晶体管的结构，其特征在于，所述第一外延结构和所述第二外延结构之间通过高阻区隔离，所述高阻区是通过在第一外延结构和第二外延结构之间的外延结构中注入离子所形成的，所述离子包括以下之一：氮离子、氦离子或者氢离子。
  10. 一种用于制备氮化镓场效应晶体管的方法，其特征在于，包括：
    提供一衬底；
    在所述衬底之上的形成第一外延结构；
    在所述第一外延结构之上形成半导体层，其中，所述半导体层的上表面设置有凹槽，所述凹槽的内壁设置有第一填充材料，所述第一填充材料的表面设置有第二填充材料；
    所述半导体层之上设置有第一源极结构、第一漏极结构和第一栅极结构，其中，所述第一源极结构和所述第一漏极结构分别设置于所述第一栅极结构的两侧、且互相隔离，所述第一栅极结构设置于所述第二填充材料之上。
  11. 根据权利要求10所述的方法，其特征在于，所述方法还包括：
    在所述衬底之上形成第二外延结构，所述第一外延结构和所述第二外延结构之间分隔开；
    所述第二外延结构之上设置有第二源极结构、第二漏极结构和第二栅极结构，所述第二源极结构和所述第二漏极设置于所述第二栅极结构两侧、且互相隔离；
    其中，所述第二栅极结构包括设置于所述第二外延结构之上的半导体结构以及设置于所述半导体结构之上的金属结构。
  12. 根据权利要求10或11所述的方法，其特征在于，所述第一外延结构和所述第二外延结构，是通过在衬底上沉积多层半导体层、将所述多层半导体层中的每一层半导体层分隔成两部分而形成的；
    其中，所述第一外延结构包括所述多层半导体层中的每一层半导体层的第一部分，所述第二外延结构包括所述多层半导体层中的每一层半导体层的第二部分。
  13. 根据权利要求10-12任一项所述的方法，其特征在于，
    所述第一填充材料为氧化镍；
    所述第二填充材料为氧化铝、氮化铝、氧化硅和氮化硅中的一项。
  14. 一种反相器，其特征在于，所述反相器包括如权利要求2所述的p沟道晶体管以及n沟道晶体管；
    所述p沟道晶体管的源极与电源端耦合，所述n沟道晶体管的源极与地端耦合；
    所述p沟道晶体管的栅极与所述n沟道晶体管的栅极耦合，以用于输入信号；
    所述p沟道晶体管的漏极与所述n沟道晶体管的漏极耦合，以用于输出反相后的信号。
PCT/CN2022/083160 2022-03-25 2022-03-25 氮化镓场效应晶体管的结构和制备方法 WO2023178684A1 (zh)

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CN107735863A (zh) * 2015-07-01 2018-02-23 香港科技大学 增强型双沟道高电子迁移率晶体管
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