WO2019184339A1 - 移位寄存器单元、栅极驱动电路、显示装置以及驱动方法 - Google Patents

移位寄存器单元、栅极驱动电路、显示装置以及驱动方法 Download PDF

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Publication number
WO2019184339A1
WO2019184339A1 PCT/CN2018/113058 CN2018113058W WO2019184339A1 WO 2019184339 A1 WO2019184339 A1 WO 2019184339A1 CN 2018113058 W CN2018113058 W CN 2018113058W WO 2019184339 A1 WO2019184339 A1 WO 2019184339A1
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Prior art keywords
transistor
node
pole
input
circuit
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PCT/CN2018/113058
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English (en)
French (fr)
Inventor
王志冲
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2019535820A priority Critical patent/JP7282677B2/ja
Priority to EP18887210.5A priority patent/EP3779955A4/en
Priority to US16/462,255 priority patent/US10978114B2/en
Priority to KR1020197020075A priority patent/KR102246726B1/ko
Publication of WO2019184339A1 publication Critical patent/WO2019184339A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/007—Use of pixel shift techniques, e.g. by mechanical shift of the physical pixels or by optical shift of the perceived pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1036—Read-write modes for single port memories, i.e. having either a random port or a serial port using data shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0216—Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • Embodiments of the present disclosure relate to a shift register unit, a gate driving circuit, a display device, and a driving method.
  • a pixel array such as a liquid crystal display typically includes a plurality of rows of gate lines and a plurality of columns of data lines interleaved therewith.
  • the driving of the gate lines can be realized by an attached integrated driving circuit.
  • the gate line driving circuit can be directly integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array) to drive the gate line.
  • GOA Gate driver On Array
  • a GOA composed of a plurality of cascaded shift register units may be used to provide a switching state voltage signal for a plurality of rows of gate lines of the pixel array, thereby controlling the plurality of rows of gate lines to be sequentially turned on, and corresponding to the pixel arrays by the data lines.
  • the pixel units of the row provide data signals to form the gray voltages required to display the gray levels of the image, thereby displaying each frame of image.
  • At least one embodiment of the present disclosure provides a shift register unit including an input circuit, a first reset circuit, an output circuit, and a node control circuit.
  • the input circuit is configured to control a level of the first node in response to an input signal; the first reset circuit configured to reset the first node in response to a first reset signal; the output circuit is Configuring to output a drive signal to the output under control of a level of the first node; and the node control circuit is configured to control a level of the second node in response to the drive signal.
  • the shift register unit provided by an embodiment of the present disclosure further includes a node noise reduction circuit and a first output noise reduction circuit.
  • the node noise reduction circuit is configured to perform noise reduction on the first node under control of a level of the second node; and the first output noise reduction circuit is configured to be at the second node Under the control of the level, the output is denoised.
  • the node control circuit includes a first transistor, a second transistor, and a third transistor.
  • a gate of the first transistor and a first pole and a clock signal terminal are connected to receive a clock signal as the driving signal, and a second pole of the first transistor is connected to the second node;
  • the second transistor a gate connected to the first node, a first pole of the second transistor being coupled to the second node, a second pole of the second transistor being coupled to the first voltage terminal to receive the first voltage;
  • the gate of the third transistor and the first pole are connected to the second node, and the second pole of the third transistor is connected to the clock signal end.
  • the node control circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor.
  • a gate of the first transistor and a first pole and a clock signal terminal are connected to receive a clock signal as the driving signal, and a second pole and a third node of the first transistor are connected;
  • a gate of the second transistor a pole connected to the first node, a first pole of the second transistor being connected to the third node, a second pole of the second transistor being coupled to the first voltage terminal to receive a first voltage;
  • a gate of the three transistor is connected to the third node, a first pole of the third transistor and the clock signal terminal are connected to receive the clock signal and serve as the driving signal, and the second transistor is second a pole connected to the second node; and
  • a gate of the fourth transistor is connected to the first node, a first pole of the fourth transistor is connected to the second node, and a fourth transistor is connected
  • the diode is coupled to the first transistor, a first pole of
  • the input circuit includes a fifth transistor. a gate and an input of the fifth transistor are connected to receive the input signal, a first pole and a second voltage terminal of the fifth transistor are connected to receive a second voltage, and a second pole of the fifth transistor The first node is connected.
  • the first reset circuit includes a sixth transistor.
  • a gate of the sixth transistor is connected to the first reset terminal to receive the first reset signal, and a first pole and a third voltage terminal of the sixth transistor are connected to receive a third voltage, the sixth transistor The second pole is coupled to the first node.
  • the output circuit includes a seventh transistor and a storage capacitor.
  • a gate of the seventh transistor is connected to the first node, a first pole of the seventh transistor is connected to a clock signal terminal to receive a clock signal and serve as the driving signal, and a second pole of the seventh transistor And connecting to the output; and the first pole of the storage capacitor is connected to the first node, and the second pole of the storage capacitor is connected to the output end.
  • the node noise reduction circuit includes an eighth transistor. a gate of the eighth transistor is connected to the second node, a first pole of the eighth transistor is connected to the first node, and a second pole of the eighth transistor is connected to the first voltage terminal to receive The first voltage.
  • the first output noise reduction circuit includes a ninth transistor.
  • a gate of the ninth transistor is connected to the second node, a first pole of the ninth transistor is connected to the output end, and a second pole of the ninth transistor is connected to the first voltage terminal to receive the first A voltage.
  • a first control node is disposed in a path in which the input circuit controls a level of the first node, and the input circuit is further configured. To control the level of the first control node.
  • the input circuit is configured to cause the first control node to be connected to the first voltage terminal under the control of the level of the second node.
  • the input circuit includes a fifth transistor, a tenth transistor, and an eleventh transistor.
  • a gate and an input of the fifth transistor are connected to receive the input signal, a first pole and a second voltage terminal of the fifth transistor are connected to receive a second voltage, and a second pole of the fifth transistor
  • the first control node is connected;
  • the gate of the tenth transistor is connected to the input terminal to receive the input signal, and the first pole of the tenth transistor is connected to the first control node, a second pole of the ten transistor is connected to the first node;
  • a gate of the eleventh transistor is connected to the second node, and a first pole of the eleventh transistor is connected to the first control node,
  • the second pole of the eleventh transistor is connected to the first voltage terminal.
  • the input circuit is configured to cause the first control node and the input end to be connected under the control of a level of the first control node,
  • the input is configured to receive the input signal.
  • the input circuit includes a fifth transistor, a tenth transistor, and an eleventh transistor.
  • a gate of the fifth transistor and the input terminal are connected to receive the input signal, a first pole and a second voltage terminal of the fifth transistor are connected to receive a second voltage, and a second of the fifth transistor a pole connected to the first control node;
  • a gate of the tenth transistor and the input terminal are connected to receive the input signal, and a first pole of the tenth transistor is connected to the first control node, a second pole of the tenth transistor is connected to the first node;
  • a gate of the eleventh transistor and a first pole are connected to the first control node, and a second pole of the eleventh transistor The input is connected.
  • the first reset circuit and the input circuit are symmetrically configured to allow bidirectional scanning.
  • a shift register unit provided by an embodiment of the present disclosure further includes a second reset circuit and a second output noise reduction circuit.
  • the second reset circuit is configured to reset the first node in response to a second reset signal; the second output noise reduction circuit is configured to drop the output in response to the second reset signal noise.
  • the second reset circuit includes a fourteenth transistor; a gate of the fourteenth transistor and a second reset terminal are connected to receive the second reset a signal, a first pole of the fourteenth transistor is coupled to the first node, and a second pole of the fourteenth transistor is coupled to the first voltage terminal to receive the first voltage.
  • the second output noise reduction circuit includes a fifteenth transistor; a gate of the fifteenth transistor and the second reset terminal are connected to receive the second reset signal, a first pole of the fifteenth transistor Connected to the output, the second pole of the fifteenth transistor and the first voltage terminal are connected to receive the first voltage.
  • At least one embodiment of the present disclosure also provides a gate driving circuit including a plurality of cascaded shift register units as provided by embodiments of the present disclosure.
  • At least one embodiment of the present disclosure also provides a display device including a gate driving circuit as provided by an embodiment of the present disclosure.
  • At least one embodiment of the present disclosure also provides a driving method of any one of the above shift register units, comprising: the node control circuit controlling a level of the second node in response to the driving signal.
  • 1 is a circuit diagram of a shift register unit
  • FIG. 2 is a timing chart of signals corresponding to the operation of the shift register unit shown in FIG. 1;
  • FIG. 3 is a schematic block diagram of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 4 is a circuit diagram showing an implementation example of the shift register unit shown in FIG. 3;
  • FIG. 5 is a circuit diagram showing another implementation example of the shift register unit shown in FIG. 3;
  • FIG. 6 is a schematic block diagram of another shift register unit according to an embodiment of the present disclosure.
  • FIG. 7 is a circuit diagram showing an implementation example of the shift register unit shown in FIG. 6;
  • FIG. 8 is a schematic block diagram of still another shift register unit according to an embodiment of the present disclosure.
  • FIG. 9 is a circuit diagram showing an implementation example of the shift register unit shown in FIG. 8;
  • Figure 10 is a timing chart of signals corresponding to the operation of the shift register unit shown in Figure 9;
  • FIG. 11 is a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 12 is a timing chart of signals corresponding to the operation of the gate driving circuit shown in FIG. 11;
  • FIG. 13 is a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • the display panel in order to realize low cost and narrow bezel, GOA (Gate driver On Array) technology can be adopted, that is, the gate driving circuit is integrated on the display panel through the thin film transistor process, thereby achieving narrow bezel and reducing assembly cost, etc.
  • GOA Gate driver On Array
  • the display panel may be a liquid crystal display (LCD) panel or an organic light emitting diode (OLED) display panel.
  • FIG. 1 shows a circuit structure of a shift register unit which can be cascaded to form a gate drive circuit.
  • the shift register unit includes ten transistors (T1 to T10) and a storage capacitor (C1).
  • the first transistor T1 has its gate and a first pole connected to a fourth voltage terminal VGH (for example, an input DC high-level signal), and a second pole connected to the third node PD_CN.
  • VGH for example, an input DC high-level signal
  • the second transistor T2 has a gate connected to the first node PU, a first pole connected to the third node PD_CN, and a second pole connected to the first voltage terminal VGL (eg, maintaining an input DC low level signal).
  • the third transistor T3 has a gate connected to the third node PD_CN, a first pole connected to the fourth voltage terminal VGH, and a second pole connected to the second node PD.
  • the fourth transistor T4 has a gate connected to the first node PU, a first pole connected to the second node PD, and a second pole connected to the first voltage terminal VGL.
  • the fifth transistor T5 has a gate connected to the input terminal INPUT, a first pole connected to the second voltage terminal VFD, and a second pole connected to the first node PU.
  • the sixth transistor T6 has a gate connected to the first reset terminal RST1, a first pole connected to the first node PU, and a second pole connected to the third voltage terminal VBD.
  • the seventh transistor T7 has a gate connected to the first node PU, a first pole connected to the clock signal terminal CLK, and a second pole connected to the output terminal OUT.
  • the eighth transistor T8 has a gate connected to the second node PD, a first pole connected to the first node PU, and a second pole connected to the first voltage terminal VGL.
  • the ninth transistor T9 has a gate connected to the second node PD, a first pole connected to the output terminal OUT, and a second pole connected to the first voltage terminal VGL.
  • the tenth transistor T10 has a gate connected to the second reset terminal RST2, a first electrode connected to the output terminal OUT, and a second electrode connected to the first voltage terminal VGL.
  • the storage capacitor C1 has a first pole connected to the first node PU and a second pole connected to the output terminal OUT.
  • the above transistors are all N-type transistors.
  • the following description is also made by taking an N-type transistor as an example, but the embodiment of the present disclosure is not limited to this case, for example, at least part of these transistors may be replaced with a P-type transistor.
  • the shift register unit shown in FIG. 1 can realize bidirectional scanning, for example, when the second voltage terminal VFD maintains an input DC high level signal and the third voltage terminal VBD maintains an output DC low level signal, forward scanning can be realized; When the second voltage terminal VFD maintains the input DC low level signal and the third voltage terminal VBD maintains the output DC high level signal, reverse scanning can be implemented. It should be noted that the forward scan and the reverse scan in the present disclosure are relative.
  • the operation principle of the shift register unit shown in FIG. 1 will be described by taking the forward scan as an example and the signal timing shown in FIG. 2, and the input phase A, the output phase B, and the reset phase C shown in FIG. 2 are three. In one stage, the shift register unit performs the following operations.
  • the clock signal terminal CLK inputs a low level signal
  • the input terminal INPUT inputs a high level signal. Since the input terminal INPUT inputs a high level signal, the third transistor T5 is turned on, so that the high level of the input terminal INPUT input charges the storage capacitor C1, and the potential of the first node PU is pulled up to the first high level.
  • the fourth voltage terminal VGH may be set to maintain the input DC high level signal, the first transistor T1 remains turned on, and the high level input by the fourth voltage terminal VGH controls the potential of the third node PD_CN, for example, to perform charging. Also, since the potential of the first node PU is at the first high level, the second transistor T2 is turned on, thereby electrically connecting the third node PD_CN and the first voltage terminal VGL.
  • the first voltage terminal VGL may be set to hold an input DC low level signal.
  • the first transistor T1 and the second transistor T2 may be configured (for example, a size ratio of the two, a threshold voltage, etc.).
  • the potential of the third node PD_CN is pulled. Down to a lower level, this low level does not cause the third transistor T3 to be fully turned on. Also, since the potential of the first node PU is at the first high level, the fourth transistor T4 is turned on, so that the potential of the second node PD is pulled low to a low level. It should be noted that the potential level of the signal timing diagram shown in FIG. 2 is only illustrative and does not represent a true potential value.
  • the seventh transistor T7 Since the first node PU is at the first high level, the seventh transistor T7 is turned on, and at this time, the clock signal terminal CLK is input to the low level, so at this stage, the output terminal OUT outputs the low level signal.
  • the clock signal terminal CLK inputs a high level signal
  • the input terminal INPUT inputs a low level signal. Since the input terminal INPUT inputs a low level signal, the fifth transistor T5 is turned off, and the first node PU maintains the first high level of the previous stage, so that the seventh transistor T7 remains turned on, since the clock signal terminal CLK is input at this stage. High level, so the output terminal OUT outputs the high level signal.
  • the high level can pass through the parasitic capacitance of the seventh transistor T7 (including the parasitic capacitance between the gate and the first electrode, and the gate and the second stage).
  • the parasitic capacitance between them) and the storage capacitor C1 raise the potential coupling of the first node PU to the second high level, so that the conduction of the seventh transistor T7 is more sufficient. Since the potential of the first node PU is at a high level, the second transistor T2 and the fourth transistor T4 continue to be turned on, so that the potential of the second node PD continues to remain at a low level.
  • the sixth transistor T6 is turned on, the first node PU is electrically connected to the first voltage terminal VGL, and the potential of the first node PU is pulled low to a low level.
  • the seventh transistor T7 is turned off.
  • the second transistor T2 and the fourth transistor T4 are turned off, the discharge paths of the third node PD_CN and the second node PD are turned off, and the potential of the second node PD is pulled high to the high level.
  • the eighth transistor T8 and the ninth transistor T9 are turned on, respectively pulling the potentials of the first node PU and the output terminal OU1 to a low level input by the first voltage terminal VGL, further eliminating the shift register unit in Noise that may be generated at the output of the non-output stage and at the first node PU.
  • the potential of the third node PD_CN may not completely turn off the third transistor T3, and the high level signal of the fourth voltage terminal VGH will raise the second node.
  • the level of the PD causes the eighth transistor T8 to be partially turned on, which will affect the charging process of the first node PU, and may seriously affect the normal output of the output terminal OUT.
  • the eighth transistor T8 and the ninth transistor T9 are subjected to stress for most of the time displayed in one frame, which affects the first The life of the eight transistor T8 and the ninth transistor T9.
  • the shift register unit when the shift register unit is in the forward scan, the second voltage terminal VFD maintains the input DC high level signal, and the fifth transistor T5 may be subjected to Negative Bias Thermal Stress (NBTS) for a long time. A threshold voltage negative offset occurs. At this time, if switching to the reverse scan, the fifth transistor T5 becomes the reset transistor, then the level of the first node PU may be leaked through the fifth transistor T5 during the input phase, so that the level of the first node PU cannot be maintained. In severe cases, it may affect the normal output of the output terminal OUT.
  • NBTS Negative Bias Thermal Stress
  • At least one embodiment of the present disclosure provides a shift register unit including an input circuit, a first reset circuit, an output circuit, and a node control circuit.
  • the input circuit is configured to control a level of the first node in response to the input signal;
  • the first reset circuit is configured to reset the first node in response to the first reset signal;
  • the output circuit is configured to be powered at the first node
  • the control signal is output to the output terminal under the control of the flat; and the node control circuit is configured to control the level of the second node in response to the drive signal.
  • At least one embodiment of the present disclosure also provides a gate driving circuit, a display device, and a driving method corresponding to the shift register unit described above.
  • the shift register unit, the gate driving circuit, the display device, and the driving method provided by the embodiments of the present disclosure may control the level of the second node PD by the node control circuit to maintain a low level during the input phase, thereby Reducing the influence of the second node PD on the first node PU, so that the first node PU can be pulled up to a higher level in the input phase; at the same time, the potential of the second node PD can be made about 50% in one frame display The low level is maintained for a long period of time, thereby extending the life of the transistor directly connected to the second node PD.
  • One example of an embodiment of the present disclosure provides a shift register unit 100 that includes an input circuit 110, a first reset circuit 120, an output circuit 130, and a node control circuit 140, as shown in FIG.
  • the input circuit 110 is configured to control the level of the first node PU in response to an input signal, such as charging the first node PU.
  • the input circuit 110 is configured to electrically connect the first node PU and the second voltage terminal VFD such that the first node PU can be charged with a high level signal input by the second voltage terminal VFD.
  • the second voltage terminal VFD can be configured to maintain an input DC high-level signal, for example, and the following embodiments are the same, and are not described again.
  • the level of one node (eg, the first node PU, the second node PD, the third node PD_CN, etc.) is controlled, including charging the node to increase the height.
  • Charging a node means, for example, electrically connecting the node to a high level voltage signal to utilize the high level voltage signal to pull up the level of the node; discharging a node indicates, for example, the node
  • a low level voltage signal is electrically coupled to utilize the low level voltage signal to pull down the level of the node.
  • a capacitor electrically coupled to the node can be provided, and charging or discharging the node means charging or discharging a capacitor electrically connected to the node.
  • the first reset circuit 120 is configured to reset the first node PU in response to the first reset signal.
  • the first reset circuit 120 is configured to be connected to the first reset terminal RST1, so that the first node PU and the low level signal or the low voltage terminal can be made under the control of the first reset signal input by the first reset terminal RST1.
  • the low voltage terminal is, for example, a third voltage terminal VBD, so that the first node PU can be reset.
  • the third voltage terminal VBD can be configured to maintain an input DC low-level signal, for example, and the following embodiments are the same, and are not described again.
  • the output circuit 130 is configured to output a drive signal to the output terminal OUT under the control of the level of the first node PU.
  • the output circuit 130 is configured to electrically connect the clock signal terminal CLK and the output terminal OUT under the control of the level of the first node PU, so that the clock signal input by the clock signal terminal CLK can be output as a driving signal to the output terminal. OUT.
  • the node control circuit 140 is configured to control the level of the second node PD in response to the drive signal.
  • the node control circuit 140 is connected to the clock signal terminal CLK, and uses a clock signal input from the clock signal terminal CLK as a driving signal, so that when the clock signal input by the clock signal terminal CLK is at a low level (for example, in the input stage),
  • the two-node PD can be discharged through the clock signal terminal CLK; for example, in a subsequent stage after the reset phase in one frame display, the potential of the second node PD can keep following the clock signal change, so that the potential of the second node PD is at The frame display remains low for approximately 50% of the time.
  • the potential of the second node PD can be kept at the low level in the input phase, thereby lowering the second node PD
  • the influence on the first node PU is such that the first node PU can be pulled up to a higher level during the input phase; at the same time, the potential of the second node PD can be kept low for about 50% of the time in one frame display.
  • the lifetime of the transistor directly connected to the second node PD can be extended.
  • the shift register unit 100 further includes a node noise reduction circuit 150 and a first output noise reduction circuit 160.
  • the node noise reduction circuit 150 is configured to perform noise reduction on the first node PU under the control of the level of the second node PD.
  • the node noise reduction circuit 150 is connected to the first voltage terminal VGL to electrically connect the first node PU and the first voltage terminal VGL under the control of the level of the second node PD, thereby performing the first node PU. Noise reduction.
  • the first voltage terminal VGL can be configured to maintain an input DC low-level signal, for example, and the following embodiments are the same, and details are not described herein again.
  • the first output noise reduction circuit 160 is configured to perform noise reduction on the output terminal OUT under the control of the level of the second node PD.
  • the first output noise reduction circuit 160 electrically connects the output terminal OUT and the first voltage terminal VGL under the control of the level of the second node PD, thereby performing noise reduction on the output terminal OUT.
  • the shift register unit 100 shown in FIG. 3 can be implemented as the circuit structure shown in FIGS. 4 and 5.
  • the node control circuit 140 can be implemented to include a first transistor T1, a second transistor T2, and a third transistor T3.
  • the gate of the first transistor T1 and the first electrode and the clock signal terminal CLK are connected to receive a clock signal as a driving signal, the second pole of the first transistor T1 is connected to the second node PD; the gate and the second transistor T2 a node PU is connected, a first pole of the second transistor T2 is connected to the second node PD, a second pole of the second transistor T2 is connected to the first voltage terminal VGL to receive the first voltage, and a gate of the third transistor T3 One pole is connected to the second node PD, and the second pole of the third transistor T3 is connected to the clock signal terminal CLK.
  • the clock signal terminal CLK inputs a low-level clock signal
  • the first transistor T1 is turned off
  • the third transistor T3 is diode-connected, so that the second node PD can pass.
  • the third transistor T3 and the clock signal terminal CLK are discharged to a low level, thereby reducing the influence of the second node PD on the first node PU such that the first node PU can be pulled high to a higher level during the input phase.
  • the second transistor T2 can be made to have a larger threshold voltage offset design margin, thereby reducing the process difficulty.
  • the clock signal in a subsequent stage after the reset phase, when the clock signal terminal CLK inputs a high-level clock signal, the clock signal can charge the second node PD through the first transistor T1, thereby making the second node PD The potential becomes a high level; when the clock signal terminal CLK inputs a low-level clock signal, the second node PD can be discharged to a low level through the third transistor T3 and the clock signal terminal CLK.
  • the potential of the second node PD may follow the clock signal change, so that the potential of the second node PD remains low for about 50% of the time in one frame display, thereby
  • the transistors directly connected to the second node PD (for example, the eighth transistor T8 and the ninth transistor T9) are not stressed for about 50% of the time in one frame display, and thus can be extended directly to the second node PD.
  • the lifetime of the connected transistor is not stressed for about 50% of the time in one frame display, and thus can be extended directly to the second node PD.
  • the node control circuit 140 can be implemented to include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.
  • the gate of the first transistor T1 and the first electrode and the clock signal terminal CLK are connected to receive a clock signal as a driving signal, the second pole of the first transistor T1 is connected to the third node PD_CN; the gate and the second transistor T2 a node PU is connected, a first pole of the second transistor T2 is connected to the third node PD_CN, a second pole of the second transistor T2 is connected to the first voltage terminal VGL to receive the first voltage, and a gate of the third transistor T3 a three-node PD_CN connection, a first pole of the third transistor T3 is connected to the clock signal terminal CLK to receive a clock signal, a second pole of the third transistor T3 is connected to the second node PD, and a gate and a first node of the fourth transistor T4
  • the PU is connected,
  • the clock signal terminal CLK inputs a clock signal of a high level, and the clock signal can charge the third node PD_CN through the first transistor T1 to make a third The potential of the node PD_CN becomes a high level.
  • the clock signal terminal CLK inputs a low-level clock signal, and since the third node PD_CN can maintain the high level of the previous stage, the third transistor T3 is turned on, and the second node PD can pass the third.
  • the transistor T3 and the clock signal terminal CLK are discharged to a low level, so that the charging process of the first node PU by the input circuit 110 is not affected, so that the charging of the first node PU is more sufficient.
  • the fourth transistor T4 can be made to have a larger threshold voltage offset design margin, thereby reducing the process difficulty.
  • the second transistor T2 and the fourth transistor T4 remain off.
  • the clock signal terminal CLK inputs a high-level clock signal
  • the clock signal can charge the third node PD_CN through the first transistor T1, thereby causing the potential of the third node PD_CN to become a high level, and the third transistor T3 is turned on.
  • the clock signal can charge the second node PD through the third transistor T3, so that the potential of the second node PD becomes a high level; when the clock signal terminal CLK inputs a low-level clock signal, since the third node PD_CN can While maintaining the high level, the third transistor T3 remains on, so the second node PD can be discharged to the low level through the third transistor T3 and the clock signal terminal CLK.
  • the potential of the second node PD may follow the clock signal change, so that the potential of the second node PD remains low for about 50% of the time in one frame display, thereby
  • the transistors directly connected to the second node PD (for example, the eighth transistor T8 and the ninth transistor T9) are not stressed for about 50% of the time in one frame display, and thus can be extended directly to the second node PD.
  • the lifetime of the connected transistor is not stressed for about 50% of the time in one frame display, and thus can be extended directly to the second node PD.
  • the input circuit 110 can be implemented as a fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the input terminal INPUT to receive an input signal
  • the first pole of the fifth transistor T5 is connected to the second voltage terminal VFD to receive the second voltage
  • the second pole of the fifth transistor T5 and the first node PU connection can be implemented as a fifth transistor T5.
  • the first reset circuit 120 can be implemented as a sixth transistor T6.
  • the gate of the sixth transistor T6 is connected to the first reset terminal RST1 to receive the first reset signal, the first pole of the sixth transistor T6 is connected to the third voltage terminal VBD to receive the third voltage, and the second pole of the sixth transistor T6 Connected to the first node PU.
  • the first reset circuit 120 and the input circuit 110 can be considered to be symmetrically arranged, so the shift register unit 100 can be used for bidirectional scanning.
  • the gate driving circuit of the shift register unit 100 is used to drive a display panel for forward scanning, an input signal is provided through the input terminal INPUT, and a first reset signal is provided through the first reset terminal RST1; and when the shift register is adopted
  • the gate driving circuit of the unit 100 drives a display panel for reverse scanning, it is necessary to provide an input signal through the first reset terminal RST1 and a first reset signal through the input terminal INPUT.
  • the output circuit 130 can be implemented to include a seventh transistor T7 and a storage capacitor C1.
  • the gate of the seventh transistor T7 is connected to the first node PU, the first pole of the seventh transistor T7 is connected to the clock signal terminal CLK to receive the clock signal and is used as a driving signal, and the second pole of the seventh transistor T7 is connected to the output terminal OUT.
  • the first pole of the storage capacitor C1 is connected to the first node PU, and the second pole of the storage capacitor C1 is connected to the output terminal OUT.
  • the node noise reduction circuit 150 can be implemented as an eighth transistor T8.
  • the gate of the eighth transistor T8 is connected to the second node PD, the first pole of the eighth transistor T8 is connected to the first node PU, and the second pole of the eighth transistor T8 is connected to the first voltage terminal VGL to receive the first voltage.
  • the first output noise reduction circuit 160 can be implemented as a ninth transistor T9.
  • the gate of the ninth transistor T9 is connected to the second node PD, the first pole of the ninth transistor T9 is connected to the output terminal OUT, and the second pole of the ninth transistor T9 is connected to the first voltage terminal VGL to receive the first voltage.
  • the level of the signal received by the first voltage terminal VGL is referred to as a first voltage, for example, the input DC low level signal is maintained; and the second voltage terminal is The level of the signal received by the VFD is referred to as a second voltage.
  • the second voltage terminal VFD maintains an input DC high level signal, for example, in the shift register unit 100.
  • the second voltage terminal VFD maintains an input DC low level signal;
  • the level of the signal received by the third voltage terminal VBD is referred to as a third voltage, for example, the shift register unit 100 is used for forward scanning.
  • the third voltage terminal VBD maintains the input DC low level signal, and the third voltage terminal VBD maintains the input DC high level signal, for example, when the shift register unit 100 is used for reverse scanning.
  • the following embodiments are the same as those described herein and will not be described again.
  • the high level and the low level are relative.
  • a high level indicates a higher voltage range (eg, a high level can be 5V, 10V, or other suitable voltage), and multiple high levels can be the same or different.
  • a low level indicates a lower voltage range (eg, a low level may employ 0V, -5V, -10V, or other suitable voltage), and multiple low levels may be the same or different.
  • the minimum value of the high level is larger than the maximum value of the low level.
  • the shift register unit 100 further includes a second reset circuit 170 and a second output noise reduction circuit 180.
  • the second reset circuit 170 is configured to reset the first node PU in response to the second reset signal.
  • the second reset circuit 170 is configured to be connected to the second reset terminal RST2, so that the first node PU and the low level signal or the low voltage terminal can be made under the control of the second reset signal input by the second reset terminal RST2.
  • the low voltage terminal is, for example, a first voltage terminal VGL, so that the first node PU can be reset.
  • a second reset signal may be provided at a blanking time between display frames and frames to the first node of all shift register units in the gate drive circuit. The PU performs a reset operation at the same time.
  • the second reset signal is provided at the beginning of the blanking time, and the embodiment of the present disclosure does not limit the specific time phase of providing the second reset signal, for example, The other reset phase of the blanking time provides a second reset signal.
  • the pulse width of the second reset signal provided by the second reset terminal RST2 is adjustable. The following embodiments are the same as those described herein and will not be described again.
  • the second output noise reduction circuit 180 is configured to noise reduce the output terminal OUT in response to the second reset signal.
  • the second output noise reduction circuit 180 is configured to be connected to the second reset terminal RST2, so that the output terminal OUT and the first voltage terminal VGL can be electrically connected under the control of the second reset signal input by the second reset terminal RST2. Therefore, the output terminal OUT is noise-reduced.
  • a second reset signal may be provided at a blanking time between the display frame and the frame to output the OUT of all shift register units in the gate drive circuit. At the same time, noise reduction is performed.
  • the second reset circuit 170 can be implemented as the fourteenth transistor T14.
  • the gate of the fourteenth transistor T14 is connected to the second reset terminal RST2 to receive the second reset signal
  • the first pole of the fourteenth transistor T14 is connected to the first node PU
  • the second pole of the fourteenth transistor T14 is first
  • the voltage terminal VGL is connected to receive the first voltage.
  • the second output noise reduction circuit 180 can be implemented as the fifteenth transistor T15.
  • the gate of the fifteenth transistor T15 is connected to the second reset terminal RST2 to receive the second reset signal, the first pole of the fifteenth transistor T15 is connected to the output terminal OUT, and the second pole of the fifteenth transistor T15 and the first voltage
  • the terminal VGL is connected to receive the first voltage.
  • a first control node N1 is disposed in a path (eg, a charging path) in which the input circuit 110 controls the level of the first node PU, and the input circuit 110 It is also configured to control the level of the first control node N1, for example to charge or discharge the first control node N1.
  • the transistor in the input circuit 110 electrically connected to the first control node N1 and the first node PU can be maintained in a zero bias state, thereby eliminating the risk of the threshold voltage negative offset and preventing the first node after switching the scanning direction.
  • the PU forms a leakage path to prevent the output terminal OUT from having a normal output, which enhances the reliability of the circuit.
  • the input circuit 110 is configured to cause the first control node N1 and the input terminal INPUT to be connected under the control of the level of the first control node N1 (the first is not shown in FIG. 6) Control node N1), the input INPUT is configured to receive an input signal. For example, when the input signal provided by the input terminal INPUT is low, the first control node N1 can be discharged through the input terminal INPUT.
  • the shift register unit 100 shown in FIG. 6 can be implemented as the circuit structure shown in FIG.
  • the input circuit 110 in the shift register unit 100 can be implemented to include a fifth transistor T5, a tenth transistor T10, and an eleventh transistor T11.
  • the gate of the fifth transistor T5 is connected to the input terminal INPUT to receive an input signal, the first pole of the fifth transistor T5 is connected to the second voltage terminal VFD to receive the second voltage, and the second pole of the fifth transistor T5 and the first control
  • the node N1 is connected; the gate of the tenth transistor T10 is connected to the input terminal INPUT to receive an input signal, the first pole of the tenth transistor T10 is connected to the first control node N1, and the second pole of the tenth transistor T10 and the first node PU are connected.
  • the gate of the eleventh transistor T11 and the first electrode are connected to the first control node N1, and the second electrode of the eleventh transistor T11 is connected to the input terminal INPUT.
  • the input signal provided by the input terminal INPUT is at a high level, and the fifth transistor T5 and the tenth transistor T10 are both turned on to make the second voltage of the second voltage terminal VFD.
  • the first node PU is charged such that the potential of the first node PU and the potential of the first control node N1 are pulled high.
  • the output phase the input signal provided by the input terminal INPUT becomes a low level, and the first control node N1 can be discharged to a low level through the eleventh transistor T11 and the input terminal INPUT, and the potential of the first control node N1 is further It is reduced by the coupling effect, for example, due to the parasitic capacitance coupling of the transistor.
  • the fifth transistor T5 since the second voltage terminal VFD maintains the input high level, the fifth transistor T5 has a risk of a negative offset, and the potential of the first control node N1 may be pulled high to the high level. In this case, the first control node N1 can also be discharged to a low level through the eleventh transistor T11 and the input terminal INPUT. In the reset phase, the potential of the first node PU is also pulled low to a low level. In this way, the tenth transistor T10 can maintain the zero bias state for most of the display of the frame, thereby eliminating the risk of the threshold voltage negative offset and preventing the first node PU from forming a leakage path after switching the scanning direction. In order to avoid the normal output of the output terminal OUT, the reliability of the circuit is enhanced.
  • the first reset circuit 120 is symmetrically disposed with the input circuit 110, so the shift register unit 100 can be used for bidirectional scanning. Accordingly, the first reset circuit 120 can be implemented to include a sixth transistor T6, a twelfth transistor T12, and a thirteenth transistor T13. The connection relationship of the transistors in the first reset circuit 120 is as shown in FIG. 7, and details are not described herein again.
  • the gate driving circuit of the shift register unit 100 is used to drive a display panel for forward scanning (ie, inputting an input signal through the input terminal INPUT, inputting a first reset signal through the first reset terminal RST1), the operation is as described above.
  • the second control The node N2 can be discharged to the low level through the thirteenth transistor T13 and the first reset terminal RST1, so that the twelfth transistor T12 can maintain the zero bias state for most of the display of one frame, thereby eliminating the threshold voltage.
  • the risk of negative offset prevents the first node PU from forming a leakage path after switching the scanning direction to avoid the normal output of the output terminal OUT, which enhances the reliability of the circuit.
  • node control circuit 140 in the shift register unit 100 shown in FIG. 6 can also adopt the node control circuit 140 in the shift register unit 100 shown in FIG. 4 , which is not limited in this disclosure.
  • the input circuit 110 is configured to connect the first control node N1 and the first voltage terminal VGL under the control of the level of the second node PD (not shown in FIG. 8) A control node N1).
  • the first control node N1 may discharge through the first voltage terminal VGL.
  • the shift register unit 100 shown in FIG. 8 can be implemented as the circuit structure shown in FIG.
  • the input circuit 110 in the shift register unit 100 can be implemented to include a fifth transistor T5, a tenth transistor T10, and an eleventh transistor T11.
  • the gate of the fifth transistor T5 is connected to the input terminal INPUT to receive an input signal, the first pole of the fifth transistor T5 is connected to the second voltage terminal VFD to receive the second voltage, and the second pole of the fifth transistor T5 and the first control
  • the node N1 is connected; the gate of the tenth transistor T10 is connected to the input terminal INPUT to receive an input signal, the first pole of the tenth transistor T10 is connected to the first control node N1, and the second pole of the tenth transistor T10 and the first node PU are connected.
  • the gate of the eleventh transistor T11 is connected to the second node PD, the first pole of the eleventh transistor T11 is connected to the first control node N1, and the second pole of the eleventh transistor T11 is connected to the first voltage terminal VGL. .
  • the input signal provided by the input terminal INPUT is at a high level, and the fifth transistor T5 and the tenth transistor T10 are both turned on to make the second voltage of the second voltage terminal VFD.
  • the first node PU is charged such that the potential of the first node PU and the potential of the first control node N1 are pulled high.
  • the output phase the input signal provided by the input terminal INPUT becomes a low level, the fifth transistor T5 and the tenth transistor T10 are turned off, and the potential of the first control node N1 is lowered to a low level due to coupling, for example, due to parasitic transistor Capacitive coupling is reduced to a low level.
  • the potential of the first node PU is pulled low to a low level.
  • the eleventh transistor T11 is turned on, so that the first control node N1 can be further discharged. In this way, the tenth transistor T10 can maintain the zero bias state for most of the display of the frame, thereby eliminating the risk of the threshold voltage negative offset and preventing the first node PU from forming a leakage path after switching the scanning direction. In order to avoid the normal output of the output terminal OUT, the reliability of the circuit is enhanced.
  • the first reset circuit 120 and the input circuit 110 are symmetrically arranged, so the shift register unit 100 can be used for bidirectional scanning.
  • the first reset circuit 120 can be implemented to include a sixth transistor T6, a twelfth transistor T12, and a thirteenth transistor T13.
  • the connection relationship of the transistors in the first reset circuit 120 is as shown in FIG. 9, and details are not described herein again.
  • the gate driving circuit of the shift register unit 100 is used to drive a display panel for forward scanning (ie, inputting an input signal through the input terminal INPUT, inputting a first reset signal through the first reset terminal RST1), the operation is as described above.
  • the second control The node N2 can be discharged to the low level through the thirteenth transistor T13, so that the twelfth transistor T12 can maintain the zero bias state for most of the display of the frame, thereby eliminating the risk of the threshold voltage negative shift.
  • the first node PU is prevented from forming a leakage path after switching the scanning direction to prevent the output terminal OUT from having a normal output, thereby enhancing the reliability of the circuit.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching device having the same characteristics.
  • a thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the embodiment of the present disclosure in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described.
  • the transistors in the embodiments of the present disclosure are all described by taking an N-type transistor as an example.
  • the first electrode may be a drain and the second electrode may be a source.
  • the present disclosure includes but is not limited thereto.
  • one or more transistors in the shift register unit provided by the embodiments of the present disclosure may also adopt a P-type transistor.
  • the first pole may be a source
  • the second pole may be a drain, and only needs to be selected.
  • the polarities of the poles of the transistor of a given type may be correspondingly connected according to the polarities of the respective poles of the respective transistors in the embodiment of the present disclosure.
  • the transistors in the shift register unit 100 all adopt N-type transistors, the first voltage terminal VGL maintains the first voltage of the input DC low level, and the second voltage terminal VFD maintains the input DC high level.
  • the second voltage, the third voltage terminal VBD maintains a third voltage of the input DC low level, and the clock signal terminal CLK inputs the clock signal.
  • the clock signal terminal CLK inputs a low-level clock signal
  • the input terminal INPUT inputs a high-level signal. Since the input terminal INTPUT inputs a high level signal, the fifth transistor T5 and the tenth transistor T10 are both turned on, so that the second voltage of the second voltage terminal VFD charges the first node PU, so that the potential of the first node PU is pulled. Up to the first high level while the potential of the first control node N1 is pulled high.
  • the first transistor T1 Since the clock signal terminal CLK inputs a low-level clock signal, the first transistor T1 is turned off, and the third transistor T3 is diode-connected, so that the second node PD can be discharged to the low level through the third transistor T3 and the clock signal terminal CLK. Thereby reducing the influence of the second node PD on the first node PU such that the first node PU can be pulled high to a higher level in the input phase A.
  • the seventh transistor T7 Since the first node PU is at the first high level, the seventh transistor T7 is turned on, and at this time, the clock signal terminal CLK inputs a low-level clock signal, so at this stage, the output terminal OUT outputs a low-level signal.
  • the clock signal terminal CLK inputs a high-level clock signal
  • the input terminal INPUT inputs a low-level signal.
  • the fifth transistor T5 and the tenth transistor T10 are turned off, and the potential of the first control node N1 is lowered to a low level due to coupling, for example, because the parasitic capacitance coupling of the transistor is lowered to a low level. Since the first node PU maintains the high level of the previous stage, so that the seventh transistor T7 is kept turned on, the output terminal OUT outputs the high level signal input from the clock signal terminal CLK at this stage.
  • the high level can pass through the parasitic capacitance of the seventh transistor T7 (including the parasitic capacitance between the gate and the first pole, and between the gate and the second stage)
  • the parasitic capacitance) and the storage capacitor C1 boost the potential coupling of the first node PU to the second high level, so that the conduction of the seventh transistor T7 is more sufficient.
  • the clock signal of the high level input by the clock signal terminal CLK may turn on the first transistor T1, and the clock signal charges the second node PD while the high level of the first node PU turns on the second transistor T2, thereby The level of the second node PD can be pulled low.
  • the first transistor T1 and the second transistor T2 may be configured (for example, a size ratio of the two, a threshold voltage, etc.). When both T1 and T2 are turned on, the potential of the second node PD is Pulling down to a lower level, the low level does not turn on the eighth transistor T8 and the ninth transistor T9.
  • the sixth transistor T6 and the twelfth transistor T12 are turned on, and the first node PU is electrically connected to the third voltage terminal VBD, the first node The potential of the PU is pulled low to the low level, so that the second transistor T2 and the seventh transistor T7 are turned off.
  • the second node PD can be discharged to a low level through the third transistor T3 and the clock signal terminal CLK. Since the second node PD is at a low level, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, and the thirteenth transistor T13 are turned off.
  • the clock signal can charge the second node PD through the first transistor T1, thereby changing the potential of the second node PD.
  • the second node PD can be discharged to a low level through the third transistor T3 and the clock signal terminal CLK. That is, in the subsequent stage after the reset phase, the potential of the second node PD can follow the clock signal change.
  • the eleventh transistor T11 is turned on, so that the first control node N1 can be further discharged.
  • a second reset signal of a high level may be provided through the second reset terminal RST2 in the blanking time between the display frame and the frame, and the fourteenth transistor T14 and the fifteenth transistor T15 are responsive to the second The reset signal is turned on, so that the first node PU of all the shift register units in the gate driving circuit can be simultaneously reset, and the output terminal OUT of all the shift register units in the gate driving circuit can be simultaneously noise-reduced .
  • the potential of the second node PD can be kept low during the input phase, thereby reducing the influence of the second node PD on the first node PU, so that the first node PU is in the input stage. Can be pulled high to a higher level.
  • the potential of the second node PD can be changed following the clock signal, so that the potential of the second node PD is kept low for about 50% of the time in one frame display, thereby enabling The transistor directly connected to the second node PD is not stressed for about 50% of the time in one frame display, thereby extending the life of the transistor directly connected to the second node PD.
  • the tenth transistor T10 can be kept in a zero bias state for most of the display of a frame, thereby eliminating the risk of negative shift of the threshold voltage and preventing the switching direction from being switched.
  • the first node PU forms a leakage path to prevent the output terminal OUT from having a normal output, thereby enhancing the reliability of the circuit.
  • the shift register unit 100 shown in FIG. 9 can exchange the input signal and the first reset signal with each other when the reverse scan is performed, that is, the input terminal INPUT inputs the first reset signal, and the first reset terminal RST1 inputs the input. signal.
  • the second voltage terminal VFD inputs a DC low level signal
  • the third voltage terminal VBD inputs a DC high level signal.
  • the shift register unit 100 operates similarly to the forward scan and will not be described again.
  • At least one embodiment of the present disclosure further provides a gate driving circuit 10, as shown in FIG. 11, the gate driving circuit 10 includes a plurality of cascaded shift register units 100, for example, the shift register unit 100 can adopt the above The shift register unit provided in the embodiment.
  • the gate driving circuit 10 can be directly integrated on the array substrate of the display device by using the same process as the thin film transistor to realize the progressive scan driving function.
  • the input terminal INPUT of the remaining stages of the shift register unit is connected to the output terminal OUT of the shift register unit of the previous stage.
  • the first reset terminal RST1 of the remaining stages of the shift register unit is connected to the output terminal OUT of the shift register unit of the next stage.
  • the input INPUT of the first stage shift register unit can be configured to receive the trigger signal STV
  • the first reset terminal RST1 of the last stage shift register unit can be configured to receive the reset signal RESET.
  • the gate driving circuit 10 may further include a first clock signal line CLK1 and a second clock signal line CLK2.
  • the first clock signal line CLK1 may be configured to be connected to the clock signal terminal CLK of the odd-numbered shift register unit 100
  • the second clock signal line CLK2 may be configured to be connected to the clock signal terminal CLK of the even-numbered shift register unit 100.
  • the first clock signal line CLK1 may also be configured to be connected to the clock signal terminal CLK of the even-numbered shift register unit 100 while the second clock signal line CLK2 is further It can be configured to be connected to the clock signal terminal CLK of the odd-numbered shift register unit 100.
  • the clock signal timings provided on the first clock signal line CLK1 and the second clock signal line CLK2 may employ the signal timings shown in FIG. 12, which are complementary to each other.
  • more clock signal lines may be used to provide more clock signals, for example, four, six, and the like.
  • the gate driving circuit 10 may further include a frame reset signal line TT_RST configured to be connected to the second reset terminal RST2 of each stage shift register 100.
  • the gate drive circuit 10 may further include a timing controller 200.
  • the timing controller 200 is configured, for example, to provide clock signals to the stages of shift register units 100, and the timing controller 200 can also be configured to provide a trigger signal STV and a reset signal RESET.
  • At least one embodiment of the present disclosure also provides a display device 1, as shown in FIG. 13, which includes any of the gate drive circuits 10 provided by the embodiments of the present disclosure.
  • the display device 1 includes an array of a plurality of pixel units 30.
  • the display device 1 may further include a data driving circuit 20.
  • the data driving circuit 20 is for providing a data signal to the pixel array;
  • the gate driving circuit 10 is for providing a gate scanning signal to the pixel array.
  • the data driving circuit 20 is electrically connected to the pixel unit 30 through the data line 21, and the gate driving circuit 10 is electrically connected to the pixel unit 30 through the gate line 11.
  • the display device 1 in this embodiment may be: a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigation device, etc. Functional product or part.
  • the display device 1 may further include other conventional components such as a display panel, and embodiments of the present disclosure are not limited thereto.
  • At least one embodiment of the present disclosure also provides a driving method that can be used to drive any of the shift register units 100 provided in the embodiments of the present disclosure, in which the node control circuit 140 responds to the second pair of driving signals.
  • the level of the node PD is controlled.
  • the second node PD is alternately discharged and charged such that the potential of the second node PD alternates between a low level and a high level.
  • the clock signal can be received through the clock signal terminal CLK and used as a drive signal.
  • the driving method includes the following operations.
  • a first phase eg, an input phase
  • the input circuit 110 charges the first node PU in response to the input signal
  • the output circuit 130 outputs a low level of the clock signal to the output terminal OUT
  • the node control circuit 140 is responsive to the clock signal The low level discharges the second node PD such that the potential of the second node PD remains at a low level.
  • the output circuit 130 outputs a high level of the clock signal to the output terminal OUT under the control of the level of the first node PU; the node control circuit 140 is responsive to the high level of the clock signal.
  • the second node PD is charged, but at the same time the node control circuit 140 has a discharge path of the second node PD such that the potential of the second node PD remains at a low level at this stage.
  • a third phase (eg, a reset phase)
  • the first reset circuit 120 resets the first node PU in response to the first reset signal
  • the node control circuit 140 discharges the second node PD in response to a low level of the clock signal such that The potential of the second node PD remains low.
  • a fourth phase (eg, a subsequent phase after the reset phase)
  • the node control circuit 140 alternately discharges and charges the second node PD in response to the clock signal such that the potential of the second node PD alternates between a low level and a high level. Variety.

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Abstract

一种移位寄存器单元、栅极驱动电路、显示装置以及驱动方法。该移位寄存器单元（100）包括输入电路（110）、第一复位电路（120）、输出电路（130）和节点控制电路（140）。输入电路（110）被配置为响应于输入信号对第一节点（PU）的电平进行控制；第一复位电路（120）被配置为响应于第一复位信号对第一节点（PU）进行复位；输出电路（130）被配置为在第一节点（PU）的电平的控制下，将驱动信号输出至输出端（OUT）；以及节点控制电路（140）被配置为响应于时钟信号对第二节点（PD）的电平进行控制。该移位寄存器单元可以避免第二节点（PD）的电平影响对第一节点（PU）的电平的控制过程。

Description

移位寄存器单元、栅极驱动电路、显示装置以及驱动方法
本申请要求于2018年3月30日递交的中国专利申请第201810276380.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器单元、栅极驱动电路、显示装置以及驱动方法。
背景技术
在显示技术领域，例如液晶显示的像素阵列通常包括多行栅线和与之交错的多列数据线。对栅线的驱动可以通过贴附的集成驱动电路实现。近几年随着非晶硅薄膜工艺的不断提高，也可以将栅线驱动电路直接集成在薄膜晶体管阵列基板上构成GOA(Gate driver On Array)来对栅线进行驱动。
例如，可以采用由多个级联的移位寄存器单元构成的GOA为像素阵列的多行栅线提供开关态电压信号，从而控制多行栅线依序打开，并由数据线向像素阵列中对应行的像素单元提供数据信号，以形成显示图像的各灰阶所需要的灰度电压，进而显示每一帧图像。
发明内容
本公开至少一实施例提供一种移位寄存器单元，包括输入电路、第一复位电路、输出电路和节点控制电路。所述输入电路被配置为响应于输入信号对第一节点的电平进行控制；所述第一复位电路被配置为响应于第一复位信号对所述第一节点进行复位；所述输出电路被配置为在所述第一节点的电平的控制下，将驱动信号输出至输出端；以及所述节点控制电路被配置为响应于所述驱动信号对第二节点的电平进行控制。
例如，本公开一实施例提供的移位寄存器单元还包括节点降噪电路、第一输出降噪电路。所述节点降噪电路被配置为在所述第二节点的电平的 控制下，对所述第一节点进行降噪；以及所述第一输出降噪电路被配置为在所述第二节点的电平的控制下，对所述输出端进行降噪。
例如，在本公开一实施例提供的移位寄存器单元中，所述节点控制电路包括第一晶体管、第二晶体管和第三晶体管。所述第一晶体管的栅极以及第一极和时钟信号端连接以接收时钟信号并作为所述驱动信号，所述第一晶体管的第二极和所述第二节点连接；所述第二晶体管的栅极和所述第一节点连接，所述第二晶体管的第一极和所述第二节点连接，所述第二晶体管的第二极和第一电压端连接以接收第一电压；以及所述第三晶体管的栅极以及第一极和所述第二节点连接，所述第三晶体管的第二极和所述时钟信号端连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述节点控制电路包括第一晶体管、第二晶体管、第三晶体管和第四晶体管。所述第一晶体管的栅极以及第一极和时钟信号端连接以接收时钟信号并作为所述驱动信号，所述第一晶体管的第二极和第三节点连接；所述第二晶体管的栅极和所述第一节点连接，所述第二晶体管的第一极和所述第三节点连接，所述第二晶体管的第二极和第一电压端连接以接收第一电压；所述第三晶体管的栅极和所述第三节点连接，所述第三晶体管的第一极和所述时钟信号端连接以接收所述时钟信号并作为所述驱动信号，所述第三晶体管的第二极和所述第二节点连接；以及所述第四晶体管的栅极和所述第一节点连接，所述第四晶体管的第一极和所述第二节点连接，所述第四晶体管的第二极和所述第一电压端连接以接收所述第一电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述输入电路包括第五晶体管。所述第五晶体管的栅极和输入端连接以接收所述输入信号，所述第五晶体管的第一极和第二电压端连接以接收第二电压，所述第五晶体管的第二极和所述第一节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一复位电路包括第六晶体管。所述第六晶体管的栅极和第一复位端连接以接收所述第一复位信号，所述第六晶体管的第一极和第三电压端连接以接收第三电压，所述第六晶体管的第二极和所述第一节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出电路包括第七晶体管和存储电容。所述第七晶体管的栅极和所述第一节点连接， 所述第七晶体管的第一极和时钟信号端连接以接收时钟信号并作为所述驱动信号，所述第七晶体管的第二极和所述输出端连接；以及所述存储电容的第一极和所述第一节点连接，所述存储电容的第二极和所述输出端连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述节点降噪电路包括第八晶体管。所述第八晶体管的栅极和所述第二节点连接，所述第八晶体管的第一极和所述第一节点连接，所述第八晶体管的第二极和第一电压端连接以接收第一电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一输出降噪电路包括第九晶体管。所述第九晶体管的栅极和所述第二节点连接，所述第九晶体管的第一极和所述输出端连接，所述第九晶体管的第二极和第一电压端连接以接收第一电压。
例如，在本公开一实施例提供的移位寄存器单元中，在所述输入电路对所述第一节点的电平进行控制的路径中设置有第一控制节点，且所述输入电路还被配置为对所述第一控制节点的电平进行控制。
例如，在本公开一实施例提供的移位寄存器单元中，所述输入电路被配置为在所述第二节点的电平的控制下使得所述第一控制节点和第一电压端连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述输入电路包括第五晶体管、第十晶体管和第十一晶体管。所述第五晶体管的栅极和输入端连接以接收所述输入信号，所述第五晶体管的第一极和第二电压端连接以接收第二电压，所述第五晶体管的第二极和所述第一控制节点连接；所述第十晶体管的栅极和所述输入端连接以接收所述输入信号，所述第十晶体管的第一极和所述第一控制节点连接，所述第十晶体管的第二极和所述第一节点连接；所述第十一晶体管的栅极和所述第二节点连接，所述第十一晶体管的第一极和所述第一控制节点连接，所述第十一晶体管的第二极和所述第一电压端连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述输入电路被配置为在所述第一控制节点的电平的控制下使得所述第一控制节点和输入端连接，所述输入端被配置为接收所述输入信号。
例如，在本公开一实施例提供的移位寄存器单元中，所述输入电路包括第五晶体管、第十晶体管和第十一晶体管。所述第五晶体管的栅极和所 述输入端连接以接收所述输入信号，所述第五晶体管的第一极和第二电压端连接以接收第二电压，所述第五晶体管的第二极和所述第一控制节点连接；所述第十晶体管的栅极和所述输入端连接以接收所述输入信号，所述第十晶体管的第一极和所述第一控制节点连接，所述第十晶体管的第二极和所述第一节点连接；所述第十一晶体管的栅极以及第一极和所述第一控制节点连接，所述第十一晶体管的第二极和所述输入端连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一复位电路和所述输入电路对称配置以允许实现双向扫描。
例如，本公开一实施例提供的移位寄存器单元还包括第二复位电路和第二输出降噪电路。所述第二复位电路被配置为响应于第二复位信号对所述第一节点进行复位；所述第二输出降噪电路被配置为响应于所述第二复位信号对所述输出端进行降噪。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二复位电路包括第十四晶体管；所述第十四晶体管的栅极和第二复位端连接以接收所述第二复位信号，所述第十四晶体管的第一极和所述第一节点连接，所述第十四晶体管的第二极和第一电压端连接以接收第一电压。所述第二输出降噪电路包括第十五晶体管；所述第十五晶体管的栅极和所述第二复位端连接以接收所述第二复位信号，所述第十五晶体管的第一极和所述输出端连接，所述第十五晶体管的第二极和所述第一电压端连接以接收所述第一电压。
本公开至少一实施例还提供一种栅极驱动电路，包括多个级联的如本公开的实施例提供的移位寄存器单元。
本公开至少一实施例还提供一种显示装置，包括如本公开的实施例提供的栅极驱动电路。
本公开至少一实施例还提供上述任意一种移位寄存器单元的驱动方法，包括：所述节点控制电路响应于所述驱动信号对所述第二节点的电平进行控制。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实 施例，而非对本公开的限制。
图1为一种移位寄存器单元的电路示意图；
图2为对应于图1中所示的移位寄存器单元工作时的信号时序图；
图3为本公开一实施例提供的一种移位寄存器单元的示意框图；
图4为图3中所示的移位寄存器单元的一种实现示例的电路示意图；
图5为图3中所示的移位寄存器单元的另一种实现示例的电路示意图；
图6为本公开一实施例提供的另一种移位寄存器单元的示意框图；
图7为图6中所示的移位寄存器单元的一种实现示例的电路示意图；
图8为本公开一实施例提供的又一种移位寄存器单元的示意框图；
图9为图8中所示的移位寄存器单元的一种实现示例的电路示意图；
图10为对应于图9中所示的移位寄存器单元工作时的信号时序图；
图11为本公开一实施例提供的一种栅极驱动电路的示意图；
图12为对应于图11中所示的栅极驱动电路工作时的信号时序图；以及
图13为本公开一实施例提供的一种显示装置的示意框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在显示面板技术中，为了实现低成本和窄边框，可以采用GOA(Gate driver On Array)技术，即将栅极驱动电路通过薄膜晶体管工艺集成在显示面板上，从而可以实现窄边框和降低装配成本等优势。该显示面板可以为液晶显示(LCD)面板或有机发光二极管(OLED)显示面板。
图1示出了一种移位寄存器单元的电路结构，该移位寄存器单元可以被级联以形成栅极驱动电路。如图1所示，该移位寄存器单元包括十个晶体管(T1至T10)和存储电容(C1)。
第一晶体管T1，其栅极以及第一极和第四电压端VGH(例如保持输入直流高电平信号)连接，第二极和第三节点PD_CN连接。
第二晶体管T2，其栅极和第一节点PU连接，第一极和第三节点PD_CN连接，第二极和第一电压端VGL(例如保持输入直流低电平信号)连接。
第三晶体管T3，其栅极和第三节点PD_CN连接，第一极和第四电压端VGH连接，第二极和第二节点PD连接。
第四晶体管T4，其栅极和第一节点PU连接，第一极和第二节点PD连接，第二极和第一电压端VGL连接。
第五晶体管T5，其栅极和输入端INPUT连接，第一极和第二电压端VFD连接，第二极和第一节点PU连接。
第六晶体管T6，其栅极和第一复位端RST1连接，第一极和第一节点PU连接，第二极和第三电压端VBD连接。
第七晶体管T7，其栅极和第一节点PU连接，第一极和时钟信号端CLK连接，第二极和输出端OUT连接。
第八晶体管T8，其栅极和第二节点PD连接，第一极和第一节点PU连接，第二极和第一电压端VGL连接。
第九晶体管T9，其栅极和第二节点PD连接，第一极和输出端OUT连接，第二极和第一电压端VGL连接。
第十晶体管T10，其栅极和第二复位端RST2连接，第一极和输出端OUT连接，第二极和第一电压端VGL连接。
存储电容C1，其第一极和第一节点PU连接，第二极和输出端OUT连接。
例如上述晶体管均为N型晶体管。下面也以N型晶体管为例进行说明，但是本公开的实施例不限于这种情形，例如这些晶体管中至少部分可以替换 为P型晶体管。
图1中所示的移位寄存器单元可以实现双向扫描，例如当第二电压端VFD保持输入直流高电平信号且第三电压端VBD保持输出直流低电平信号时，可以实现正向扫描；当第二电压端VFD保持输入直流低电平信号且第三电压端VBD保持输出直流高电平信号时，可以实现反向扫描。需要说明的是，本公开中的正向扫描和反向扫描是相对而言的。
下面以正向扫描为例并结合图2所示的信号时序来说明图1所示的移位寄存器单元的工作原理，在图2所示的输入阶段A、输出阶段B以及复位阶段C共三个阶段中，该移位寄存器单元进行如下操作。
在输入阶段A，时钟信号端CLK输入低电平信号，输入端INPUT输入高电平信号。由于输入端INPUT输入高电平信号，第三晶体管T5导通，使得输入端INPUT输入的高电平对存储电容C1进行充电，第一节点PU的电位被拉高至第一高电平。
例如第四电压端VGH可以设置为保持输入直流高电平信号，第一晶体管T1保持导通，第四电压端VGH输入的高电平对第三节点PD_CN的电位进行控制，例如进行充电。又由于第一节点PU的电位为第一高电平，第二晶体管T2导通，从而使得第三节点PD_CN和第一电压端VGL电连接。这里，例如第一电压端VGL可以设置为保持输入直流低电平信号。在晶体管的设计上，可以将第一晶体管T1和第二晶体管T2配置为(例如对二者的尺寸比、阈值电压等配置)在T1和T2均导通时，第三节点PD_CN的电位被拉低到一个较低的电平，该低电平不会使第三晶体管T3完全开启。又由于第一节点PU的电位为第一高电平，第四晶体管T4导通，使得第二节点PD的电位被拉低至低电平。需要说明的是，图2中所示的信号时序图的电位高低仅是示意性的，不代表真实电位值。
由于第一节点PU处于第一高电平，第七晶体管T7导通，此时时钟信号端CLK输入低电平，所以在此阶段，输出端OUT输出该低电平信号。
在输出阶段B，时钟信号端CLK输入高电平信号，输入端INPUT输入低电平信号。由于输入端INPUT输入低电平信号，第五晶体管T5截止，第一节点PU保持上一阶段的第一高电平，从而使得第七晶体管T7保持导通，由于在此阶段时钟信号端CLK输入高电平，所以输出端OUT输出该高电平信号。
同时，由于时钟信号端CLK以及输出端OUT为高电平，该高电平可以通过第七晶体管T7的寄生电容(包括栅极和第一极之间的寄生电容，以及栅极和第二级之间的寄生电容)和存储电容C1将第一节点PU的电位耦合升高至第二高电平，使得第七晶体管T7的导通更充分。由于第一节点PU的电位为高电平，第二晶体管T2和第四晶体管T4继续导通，使得第二节点PD的电位继续保持在低电平。
在复位阶段C，由于第一复位端RST1输入高电平信号，第六晶体管T6导通，第一节点PU与第一电压端VGL电连接，第一节点PU的电位被拉低至低电平，从而第七晶体管T7截止。
由于第一节点PU的电位处于低电平，第二晶体管T2和第四晶体管T4截止，第三节点PD_CN和第二节点PD的放电路径被截止，第二节点PD的电位被拉高至高电平，由此使得第八晶体管T8和第九晶体管T9导通，分别将第一节点PU以及输出端OU1的电位拉低至第一电压端VGL输入的低电平，进一步消除了移位寄存器单元在非输出阶段其输出端和第一节点PU处可能产生的噪声。
上述移位寄存器单元在工作时，在输入阶段A中，第三节点PD_CN的电位可能无法将第三晶体管T3完全截止，此时第四电压端VGH的高电平信号就会拉高第二节点PD的电平，从而造成第八晶体管T8部分导通，这将会影响第一节点PU的充电过程，严重时可能会影响输出端OUT的正常输出。在复位阶段C以及以后的阶段中，由于第二节点PD一直保持高电平，使得第八晶体管T8和第九晶体管T9在一帧显示的大部分时间内都受到应力(stress)，会影响第八晶体管T8和第九晶体管T9的寿命。
另外，上述移位寄存器单元在正向扫描时，第二电压端VFD保持输入直流高电平信号，第五晶体管T5因长时间受负偏压热应力(Negative Bias Thermal Stress,NBTS)而可能会发生阈值电压负向偏移。此时如果切换为反向扫描，第五晶体管T5变为复位晶体管，那么在输入阶段第一节点PU的电平可能通过第五晶体管T5而发生漏电，从而使得第一节点PU的电平无法保持，严重时可能会影响输出端OUT的正常输出。
本公开至少一实施例提供一种移位寄存器单元，其包括输入电路、第一复位电路、输出电路和节点控制电路。输入电路被配置为响应于输入信号对第一节点的电平进行控制；第一复位电路被配置为响应于第一复位信号对第 一节点进行复位；输出电路被配置为在第一节点的电平的控制下，将驱动信号输出至输出端；以及节点控制电路被配置为响应于驱动信号对第二节点的电平进行控制。
本公开至少一实施例还提供对应于上述移位寄存器单元的栅极驱动电路、显示装置以及驱动方法。
本公开的实施例提供的移位寄存器单元、栅极驱动电路、显示装置以及驱动方法，可以通过节点控制电路对第二节点PD的电平进行控制，使其在输入阶段保持低电平，从而降低第二节点PD对第一节点PU的影响，使得第一节点PU在输入阶段可以被拉高至较高的电平；同时可以使得第二节点PD的电位在一帧显示中约50％的时间内保持低电平，从而可以延长和第二节点PD直接连接的晶体管的使用寿命。
下面结合附图对本公开的实施例及其示例进行详细说明。
本公开的实施例的一个示例提供一种移位寄存器单元100，如图3所示，该移位寄存器单元100包括输入电路110、第一复位电路120、输出电路130和节点控制电路140。
该输入电路110被配置为响应于输入信号对第一节点PU的电平进行控制，例如对第一节点PU进行充电。例如，该输入电路110配置为使第一节点PU和第二电压端VFD电连接，从而可以利用第二电压端VFD输入的高电平信号对第一节点PU进行充电。需要说明的是，第二电压端VFD例如可以配置为保持输入直流高电平信号，以下各实施例与此相同，不再赘述。
需要说明的是，在本公开的实施例中，对一个节点(例如第一节点PU、第二节点PD、第三节点PD_CN等)的电平进行控制，包括对该节点进行充电以拉高该节点的电平，或者对该节点进行放电以拉低该节点的电平。对一个节点进行充电表示例如将该节点与一个高电平的电压信号电连接，从而利用该高电平的电压信号以拉高该节点的电平；对一个节点进行放电表示例如将该节点与一个低电平的电压信号电连接，从而利用该低电平的电压信号以拉低该节点的电平。例如，可以设置一个与该节点电连接的电容，对该节点进行充电或放电即表示对与该节点电连接的电容进行充电或放电。
该第一复位电路120被配置为响应于第一复位信号对第一节点PU进行复位。例如，该第一复位电路120配置为和第一复位端RST1连接，从而可以在第一复位端RST1输入的第一复位信号的控制下，使得第一节点PU和 低电平信号或低电压端电连接，该低电压端例如为第三电压端VBD，从而可以对第一节点PU进行复位。需要说明的是，第三电压端VBD例如可以配置为保持输入直流低电平信号，以下各实施例与此相同，不再赘述。
该输出电路130被配置为在第一节点PU的电平的控制下，将驱动信号输出至输出端OUT。例如，该输出电路130配置为在第一节点PU的电平的控制下，使时钟信号端CLK和输出端OUT电连接，从而可以将时钟信号端CLK输入的时钟信号作为驱动信号输出至输出端OUT。
该节点控制电路140被配置为响应于驱动信号对第二节点PD的电平进行控制。例如，该节点控制电路140和时钟信号端CLK连接，将时钟信号端CLK输入的时钟信号作为驱动信号，从而在时钟信号端CLK输入的时钟信号为低电平时(例如在输入阶段时)，第二节点PD可以通过时钟信号端CLK放电；又例如，在一帧显示中复位阶段以后的后续阶段中，第二节点PD的电位可以保持跟随时钟信号变化，从而使得第二节点PD的电位在一帧显示中约50％的时间内保持低电平。
在本公开的实施例提供的移位寄存器单元100中，通过设置和时钟信号端CLK连接的节点控制电路140可以使得第二节点PD的电位在输入阶段保持低电平，从而降低第二节点PD对第一节点PU的影响，使得第一节点PU在输入阶段可以拉高至较高的电平；同时可以使得第二节点PD的电位在一帧显示中约50％的时间内保持低电平，从而可以延长和第二节点PD直接连接的晶体管的使用寿命。
例如，如图3所示，在本实施例的另一个示例中，该移位寄存器单元100还包括节点降噪电路150和第一输出降噪电路160。
该节点降噪电路150被配置为在第二节点PD的电平的控制下，对第一节点PU进行降噪。例如，该节点降噪电路150和第一电压端VGL连接，以在第二节点PD的电平的控制下，使第一节点PU和第一电压端VGL电连接，从而对第一节点PU进行降噪。需要说明的是，第一电压端VGL例如可以配置为保持输入直流低电平信号，以下各实施例与此相同，不再赘述。
该第一输出降噪电路160被配置为在第二节点PD的电平的控制下，对输出端OUT进行降噪。例如，该第一输出降噪电路160在第二节点PD的电平的控制下，使输出端OUT和第一电压端VGL电连接，从而对输出端OUT进行降噪。
例如，图3中所示的移位寄存器单元100可以实现为图4和图5所示的电路结构。
如图4所示，在一个示例中，节点控制电路140可以实现为包括第一晶体管T1、第二晶体管T2和第三晶体管T3。第一晶体管T1的栅极以及第一极和时钟信号端CLK连接以接收时钟信号并作为驱动信号，第一晶体管T1的第二极和第二节点PD连接；第二晶体管T2的栅极和第一节点PU连接，第二晶体管T2的第一极和第二节点PD连接，第二晶体管T2的第二极和第一电压端VGL连接以接收第一电压；第三晶体管T3的栅极以及第一极和第二节点PD连接，第三晶体管T3的第二极和时钟信号端CLK连接。
在图4所示的示例中，例如在输入阶段中，时钟信号端CLK输入低电平的时钟信号，第一晶体管T1关闭，第三晶体管T3由于采用二极管连接方式，所以第二节点PD可以通过第三晶体管T3以及时钟信号端CLK放电至低电平，从而降低第二节点PD对第一节点PU的影响，使得第一节点PU在输入阶段可以被拉高至较高的电平。同时由于第二节点PD不再仅通过第二晶体管T2进行放电，所以可以使得第二晶体管T2有较大的阈值电压偏移设计余量，从而可以降低工艺难度。
又例如，在复位阶段以后的后续阶段中，当时钟信号端CLK输入高电平的时钟信号时，该时钟信号可以通过第一晶体管T1对第二节点PD进行充电，从而使第二节点PD的电位变为高电平；当时钟信号端CLK输入低电平的时钟信号时，第二节点PD可以通过第三晶体管T3以及时钟信号端CLK放电至低电平。也就是说，在复位阶段以后的后续阶段中，第二节点PD的电位可以跟随时钟信号变化，使得第二节点PD的电位在一帧显示中约50％的时间内保持低电平，从而可以使和第二节点PD直接连接的晶体管(例如第八晶体管T8和第九晶体管T9)在一帧显示中的约50％的时间内不受应力(stress)，进而可以延长和第二节点PD直接连接的晶体管的使用寿命。
如图5所示，在另一个示例中，节点控制电路140可以实现为包括第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4。第一晶体管T1的栅极以及第一极和时钟信号端CLK连接以接收时钟信号并作为驱动信号，第一晶体管T1的第二极和第三节点PD_CN连接；第二晶体管T2的栅极和第一节点PU连接，第二晶体管T2的第一极和第三节点PD_CN连接，第二晶体管T2的第二极和第一电压端VGL连接以接收第一电压；第三晶体 管T3的栅极和第三节点PD_CN连接，第三晶体管T3的第一极和时钟信号端CLK连接以接收时钟信号，第三晶体管T3的第二极和第二节点PD连接；第四晶体管T4的栅极和第一节点PU连接，第四晶体管T4的第一极和第二节点PD连接，第四晶体管T4的第二极和第一电压端VGL连接以接收第一电压。
在图5所示的示例中，例如在输入阶段前的阶段中，时钟信号端CLK输入高电平的时钟信号，该时钟信号可以通过第一晶体管T1对第三节点PD_CN进行充电，使第三节点PD_CN的电位变为高电平。随后在输入阶段开始时，时钟信号端CLK输入低电平的时钟信号，又由于第三节点PD_CN可以保持上一阶段的高电平，所以第三晶体管T3开启，第二节点PD可以通过第三晶体管T3以及时钟信号端CLK放电至低电平，从而不影响输入电路110对第一节点PU的充电过程，使得第一节点PU的充电更充分。同时由于第二节点PD不再仅通过第四晶体管T4进行放电，所以可以使得第四晶体管T4有较大的阈值电压偏移设计余量，从而可以降低工艺难度。
又例如，在复位阶段以后的后续阶段中，由于第一节点PU保持低电平，所以第二晶体管T2和第四晶体管T4保持关闭。当时钟信号端CLK输入高电平的时钟信号时，该时钟信号可以通过第一晶体管T1对第三节点PD_CN进行充电，从而使第三节点PD_CN的电位变为高电平，第三晶体管T3开启，时钟信号可以通过第三晶体管T3对第二节点PD进行充电，使得第二节点PD的电位变为高电平；当时钟信号端CLK输入低电平的时钟信号时，由于第三节点PD_CN可以保持高电平，第三晶体管T3保持开启，所以第二节点PD可以通过第三晶体管T3以及时钟信号端CLK放电至低电平。也就是说，在复位阶段以后的后续阶段中，第二节点PD的电位可以跟随时钟信号变化，使得第二节点PD的电位在一帧显示中约50％的时间内保持低电平，从而可以使和第二节点PD直接连接的晶体管(例如第八晶体管T8和第九晶体管T9)在一帧显示中的约50％的时间内不受应力(stress)，进而可以延长和第二节点PD直接连接的晶体管的使用寿命。
在图4和图5所示的示例中，输入电路110可以实现为第五晶体管T5。第五晶体管T5的栅极和输入端INPUT连接以接收输入信号，第五晶体管T5的第一极和第二电压端VFD连接以接收第二电压，第五晶体管T5的第二极和第一节点PU连接。
在图4和图5所示的示例中，第一复位电路120可以实现为第六晶体管T6。第六晶体管T6的栅极和第一复位端RST1连接以接收第一复位信号，第六晶体管T6的第一极和第三电压端VBD连接以接收第三电压，第六晶体管T6的第二极和第一节点PU连接。
在上述示例中，可以认为第一复位电路120与输入电路110是对称设置的，所以该移位寄存器单元100可以用于双向扫描。当采用该移位寄存器单元100的栅极驱动电路驱动一显示面板进行正向扫描时，通过输入端INPUT提供输入信号，通过第一复位端RST1提供第一复位信号；而当采用该移位寄存器单元100的栅极驱动电路驱动一显示面板进行反向扫描时，需要通过第一复位端RST1提供输入信号，而通过输入端INPUT提供第一复位信号。
在图4和图5所示的示例中，输出电路130可以实现为包括第七晶体管T7和存储电容C1。第七晶体管T7的栅极和第一节点PU连接，第七晶体管T7的第一极和时钟信号端CLK连接以接收时钟信号并作为驱动信号，第七晶体管T7的第二极和输出端OUT连接；存储电容C1的第一极和第一节点PU连接，存储电容C1的第二极和输出端OUT连接。
在图4和图5所示的示例中，节点降噪电路150可以实现为第八晶体管T8。第八晶体管T8的栅极和第二节点PD连接，第八晶体管T8的第一极和第一节点PU连接，第八晶体管T8的第二极和第一电压端VGL连接以接收第一电压。
在图4和图5所示的示例中，第一输出降噪电路160可以实现为第九晶体管T9。第九晶体管T9的栅极和第二节点PD连接，第九晶体管T9的第一极和输出端OUT连接，第九晶体管T9的第二极和第一电压端VGL连接以接收第一电压。
需要说明的是，在本公开的实施例提供的移位寄存器单元100中，第一电压端VGL接收的信号的电平称为第一电压，例如保持输入直流低电平信号；第二电压端VFD接收的信号的电平称为第二电压，例如在该移位寄存器单元100用于正向扫描时，第二电压端VFD保持输入直流高电平信号，又例如在该移位寄存器单元100用于反向扫描时，第二电压端VFD保持输入直流低电平信号；第三电压端VBD接收的信号的电平称为第三电压，例如在该移位寄存器单元100用于正向扫描时，第三电压端VBD保持输入直流低电平信号，又例如在该移位寄存器单元100用于反向扫描时，第三电压 端VBD保持输入直流高电平信号。以下各实施例与此相同，不再赘述。
另外，需要说明的是，在本公开的实施例中，高电平和低电平是相对而言的。高电平表示一个较高的电压范围(例如，高电平可以采用5V、10V或其他合适的电压)，且多个高电平可以相同也可以不同。类似地，低电平表示一个较低的电压范围(例如，低电平可以采用0V、-5V、-10V或其他合适的电压)，且多个低电平可以相同也可以不同。例如，高电平的最小值比低电平的最大值大。
在本公开的实施例提供的移位寄存器单元100中，如图6所示，该移位寄存器单元100还包括第二复位电路170和第二输出降噪电路180。
该第二复位电路170被配置为响应于第二复位信号对第一节点PU进行复位。例如，该第二复位电路170配置为和第二复位端RST2连接，从而可以在第二复位端RST2输入的第二复位信号的控制下，使得第一节点PU和低电平信号或低电压端电连接，该低电压端例如为第一电压端VGL，从而可以对第一节点PU进行复位。例如，参考如图10所示的时序图，可以在显示帧与帧之间的间隔时间(blanking time)提供第二复位信号，以对栅极驱动电路中的所有移位寄存器单元的第一节点PU同时进行复位操作。需要说明的是，在图10所示的时序图中，是在blanking time的开始阶段提供第二复位信号，本公开的实施例对提供第二复位信号的具体时间阶段不作限制，例如还可以在blanking time的其他任意阶段提供第二复位信号。同时，第二复位端RST2提供的第二复位信号的脉冲宽度是可调的。以下各实施例与此相同，不再赘述。
该第二输出降噪电路180被配置为响应于第二复位信号对输出端OUT进行降噪。例如，该第二输出降噪电路180配置为和第二复位端RST2连接，从而可以在第二复位端RST2输入的第二复位信号的控制下，使输出端OUT和第一电压端VGL电连接，从而对输出端OUT进行降噪。例如，参考如图10所示的时序图，可以在显示帧与帧之间的间隔时间(blanking time)提供第二复位信号，以对栅极驱动电路中的所有移位寄存器单元的输出端OUT同时进行降噪。
例如，在图7和图9所示的示例中，第二复位电路170可以实现为第十四晶体管T14。第十四晶体管T14的栅极和第二复位端RST2连接以接收第二复位信号，第十四晶体管T14的第一极和第一节点PU连接，第十四晶体 管T14的第二极和第一电压端VGL连接以接收第一电压。
例如，在图7和图9所示的示例中，第二输出降噪电路180可以实现为第十五晶体管T15。第十五晶体管T15的栅极和第二复位端RST2连接以接收第二复位信号，第十五晶体管T15的第一极和输出端OUT连接，第十五晶体管T15的第二极和第一电压端VGL连接以接收第一电压。
在本公开的一个实施例提供的移位寄存器单元100中，在输入电路110对第一节点PU的电平进行控制的路径(例如充电路径)中设置有第一控制节点N1，且输入电路110还被配置为对第一控制节点N1的电平进行控制，例如对第一控制节点N1进行充电或放电。采用这种方式可以使得输入电路110中与第一控制节点N1以及第一节点PU电连接的晶体管维持零偏压状态，从而可以消除阈值电压负向偏移风险，防止切换扫描方向后第一节点PU形成漏电通路，以避免输出端OUT无正常输出，增强了电路的信赖性。
例如，在如图6所示的示例中，输入电路110被配置为在第一控制节点N1的电平的控制下使得第一控制节点N1和输入端INPUT连接(图6中未示出第一控制节点N1)，输入端INPUT被配置为接收输入信号。例如，当输入端INPUT提供的输入信号为低电平时，第一控制节点N1可以通过输入端INPUT进行放电。
例如，在一个示例中，图6中所示的移位寄存器单元100可以实现为图7所示的电路结构。该移位寄存器单元100中的输入电路110可以实现为包括第五晶体管T5、第十晶体管T10和第十一晶体管T11。第五晶体管T5的栅极和输入端INPUT连接以接收输入信号，第五晶体管T5的第一极和第二电压端VFD连接以接收第二电压，第五晶体管T5的第二极和第一控制节点N1连接；第十晶体管T10的栅极和输入端INPUT连接以接收输入信号，第十晶体管T10的第一极和第一控制节点N1连接，第十晶体管T10的第二极和第一节点PU连接；第十一晶体管T11的栅极以及第一极和第一控制节点N1连接，第十一晶体管T11的第二极和输入端INPUT连接。
在图7所示的示例中，例如在输入阶段中，输入端INPUT提供的输入信号为高电平，第五晶体管T5和第十晶体管T10均开启，以使第二电压端VFD的第二电压对第一节点PU进行充电，使得第一节点PU的电位以及第一控制节点N1的电位被拉高至高电平。在输出阶段中，输入端INPUT提供的输入信号变为低电平，第一控制节点N1可以通过第十一晶体管T11和输 入端INPUT放电至低电平，同时第一控制节点N1的电位还会因为耦合作用而降低，例如因为晶体管的寄生电容耦合作用而降低。同时，在后续的阶段中，由于第二电压端VFD保持输入高电平，第五晶体管T5存在负向偏移风险，第一控制节点N1的电位可能会被拉高至高电平，在这种情形下，第一控制节点N1也可以通过第十一晶体管T11和输入端INPUT放电至低电平。在复位阶段中，第一节点PU的电位也被拉低至低电平。采用这种方式可以使得第十晶体管T10在一帧显示的大部分时间内都保持零偏压状态，从而可以消除阈值电压负向偏移风险，防止切换扫描方向后第一节点PU形成漏电通路，以避免输出端OUT无正常输出，增强了电路的信赖性。
在图7所示的示例中，第一复位电路120与输入电路110是对称设置的，所以该移位寄存器单元100可以用于双向扫描。相应地，第一复位电路120可以实现为包括第六晶体管T6、第十二晶体管T12和第十三晶体管T13。第一复位电路120中各晶体管的连接关系如图7所示，这里不再赘述。当采用该移位寄存器单元100的栅极驱动电路驱动一显示面板进行正向扫描时(即通过输入端INPUT输入输入信号，通过第一复位端RST1输入第一复位信号)，其操作如上所述，而当采用该移位寄存器单元100的栅极驱动电路驱动一显示面板进行反向扫描时(即通过第一复位端RST1输入输入信号，通过输入端INPUT输入第一复位信号)，第二控制节点N2可以通过第十三晶体管T13和第一复位端RST1放电至低电平，这样可以使得第十二晶体管T12在一帧显示的大部分时间内都保持零偏压状态，从而可以消除阈值电压负向偏移风险，防止切换扫描方向后第一节点PU形成漏电通路，以避免输出端OUT无正常输出，增强了电路的信赖性。
需要说明的是，在图6所示的移位寄存器单元100中的节点控制电路140也可以采用图4所示的移位寄存器单元100中的节点控制电路140，本公开对此不作限定。
例如，在如图8所示的示例中，输入电路110被配置为在第二节点PD的电平的控制下使得第一控制节点N1和第一电压端VGL连接(图8中未示出第一控制节点N1)。例如，当第二节点PD为高电平时，第一控制节点N1可以通过第一电压端VGL进行放电。
例如，在一个示例中，图8中所示的移位寄存器单元100可以实现为图9所示的电路结构。该移位寄存器单元100中的输入电路110可以实现为包 括第五晶体管T5、第十晶体管T10和第十一晶体管T11。第五晶体管T5的栅极和输入端INPUT连接以接收输入信号，第五晶体管T5的第一极和第二电压端VFD连接以接收第二电压，第五晶体管T5的第二极和第一控制节点N1连接；第十晶体管T10的栅极和输入端INPUT连接以接收输入信号，第十晶体管T10的第一极和第一控制节点N1连接，第十晶体管T10的第二极和第一节点PU连接；第十一晶体管T11的栅极和第二节点PD连接，第十一晶体管T11的第一极和第一控制节点N1连接，第十一晶体管T11的第二极和第一电压端VGL连接。
在图9所示的示例中，例如在输入阶段中，输入端INPUT提供的输入信号为高电平，第五晶体管T5和第十晶体管T10均开启，以使第二电压端VFD的第二电压对第一节点PU进行充电，使得第一节点PU的电位以及第一控制节点N1的电位被拉高至高电平。在输出阶段中，输入端INPUT提供的输入信号变为低电平，第五晶体管T5和第十晶体管T10关闭，第一控制节点N1的电位因为耦合作用降为低电平，例如因为晶体管的寄生电容耦合作用降为低电平。在复位阶段中，第一节点PU的电位被拉低至低电平。在复位阶段之后的后续阶段中，当第二节点PD的电位为高电平时，第十一晶体管T11开启，从而可以对第一控制节点N1进一步放电。采用这种方式可以使得第十晶体管T10在一帧显示的大部分时间内都保持零偏压状态，从而可以消除阈值电压负向偏移风险，防止切换扫描方向后第一节点PU形成漏电通路，以避免输出端OUT无正常输出，增强了电路的信赖性。
在图9所示的示例中，第一复位电路120与输入电路110是对称设置的，所以该移位寄存器单元100可以用于双向扫描。相应地，第一复位电路120可以实现为包括第六晶体管T6、第十二晶体管T12和第十三晶体管T13。第一复位电路120中各晶体管的连接关系如图9所示，这里不再赘述。当采用该移位寄存器单元100的栅极驱动电路驱动一显示面板进行正向扫描时(即通过输入端INPUT输入输入信号，通过第一复位端RST1输入第一复位信号)，其操作如上所述，而当采用该移位寄存器单元100的栅极驱动电路驱动一显示面板进行反向扫描时(即通过第一复位端RST1输入输入信号，通过输入端INPUT输入第一复位信号)，第二控制节点N2可以通过第十三晶体管T13放电至低电平，这样可以使得第十二晶体管T12在一帧显示的大部分时间内都保持零偏压状态，从而可以消除阈值电压负向偏移风险，防止切 换扫描方向后第一节点PU形成漏电通路，以避免输出端OUT无正常输出，增强了电路的信赖性。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，在本公开的实施例中的晶体管均以N型晶体管为例进行说明，此时，第一极可以是漏极，第二极可以是源极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的移位寄存器单元中的一个或多个晶体管也可以采用P型晶体管，此时，第一极可以是源极，第二极可以是漏极，只需将选定类型的晶体管的各极的极性按照本公开的实施例中的相应晶体管的各极的极性相应连接即可。
例如，如图9所示，该移位寄存器单元100中的晶体管均采用N型晶体管，第一电压端VGL保持输入直流低电平的第一电压，第二电压端VFD保持输入直流高电平的第二电压，第三电压端VBD保持输入直流低电平的第三电压，时钟信号端CLK输入时钟信号。
下面结合图10所示的信号时序图，对图9所示的移位寄存器单元100的工作原理进行说明(以正向扫描为例进行说明)，在图10所示的输入阶段A、输出阶段B以及复位阶段C中，该移位寄存器单元100进行如下操作。
在输入阶段A中，时钟信号端CLK输入低电平的时钟信号，输入端INPUT输入高电平信号。由于输入端INTPUT输入高电平信号，第五晶体管T5和第十晶体管T10均开启，以使第二电压端VFD的第二电压对第一节点PU进行充电，使得第一节点PU的电位被拉高至第一高电平，同时第一控制节点N1的电位被拉高至高电平。
由于时钟信号端CLK输入低电平的时钟信号，第一晶体管T1关闭，第三晶体管T3由于采用二极管连接方式，所以第二节点PD可以通过第三晶体管T3以及时钟信号端CLK放电至低电平，从而降低第二节点PD对第一节点PU的影响，使得第一节点PU在输入阶段A中可以被拉高至较高的电平。
由于第一节点PU处于第一高电平，第七晶体管T7导通，此时时钟信号 端CLK输入低电平的时钟信号，所以在此阶段，输出端OUT输出低电平信号。
在输出阶段B，时钟信号端CLK输入高电平的时钟信号，输入端INPUT输入低电平信号。第五晶体管T5和第十晶体管T10关闭，第一控制节点N1的电位因为耦合作用降为低电平，例如因为晶体管的寄生电容耦合作用降为低电平。由于第一节点PU保持上一阶段的高电平，从而使得第七晶体管T7保持导通，所以在此阶段输出端OUT将时钟信号端CLK输入的高电平信号输出。
由于时钟信号端CLK以及输出端OUT为高电平，该高电平可以通过第七晶体管T7的寄生电容(包括栅极和第一极之间的寄生电容，以及栅极和第二级之间的寄生电容)和存储电容C1将第一节点PU的电位耦合升高至第二高电平，使得第七晶体管T7的导通更充分。
时钟信号端CLK输入的高电平的时钟信号可以使得第一晶体管T1导通，该时钟信号对第二节点PD进行充电，同时第一节点PU的高电平使得第二晶体管T2导通，从而可以拉低第二节点PD的电平。例如在晶体管的设计上，可以将第一晶体管T1和第二晶体管T2配置为(例如对二者的尺寸比、阈值电压等配置)在T1和T2均导通时，第二节点PD的电位被拉低至一个较低的电平，该低电平不会使第八晶体管T8和第九晶体管T9开启。
在复位阶段C，由于第一复位端RST1输入高电平的第一复位信号，第六晶体管T6和第十二晶体管T12导通，第一节点PU与第三电压端VBD电连接，第一节点PU的电位被拉低至低电平，从而第二晶体管T2和第七晶体管T7截止。
由于在此阶段时钟信号端CLK输入低电平的时钟信号，和输入阶段类似地，第二节点PD可以通过第三晶体管T3以及时钟信号端CLK放电至低电平。由于第二节点PD为低电平，所以第八晶体管T8、第九晶体管T9、第十一晶体管T11以及第十三晶体管T13截止。
在复位阶段C以后的后续阶段中，当时钟信号端CLK输入高电平的时钟信号时，该时钟信号可以通过第一晶体管T1对第二节点PD进行充电，从而使第二节点PD的电位变为高电平；当时钟信号端CLK输入低电平的时钟信号时，第二节点PD可以通过第三晶体管T3以及时钟信号端CLK放电至低电平。也就是说，在复位阶段以后的后续阶段中，第二节点PD的电位可 以跟随时钟信号变化。同时当第二节点PD的电位为高电平时，第十一晶体管T11开启，从而可以对第一控制节点N1进一步放电。
另外，在显示帧与帧之间的间隔时间(blanking time)中可以通过第二复位端RST2提供高电平的第二复位信号，第十四晶体管T14和第十五晶体管T15响应于该第二复位信号而开启，从而可以对栅极驱动电路中的所有移位寄存器单元的第一节点PU同时进行复位操作，以及对栅极驱动电路中的所有移位寄存器单元的输出端OUT同时进行降噪。
采用图9所示的移位寄存器单元100，在输入阶段可以使第二节点PD的电位保持低电平，从而降低第二节点PD对第一节点PU的影响，使得第一节点PU在输入阶段可以被拉高至较高的电平。同时可以在复位阶段以后的后续阶段中，使第二节点PD的电位可以跟随时钟信号变化，使得第二节点PD的电位在一帧显示中约50％的时间内保持低电平，从而可以使和第二节点PD直接连接的晶体管在一帧显示中的约50％的时间内不受应力(stress)，进而可以延长和第二节点PD直接连接的晶体管的使用寿命。
另外采用图9所示的移位寄存器单元100还可以使得第十晶体管T10在一帧显示的大部分时间内都保持零偏压状态，从而可以消除阈值电压负向偏移风险，防止切换扫描方向后第一节点PU形成漏电通路，以避免输出端OUT无正常输出，增强了电路的信赖性。
例如，图9所示的移位寄存器单元100在进行反向扫描时，将输入信号和第一复位信号彼此交换即可，即输入端INPUT输入第一复位信号，而第一复位端RST1输入输入信号。此时，第二电压端VFD输入直流低电平信号，而第三电压端VBD输入直流高电平信号。反向扫描时，移位寄存器单元100的工作原理与正向扫描时类似，不再赘述。
本公开的至少一实施例还提供一种栅极驱动电路10，如图11所示，该栅极驱动电路10包括多个级联的移位寄存器单元100，例如移位寄存器单元100可以采用上述实施例中提供的移位寄存器单元。该栅极驱动电路10可以采用与薄膜晶体管同样制程的工艺直接集成在显示装置的阵列基板上，实现逐行扫描驱动功能。
例如，如图11所示，除第一级移位寄存器单元外，其余各级移位寄存器单元的输入端INPUT和上一级移位寄存器单元的输出端OUT连接。除最后一级移位寄存器单元外，其余各级移位寄存器单元的第一复位端RST1和 下一级移位寄存器单元的输出端OUT连接。例如，第一级移位寄存器单元的输入端INPUT可以被配置为接收触发信号STV，最后一级移位寄存器单元的第一复位端RST1可以被配置为接收复位信号RESET。当然，上述为正向扫描的情形，当反向扫描时，将上述用于第一级的触发信号STV替换为复位信号RESET，而将上述用于最后一级的复位信号RESET替换为触发信号STV。
例如，该栅极驱动电路10还可以包括第一时钟信号线CLK1和第二时钟信号线CLK2。例如，第一时钟信号线CLK1可以配置为和奇数级移位寄存器单元100的时钟信号端CLK连接，第二时钟信号线CLK2可以配置为和偶数级移位寄存器单元100的时钟信号端CLK连接。
需要说明的是，本公开的实施例包括但不限于此，例如第一时钟信号线CLK1还可以配置为和偶数级移位寄存器单元100的时钟信号端CLK连接，同时第二时钟信号线CLK2还可以配置为和奇数级移位寄存器单元100的时钟信号端CLK连接。
例如，第一时钟信号线CLK1和第二时钟信号线CLK2上提供的时钟信号时序可以采用图12中所示的信号时序，二者彼此互补。
需要说明的是，在不同的示例中，根据不同的配置，还可以采用更多条时钟信号线以提供更多时钟信号，例如4个、6个等。
例如，该栅极驱动电路10还可以包括帧复位信号线TT_RST，该帧复位信号线TT_RST配置为和各级移位寄存器100的第二复位端RST2连接。
例如，如图11所示，栅极驱动电路10还可以包括时序控制器200。该时序控制器200例如被配置为向各级移位寄存器单元100提供时钟信号，时序控制器200还可以被配置为提供触发信号STV以及复位信号RESET。
本公开的实施例提供的栅极驱动电路10的技术效果，可以参考上述实施例中关于移位寄存器单元100的相应描述，这里不再赘述。
本公开的至少一实施例还提供一种显示装置1，如图13所示，该显示装置1包括本公开的实施例提供的任一栅极驱动电路10。该显示装置1包括由多个像素单元30构成的阵列。例如，该显示装置1还可以包括数据驱动电路20。数据驱动电路20用于提供数据信号给像素阵列；栅极驱动电路10用于提供栅极扫描信号给像素阵列。数据驱动电路20通过数据线21与像素单元30电连接，栅极驱动电路10通过栅线11与像素单元30电连接。
需要说明的是，本实施例中的显示装置1可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置1还可以包括显示面板等其他常规部件，本公开的实施例对此不作限制。
本公开的实施例提供的显示装置1的技术效果，可以参考上述实施例中关于移位寄存器单元100的相应描述，这里不再赘述。
本公开的至少一实施例还提供一种驱动方法，可以用于驱动本公开的实施例中提供的任一移位寄存器单元100，在该方法中，节点控制电路140响应于驱动信号对第二节点PD的电平进行控制。例如，使得第二节点PD交替进行放电和充电，使得第二节点PD的电位在低电平和高电平之间交替变化。。例如，可以通过时钟信号端CLK接收时钟信号并作为驱动信号。例如，在一个具体示例中，该驱动方法包括如下操作。
在第一阶段(例如输入阶段)，输入电路110响应于输入信号对第一节点PU进行充电，输出电路130将时钟信号的低电平输出至输出端OUT，节点控制电路140响应于时钟信号的低电平对第二节点PD进行放电，使得第二节点PD的电位保持低电平。
在第二阶段(例如输出阶段)，输出电路130在第一节点PU的电平的控制下，将时钟信号的高电平输出至输出端OUT；节点控制电路140响应于时钟信号的高电平对第二节点PD进行充电，但同时节点控制电路140存在第二节点PD的放电路径，使得第二节点PD的电位在本阶段保持低电平。
在第三阶段(例如复位阶段)，第一复位电路120响应于第一复位信号对第一节点PU进行复位，节点控制电路140响应于时钟信号的低电平对第二节点PD进行放电，使得第二节点PD的电位保持低电平。
在第四阶段(例如复位阶段以后的后续阶段)，节点控制电路140响应于时钟信号对第二节点PD交替进行放电和充电，使得第二节点PD的电位在低电平和高电平之间交替变化。
需要说明的是，关于该驱动方法的详细描述以及技术效果可以参考本公开的实施例中对于移位寄存器单元100的工作原理的描述，这里不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种移位寄存器单元，包括输入电路、第一复位电路、输出电路和节点控制电路；其中，
    所述输入电路被配置为响应于输入信号对第一节点的电平进行控制；
    所述第一复位电路被配置为响应于第一复位信号对所述第一节点进行复位；
    所述输出电路被配置为在所述第一节点的电平的控制下，将驱动信号输出至输出端；以及
    所述节点控制电路被配置为响应于所述驱动信号对第二节点的电平进行控制。
  2. 根据权利要求1所述的移位寄存器单元，还包括节点降噪电路、第一输出降噪电路；其中，
    所述节点降噪电路被配置为在所述第二节点的电平的控制下，对所述第一节点进行降噪；以及
    所述第一输出降噪电路被配置为在所述第二节点的电平的控制下，对所述输出端进行降噪。
  3. 根据权利要求1或2所述的移位寄存器单元，其中，所述节点控制电路包括第一晶体管、第二晶体管和第三晶体管；
    所述第一晶体管的栅极以及第一极和时钟信号端连接以接收时钟信号并作为所述驱动信号，所述第一晶体管的第二极和所述第二节点连接；
    所述第二晶体管的栅极和所述第一节点连接，所述第二晶体管的第一极和所述第二节点连接，所述第二晶体管的第二极和第一电压端连接以接收第一电压；以及
    所述第三晶体管的栅极以及第一极和所述第二节点连接，所述第三晶体管的第二极和所述时钟信号端连接。
  4. 根据权利要求1或2所述的移位寄存器单元，其中，所述节点控制电路包括第一晶体管、第二晶体管、第三晶体管和第四晶体管；
    所述第一晶体管的栅极以及第一极和时钟信号端连接以接收时钟信号并作为所述驱动信号，所述第一晶体管的第二极和第三节点连接；
    所述第二晶体管的栅极和所述第一节点连接，所述第二晶体管的第一 极和所述第三节点连接，所述第二晶体管的第二极和第一电压端连接以接收第一电压；
    所述第三晶体管的栅极和所述第三节点连接，所述第三晶体管的第一极和所述时钟信号端连接以接收所述时钟信号并作为所述驱动信号，所述第三晶体管的第二极和所述第二节点连接；以及
    所述第四晶体管的栅极和所述第一节点连接，所述第四晶体管的第一极和所述第二节点连接，所述第四晶体管的第二极和所述第一电压端连接以接收所述第一电压。
  5. 根据权利要求1-4任一所述的移位寄存器单元，其中，所述输入电路包括第五晶体管；
    所述第五晶体管的栅极和输入端连接以接收所述输入信号，所述第五晶体管的第一极和第二电压端连接以接收第二电压，所述第五晶体管的第二极和所述第一节点连接。
  6. 根据权利要求1-5任一所述的移位寄存器单元，其中，所述第一复位电路包括第六晶体管；
    所述第六晶体管的栅极和第一复位端连接以接收所述第一复位信号，所述第六晶体管的第一极和第三电压端连接以接收第三电压，所述第六晶体管的第二极和所述第一节点连接。
  7. 根据权利要求1或2所述的移位寄存器单元，其中，所述输出电路包括第七晶体管和存储电容；
    所述第七晶体管的栅极和所述第一节点连接，所述第七晶体管的第一极和时钟信号端连接以接收时钟信号并作为所述驱动信号，所述第七晶体管的第二极和所述输出端连接；以及
    所述存储电容的第一极和所述第一节点连接，所述存储电容的第二极和所述输出端连接。
  8. 根据权利要求2所述的移位寄存器单元，其中，所述节点降噪电路包括第八晶体管；
    所述第八晶体管的栅极和所述第二节点连接，所述第八晶体管的第一极和所述第一节点连接，所述第八晶体管的第二极和第一电压端连接以接收第一电压。
  9. 根据权利要求2所述的移位寄存器单元，其中，所述第一输出降 噪电路包括第九晶体管；
    所述第九晶体管的栅极和所述第二节点连接，所述第九晶体管的第一极和所述输出端连接，所述第九晶体管的第二极和第一电压端连接以接收第一电压。
  10. 根据权利要求1或2所述的移位寄存器单元，其中，
    在所述输入电路对所述第一节点的电平进行控制的路径中设置有第一控制节点，且所述输入电路还被配置为对所述第一控制节点的电平进行控制。
  11. 根据权利要求10所述的移位寄存器单元，其中，
    所述输入电路被配置为在所述第二节点的电平的控制下使得所述第一控制节点和第一电压端连接。
  12. 根据权利要求11所述的移位寄存器单元，其中，所述输入电路包括第五晶体管、第十晶体管和第十一晶体管；
    其中，所述第五晶体管的栅极和输入端连接以接收所述输入信号，所述第五晶体管的第一极和第二电压端连接以接收第二电压，所述第五晶体管的第二极和所述第一控制节点连接；所述第十晶体管的栅极和所述输入端连接以接收所述输入信号，所述第十晶体管的第一极和所述第一控制节点连接，所述第十晶体管的第二极和所述第一节点连接；所述第十一晶体管的栅极和所述第二节点连接，所述第十一晶体管的第一极和所述第一控制节点连接，所述第十一晶体管的第二极和所述第一电压端连接。
  13. 根据权利要求10所述的移位寄存器单元，其中，
    所述输入电路被配置为在所述第一控制节点的电平的控制下使得所述第一控制节点和输入端连接，所述输入端被配置为接收所述输入信号。
  14. 根据权利要求13所述的移位寄存器单元，其中，所述输入电路包括第五晶体管、第十晶体管和第十一晶体管；
    其中，所述第五晶体管的栅极和所述输入端连接以接收所述输入信号，所述第五晶体管的第一极和第二电压端连接以接收第二电压，所述第五晶体管的第二极和所述第一控制节点连接；所述第十晶体管的栅极和所述输入端连接以接收所述输入信号，所述第十晶体管的第一极和所述第一控制节点连接，所述第十晶体管的第二极和所述第一节点连接；所述第十一晶体管的栅极以及第一极和所述第一控制节点连接，所述第十一晶体管 的第二极和所述输入端连接。
  15. 根据权利要求1-14任一所述的移位寄存器单元，其中，所述第一复位电路和所述输入电路对称配置以允许实现双向扫描。
  16. 根据权利要求1或2所述的移位寄存器单元，还包括第二复位电路和第二输出降噪电路，其中，
    所述第二复位电路被配置为响应于第二复位信号对所述第一节点进行复位；
    所述第二输出降噪电路被配置为响应于所述第二复位信号对所述输出端进行降噪。
  17. 根据权利要求16所述的移位寄存器单元，其中，
    所述第二复位电路包括第十四晶体管；
    其中，所述第十四晶体管的栅极和第二复位端连接以接收所述第二复位信号，所述第十四晶体管的第一极和所述第一节点连接，所述第十四晶体管的第二极和第一电压端连接以接收第一电压；
    所述第二输出降噪电路包括第十五晶体管；
    其中，所述第十五晶体管的栅极和所述第二复位端连接以接收所述第二复位信号，所述第十五晶体管的第一极和所述输出端连接，所述第十五晶体管的第二极和所述第一电压端连接以接收所述第一电压。
  18. 一种栅极驱动电路，包括多个级联的如权利要求1-17任一所述的移位寄存器单元。
  19. 一种显示装置，包括如权利要求18所述的栅极驱动电路。
  20. 一种如权利要求1-17任一所述的移位寄存器单元的驱动方法，包括：所述节点控制电路响应于所述驱动信号对所述第二节点的电平进行控制。
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