WO2022193215A1 - 移位寄存器、栅极驱动电路及显示装置 - Google Patents

移位寄存器、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2022193215A1
WO2022193215A1 PCT/CN2021/081477 CN2021081477W WO2022193215A1 WO 2022193215 A1 WO2022193215 A1 WO 2022193215A1 CN 2021081477 W CN2021081477 W CN 2021081477W WO 2022193215 A1 WO2022193215 A1 WO 2022193215A1
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Prior art keywords
transistor
electrically connected
node
terminal
signal terminal
Prior art date
Application number
PCT/CN2021/081477
Other languages
English (en)
French (fr)
Inventor
闫岩
王旭
陈维涛
马禹
麻志强
陆顺沙
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Filing date
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/770,415 priority Critical patent/US11862060B2/en
Priority to PCT/CN2021/081477 priority patent/WO2022193215A1/zh
Priority to CN202180000532.3A priority patent/CN115668352A/zh
Publication of WO2022193215A1 publication Critical patent/WO2022193215A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a shift register, a gate driving circuit and a display device.
  • the GOA Gate Driver on Array, array substrate row drive
  • TFT Thin Film Transistor, thin film transistor
  • the gate drive circuit is usually composed of a plurality of cascaded shift registers.
  • An embodiment of the present disclosure provides a shift register, including:
  • a first input circuit configured to provide a signal at the first reference signal terminal to the first node in response to a signal at the first input signal terminal;
  • a second input circuit configured to provide a signal at the second reference signal terminal to the first node in response to a signal at the second input signal terminal;
  • control circuit configured to control the signals of the first node and the second node
  • an output circuit configured to provide a signal from a clock signal terminal to a driver output terminal in response to a signal from the first node; and to provide a signal from a third reference signal terminal to the driver output terminal in response to a signal from the second node end;
  • one of the first input signal terminal and the second input signal terminal is loaded with a valid signal in the input stage, and the other is loaded with a valid signal in the reset stage.
  • the second node includes: a first child node and a second child node;
  • the control circuit includes a first sub-control circuit and a second sub-control circuit, the first sub-control circuit is configured to control the signals of the first node and the first sub-node; the second sub-control circuit is configured to control the signals of the first node and the second child node;
  • the output circuit is configured to provide a signal from the third reference signal terminal to the drive output terminal in response to a signal from the first sub-node, and to provide the drive output terminal in response to a signal from the second sub-node
  • the signal of the third reference signal terminal is provided to the driving output terminal.
  • the first sub-control circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor;
  • the gate and the first electrode of the first transistor are both electrically connected to the first control terminal, and the second electrode of the first transistor is electrically connected to the gate of the second transistor;
  • the first pole of the second transistor is electrically connected to the first control terminal, and the second pole of the second transistor is electrically connected to the first sub-node;
  • the gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the third reference signal terminal, and the second electrode of the third transistor is electrically connected to the first node.
  • a sub-node is electrically connected;
  • the gate of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the third reference signal terminal, and the second electrode of the fourth transistor is electrically connected to the third reference signal terminal.
  • the gates of the two transistors are electrically connected;
  • the gate of the fifth transistor is electrically connected to the first sub-node, the first pole of the fifth transistor is electrically connected to the third reference signal terminal, and the second pole of the fifth transistor is electrically connected to the third reference signal terminal.
  • the first node is electrically connected.
  • the first sub-control circuit further includes: a sixth transistor and a seventh transistor;
  • the gate of the sixth transistor is electrically connected to the first input signal terminal, the first pole of the sixth transistor is electrically connected to the third reference signal terminal, and the second pole of the sixth transistor is electrically connected to the third reference signal terminal.
  • the first sub-node is electrically connected;
  • the gate of the seventh transistor is electrically connected to the second input signal terminal, the first pole of the seventh transistor is electrically connected to the third reference signal terminal, and the second pole of the seventh transistor is electrically connected to the third reference signal terminal.
  • the first sub-node is electrically connected.
  • the second sub-control circuit includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor transistor;
  • the gate electrode and the first electrode of the eighth transistor are both electrically connected to the second control terminal, and the second electrode of the eighth transistor is electrically connected to the gate electrode of the ninth transistor;
  • the first pole of the ninth transistor is electrically connected to the second control terminal, and the second pole of the ninth transistor is electrically connected to the second sub-node;
  • the gate of the tenth transistor is electrically connected to the first node, the first pole of the tenth transistor is electrically connected to the third reference signal terminal, and the second pole of the tenth transistor is electrically connected to the third reference signal terminal.
  • the two sub-nodes are electrically connected;
  • the gate of the eleventh transistor is electrically connected to the first node, the first pole of the eleventh transistor is electrically connected to the third reference signal terminal, and the second pole of the eleventh transistor is electrically connected to the third reference signal terminal.
  • the gate of the ninth transistor is electrically connected;
  • the gate of the twelfth transistor is electrically connected to the second sub-node, the first pole of the twelfth transistor is electrically connected to the third reference signal terminal, and the second pole of the twelfth transistor is electrically connected is electrically connected to the first node.
  • the second sub-control circuit further includes: a thirteenth transistor and a fourteenth transistor;
  • the gate of the thirteenth transistor is electrically connected to the first input signal terminal, the first pole of the thirteenth transistor is electrically connected to the third reference signal terminal, and the second terminal of the thirteenth transistor is electrically connected the pole is electrically connected to the second sub-node;
  • the gate of the fourteenth transistor is electrically connected to the second input signal terminal, the first pole of the fourteenth transistor is electrically connected to the third reference signal terminal, and the second terminal of the fourteenth transistor is electrically connected The pole is electrically connected to the second sub-node.
  • the output circuit includes: a storage capacitor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor;
  • the gate of the fifteenth transistor is electrically connected to the first node, the first pole of the fifteenth transistor is electrically connected to the clock signal terminal, and the second pole of the fifteenth transistor is electrically connected to the clock signal terminal.
  • the drive output terminal is electrically connected;
  • the gate of the sixteenth transistor is electrically connected to the first sub-node, the first pole of the sixteenth transistor is electrically connected to the third reference signal terminal, and the second pole of the sixteenth transistor is electrically connected electrically connected to the drive output;
  • the gate of the seventeenth transistor is electrically connected to the second sub-node, the first pole of the seventeenth transistor is electrically connected to the third reference signal terminal, and the second pole of the seventeenth transistor is electrically connected electrically connected to the drive output;
  • the first electrode plate of the storage capacitor is electrically connected to the first node, and the second electrode plate of the storage capacitor is electrically connected to the drive output end.
  • the first input circuit includes an eighteenth transistor
  • the gate of the eighteenth transistor is electrically connected to the first input signal terminal, the first pole of the eighteenth transistor is electrically connected to the first reference signal terminal, and the second pole of the eighteenth transistor is electrically connected to the first reference signal terminal.
  • the pole is electrically connected to the first node.
  • the second input circuit includes: a nineteenth transistor
  • the gate of the nineteenth transistor is electrically connected to the second input signal terminal, the first pole of the nineteenth transistor is electrically connected to the second reference signal terminal, and the second terminal of the nineteenth transistor is electrically connected.
  • the pole is electrically connected to the first node.
  • the shift register further includes: a twentieth transistor;
  • the gate of the twentieth transistor is electrically connected to the first frame reset signal terminal, the first pole of the twentieth transistor is electrically connected to the third reference signal terminal, and the second pole of the twentieth transistor is electrically connected is electrically connected to the first node.
  • the shift register further includes: a twenty-first transistor; wherein a gate of the twenty-first transistor is connected to the second The frame reset signal terminal is electrically connected, the first pole of the twenty-first transistor is electrically connected to the third reference signal terminal, and the second pole of the twenty-first transistor is electrically connected to the driving output terminal.
  • an embodiment of the present disclosure further provides a gate driving circuit, including a plurality of cascaded shift registers provided by the embodiments of the present disclosure;
  • the first input signal terminal of the first stage shift register is electrically connected with the first frame trigger signal terminal, and the second input signal terminal of the last stage shift register is electrically connected with the second frame trigger signal terminal;
  • the first input signal terminal of the next-stage shift register is electrically connected to the driving output terminal of the previous-stage shift register, and the second input signal terminal of the previous-stage shift register is electrically connected to the next-stage shift register.
  • the drive output terminals of the shift register are electrically connected.
  • an embodiment of the present disclosure further provides a display device including the gate driving circuit provided by the embodiment of the present disclosure.
  • the display device further includes: a first reference signal line, a second reference signal line, and a third reference signal line that are spaced apart from each other, and a first reference terminal electrically connected to the first reference signal line, a second reference terminal electrically connected to the second reference signal line, and a third reference terminal electrically connected to the third reference signal line;
  • the first reference signal terminal of the shift register in the gate driving circuit is electrically connected to the first reference signal line;
  • the second reference signal terminal of the shift register in the gate driving circuit is electrically connected to the second reference signal line;
  • the third reference signal terminal of the shift register in the gate driving circuit is electrically connected to the third reference signal line.
  • the display device further includes: a driver chip;
  • the driver chip is respectively bonded to the first reference terminal, the second reference terminal and the third reference terminal, and the driver chip is configured to drive the gate through the first reference terminal
  • the first reference signal terminal of the shift register in the circuit is loaded with a signal
  • the second reference signal terminal of the shift register in the gate driving circuit is loaded with a signal through the second reference terminal
  • the signal is loaded through the second reference terminal of the shift register in the gate driving circuit.
  • the third reference terminal loads a signal to the third reference signal terminal of the shift register in the gate driving circuit.
  • FIG. 1 is a schematic diagram of some structures of a shift register provided by an embodiment of the present disclosure
  • FIG. 2 is another schematic structural diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of some specific structures of a shift register provided by an embodiment of the present disclosure.
  • FIG. 4 provides some signal timing diagrams according to an embodiment of the present disclosure
  • FIG. 6 provides further signal timing diagrams according to embodiments of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present disclosure.
  • FIG. 8 is a simulation diagram of a first input signal terminal/second input signal terminal and a signal output by an eighteenth transistor/nineteenth transistor in a shift register provided by an embodiment of the present disclosure
  • FIG. 9 is a potential simulation diagram of a first node in a shift register provided by an embodiment of the present disclosure.
  • FIG. 10 is a potential simulation diagram of a drive output terminal in a shift register according to an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a shift register, as shown in FIG. 1 , which may include: a first input circuit 1 , a second input circuit 2 , a control circuit 3 , and an output circuit 4 ;
  • the first input circuit 1 is configured to provide the signal of the first reference signal terminal VREF1 to the first node N1 in response to the signal of the first input signal terminal IP1;
  • the second input circuit 2 is configured to provide the signal of the second reference signal terminal VREF2 to the first node N1 in response to the signal of the second input signal terminal IP2;
  • the control circuit 3 is configured to control the signals of the first node N1 and the second node N2;
  • the output circuit 4 is configured to provide the signal of the clock signal terminal CLK to the driving output terminal GOUT in response to the signal of the first node N1; in response to the signal of the second node N2, provide the signal of the third reference signal terminal VREF3 to Drive output terminal GOUT;
  • one of the first input signal terminal IP1 and the second input signal terminal IP2 is loaded with a valid signal in the input stage, and the other is loaded with a valid signal in the reset stage.
  • the internal structure of the above-mentioned shift register adjustment provided by the embodiment of the present disclosure, by setting the first input circuit 1 and the second input circuit 2 to a symmetrical structure design, so that the charging and discharging of the first node N1 can be performed during forward and reverse scanning. Symmetrical design is achieved, so as to realize the function of bidirectional scanning.
  • the first input circuit 1 can be used as a signal input circuit, and the corresponding first input signal terminal IP1 is loaded with a valid signal in the input stage, that is, the first input signal terminal IP1 is connected to the previous row shift.
  • the signal output by the drive output terminal GOUT of the register after the first input circuit 1 is turned on, the signal of the first reference signal terminal VREF1 is provided to the first node N1 for charging;
  • the second input circuit 2 can be used as a signal reset circuit,
  • the corresponding second input signal terminal IP2 is loaded with a valid signal in the reset phase, that is, the second input signal terminal IP2 is connected to the signal output by the drive output terminal GOUT of the shift register of the next row, and when the shift register of the next row outputs a valid signal, the second input signal terminal IP2
  • the first node N1 is discharged through the second reference signal terminal VREF2.
  • the second input circuit 2 can be used as a signal input circuit, and the corresponding second input signal terminal IP2 is loaded with a valid signal in the input stage, that is, the second input signal terminal IP2 is connected to the next row of shift registers.
  • the signal output by the drive output terminal GOUT after the second input circuit 1 is turned on, the signal of the second reference signal terminal VREF2 is supplied to the first node N1 for charging; correspondingly, the first input circuit 1 can be used as a signal reset circuit, and the corresponding The first input signal terminal IP1 is loaded with a valid signal in the reset stage, that is, the first input signal terminal IP1 is connected to the signal output by the drive output terminal GOUT of the shift register of the previous row.
  • the shift register of the previous row outputs a valid signal
  • the first input signal After the circuit 1 is turned on, the first node N1 is discharged through the first reference signal terminal VREF1.
  • a high-level signal may be loaded on the first reference signal terminal VREF1, and a low-level signal may be loaded on the second reference signal terminal VREF2; during reverse scanning, the first reference signal terminal may be loaded with a low-level signal.
  • the VREF1 is loaded with a low-level signal
  • the second reference signal terminal VREF2 is loaded with a high-level signal.
  • the structural design of the shift register ensures the symmetry of forward and reverse scanning, and, compared with the circuit structure of the traditional unidirectional scanning shift register, the transistor (TFT) inside the circuit structure There is no obvious difference in the duty cycle of the circuit and the charge and discharge of each important node, which ensures the reliability and stability of the circuit structure.
  • the second node N2 may include: a first child node N21 and a second child node N22.
  • the control circuit 3 includes a first sub-control circuit 31 and a second sub-control circuit 32; wherein, the first sub-control circuit 31 is configured to control the signals of the first node N1 and the first sub-node N21; the second sub-control circuit 32 is configured to control the signals of the first node N1 and the second child node N22.
  • the output circuit 4 is configured to provide the signal of the third reference signal terminal VREF3 to the drive output terminal GOUT in response to the signal of the first sub-node N21, and to provide the third reference signal in response to the signal of the second sub-node N22
  • the signal at the terminal VREF3 is supplied to the drive output terminal GOUT.
  • the first sub-control circuit 31 may include: a first transistor M1 , a second transistor M2 , a third transistor M3 , a fourth transistor M4 and a fifth transistor M5;
  • the gate and the first electrode of the first transistor M1 are both electrically connected to the first control terminal VN1, and the second electrode of the first transistor M1 is electrically connected to the gate of the second transistor M2;
  • the first pole of the second transistor M2 is electrically connected to the first control terminal VN1, and the second pole of the second transistor M2 is electrically connected to the first sub-node N21;
  • the gate of the third transistor M3 is electrically connected to the first node N1, the first pole of the third transistor M3 is electrically connected to the third reference signal terminal VREF3, and the second pole of the third transistor M3 is electrically connected to the first sub-node N21;
  • the gate of the fourth transistor M4 is electrically connected to the first node N1, the first pole of the fourth transistor M4 is electrically connected to the third reference signal terminal VREF3, and the second pole of the fourth transistor M4 is electrically connected to the gate of the second transistor M2. connect;
  • the gate of the fifth transistor M5 is electrically connected to the first sub-node N21, the first electrode of the fifth transistor M5 is electrically connected to the third reference signal terminal VREF3, and the second electrode of the fifth transistor M5 is electrically connected to the first node N1.
  • the second sub-control circuit 32 may include: an eighth transistor M8 , a ninth transistor M9 , a tenth transistor M10 , an eleventh transistor M11 , and a tenth transistor M11 .
  • the gate and the first electrode of the eighth transistor M8 are both electrically connected to the second control terminal VN2, and the second electrode of the eighth transistor M8 is electrically connected to the gate of the ninth transistor M9;
  • the first pole of the ninth transistor M9 is electrically connected to the second control terminal VN2, and the second pole of the ninth transistor M9 is electrically connected to the second sub-node N22;
  • the gate of the tenth transistor M10 is electrically connected to the first node N1, the first pole of the tenth transistor M10 is electrically connected to the third reference signal terminal VREF3, and the second pole of the tenth transistor M10 is electrically connected to the second sub-node N22;
  • the gate of the eleventh transistor M11 is electrically connected to the first node N1, the first pole of the eleventh transistor M11 is electrically connected to the third reference signal terminal VREF3, and the second pole of the eleventh transistor M11 is electrically connected to the ninth transistor M9 grid electrical connection;
  • the gate of the twelfth transistor M12 is electrically connected to the second sub-node N22, the first pole of the twelfth transistor M12 is electrically connected to the third reference signal terminal VREF3, and the second pole of the twelfth transistor M12 is electrically connected to the first node N1 electrical connection.
  • the output circuit 4 may include: a storage capacitor CST, a fifteenth transistor M15 , a sixteenth transistor M16 and a seventeenth transistor M17 ;
  • the gate of the fifteenth transistor M15 is electrically connected to the first node N1, the first pole of the fifteenth transistor M15 is electrically connected to the clock signal terminal CLK, and the second pole of the fifteenth transistor M15 is electrically connected to the driving output terminal GOUT;
  • the gate of the sixteenth transistor M16 is electrically connected to the first sub-node N21, the first pole of the sixteenth transistor M16 is electrically connected to the third reference signal terminal VREF3, and the second pole of the sixteenth transistor M16 is electrically connected to the driving output terminal GOUT electrical connection;
  • the gate of the seventeenth transistor M17 is electrically connected to the second sub-node N22, the first pole of the seventeenth transistor M17 is electrically connected to the third reference signal terminal VREF3, and the second pole of the seventeenth transistor M17 is electrically connected to the driving output terminal GOUT electrical connection;
  • the first electrode plate of the storage capacitor CST is electrically connected to the first node N1, and the second electrode plate of the storage capacitor CST is electrically connected to the driving output terminal GOUT.
  • the first input circuit 1 may include an eighteenth transistor M18;
  • the gate of the eighteenth transistor M18 is electrically connected to the first input signal terminal IP1, the first pole of the eighteenth transistor M18 is electrically connected to the first reference signal terminal VREF1, and the second pole of the eighteenth transistor M18 is electrically connected to the first node N1 is electrically connected.
  • the second input circuit 2 may include: a nineteenth transistor M19;
  • the gate of the nineteenth transistor M19 is electrically connected to the second input signal terminal IP2, the first pole of the nineteenth transistor M19 is electrically connected to the second reference signal terminal VREF2, and the second pole of the nineteenth transistor M19 is electrically connected to the first node N1 is electrically connected.
  • the above is only an example to illustrate the specific structure of the shift register provided by the embodiment of the present disclosure.
  • the specific structure of the above-mentioned circuits is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be other structures known to those skilled in the art. The structure is not limited here.
  • all transistors may be N-type transistors.
  • the signal of the first reference signal terminal VREF1 may be a high-level signal
  • the signal of the second reference signal terminal VREF2 may be a low-level signal
  • the first reference signal terminal VREF1 The signal of VREF2 may be a low-level signal
  • the signal of the second reference signal terminal VREF2 may be a high-level signal
  • the signal of the third reference signal terminal VREF3 is always a low-level signal.
  • all transistors may also be P-type transistors, which are not limited herein.
  • the signal of the first control terminal VN1 and the signal of the second control terminal VN2 may be pulse signals switched between high level and low level respectively, and the level of the first control terminal VN1 and the signal of the second control terminal VN2 The level is opposite.
  • the first control terminal VN1 is a high-level signal
  • the second control terminal VN2 is a low-level signal
  • the first control terminal VN1 is a low-level signal
  • the second control terminal VN2 is a high-level signal.
  • the maintenance duration of the T10 phase can be made the same as the maintenance duration of the T20 phase.
  • the maintenance duration of the T10 stage and the maintenance duration of the T20 stage are respectively set to the duration of one display frame, the duration of multiple display frames, 2s, 1h, or 24h, etc., which are not limited here.
  • the signal of the first control terminal VN1 and the signal of the second control terminal VN2 may also be DC signals, respectively.
  • the first control terminal VN1 is loaded with a high-level DC signal
  • the second control terminal VN2 is not loaded with a signal or is loaded with a low-level DC signal.
  • the first control terminal VN1 is not loaded with a signal or is loaded with a low-level DC signal.
  • the first control terminal VN1 is a high-level DC signal
  • the second control terminal VN2 is a low-level DC signal.
  • the first control terminal VN1 is a low-level DC signal
  • the second control terminal VN2 is a high-level DC signal.
  • the maintenance duration of the T10 phase can be made the same as the maintenance duration of the T20 phase.
  • the maintenance duration of the T10 stage and the maintenance duration of the T20 stage are respectively set to the duration of one display frame, the duration of multiple display frames, 2s, 1h, or 24h, etc., which are not limited here.
  • the sequence of the T10 stage and the T20 stage can be determined according to the actual application. For example, the work process in the T10 stage may be executed first, and then the work process in the T20 stage may be executed. Alternatively, the work process in the T20 stage can also be executed first, and then the work process in the T10 stage is executed.
  • 1 represents a high-level signal
  • 0 represents a low-level signal
  • 1 and 0 represent its logic levels, which are only for better explanation of the working process of the above-mentioned shift register provided by the embodiments of the present disclosure. , rather than the potential applied to the gate of each transistor during implementation.
  • the T10 stage and the T20 stage in the signal timing diagram shown in FIG. 4 are selected.
  • the input stage T11, the reset stage T12, and the output stage T13 are selected.
  • the eighth transistor M8 is turned off.
  • the turned-on fourth transistor M4 may provide a low level signal of the third reference signal terminal VREF3 to the gate of the second transistor M2 to control the second transistor M2 to be turned off.
  • the turned-on third transistor M3 can provide a low-level signal of the third reference signal terminal VREF3 to the first sub-node N21, so that the first sub-node N21 is a low-level signal, thereby controlling the fifth transistor M5 and the tenth
  • the six transistors M16 are all turned off.
  • the turned-on eleventh transistor M11 may provide a low level signal of the third reference signal terminal VREF3 to the gate of the ninth transistor M9 to control the ninth transistor M9 to be turned off.
  • the turned-on tenth transistor M10 can provide the low-level signal of the third reference signal terminal VREF3 to the second sub-node N22, so that the second sub-node N22 is a low-level signal, thereby controlling the twelfth transistor M12 and the second sub-node N22.
  • the seventeen transistors M17 are all turned off.
  • the turned-on fifteenth transistor M15 may provide the low-level signal of the clock signal terminal CLK to the driving signal output terminal GOUT, so that the driving signal output terminal GOUT outputs a low-level signal.
  • the turned-on third transistor M3 can provide a low-level signal of the third reference signal terminal VREF3 to the first sub-node N21, so that the first sub-node N21 is a low-level signal, thereby controlling the fifth transistor M5 and the tenth
  • the six transistors M16 are all turned off.
  • the turned-on eleventh transistor M11 may provide a low level signal of the third reference signal terminal VREF3 to the gate of the ninth transistor M9 to control the ninth transistor M9 to be turned off.
  • the turned-on tenth transistor M10 can provide the low-level signal of the third reference signal terminal VREF3 to the second sub-node N22, so that the second sub-node N22 is a low-level signal, thereby controlling the twelfth transistor M12 and the second sub-node N22.
  • the seventeen transistors M17 are all turned off.
  • the turned-on fifteenth transistor M15 may provide the high-level signal of the clock signal terminal CLK to the driving signal output terminal GOUT. Because the first node N1 is floating, the first node N1 is further pulled up by the action of the storage capacitor, so that the fifteenth transistor M15 can be turned on as completely as possible, so that the high-level signal of the clock signal terminal CLK can be fully turned on. It is possible to provide the driving signal output terminal GOUT without voltage loss, so that the driving signal output terminal GOUT outputs a high-level signal.
  • the first transistor M1 is turned on under the control of the high-level signal of the first control terminal VN1 to provide the high-level signal of the first control terminal VN1 to the gate of the second transistor M2, thereby controlling the conduction of the second transistor M2. Pass.
  • the turned-on second transistor M2 can provide the high-level signal of the first control terminal VN1 to the first sub-node N21, so that the first sub-node N21 is a high-level signal, thereby controlling the fifth transistor M5 and the sixteenth
  • the transistors M16 are all turned on.
  • the turned-on fifth transistor M5 may provide a low-level signal of the third reference signal terminal VREF3 to the first node N1, so that the first node N1 is further a low-level signal.
  • the turned-on sixteenth transistor M16 may provide the low-level signal of the third reference signal terminal VREF3 to the driving signal output terminal GOUT, so that the driving signal output terminal GOUT outputs a low-level signal.
  • the first transistor M1 is turned off.
  • the turned-on fourth transistor M4 may provide a low level signal of the third reference signal terminal VREF3 to the gate of the second transistor M2 to control the second transistor M2 to be turned off.
  • the turned-on third transistor M3 can provide a low-level signal of the third reference signal terminal VREF3 to the first sub-node N21, so that the first sub-node N21 is a low-level signal, thereby controlling the fifth transistor M5 and the tenth
  • the six transistors M16 are all turned off.
  • the turned-on eleventh transistor M11 may provide a low level signal of the third reference signal terminal VREF3 to the gate of the ninth transistor M9 to control the ninth transistor M9 to be turned off.
  • the turned-on tenth transistor M10 can provide the low-level signal of the third reference signal terminal VREF3 to the second sub-node N22, so that the second sub-node N22 is a low-level signal, thereby controlling the twelfth transistor M12 and the second sub-node N22.
  • the seventeen transistors M17 are all turned off.
  • the turned-on fifteenth transistor M15 may provide the low-level signal of the clock signal terminal CLK to the driving signal output terminal GOUT, so that the driving signal output terminal GOUT outputs a low-level signal.
  • the turned-on fourth transistor M4 may provide a low level signal of the third reference signal terminal VREF3 to the gate of the second transistor M2 to control the second transistor M2 to be turned off.
  • the turned-on third transistor M3 can provide a low-level signal of the third reference signal terminal VREF3 to the first sub-node N21, so that the first sub-node N21 is a low-level signal, thereby controlling the fifth transistor M5 and the tenth
  • the six transistors M16 are all turned off.
  • the turned-on eleventh transistor M10 may provide a low level signal of the third reference signal terminal VREF3 to the gate of the ninth transistor M9 to control the ninth transistor M9 to be turned off.
  • the turned-on tenth transistor M10 can provide the low-level signal of the third reference signal terminal VREF3 to the second sub-node N22, so that the second sub-node N22 is a low-level signal, thereby controlling the twelfth transistor M12 and the second sub-node N22.
  • the seventeen transistors M17 are all turned off.
  • the turned-on fifteenth transistor M15 may provide the high-level signal of the clock signal terminal CLK to the driving signal output terminal GOUT. Because the first node N1 is floating, the first node N1 is further pulled up by the action of the storage capacitor, so that the fifteenth transistor M15 can be turned on as completely as possible, so that the high-level signal of the clock signal terminal CLK can be fully turned on. It is possible to provide the driving signal output terminal GOUT without voltage loss, so that the driving signal output terminal GOUT outputs a high-level signal.
  • the eighth transistor M8 is turned on under the control of the high-level signal of the second control terminal VN2, so as to provide the high-level signal of the second control terminal VN2 to the gate of the ninth transistor M9, thereby controlling the ninth transistor M9 to conduct. Pass.
  • the turned-on ninth transistor M9 can provide the high-level signal of the second control terminal VN2 to the second sub-node N22, so that the second sub-node N22 is a high-level signal, thereby controlling the twelfth transistor M12 and the tenth transistor M12.
  • the seven transistors M17 are all turned on.
  • the turned-on twelfth transistor M12 may provide a low-level signal of the third reference signal terminal VREF3 to the first node N1, so that the first node N1 is further a low-level signal.
  • the turned-on seventeenth transistor M17 may provide the low-level signal of the third reference signal terminal VREF3 to the driving signal output terminal GOUT, so that the driving signal output terminal GOUT outputs a low-level signal.
  • Embodiments of the present disclosure further provide schematic structural diagrams of some shift registers, as shown in FIG. 5 , which are modified from the implementation of the foregoing embodiments. Only the differences between this embodiment and the above-mentioned embodiments will be described below, and the similarities will not be repeated here.
  • the first sub-control circuit 31 may further include: a sixth transistor M6 and a seventh transistor M7; wherein the gate of the sixth transistor M6 is connected to the first transistor M6
  • the input signal terminal IP1 is electrically connected, the first pole of the sixth transistor M6 is electrically connected to the third reference signal terminal VREF3, the second pole of the sixth transistor M6 is electrically connected to the first sub-node N21; the gate of the seventh transistor M7 is electrically connected to The second input signal terminal IP2 is electrically connected, the first pole of the seventh transistor M7 is electrically connected to the third reference signal terminal VREF3, and the second pole of the seventh transistor M7 is electrically connected to the first sub-node N21.
  • the second sub-control circuit 32 may further include: a thirteenth transistor M13 and a fourteenth transistor M14; wherein, the gate of the thirteenth transistor M13 is electrically connected to the first input signal terminal IP1, the first pole of the thirteenth transistor M13 is electrically connected to the third reference signal terminal VREF3, and the second pole of the thirteenth transistor M13 is electrically connected to the second sub-node N22; the fourteenth transistor M13 is electrically connected to the second sub-node N22; The gate of the transistor M14 is electrically connected to the second input signal terminal IP2, the first pole of the fourteenth transistor M14 is electrically connected to the third reference signal terminal VREF3, and the second pole of the fourteenth transistor M14 is electrically connected to the second sub-node N22. connect.
  • the sixth transistor M6 added in the first sub-control circuit 31 and the thirteenth transistor M13 added in the second sub-control circuit 32 can quickly pull down the second node N2 during forward scanning (ie, the potentials of the first sub-node N21 and the second sub-node N22 ), control the leakage problem of the fifth transistor M5 and the twelfth transistor M12 , and improve the signal quality of the first node N1 .
  • the seventh transistor M7 added in the first sub-control circuit 31 and the fourteenth transistor M14 added in the second sub-control circuit 32 can quickly pull down the second node N2 (that is, the first sub-controller) during reverse scanning.
  • the potential of the node N21 and the second sub-node N22) controls the leakage problem of the fifth transistor M5 and the twelfth transistor M12, and improves the signal quality of the first node N1.
  • FIG. 8 shows the signals input by the first input signal terminal IP1 during forward scanning and the second input signal terminal IP2 during reverse scanning in the shift register provided by the embodiment of the present disclosure, and the signals are the previous stage shift From the signal 1 output by the drive signal output terminal GOUT of the register, it can be seen that the signal rises faster and the Vmax value is higher.
  • FIG. 8 also shows the signal output by the eighteenth transistor M18 to the first node N1 during forward scanning and the signal output by the nineteenth transistor M19 to the first node during reverse scanning in the shift register provided by the embodiment of the present disclosure Signal 2 of N1.
  • FIG. 9 shows a schematic diagram of the potential of the first node N1 in the input stage 3, the output stage 4 and the reset stage 5.
  • FIG. 10 shows a schematic diagram of the potential of the driving signal output terminal GOUT. It can be seen that when the shift register structure provided by the embodiment of the present disclosure (ie, after optimization) is adopted, compared with the traditional shift register structure (ie, before optimization), it can be Reduce the tailing problem of the drive signal output terminal GOUT in the reset stage 6, prevent the occurrence of defects (horizontal black lines), ensure the signal quality of the drive signal output terminal GOUT, and improve the life of the shift register to a certain extent. In addition, it can be seen from the simulation test that the shift register provided by the embodiments of the present disclosure can support higher temperature reliability operating conditions (-20-70° C.), so as to solve the problem of high temperature life.
  • the shift register may further include: a twentieth transistor M20; wherein the gate of the twentieth transistor M20 is electrically connected to the first frame reset signal terminal SRE1 connected, the first pole of the twentieth transistor M20 is electrically connected to the third reference signal terminal VREF3, and the second pole of the twentieth transistor M20 is electrically connected to the first node N1.
  • the shift register may further include: a twenty-first transistor M21; wherein the gate of the twenty-first transistor M21 and the second frame reset signal terminal SRE2 is electrically connected, the first pole of the twenty-first transistor M21 is electrically connected to the third reference signal terminal VREF3, and the second pole of the twenty-first transistor M21 is electrically connected to the driving output terminal GOUT.
  • a frame reset stage T01 may also be included.
  • the first frame reset signal terminal SRE1 is a high-level signal
  • the twentieth transistor M20 can be controlled to be turned on, so as to provide the low-level signal of the third reference signal terminal VREF3 to the first node N1, As a result, the first node N1 is pre-reset, thereby further reducing the noise of the driving output terminal GOUT.
  • the second frame reset signal terminal SRE2 is a high-level signal
  • the twenty-first transistor M21 can be controlled to be turned on, so as to provide the low-level signal of the third reference signal terminal VREF3 to the driving output terminal GOUT, thereby driving the output
  • the terminal GOUT is pre-reset, so that the noise of the driving output terminal GOUT can be further reduced.
  • the sixth transistor M6 is turned on under the control of the high-level signal of the first input signal terminal IP1 to provide the low-level signal of the third reference signal terminal VREF3 to the first sub-node N21 , so that the first sub-node N21 can be further made to be a level signal, thereby further reducing the noise of the driving output terminal GOUT.
  • the thirteenth transistor M13 is turned on under the control of the high-level signal of the first input signal terminal IP1 to provide the low-level signal of the third reference signal terminal VREF3 to the second sub-node N22, so that the second sub-node N22 can be further enabled
  • the sub-node N22 is a low-level signal, which can further reduce the noise of the driving output terminal GOUT.
  • the seventh transistor M7 is turned on under the control of the high-level signal of the second input signal terminal IP2 to provide the low-level signal of the third reference signal terminal VREF3 to the
  • the first sub-node N21 can further make the first sub-node N21 a level signal, thereby further reducing the noise of the drive output terminal GOUT.
  • the fourteenth transistor M14 is controlled by the high-level signal of the second input signal terminal IP2 turn on down to provide the low-level signal of the third reference signal terminal VREF3 to the second sub-node N22, so that the second sub-node N22 can be further made to be a low-level signal, which can further reduce the noise of the driving output terminal GOUT .
  • a frame reset stage T02 may also be included.
  • the first frame reset signal terminal SRE1 is a high-level signal
  • the twentieth transistor M20 can be controlled to be turned on, so as to provide the low-level signal of the third reference signal terminal VREF3 to the first node N1, As a result, the first node N1 is pre-reset, thereby further reducing the noise of the driving output terminal GOUT.
  • the second frame reset signal terminal SRE2 is a high-level signal
  • the twenty-first transistor M21 can be controlled to be turned on, so as to provide the low-level signal of the third reference signal terminal VREF3 to the driving output terminal GOUT, thereby driving the output
  • the terminal GOUT is pre-reset, so that the noise of the driving output terminal GOUT can be further reduced.
  • the sixth transistor M6 is turned on under the control of the high-level signal of the first input signal terminal IP1 to provide the low-level signal of the third reference signal terminal VREF3 to the first sub-node N21 , so that the first sub-node N21 can be further made to be a level signal, thereby further reducing the noise of the driving output terminal GOUT.
  • the thirteenth transistor M13 is turned on under the control of the high-level signal of the first input signal terminal IP1 to provide the low-level signal of the third reference signal terminal VREF3 to the second sub-node N22, so that the second sub-node N22 can be further enabled
  • the sub-node N22 is a low-level signal, which can further reduce the noise of the driving output terminal GOUT.
  • the seventh transistor M7 is turned on under the control of the high-level signal of the second input signal terminal IP2 to provide the low-level signal of the third reference signal terminal VREF3 to the
  • the first sub-node N21 can further make the first sub-node N21 a level signal, thereby further reducing the noise of the drive output terminal GOUT.
  • the fourteenth transistor M14 is controlled by the high-level signal of the second input signal terminal IP2 turn on down to provide the low-level signal of the third reference signal terminal VREF3 to the second sub-node N22, so that the second sub-node N22 can be further made to be a low-level signal, which can further reduce the noise of the driving output terminal GOUT .
  • An embodiment of the present disclosure further provides a gate driving circuit, as shown in FIG. 7 , which includes a plurality of cascaded shift registers provided by the embodiment of the present disclosure: SR(1), SR(2), . . . SR(n -1), SR(n)...SR(N-1), SR(N) (N shift registers in total, 1 ⁇ n ⁇ N, n and N are positive integers), where:
  • the first input signal terminal IP1 of the first stage shift register SR(1) is electrically connected to the first frame trigger signal terminal STV1
  • the second input signal terminal IP2 of the last stage shift register SR(N) is electrically connected to the second frame trigger signal terminal STV1.
  • the signal terminal STV2 is electrically connected;
  • the first input signal terminal IP1 of the next-stage shift register SR(n) is electrically connected to the driving output terminal GOUT of the previous-stage shift register SR(n-1), and the previous-stage shift register SR(n-1)
  • the second input signal terminal IP2 of the bit register SR(n-1) is electrically connected to the driving output terminal GOUT of the shift register SR(n) of the next stage.
  • every two stages of shift registers may refer to one or more shift registers at intervals, which is not limited here.
  • each shift register in the gate driving circuit described above is the same in function and structure as the shift register provided by the embodiment of the present disclosure, and repeated details are not repeated here. It is worth noting that during forward scanning, the frame start signal is loaded from the first frame trigger signal terminal STV1, and the gate drive circuit starts from the drive output terminal GOUT of the first stage shift register SR(1) as the starting sequence. Output a valid signal; during reverse scanning, the frame start signal is loaded from the second frame trigger signal terminal STV2, and the gate drive circuit is sequentially output from the drive output terminal GOUT of the last stage shift register SR(n) as the start valid signal.
  • the clock signal terminals CLK of the odd-numbered stage shift registers are all electrically connected to the same clock line clk1, and the even-numbered stage shift registers are electrically connected to the same clock line clk1.
  • the clock signal terminals CLK are all electrically connected to the same clock line clk2.
  • the first reference signal terminal VREF1 of each stage of the shift register is electrically connected to the same first reference signal line ref1 .
  • the second reference signal terminal VREF2 of each stage of the shift register is electrically connected to the same second reference signal line ref2.
  • the third reference signal terminal VREF3 of each stage of the shift register is electrically connected to the same third reference signal line ref3.
  • the first reference signal line ref1 loads a high-level signal to the first reference signal terminal VREF1 of the shift registers of each stage
  • the second reference signal line ref2 loads the second reference signal terminal VREF2 of the shift registers of each stage Load low level signal.
  • the first reference signal line ref1 loads a low-level signal to the first reference signal terminal VREF1 of the shift registers of each stage
  • the second reference signal line ref2 loads the second reference signal terminal VREF2 of the shift registers of each stage Load a high level signal
  • the third reference signal line ref3 loads a low-level signal to the third reference signal terminal VREF3 of the shift registers of each stage.
  • the first frame reset signal terminal SRE1 of each stage of the shift register can be made to be the same as the same first frame reset signal terminal SRE1.
  • a frame reset terminal is electrically connected. In this way, the first node N1 of each stage of the shift register can be pre-reset at the same time.
  • the second input signal end SRE2 of the second frame of each stage of the shift register can be It is electrically connected to the same second frame reset terminal. In this way, the drive output terminal GOUT of each stage of shift registers can be pre-reset at the same time.
  • an embodiment of the present disclosure further provides a display device including the above gate driving circuit provided by the embodiment of the present disclosure.
  • the principle of solving the problem of the display device is similar to that of the aforementioned gate driving circuit. Therefore, the implementation of the display device can refer to the implementation of the aforementioned gate driving circuit, and the repetition will not be repeated here.
  • the display device may further include: a first reference signal line, a second reference signal line and a third reference signal line that are spaced apart from each other, a third reference signal line electrically connected to the first reference signal line a reference terminal, a second reference terminal electrically connected to the second reference signal line, and a third reference terminal electrically connected to the third reference signal line; wherein, the first reference signal terminal of the shift register in the gate driving circuit VREF1 is electrically connected to the first reference signal line, the second reference signal terminal VREF2 of the shift register in the gate driving circuit is electrically connected to the second reference signal line, and the third reference signal terminal of the shift register in the gate driving circuit VREF3 is electrically connected to the third reference signal line.
  • the display device may further include: a driver chip; wherein the driver chip is bonded to the first reference terminal, the second reference terminal and the third reference terminal, respectively, and the driver chip is configured to pass
  • the first reference terminal loads a signal to the first reference signal terminal VREF1 of the shift register in the gate driving circuit
  • the second reference terminal loads a signal to the second reference signal terminal VREF2 of the shift register in the gate driving circuit through the second reference terminal.
  • the third reference terminal loads a signal to the third reference signal terminal VREF3 of the shift register in the gate driving circuit.
  • the display device may be any product or component with display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a mobile phone such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present disclosure.
  • the first input circuit can provide the signal of the first reference signal terminal to the input stage through the first input circuit in response to the signal of the first input signal terminal.
  • the first node in the reset phase, can provide the signal of the second reference signal terminal to the first node through the second input circuit in response to the signal of the second input signal terminal.
  • the second reference signal terminal can be supplied to the first node through the second input circuit in response to the signal at the second input signal terminal in the input phase, and the first input circuit can be used in the reset phase in response to the first input.
  • the signal at the signal terminal may provide the signal at the first reference signal terminal to the first node.
  • the signals of the first node and the second node can be controlled by the control circuit.
  • the signal at the clock signal terminal may be provided to the driver output terminal by the output circuit in response to the signal at the first node, and the signal at the third reference signal terminal may be supplied to the driver output terminal in response to the signal at the second node.

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Abstract

本公开实施例提供了一种移位寄存器、栅极驱动电路及显示装置，将第一输入电路和第二输入电路设置为对称结构设计，在正向扫描时，在输入阶段通过第一输入电路响应于第一输入信号端的信号可以将第一参考信号端的信号提供给第一节点，在复位阶段，通过第二输入电路响应于第二输入信号端的信号可以将第二参考信号端的信号提供给第一节点。在反向扫描时，在输入阶段通过第而输入电路响应于第二输入信号端的信号可以将第二参考信号端的信号提供给第一节点，在复位阶段，通过第一输入电路响应于第一输入信号端的信号可以将第一参考信号端的信号提供给第一节点。使第一节点的充电和放电在正反向扫描时都可以做到对称性设计，从而实现双向扫描的功能。

Description

移位寄存器、栅极驱动电路及显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种移位寄存器、栅极驱动电路及显示装置。
背景技术
随着显示技术的飞速发展，显示装置越来越向着高集成度和低成本的方向发展。其中，GOA(Gate Driver on Array，阵列基板行驱动)技术将TFT(Thin Film Transistor，薄膜晶体管)栅极驱动电路集成在显示装置的阵列基板上以形成对显示装置的扫描驱动。其中，栅极驱动电路通常由多个级联的移位寄存器构成。
发明内容
本公开实施例提供了一种移位寄存器，包括：
第一输入电路，被配置为响应于第一输入信号端的信号，将第一参考信号端的信号提供给第一节点；
第二输入电路，被配置为响应于第二输入信号端的信号，将第二参考信号端的信号提供给所述第一节点；
控制电路，被配置为控制所述第一节点与第二节点的信号；
输出电路，被配置为响应于所述第一节点的信号，将时钟信号端的信号提供给驱动输出端；响应于所述第二节点的信号，将第三参考信号端的信号提供给所述驱动输出端；
其中，所述第一输入信号端和所述第二输入信号端中的一个在输入阶段加载有效信号，另一个在复位阶段加载有效信号。
在一种可能的实现方式中，在本公开实施例提供的移位寄存器中，所述第二节点包括：第一子节点和第二子节点；
所述控制电路包括第一子控制电路和第二子控制电路，所述第一子控制电路被配置为控制所述第一节点与所述第一子节点的信号；所述第二子控制电路被配置为控制所述第一节点与所述第二子节点的信号；
所述输出电路被配置为响应于所述第一子节点的信号，将所述第三参考信号端的信号提供给所述驱动输出端，以及响应于所述第二子节点的信号，将所述第三参考信号端的信号提供给所述驱动输出端。
在一种可能的实现方式中，在本公开实施例提供的移位寄存器中，所述第一子控制电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管以及第五晶体管；
所述第一晶体管的栅极与第一极均与第一控制端电连接，所述第一晶体管的第二极与所述第二晶体管的栅极电连接；
所述第二晶体管的第一极与所述第一控制端电连接，所述第二晶体管的第二极与所述第一子节点电连接；
所述第三晶体管的栅极与所述第一节点电连接，所述第三晶体管的第一极与所述第三参考信号端电连接，所述第三晶体管的第二极与所述第一子节点电连接；
所述第四晶体管的栅极与所述第一节点电连接，所述第四晶体管的第一极与所述第三参考信号端电连接，所述第四晶体管的第二极与所述第二晶体管的栅极电连接；
所述第五晶体管的栅极与所述第一子节点电连接，所述第五晶体管的第一极与所述第三参考信号端电连接，所述第五晶体管的第二极与所述第一节点电连接。
在一种可能的实现方式中，在本公开实施例提供的移位寄存器中，所述第一子控制电路还包括：第六晶体管和第七晶体管；
所述第六晶体管的栅极与所述第一输入信号端电连接，所述第六晶体管的第一极与所述第三参考信号端电连接，所述第六晶体管的第二极与所述第一子节点电连接；
所述第七晶体管的栅极与所述第二输入信号端电连接，所述第七晶体管的第一极与所述第三参考信号端电连接，所述第七晶体管的第二极与所述第一子节点电连接。
在一种可能的实现方式中，在本公开实施例提供的移位寄存器中，所述第二子控制电路包括：第八晶体管、第九晶体管、第十晶体管、第十一晶体管以及第十二晶体管；
所述第八晶体管的栅极与第一极均与第二控制端电连接，所述第八晶体管的第二极与所述第九晶体管的栅极电连接；
所述第九晶体管的第一极与所述第二控制端电连接，所述第九晶体管的第二极与所述第二子节点电连接；
所述第十晶体管的栅极与所述第一节点电连接，所述第十晶体管的第一极与所述第三参考信号端电连接，所述第十晶体管的第二极与所述第二子节点电连接；
所述第十一晶体管的栅极与所述第一节点电连接，所述第十一晶体管的第一极与所述第三参考信号端电连接，所述第十一晶体管的第二极与所述第九晶体管的栅极电连接；
所述第十二晶体管的栅极与所述第二子节点电连接，所述第十二晶体管的第一极与所述第三参考信号端电连接，所述第十二晶体管的第二极与所述第一节点电连接。
在一种可能的实现方式中，在本公开实施例提供的移位寄存器中，所述第二子控制电路还包括：第十三晶体管和第十四晶体管；
所述第十三晶体管的栅极与所述第一输入信号端电连接，所述第十三晶体管的第一极与所述第三参考信号端电连接，所述第十三晶体管的第二极与所述第二子节点电连接；
所述第十四晶体管的栅极与所述第二输入信号端电连接，所述第十四晶体管的第一极与所述第三参考信号端电连接，所述第十四晶体管的第二极与所述第二子节点电连接。
在一种可能的实现方式中，在本公开实施例提供的移位寄存器中，所述输出电路包括：存储电容、第十五晶体管、第十六晶体管以及第十七晶体管；
所述第十五晶体管的栅极与所述第一节点电连接，所述第十五晶体管的第一极与所述时钟信号端电连接，所述第十五晶体管的第二极与所述驱动输出端电连接；
所述第十六晶体管的栅极与所述第一子节点电连接，所述第十六晶体管的第一极与所述第三参考信号端电连接，所述第十六晶体管的第二极与所述驱动输出端电连接；
所述第十七晶体管的栅极与所述第二子节点电连接，所述第十七晶体管的第一极与所述第三参考信号端电连接，所述第十七晶体管的第二极与所述驱动输出端电连接；
所述存储电容的第一电极板与所述第一节点电连接，所述存储电容的第二电极板与所述驱动输出端电连接。
在一种可能的实现方式中，在本公开实施例提供的移位寄存器中，所述第一输入电路包括第十八晶体管；
所述第十八晶体管的栅极与所述第一输入信号端电连接，所述第十八晶体管的第一极与所述第一参考信号端电连接，所述第十八晶体管的第二极与所述第一节点电连接。
在一种可能的实现方式中，在本公开实施例提供的移位寄存器中，所述第二输入电路包括：第十九晶体管；
所述第十九晶体管的栅极与所述第二输入信号端电连接，所述第十九晶体管的第一极与所述第二参考信号端电连接，所述第十九晶体管的第二极与所述第一节点电连接。
在一种可能的实现方式中，在本公开实施例提供的移位寄存器中，所述移位寄存器还包括：第二十晶体管；
所述第二十晶体管的栅极与第一帧复位信号端电连接，所述第二十晶体管的第一极与所述第三参考信号端电连接，所述第二十晶体管的第二极与所 述第一节点电连接。
在一种可能的实现方式中，在本公开实施例提供的移位寄存器中，所述移位寄存器还包括：第二十一晶体管；其中，所述第二十一晶体管的栅极与第二帧复位信号端电连接，所述第二十一晶体管的第一极与所述第三参考信号端电连接，所述第二十一晶体管的第二极与所述驱动输出端电连接。
另一方面，本公开实施例还提供了一种栅极驱动电路，包括级联的多个本公开实施例提供的移位寄存器；
第一级移位寄存器的第一输入信号端与第一帧触发信号端电连接，最后一级移位寄存器的第二输入信号端与第二帧触发信号端电连接；
每两级移位寄存器中，下一级移位寄存器的第一输入信号端与上一级移位寄存器的驱动输出端电连接，上一级移位寄存器的第二输入信号端与下一级移位寄存器的驱动输出端电连接。
另一方面，本公开实施例还提供了一种显示装置，包括本公开实施例提供的栅极驱动电路。
在一种可能的实现方式中，在本公开实施例提供的显示装置中，所述显示装置还包括：相互间隔设置的第一参考信号线、第二参考信号线和第三参考信号线，与所述第一参考信号线电连接的第一参考端子，与所述第二参考信号线电连接的第二参考端子，以及与所述第三参考信号线电连接的第三参考端子；
所述栅极驱动电路中的移位寄存器的所述第一参考信号端与所述第一参考信号线电连接；
所述栅极驱动电路中的移位寄存器的所述第二参考信号端与所述第二参考信号线电连接；
所述栅极驱动电路中的移位寄存器的所述第三参考信号端与所述第三参考信号线电连接。
在一种可能的实现方式中，在本公开实施例提供的显示装置中，所述显示装置还包括：驱动芯片；
所述驱动芯片分别与所述第一参考端子、所述第二参考端子和所述第三参考端子邦定，且所述驱动芯片被配置为通过所述第一参考端子向所述栅极驱动电路中的移位寄存器的所述第一参考信号端加载信号，通过所述第二参考端子向所述栅极驱动电路中的移位寄存器的所述第二参考信号端加载信号，通过所述第三参考端子向所述栅极驱动电路中的移位寄存器的所述第三参考信号端加载信号。
附图说明
图1为本公开实施例提供的移位寄存器的一些结构示意图；
图2为本公开实施例提供的移位寄存器的又一些结构示意图；
图3为本公开实施例提供的移位寄存器的一些具体结构示意图；
图4为本公开实施例提供的一些信号时序图；
图5为本公开实施例提供的移位寄存器的又一些具体结构示意图；
图6为本公开实施例提供的又一些信号时序图；
图7为本公开实施例提供的栅极驱动电路的结构示意图；
图8为本公开实施例提供的移位寄存器中第一输入信号端/第二输入信号端和第十八晶体管/第十九晶体管输出的信号的模拟图；
图9为本公开实施例提供的移位寄存器中第一节点的电位模拟图；
图10为本公开实施例提供的移位寄存器中驱动输出端的电位模拟图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
本公开实施例提供一种移位寄存器，如图1所示，可以包括：第一输入电路1、第二输入电路2、控制电路3以及输出电路4；
第一输入电路1，被配置为响应于第一输入信号端IP1的信号，将第一参考信号端VREF1的信号提供给第一节点N1；
第二输入电路2，被配置为响应于第二输入信号端IP2的信号，将第二参考信号端VREF2的信号提供给第一节点N1；
控制电路3，被配置为控制第一节点N1与第二节点N2的信号；
输出电路4，被配置为响应于第一节点N1的信号，将时钟信号端CLK的信号提供给驱动输出端GOUT；响应于第二节点N2的信号，将第三参考信号端VREF3的信号提供给驱动输出端GOUT；
其中，第一输入信号端IP1和第二输入信号端IP2中的一个在输入阶段加载有效信号，另一个在复位阶段加载有效信号。
本公开实施例提供的上述移位寄存器调整内部结构，通过将第一输入电路1和第二输入电路2设置为对称结构设计，使第一节点N1的充电和放电在正反向扫描时都可以做到对称性设计，从而实现双向扫描的功能。
示例性地，在正向扫描时，可以将第一输入电路1作为信号输入电路，对应的第一输入信号端IP1在输入阶段加载有效信号，即第一输入信号端IP1 接入上一行移位寄存器的驱动输出端GOUT输出的信号，第一输入电路1导通后将第一参考信号端VREF1的信号提供给第一节点N1充电；对应地，可以将第二输入电路2作为信号复位电路，对应的第二输入信号端IP2在复位阶段加载有效信号，即第二输入信号端IP2接入下一行移位寄存器的驱动输出端GOUT输出的信号，当下一行移位寄存器输出有效信号时，第二输入电路2导通后通过第二参考信号端VREF2对第一节点N1放电。
反之，在反向扫描时，可以将第二输入电路2作为信号输入电路，对应的第二输入信号端IP2在输入阶段加载有效信号，即第二输入信号端IP2接入下一行移位寄存器的驱动输出端GOUT输出的信号，第二输入电路1导通后将第二参考信号端VREF2的信号提供给第一节点N1充电；对应地，可以将第一输入电路1作为信号复位电路，对应的第一输入信号端IP1在复位阶段加载有效信号，即第一输入信号端IP1接入上一行移位寄存器的驱动输出端GOUT输出的信号，当上一行移位寄存器输出有效信号时，第一输入电路1导通后通过第一参考信号端VREF1对第一节点N1放电。
示例性地，在正向扫描时，可以对第一参考信号端VREF1加载高电平信号，对第二参考信号端VREF2加载低电平信号；在反向扫描时，可以对第一参考信号端VREF1加载低电平信号，对第二参考信号端VREF2加载高电平信号。
具体地，本公开实施例提供的移位寄存器的结构设计保证了正反向扫描的对称性，并且，相比传统的单向扫描的移位寄存器的电路结构，电路结构内部的晶体管(TFT)的占空比(Duty Cycle)以及各个重要节点的充放电均没有明显差异，这样保证了电路结构的信赖性和稳定性。
在具体实施时，在本公开实施例中，如图2所示，可以使第二节点N2包括：第一子节点N21和第二子节点N22。并且，控制电路3包括第一子控制电路31和第二子控制电路32；其中，第一子控制电路31被配置为控制第一节点N1与第一子节点N21的信号；第二子控制电路32被配置为控制第一节点N1与第二子节点N22的信号。以及，输出电路4被配置为响应于第一子 节点N21的信号，将第三参考信号端VREF3的信号提供给驱动输出端GOUT，以及响应于第二子节点N22的信号，将第三参考信号端VREF3的信号提供给驱动输出端GOUT。
在具体实施时，在本公开实施例中，如图3所示，第一子控制电路31可以包括：第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4以及第五晶体管M5；
第一晶体管M1的栅极与第一极均与第一控制端VN1电连接，第一晶体管M1的第二极与第二晶体管M2的栅极电连接；
第二晶体管M2的第一极与第一控制端VN1电连接，第二晶体管M2的第二极与第一子节点N21电连接；
第三晶体管M3的栅极与第一节点N1电连接，第三晶体管M3的第一极与第三参考信号端VREF3电连接，第三晶体管M3的第二极与第一子节点N21电连接；
第四晶体管M4的栅极与第一节点N1电连接，第四晶体管M4的第一极与第三参考信号端VREF3电连接，第四晶体管M4的第二极与第二晶体管M2的栅极电连接；
第五晶体管M5的栅极与第一子节点N21电连接，第五晶体管M5的第一极与第三参考信号端VREF3电连接，第五晶体管M5的第二极与第一节点N1电连接。
在具体实施时，在本公开实施例中，如图3所示，第二子控制电路32可以包括：第八晶体管M8、第九晶体管M9、第十晶体管M10、第十一晶体管M11以及第十二晶体管M12；
第八晶体管M8的栅极与第一极均与第二控制端VN2电连接，第八晶体管M8的第二极与第九晶体管M9的栅极电连接；
第九晶体管M9的第一极与第二控制端VN2电连接，第九晶体管M9的第二极与第二子节点N22电连接；
第十晶体管M10的栅极与第一节点N1电连接，第十晶体管M10的第一 极与第三参考信号端VREF3电连接，第十晶体管M10的第二极与第二子节点N22电连接；
第十一晶体管M11的栅极与第一节点N1电连接，第十一晶体管M11的第一极与第三参考信号端VREF3电连接，第十一晶体管M11的第二极与第九晶体管M9的栅极电连接；
第十二晶体管M12的栅极与第二子节点N22电连接，第十二晶体管M12的第一极与第三参考信号端VREF3电连接，第十二晶体管M12的第二极与第一节点N1电连接。
在具体实施时，在本公开实施例中，如图3所示，输出电路4可以包括：存储电容CST、第十五晶体管M15、第十六晶体管M16以及第十七晶体管M17；
第十五晶体管M15的栅极与第一节点N1电连接，第十五晶体管M15的第一极与时钟信号端CLK电连接，第十五晶体管M15的第二极与驱动输出端GOUT电连接；
第十六晶体管M16的栅极与第一子节点N21电连接，第十六晶体管M16的第一极与第三参考信号端VREF3电连接，第十六晶体管M16的第二极与驱动输出端GOUT电连接；
第十七晶体管M17的栅极与第二子节点N22电连接，第十七晶体管M17的第一极与第三参考信号端VREF3电连接，第十七晶体管M17的第二极与驱动输出端GOUT电连接；
存储电容CST的第一电极板与第一节点N1电连接，存储电容CST的第二电极板与驱动输出端GOUT电连接。
在具体实施时，在本公开实施例中，如图3所示，第一输入电路1可以包括第十八晶体管M18；
第十八晶体管M18的栅极与第一输入信号端IP1电连接，第十八晶体管M18的第一极与第一参考信号端VREF1电连接，第十八晶体管M18的第二极与第一节点N1电连接。
在具体实施时，在本公开实施例中，如图3所示，第二输入电路2可以包括：第十九晶体管M19；
第十九晶体管M19的栅极与第二输入信号端IP2电连接，第十九晶体管M19的第一极与第二参考信号端VREF2电连接，第十九晶体管M19的第二极与第一节点N1电连接。
以上仅是举例说明本公开实施例提供的移位寄存器的具体结构，在具体实施时，上述各电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
为了降低制备工艺，在具体实施时，如图3所示，所有晶体管均可以为N型晶体管。并且，在正向扫描时，第一参考信号端VREF1的信号可以为高电平信号，第二参考信号端VREF2的信号可以为低电平信号；在反向扫描时，第一参考信号端VREF1的信号可以为低电平信号，第二参考信号端VREF2的信号可以为高电平信号，并且，第三参考信号端VREF3的信号始终为低电平信号。当然，在具体实施时，所有晶体管也均可以为P型晶体管，在此不作限定。
在具体实施时，第一控制端VN1的信号和第二控制端VN2的信号可以分别为高电平和低电平切换的脉冲信号，并且，第一控制端VN1的电平和第二控制端VN2的电平相反。例如，如图4所示，在T10阶段中，第一控制端VN1为高电平信号，第二控制端VN2为低电平信号。在T20阶段中，第一控制端VN1为低电平信号，第二控制端VN2为高电平信号。示例性地，可以使T10阶段的维持时长与T20阶段的维持时长相同。例如将T10阶段的维持时长与T20阶段的维持时长分别设置为1个显示帧的时长、多个显示帧的时长、2s、1h或24h等，在此不作限定。
在具体实施时，第一控制端VN1的信号和第二控制端VN2的信号也可以分别为直流信号。并且，在第一控制端VN1加载高电平的直流信号时，第二控制端VN2不加载信号或加载低电平的直流信号。在第二控制端加载高电平的直流信号时，第一控制端VN1不加载信号或加载低电平的直流信号。例如， 在T10阶段中，第一控制端VN1为高电平的直流信号，第二控制端VN2为低电平的直流信号。在T20阶段中，第一控制端VN1为低电平的直流信号，第二控制端VN2为高电平的直流信号。示例性地，可以使T10阶段的维持时长与T20阶段的维持时长相同。例如将T10阶段的维持时长与T20阶段的维持时长分别设置为1个显示帧的时长、多个显示帧的时长、2s、1h或24h等，在此不作限定。
其中，T10阶段和T20阶段可以根据实际应用来确定先后顺序。例如，可以先执行T10阶段中的工作过程，之后再执行T20阶段中的工作过程。或者，也可以先执行T20阶段中的工作过程，之后再执行T10阶段中的工作过程。
下面以图3所示的移位寄存器的结构为例，结合图4所示的信号时序图，以正向扫描为例，对本公开实施例提供的上述移位寄存器的工作过程作以详细的描述。下述描述中以1表示高电平信号，0表示低电平信号，其中，1和0代表其逻辑电平，仅是为了更好的解释本公开实施例提供的上述移位寄存器的工作过程，而不是在具体实施时施加在各晶体管的栅极的电位。
其中，选取图4所示的信号时序图中的T10阶段和T20阶段。并且，选取T10阶段中的输入阶段T11、复位阶段T12、输出阶段T13。以及选取T20阶段中的输入阶段T21、复位阶段T22、输出阶段T23。
在T10阶段中，由于第二控制端VN2为低电平信号，因此第八晶体管M8截止。
在输入阶段T11，IP1＝1，CLK＝0，IP2＝0。
由于IP2＝0，因此第十九晶体管M19截止。由于IP1＝1，因此第十八晶体管M18导通，以将第一参考信号端VREF1的高电平信号提供给第一节点N1，使第一节点N1为高电平信号，从而控制第三晶体管M3、第四晶体管M4、第十晶体管M10、第十一晶体管M11以及第十五晶体管M15均导通。导通的第四晶体管M4可以将第三参考信号端VREF3的低电平信号提供给第二晶体管M2的栅极，以控制第二晶体管M2截止。导通的第三晶体管M3可以将第 三参考信号端VREF3的低电平信号提供给第一子节点N21，以使第一子节点N21为低电平信号，从而控制第五晶体管M5以及第十六晶体管M16均截止。导通的第十一晶体管M11可以将第三参考信号端VREF3的低电平信号提供给第九晶体管M9的栅极，以控制第九晶体管M9截止。导通的第十晶体管M10可以将第三参考信号端VREF3的低电平信号提供给第二子节点N22，以使第二子节点N22为低电平信号，从而控制第十二晶体管M12以及第十七晶体管M17均截止。导通的第十五晶体管M15可以将时钟信号端CLK的低电平信号提供给驱动信号输出端GOUT，以使驱动信号输出端GOUT输出低电平信号。
在输出阶段T12，IP1＝0，CLK＝1，IP2＝0。
由于IP2＝0，因此第十九晶体管M19截止。由于IP1＝0，因此第十八晶体管M18截止。因此，第一节点N1处于浮接状态。由于存储电容的作用，可以使第一节点N1保持为高电平信号。由于第一节点N1为高电平信号，从而控制第三晶体管M3、第四晶体管M4、第十晶体管M10、第十一晶体管M11以及第十五晶体管M15均导通。导通的第四晶体管M4可以将第三参考信号端VREF3的低电平信号提供给第二晶体管M2的栅极，以控制第二晶体管M2截止。导通的第三晶体管M3可以将第三参考信号端VREF3的低电平信号提供给第一子节点N21，以使第一子节点N21为低电平信号，从而控制第五晶体管M5以及第十六晶体管M16均截止。导通的第十一晶体管M11可以将第三参考信号端VREF3的低电平信号提供给第九晶体管M9的栅极，以控制第九晶体管M9截止。导通的第十晶体管M10可以将第三参考信号端VREF3的低电平信号提供给第二子节点N22，以使第二子节点N22为低电平信号，从而控制第十二晶体管M12以及第十七晶体管M17均截止。
导通的第十五晶体管M15可以将时钟信号端CLK的高电平信号提供给驱动信号输出端GOUT。由于第一节点N1浮接，通过存储电容的作用，第一节点N1被进一步拉高，从而使第十五晶体管M15可以尽可能完全导通，以使时钟信号端CLK的高电平信号可以尽可能无电压损失的提供给驱动信号输出 端GOUT，以使驱动信号输出端GOUT输出高电平信号。
在复位阶段T13，IP1＝0，CLK＝0，IP2＝1。
由于IP1＝0，因此第十八晶体管M18截止。由于IP2＝1，因此第十九晶体管M19导通，将第二参考信号端VREF2的低电平信号提供给第一节点N1，以使第一节点N1为低电平信号，从而控制第三晶体管M3、第四晶体管M4、第十晶体管M10、第十一晶体管M11以及第十五晶体管M15均截止。并且，第二子节点N22保持为低电平信号，从而控制第十二晶体管M12以及第十七晶体管M17均截止。
第一晶体管M1在第一控制端VN1的高电平信号的控制下导通，以将第一控制端VN1的高电平信号提供给第二晶体管M2的栅极，从而控制第二晶体管M2导通。导通的第二晶体管M2可以将第一控制端VN1的高电平信号提供给第一子节点N21，以使第一子节点N21为高电平信号，从而控制第五晶体管M5以及第十六晶体管M16均导通。导通的第五晶体管M5可以将第三参考信号端VREF3的低电平信号提供给第一节点N1，以使第一节点N1进一步为低电平信号。导通的第十六晶体管M16可以将第三参考信号端VREF3的低电平信号提供给驱动信号输出端GOUT，以使驱动信号输出端GOUT输出低电平信号。
在T20阶段中，由于第一控制端VN1为低电平信号，因此第一晶体管M1截止。
在输入阶段T21，IP1＝1，CLK＝0，IP2＝0。
由于IP2＝0，因此第十九晶体管M19截止。由于IP1＝1，因此第十八晶体管M18导通，以将第一参考信号端VREF1的高电平信号提供给第一节点N1，使第一节点N1为高电平信号，从而控制第三晶体管M3、第四晶体管M4、第十晶体管M10、第十一晶体管M11以及第十五晶体管M15均导通。导通的第四晶体管M4可以将第三参考信号端VREF3的低电平信号提供给第二晶体管M2的栅极，以控制第二晶体管M2截止。导通的第三晶体管M3可以将第三参考信号端VREF3的低电平信号提供给第一子节点N21，以使第一子节点 N21为低电平信号，从而控制第五晶体管M5以及第十六晶体管M16均截止。导通的第十一晶体管M11可以将第三参考信号端VREF3的低电平信号提供给第九晶体管M9的栅极，以控制第九晶体管M9截止。导通的第十晶体管M10可以将第三参考信号端VREF3的低电平信号提供给第二子节点N22，以使第二子节点N22为低电平信号，从而控制第十二晶体管M12以及第十七晶体管M17均截止。导通的第十五晶体管M15可以将时钟信号端CLK的低电平信号提供给驱动信号输出端GOUT，以使驱动信号输出端GOUT输出低电平信号。
在输出阶段T22，IP1＝0，CLK＝1，IP2＝0。
由于IP2＝0，因此第十九晶体管M19截止。由于IP1＝0，因此第十八晶体管M18截止。因此，第一节点N1处于浮接状态。由于存储电容的作用，可以使第一节点N1保持为高电平信号。由于第一节点N1为高电平信号，从而控制第三晶体管M3、第四晶体管M4、第十晶体管M10、第十一晶体管M11以及第十五晶体管M15均导通。导通的第四晶体管M4可以将第三参考信号端VREF3的低电平信号提供给第二晶体管M2的栅极，以控制第二晶体管M2截止。导通的第三晶体管M3可以将第三参考信号端VREF3的低电平信号提供给第一子节点N21，以使第一子节点N21为低电平信号，从而控制第五晶体管M5以及第十六晶体管M16均截止。导通的第十一晶体管M10可以将第三参考信号端VREF3的低电平信号提供给第九晶体管M9的栅极，以控制第九晶体管M9截止。导通的第十晶体管M10可以将第三参考信号端VREF3的低电平信号提供给第二子节点N22，以使第二子节点N22为低电平信号，从而控制第十二晶体管M12以及第十七晶体管M17均截止。
导通的第十五晶体管M15可以将时钟信号端CLK的高电平信号提供给驱动信号输出端GOUT。由于第一节点N1浮接，通过存储电容的作用，第一节点N1被进一步拉高，从而使第十五晶体管M15可以尽可能完全导通，以使时钟信号端CLK的高电平信号可以尽可能无电压损失的提供给驱动信号输出端GOUT，以使驱动信号输出端GOUT输出高电平信号。
在复位阶段T23，IP1＝0，CLK＝0，IP2＝1。
由于IP2＝0，因此第十八晶体管M18截止。由于IP2＝1，因此第十九晶体管M19导通，将第二参考信号端VREF3的低电平信号提供给第一节点N1，以使第一节点N1为低电平信号，从而控制第三晶体管M3、第四晶体管M4、第十晶体管M10、第十一晶体管M11以及第十五晶体管M15均截止。并且，第一子节点N21保持为低电平信号，从而控制第五晶体管M5以及第十六晶体管M16均截止。
第八晶体管M8在第二控制端VN2的高电平信号的控制下导通，以将第二控制端VN2的高电平信号提供给第九晶体管M9的栅极，从而控制第九晶体管M9导通。导通的第九晶体管M9可以将第二控制端VN2的高电平信号提供给第二子节点N22，以使第二子节点N22为高电平信号，从而控制第十二晶体管M12以及第十七晶体管M17均导通。导通的第十二晶体管M12可以将第三参考信号端VREF3的低电平信号提供给第一节点N1，以使第一节点N1进一步为低电平信号。导通的第十七晶体管M17可以将第三参考信号端VREF3的低电平信号提供给驱动信号输出端GOUT，以使驱动信号输出端GOUT输出低电平信号。
本公开实施例又提供了一些移位寄存器的结构示意图，如图5所示，其针对上述实施例的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图5所示，第一子控制电路31还可以包括：第六晶体管M6和第七晶体管M7；其中，第六晶体管M6的栅极与第一输入信号端IP1电连接，第六晶体管M6的第一极与第三参考信号端VREF3电连接，第六晶体管M6的第二极与第一子节点N21电连接；第七晶体管M7的栅极与第二输入信号端IP2电连接，第七晶体管M7的第一极与第三参考信号端VREF3电连接，第七晶体管M7的第二极与第一子节点N21电连接。
在具体实施时，在本公开实施例中，如图5所示，第二子控制电路32还 可以包括：第十三晶体管M13和第十四晶体管M14；其中，第十三晶体管M13的栅极与第一输入信号端IP1电连接，第十三晶体管M13的第一极与第三参考信号端VREF3电连接，第十三晶体管M13的第二极与第二子节点N22电连接；第十四晶体管M14的栅极与第二输入信号端IP2电连接，第十四晶体管M14的第一极与第三参考信号端VREF3电连接，第十四晶体管M14的第二极与第二子节点N22电连接。
通过模拟计算可知，在第一子控制电路31中增加的第六晶体管M6和在第二子控制电路32中增加的第十三晶体管M13，可以在正向扫描时，迅速拉低第二节点N2(即第一子节点N21和第二子节点N22)的电位，控制第五晶体管M5和第十二晶体管M12的漏电问题，提升第一节点N1的信号质量。在第一子控制电路31中增加的第七晶体管M7和在第二子控制电路32中增加的第十四晶体管M14，可以在反向扫描时，迅速拉低第二节点N2(即第一子节点N21和第二子节点N22)的电位，控制第五晶体管M5和第十二晶体管M12的漏电问题，提升第一节点N1的信号质量。
图8示出了本公开实施例提供的移位寄存器中在正向扫描时第一输入信号端IP1和在反向扫描时第二输入信号端IP2输入的信号，该信号为上一级移位寄存器的驱动信号输出端GOUT输出的信号①，可以看出，该信号抬升更快，Vmax值更高。图8还示出了本公开实施例提供的移位寄存器中在正向扫描时第十八晶体管M18输出到第一节点N1的信号和在反向扫描时第十九晶体管M19输出到第一节点N1的信号②。图9示出了第一节点N1在输入阶段③、输出阶段④和复位阶段⑤的电位示意图，可以看出在采用本公开实施例提供的移位寄存器结构(即优化后)，相对于传统的移位寄存器结构(即优化前)，可以提高第一节点N1的信号电位质量。图10示出了驱动信号输出端GOUT的电位示意图，可以看出在采用本公开实施例提供的移位寄存器结构(即优化后)，相对于传统的移位寄存器结构(即优化前)，可以降低驱动信号输出端GOUT在复位阶段⑥的拖尾问题，防止不良(水平黑线)发生，保证了驱动信号输出端GOUT的信号质量，可以一定程度上提升移位寄存器的 寿命。并且，通过模拟测试可知，本公开实施例提供的移位寄存器能够支持更高温信赖性运行条件(-20～70℃)，来解决高温寿命的问题。
在具体实施时，在本公开实施例中，如图5所示，移位寄存器还可以包括：第二十晶体管M20；其中，第二十晶体管M20的栅极与第一帧复位信号端SRE1电连接，第二十晶体管M20的第一极与第三参考信号端VREF3电连接，第二十晶体管M20的第二极与第一节点N1电连接。
在具体实施时，在本公开实施例中，如图5所示，移位寄存器还可以包括：第二十一晶体管M21；其中，第二十一晶体管M21的栅极与第二帧复位信号端SRE2电连接，第二十一晶体管M21的第一极与第三参考信号端VREF3电连接，第二十一晶体管M21的第二极与驱动输出端GOUT电连接。
下面以图5所示的移位寄存器的结构为例，结合图6所示的信号时序图，以正向扫描为例，对本公开实施例提供的上述移位寄存器的工作过程作以描述。其中，本实施例对应的工作过程与图3所示的移位寄存器的工作过程部分相同，下面仅说明工作过程不同的内容。
在T10阶段中，在输入阶段T11之前，还可以包括帧复位阶段T01。在帧复位阶段T01中，第一帧复位信号端SRE1为高电平信号，可以控制第二十晶体管M20导通，以将第三参考信号端VREF3的低电平信号提供给第一节点N1，从而对第一节点N1进行预复位，进而可以进一步降低驱动输出端GOUT的噪声。并且，第二帧复位信号端SRE2为高电平信号，可以控制第二十一晶体管M21导通，以将第三参考信号端VREF3的低电平信号提供给驱动输出端GOUT，从而对驱动输出端GOUT进行预复位，进而可以进一步降低驱动输出端GOUT的噪声。以及，在输入阶段T11中，第六晶体管M6在第一输入信号端IP1的高电平信号的控制下导通，以将第三参考信号端VREF3的低电平信号提供给第一子节点N21，从而可以进一步使第一子节点N21为电平信号，进而可以进一步降低驱动输出端GOUT的噪声。第十三晶体管M13在第一输入信号端IP1的高电平信号的控制下导通，以将第三参考信号端VREF3的低电平信号提供给第二子节点N22，从而可以进一步使第二子节 点N22为低电平信号，进而可以进一步降低驱动输出端GOUT的噪声。(在反向扫描时，在输入阶段T11中，第七晶体管M7在第二输入信号端IP2的高电平信号的控制下导通，以将第三参考信号端VREF3的低电平信号提供给第一子节点N21，从而可以进一步使第一子节点N21为电平信号，进而可以进一步降低驱动输出端GOUT的噪声。第十四晶体管M14在第二输入信号端IP2的高电平信号的控制下导通，以将第三参考信号端VREF3的低电平信号提供给第二子节点N22，从而可以进一步使第二子节点N22为低电平信号，进而可以进一步降低驱动输出端GOUT的噪声。)
在T20阶段中，在输入阶段T21之前，还可以包括帧复位阶段T02。在帧复位阶段T02中，第一帧复位信号端SRE1为高电平信号，可以控制第二十晶体管M20导通，以将第三参考信号端VREF3的低电平信号提供给第一节点N1，从而对第一节点N1进行预复位，进而可以进一步降低驱动输出端GOUT的噪声。并且，第二帧复位信号端SRE2为高电平信号，可以控制第二十一晶体管M21导通，以将第三参考信号端VREF3的低电平信号提供给驱动输出端GOUT，从而对驱动输出端GOUT进行预复位，进而可以进一步降低驱动输出端GOUT的噪声。以及，在输入阶段T11中，第六晶体管M6在第一输入信号端IP1的高电平信号的控制下导通，以将第三参考信号端VREF3的低电平信号提供给第一子节点N21，从而可以进一步使第一子节点N21为电平信号，进而可以进一步降低驱动输出端GOUT的噪声。第十三晶体管M13在第一输入信号端IP1的高电平信号的控制下导通，以将第三参考信号端VREF3的低电平信号提供给第二子节点N22，从而可以进一步使第二子节点N22为低电平信号，进而可以进一步降低驱动输出端GOUT的噪声。(在反向扫描时，在输入阶段T11中，第七晶体管M7在第二输入信号端IP2的高电平信号的控制下导通，以将第三参考信号端VREF3的低电平信号提供给第一子节点N21，从而可以进一步使第一子节点N21为电平信号，进而可以进一步降低驱动输出端GOUT的噪声。第十四晶体管M14在第二输入信号端IP2的高电平信号的控制下导通，以将第三参考信号端VREF3的低电平信号提供 给第二子节点N22，从而可以进一步使第二子节点N22为低电平信号，进而可以进一步降低驱动输出端GOUT的噪声。)
本公开实施例还提供了一种栅极驱动电路，如图7所示，包括级联的多个本公开实施例提供的移位寄存器：SR(1)、SR(2)……SR(n-1)、SR(n)……SR(N-1)、SR(N)(共N个移位寄存器，1≤n≤N，n和N为正整数)，其中：
第一级移位寄存器SR(1)的第一输入信号端IP1与第一帧触发信号端STV1电连接，最后一级移位寄存器SR(N)的第二输入信号端IP2与第二帧触发信号端STV2电连接；
每两级移位寄存器中，下一级移位寄存器SR(n)的第一输入信号端IP1与上一级移位寄存器SR(n-1)的驱动输出端GOUT电连接，上一级移位寄存器SR(n-1)的第二输入信号端IP2与下一级移位寄存器SR(n)的驱动输出端GOUT电连接。值得注意的是，图7是以每相邻的两级移位寄存器中，下一级移位寄存器SR(n)的第一输入信号端IP1与上一级移位寄存器SR(n-1)的驱动输出端GOUT电连接，上一级移位寄存器SR(n-1)的第二输入信号端IP2与下一级移位寄存器SR(n)的驱动输出端GOUT电连接为例进行说明的，在实际应用中，每两级移位寄存器可以是指间隔一个或多个移位寄存器，在此不做限定。
具体地，上述栅极驱动电路中的每个移位寄存器与本公开实施例提供的移位寄存器在功能和结构上均相同，重复之处不再赘述。值得注意的是，在正向扫描时，从第一帧触发信号端STV1加载帧起始信号，栅极驱动电路中从第一级移位寄存器SR(1)的驱动输出端GOUT作为起始依次输出有效信号；在反向扫描时，从第二帧触发信号端STV2加载帧起始信号，栅极驱动电路中从最后一级移位寄存器SR(n)的驱动输出端GOUT作为起始依次输出有效信号。
在具体实施时，在本公开实施例提供的栅极驱动电路中，如图7所示，第奇数级移位寄存器的时钟信号端CLK均与同一时钟线clk1电连接，第偶数级移位寄存器的时钟信号端CLK均与同一时钟线clk2电连接。
在具体实施时，在本公开实施例提供的栅极驱动电路中，如图7所示， 每一级移位寄存器的第一参考信号端VREF1均与同一第一参考信号线ref1电连接。每一级移位寄存器的第二参考信号端VREF2均与同一第二参考信号线ref2电连接。每一级移位寄存器的第三参考信号端VREF3均与同一第三参考信号线ref3电连接。在正向扫描时，第一参考信号线ref1向各级移位寄存器的第一参考信号端VREF1加载高电平信号，第二参考信号线ref2向各级移位寄存器的第二参考信号端VREF2加载低电平信号。在反向扫描时，第一参考信号线ref1向各级移位寄存器的第一参考信号端VREF1加载低电平信号，第二参考信号线ref2向各级移位寄存器的第二参考信号端VREF2加载高电平信号。在正向扫描和反向扫描时，第三参考信号线ref3均向各级移位寄存器的第三参考信号端VREF3加载低电平信号。
在具体实施时，在移位寄存器包括第二十晶体管M20时，在本公开实施例提供的栅极驱动电路中，可以使每一级移位寄存器的第一帧复位信号端SRE1均与同一第一帧复位端电连接。这样可以同时对每一级移位寄存器的第一节点N1进行预复位。
在具体实施时，在移位寄存器包括第二十一晶体管M21时，在本公开实施例提供的栅极驱动电路中，可以使每一级移位寄存器的第二帧第二输入信号端SRE2均与同一第二帧复位端电连接。这样可以同时对每一级移位寄存器的驱动输出端GOUT进行预复位。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述栅极驱动电路。该显示装置解决问题的原理与前述栅极驱动电路相似，因此该显示装置的实施可以参见前述栅极驱动电路的实施，重复之处在此不再赘述。
在具体实施时，在本公开实施例中，显示装置还可以包括：相互间隔设置的第一参考信号线、第二参考信号线和第三参考信号线，与第一参考信号线电连接的第一参考端子，与第二参考信号线电连接的第二参考端子，以及与第三参考信号线电连接的第三参考端子；其中，栅极驱动电路中的移位寄存器的第一参考信号端VREF1与第一参考信号线电连接，栅极驱动电路中的 移位寄存器的第二参考信号端VREF2与第二参考信号线电连接，栅极驱动电路中的移位寄存器的第三参考信号端VREF3与第三参考信号线电连接。
在具体实施时，在本公开实施例中，显示装置还可以包括：驱动芯片；其中，驱动芯片分别与第一参考端子、第二参考端子第三参考端子邦定，且驱动芯片被配置为通过第一参考端子向栅极驱动电路中的移位寄存器的第一参考信号端VREF1加载信号，通过第二参考端子向栅极驱动电路中的移位寄存器的第二参考信号端VREF2加载信号，通过第三参考端子向栅极驱动电路中的移位寄存器的第三参考信号端VREF3加载信号。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的移位寄存器、栅极驱动电路及显示装置，在正向扫描时，在输入阶段通过第一输入电路响应于第一输入信号端的信号可以将第一参考信号端的信号提供给第一节点，在复位阶段，通过第二输入电路响应于第二输入信号端的信号可以将第二参考信号端的信号提供给第一节点。在反向扫描时，在输入阶段通过第而输入电路响应于第二输入信号端的信号可以将第二参考信号端的信号提供给第一节点，在复位阶段，通过第一输入电路响应于第一输入信号端的信号可以将第一参考信号端的信号提供给第一节点。通过控制电路可以控制第一节点与第二节点的信号。通过输出电路响应于第一节点的信号，可以将时钟信号端的信号提供给驱动输出端，以及响应于第二节点的信号，可以将第三参考信号端的信号提供给驱动输出端。通过将第一输入电路和第二输入电路设置为对称结构设计，使第一节点的充电和放电在正反向扫描时都可以做到对称性设计，从而实现双向扫描的功能。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要 求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (15)

  1. 一种移位寄存器，其中，包括：
    第一输入电路，被配置为响应于第一输入信号端的信号，将第一参考信号端的信号提供给第一节点；
    第二输入电路，被配置为响应于第二输入信号端的信号，将第二参考信号端的信号提供给所述第一节点；
    控制电路，被配置为控制所述第一节点与第二节点的信号；
    输出电路，被配置为响应于所述第一节点的信号，将时钟信号端的信号提供给驱动输出端；响应于所述第二节点的信号，将第三参考信号端的信号提供给所述驱动输出端；
    其中，所述第一输入信号端和所述第二输入信号端中的一个在输入阶段加载有效信号，另一个在复位阶段加载有效信号。
  2. 如权利要求1所述的移位寄存器，其中，所述第二节点包括：第一子节点和第二子节点；
    所述控制电路包括第一子控制电路和第二子控制电路，所述第一子控制电路被配置为控制所述第一节点与所述第一子节点的信号；所述第二子控制电路被配置为控制所述第一节点与所述第二子节点的信号；
    所述输出电路被配置为响应于所述第一子节点的信号，将所述第三参考信号端的信号提供给所述驱动输出端，以及响应于所述第二子节点的信号，将所述第三参考信号端的信号提供给所述驱动输出端。
  3. 如权利要求2所述的移位寄存器，其中，所述第一子控制电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管以及第五晶体管；
    所述第一晶体管的栅极与第一极均与第一控制端电连接，所述第一晶体管的第二极与所述第二晶体管的栅极电连接；
    所述第二晶体管的第一极与所述第一控制端电连接，所述第二晶体管的第二极与所述第一子节点电连接；
    所述第三晶体管的栅极与所述第一节点电连接，所述第三晶体管的第一极与所述第三参考信号端电连接，所述第三晶体管的第二极与所述第一子节点电连接；
    所述第四晶体管的栅极与所述第一节点电连接，所述第四晶体管的第一极与所述第三参考信号端电连接，所述第四晶体管的第二极与所述第二晶体管的栅极电连接；
    所述第五晶体管的栅极与所述第一子节点电连接，所述第五晶体管的第一极与所述第三参考信号端电连接，所述第五晶体管的第二极与所述第一节点电连接。
  4. 如权利要求3所述的移位寄存器，其中，所述第一子控制电路还包括：第六晶体管和第七晶体管；
    所述第六晶体管的栅极与所述第一输入信号端电连接，所述第六晶体管的第一极与所述第三参考信号端电连接，所述第六晶体管的第二极与所述第一子节点电连接；
    所述第七晶体管的栅极与所述第二输入信号端电连接，所述第七晶体管的第一极与所述第三参考信号端电连接，所述第七晶体管的第二极与所述第一子节点电连接。
  5. 如权利要求2所述的移位寄存器，其中，所述第二子控制电路包括：第八晶体管、第九晶体管、第十晶体管、第十一晶体管以及第十二晶体管；
    所述第八晶体管的栅极与第一极均与第二控制端电连接，所述第八晶体管的第二极与所述第九晶体管的栅极电连接；
    所述第九晶体管的第一极与所述第二控制端电连接，所述第九晶体管的第二极与所述第二子节点电连接；
    所述第十晶体管的栅极与所述第一节点电连接，所述第十晶体管的第一极与所述第三参考信号端电连接，所述第十晶体管的第二极与所述第二子节点电连接；
    所述第十一晶体管的栅极与所述第一节点电连接，所述第十一晶体管的 第一极与所述第三参考信号端电连接，所述第十一晶体管的第二极与所述第九晶体管的栅极电连接；
    所述第十二晶体管的栅极与所述第二子节点电连接，所述第十二晶体管的第一极与所述第三参考信号端电连接，所述第十二晶体管的第二极与所述第一节点电连接。
  6. 如权利要求5所述的移位寄存器，其中，所述第二子控制电路还包括：第十三晶体管和第十四晶体管；
    所述第十三晶体管的栅极与所述第一输入信号端电连接，所述第十三晶体管的第一极与所述第三参考信号端电连接，所述第十三晶体管的第二极与所述第二子节点电连接；
    所述第十四晶体管的栅极与所述第二输入信号端电连接，所述第十四晶体管的第一极与所述第三参考信号端电连接，所述第十四晶体管的第二极与所述第二子节点电连接。
  7. 如权利要求2所述的移位寄存器，其中，所述输出电路包括：存储电容、第十五晶体管、第十六晶体管以及第十七晶体管；
    所述第十五晶体管的栅极与所述第一节点电连接，所述第十五晶体管的第一极与所述时钟信号端电连接，所述第十五晶体管的第二极与所述驱动输出端电连接；
    所述第十六晶体管的栅极与所述第一子节点电连接，所述第十六晶体管的第一极与所述第三参考信号端电连接，所述第十六晶体管的第二极与所述驱动输出端电连接；
    所述第十七晶体管的栅极与所述第二子节点电连接，所述第十七晶体管的第一极与所述第三参考信号端电连接，所述第十七晶体管的第二极与所述驱动输出端电连接；
    所述存储电容的第一电极板与所述第一节点电连接，所述存储电容的第二电极板与所述驱动输出端电连接。
  8. 如权利要求1-7任一项所述的移位寄存器，其中，所述第一输入电路 包括第十八晶体管；
    所述第十八晶体管的栅极与所述第一输入信号端电连接，所述第十八晶体管的第一极与所述第一参考信号端电连接，所述第十八晶体管的第二极与所述第一节点电连接。
  9. 如权利要求1-7任一项所述的移位寄存器，其中，所述第二输入电路包括：第十九晶体管；
    所述第十九晶体管的栅极与所述第二输入信号端电连接，所述第十九晶体管的第一极与所述第二参考信号端电连接，所述第十九晶体管的第二极与所述第一节点电连接。
  10. 如权利要求1-7任一项所述的移位寄存器，其中，所述移位寄存器还包括：第二十晶体管；
    所述第二十晶体管的栅极与第一帧复位信号端电连接，所述第二十晶体管的第一极与所述第三参考信号端电连接，所述第二十晶体管的第二极与所述第一节点电连接。
  11. 如权利要求1-7任一项所述的移位寄存器，其中，所述移位寄存器还包括：第二十一晶体管；其中，所述第二十一晶体管的栅极与第二帧复位信号端电连接，所述第二十一晶体管的第一极与所述第三参考信号端电连接，所述第二十一晶体管的第二极与所述驱动输出端电连接。
  12. 一种栅极驱动电路，其中，包括级联的多个如权利要求1-11任一项所述的移位寄存器；
    第一级移位寄存器的第一输入信号端与第一帧触发信号端电连接，最后一级移位寄存器的第二输入信号端与第二帧触发信号端电连接；
    每两级移位寄存器中，下一级移位寄存器的第一输入信号端与上一级移位寄存器的驱动输出端电连接，上一级移位寄存器的第二输入信号端与下一级移位寄存器的驱动输出端电连接。
  13. 一种显示装置，其中，包括如权利要求12所述的栅极驱动电路。
  14. 如权利要求13所述的显示装置，其中，所述显示装置还包括：相互 间隔设置的第一参考信号线、第二参考信号线和第三参考信号线，与所述第一参考信号线电连接的第一参考端子，与所述第二参考信号线电连接的第二参考端子，以及与所述第三参考信号线电连接的第三参考端子；
    所述栅极驱动电路中的移位寄存器的所述第一参考信号端与所述第一参考信号线电连接；
    所述栅极驱动电路中的移位寄存器的所述第二参考信号端与所述第二参考信号线电连接；
    所述栅极驱动电路中的移位寄存器的所述第三参考信号端与所述第三参考信号线电连接。
  15. 如权利要求14所述的显示装置，其中，所述显示装置还包括：驱动芯片；
    所述驱动芯片分别与所述第一参考端子、所述第二参考端子和所述第三参考端子邦定，且所述驱动芯片被配置为通过所述第一参考端子向所述栅极驱动电路中的移位寄存器的所述第一参考信号端加载信号，通过所述第二参考端子向所述栅极驱动电路中的移位寄存器的所述第二参考信号端加载信号，通过所述第三参考端子向所述栅极驱动电路中的移位寄存器的所述第三参考信号端加载信号。
PCT/CN2021/081477 2021-03-18 2021-03-18 移位寄存器、栅极驱动电路及显示装置 WO2022193215A1 (zh)

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