WO2016127589A1 - 栅极驱动电路及其驱动方法、阵列基板、显示装置 - Google Patents

栅极驱动电路及其驱动方法、阵列基板、显示装置 Download PDF

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Publication number
WO2016127589A1
WO2016127589A1 PCT/CN2015/085009 CN2015085009W WO2016127589A1 WO 2016127589 A1 WO2016127589 A1 WO 2016127589A1 CN 2015085009 W CN2015085009 W CN 2015085009W WO 2016127589 A1 WO2016127589 A1 WO 2016127589A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
clock signal
odd
array
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PCT/CN2015/085009
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English (en)
French (fr)
Inventor
张元波
韩承佑
郑皓亮
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京东方科技集团股份有限公司
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Priority to US14/906,781 priority Critical patent/US9905155B2/en
Publication of WO2016127589A1 publication Critical patent/WO2016127589A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display devices, and in particular to a gate driving circuit, a driving method of the gate driving circuit, an array substrate including the gate driving circuit, and a display device.
  • the gate drive circuit implements a shift register function, and the gate drive circuit includes a plurality of sets of shift register units. For each of the three shift register units in each set of shift register units, the second shift register unit It is used to input the third shift register unit and to reset the first shift register unit to implement the function of the sequential output. Therefore, the first shift register unit needs to add an additional start signal STV to perform the initial input of each frame, and the last shift register unit also needs to perform additional reset control to achieve normal shutdown.
  • FIG. 1 and FIG. 2 are schematic diagrams of cascaded gate drive circuits (taking four clock signals CLK1, CLK2, CLK3, and CLK4 as an example).
  • the shift register unit 11 corresponding to the output signal gate output N supplies a scan signal output for the last row of pixels.
  • the last shift register unit for outputting the scan signal is reset using a normal additional set of ordinary shift register units, as shown in the figure, the output signal reset output (Reset output) 1 A shift register unit corresponding to the output signal Reset output 2.
  • the shift register pair and output signal with two additional reset functions are used.
  • the shift register unit corresponding to the reset output 1 and the shift register unit corresponding to the output signal Reset output 2 are reset.
  • a Reset Output 3 outputted by a shift register unit having a self-reset function is used to reset a reset unit of the output Reset output 1, and another shift register having a self-reset function.
  • Reset of unit output Output 4 is used to reset the reset unit of the output Reset output 2.
  • the shift register unit with self-reset function needs to add additional TFT devices, which increases the space occupied by the gate drive circuit, which is not conducive to the narrow bezel design and may affect the picture quality.
  • the reset signal is directly input from the driving IC (ie, the reset signal line RST is increased), and the shift register unit corresponding to the output signal Reset output 1 corresponds to the output signal Reset output 2
  • the shift register unit performs a reset. This will also increase the border width and IC cost.
  • An object of the present disclosure is to provide a gate driving circuit including a matrix substrate of the gate driving circuit and a display device including the array substrate, the gate driving circuit capable of The reset of the last stage shift register unit is implemented without adding components.
  • a gate driving circuit including at least one set of clock signal lines and cascaded multi-stage shift register units, the at least one set of clocks
  • Each set of clock signal lines in the signal line includes two of the clock signal lines, the plurality of stages of the shift register unit are divided into at least one group, and each of the sets of the clock signal lines corresponds to a set of the shifts a register unit, wherein one of the clock signal lines of each group of clock signal lines is connected to a reset signal input terminal of a last-stage shift register unit of a group of shift register units corresponding to the group of clock signal lines, to A reset signal is provided to the reset signal input terminal of the last stage shift register unit of the set of shift register units at the beginning of the reset phase.
  • the gate driving circuit includes an even-numbered shift register unit
  • the gate driving circuit includes an odd-array clock signal line and an even-array clock signal line
  • the odd-array clock signal line includes a first odd-numbered clock signal line and a second odd clock signal line
  • the even array clock signal line includes a first even clock signal line and a second even clock signal line
  • the plurality of stages of the shift register unit are divided into odd array shift registers corresponding to odd line gate lines a cell and an even array shift register unit corresponding to an even row gate line
  • a last stage shift register unit of the odd array shift register unit is used as an odd array reset unit
  • the last stage shift register unit of the array shift register unit is used as an even array reset unit
  • the first even clock signal line is connected to the reset signal input end of the odd array reset unit
  • the second odd clock signal line is connected to the even number
  • the reset signal input end of the group reset unit is connected
  • the output end of the odd array reset unit is connected to the input end of the even array reset unit, and
  • the shift register unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, and an eighth thin film transistor a ninth thin film transistor and a storage capacitor, a gate and a first pole of the first thin film transistor being connected to a signal input end of the shift register unit, a second pole of the first thin film transistor and the second a first pole of the thin film transistor is connected, a gate of the second thin film transistor is connected to a reset signal input end of the shift register unit, and a second pole of the second thin film transistor is connected to a low level input end.
  • a first pole of the third thin film transistor is connected to the first clock signal input end, a gate of the third thin film transistor is connected to a second pole of the first thin film transistor, and a second pole of the third thin film transistor Connected to an output of the shift register unit, a first pole of the fourth thin film transistor is connected to a second clock signal input terminal, and a second pole of the fourth thin film transistor a first pole of the fifth thin film transistor is connected, a gate of the fourth thin film transistor is connected to a second pole of the seventh thin film transistor, a gate of the fifth thin film transistor and the third thin film transistor Connected to the gate, the second electrode of the fifth thin film transistor is connected to the low level input terminal, and the gate of the sixth thin film transistor is connected to the gate of the fifth thin film transistor, the sixth a first pole of the thin film transistor is connected to a gate of the fourth thin film transistor, a second pole of the sixth thin film transistor is connected to the low level input terminal, and a gate of the seventh thin film transistor is a second clock signal
  • the first pole of the eighth thin film transistor is connected to the first pole of the second thin film transistor, and the second pole of the eighth thin film transistor is Low level input Connected to the ninth electrode connected to said first thin film transistor and the signal output terminal of shift register means, a second thin film electrode of the ninth transistor and the low level input terminal
  • the first end of the storage capacitor is connected to the gate of the third thin film transistor, and the second end of the storage capacitor is connected to the signal output end of the shift register unit.
  • the shift register unit further includes a tenth thin film transistor, the first pole of the tenth thin film transistor is connected to the first pole of the ninth thin film transistor, and the second thin film transistor is The pole is connected to the second pole of the ninth thin film transistor, and the gate of the tenth thin film transistor is connected to the reset signal input end.
  • an array substrate including the above-described gate driving circuit provided by the present disclosure is provided.
  • a display device including the above array substrate provided by the present disclosure is provided.
  • a driving method of a gate driving circuit wherein the gate driving circuit is the gate driving circuit according to claim 1, the gate circuit driving method includes a plurality of driving The cycle, each drive cycle includes a display phase and a reset phase, the reset phase including a reset cell output phase, a reset cell output discharge phase, and a reset cell pull-up node discharge phase:
  • a high level signal is input to the first clock signal input end of the reset unit, so that the reset unit outputs high power to the reset end of the shift register unit of the reset unit Flat signal
  • the second clock signal input terminal inputs a high level signal to discharge the pull-up node of the reset unit.
  • the gate driving circuit includes an odd array clock signal line and an even array clock signal line
  • the odd array clock signal line includes a first odd clock signal line and a second odd clock signal line
  • the even array clock signal line includes the first An even clock signal line and a second even clock signal line
  • the plurality of stages of the shift register unit being divided into odd array shift register units corresponding to odd line gate lines and corresponding to even lines
  • the even array shift register unit of the gate line, the last stage shift register unit of the odd array shift register unit is used as the odd array reset unit, and the last stage shift register unit of the even array shift register unit is used as the even array reset.
  • an output of one of the previous stages is connected to an input of one of the latter stages
  • the output of the odd array reset unit is Corresponding to the reset end of the odd array shift register unit of the last row of odd row gate lines
  • the output end of the even array reset unit is connected to the reset end of the even array shift register unit corresponding to the last row of even row gate lines
  • a second odd clock signal line providing a reset signal for the odd array reset unit
  • the first even clock signal line providing a reset signal for the even array reset unit
  • the reset output stage includes:
  • An odd-array reset unit output stage inputting a high-level signal to a first clock signal input end of the odd-array reset unit to shift the odd-array reset unit to a register-level register unit of the odd-level reset unit
  • the reset terminal outputs a high level signal
  • Even array reset unit output stage inputting a high level signal to the first clock signal input end of the even array reset unit, so that the even array reset unit shifts the register unit to the upper stage of the even array reset unit
  • the reset terminal outputs a high level signal
  • the discharge phase of the output of the reset unit includes:
  • An odd-array reset unit output discharge stage in the discharge phase of the odd-array reset unit output terminal, inputting a low level to the first clock signal input end and the second clock signal input end of the odd-array reset unit Signaling to discharge the output of the odd-array reset unit;
  • Even array reset unit output discharge stage in the discharge stage of the even array reset unit output stage, inputting a low level to the first clock signal input end and the second clock signal input end of the even array reset unit Signaling to discharge the output of the even array reset unit;
  • the reset unit pull-up node discharge phase includes:
  • An odd array reset unit pull-up node discharge phase in the odd-array reset unit pull-up node discharge phase, a low-level signal is input to the first clock signal input end of the odd-array reset unit, and the even-array clock is utilized The signal line inputs a high level signal to the reset signal input end of the odd array reset unit to discharge the pull-up node of the odd-array reset unit;
  • Even array reset unit pull-up node discharge phase in the even-array reset unit pull-up node discharge phase, input a low-level signal to the first clock signal input end of the even-array reset unit, and And inputting a high level signal to the reset signal input end of the even array reset unit by using the odd array clock signal line to discharge the pull-up node of the even array reset unit.
  • the odd array reset unit output stage, the odd array reset unit output stage discharge stage, and the odd array reset unit pull up node discharge stage are continuous.
  • the even array reset unit output stage, the even array reset unit output stage discharge stage, and the even array reset unit pull up node discharge stage are continuous.
  • the shift register unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, and an eighth thin film transistor a ninth thin film transistor and a storage capacitor, a gate and a first pole of the first thin film transistor being connected to a signal input end of the shift register unit, a second pole of the first thin film transistor and the second a first pole of the thin film transistor is connected, a gate of the second thin film transistor is connected to a reset signal input end of the shift register unit, and a second pole of the second thin film transistor is connected to a low level input end.
  • a first pole of the third thin film transistor is connected to the first clock signal input end, a gate of the third thin film transistor is connected to a second pole of the first thin film transistor, and a second pole of the third thin film transistor Connected to an output of the shift register unit, a first pole of the fourth thin film transistor is connected to a second clock signal input terminal, and a second pole of the fourth thin film transistor a first pole of the fifth thin film transistor is connected, a gate of the fourth thin film transistor is connected to a second pole of the seventh thin film transistor, a gate of the fifth thin film transistor and the third thin film transistor Connected to the gate, the second electrode of the fifth thin film transistor is connected to the low level input terminal, and the gate of the sixth thin film transistor is connected to the gate of the fifth thin film transistor, the sixth a first pole of the thin film transistor is connected to a gate of the fourth thin film transistor, a second pole of the sixth thin film transistor is connected to the low level input terminal, and a gate of the seventh thin film transistor is a second clock signal
  • the first pole of the eighth thin film transistor is connected to the first pole of the second thin film transistor, and the second pole of the eighth thin film transistor is Low level input Connected, a first pole of the ninth thin film transistor is connected to a signal output end of the shift register unit, and a second pole of the ninth thin film transistor is connected to the low level input terminal, the storage capacitor The first end is connected to the gate of the third thin film transistor, and the storage battery The second end of the capacitor is connected to the signal output end of the shift register unit,
  • the driving method includes, during the same driving cycle:
  • a high-level signal is supplied to the first even-numbered clock signal line to the first odd-numbered clock signal line, the second odd-numbered clock signal line, and
  • the second even clock signal line provides a low level signal to pass through the odd array reset unit pull-up node discharge phase while passing through the output stage of the even array reset unit;
  • the odd-array reset unit pulls up the node discharge phase beam, to the first odd clock signal line, the first even clock signal line, the second odd clock signal line, and the second even clock signal
  • the line provides a low level signal to pass through the even array reset unit output discharge stage
  • the shift register unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, and an eighth thin film transistor a ninth thin film transistor, a tenth thin film transistor, and a storage capacitor, wherein a gate and a first pole of the first thin film transistor are connected to a signal input end of the shift register unit, and a second pole of the first thin film transistor Connected to the first pole of the second thin film transistor, the gate of the second thin film transistor is connected to the reset signal input end of the shift register unit, and the second pole and the low level of the second thin film transistor The input ends are connected, the first electrode of the third thin film transistor is connected to the first clock signal input end, and the gate of the third thin film transistor is connected to the second electrode of the first thin film transistor, the third film a second pole of the transistor is connected to an output end of the shift register unit, and a first pole of the fourth thin film
  • the driving method further includes, during the same driving period:
  • a high-level signal is supplied to the second odd-numbered clock signal line to the first odd-numbered clock signal a line, the first even clock signal line, and the second even clock signal line provide a low level signal such that the second thin film transistor and the tenth thin film transistor of the even array reset unit are turned on to
  • the even-array reset unit pull-up node pull-down phase and the even-array reset unit output pull-down phase are performed.
  • the pulse width of the reset phase clock signal is half of the width of the display phase pulse signal.
  • a clock signal input through a clock signal line supplies a reset signal to a shift register unit serving as a reset unit, thereby eliminating the need to add an additional reset unit or an additional thin film transistor in the gate drive circuit, thereby simplifying
  • the overall structure of the gate drive circuit facilitates the implementation of a narrow bezel design of a display device including the gate drive circuit.
  • FIG. 1 is a schematic diagram of a conventional gate driving circuit capable of realizing resetting
  • FIG. 2 is a schematic diagram of another conventional gate driving circuit capable of implementing resetting
  • FIG. 3 is a schematic diagram of a gate driving circuit provided by the present disclosure.
  • FIG. 4 is a circuit diagram of an embodiment of a shift register unit in the gate drive circuit shown in FIG. 3;
  • FIG. 5 is a timing chart when the gate driving circuit provided by the present disclosure includes the shift register unit shown in FIG. 4;
  • FIG. 6 is another embodiment of a shift register unit in the gate drive circuit shown in FIG. Circuit diagram
  • FIG. 7 is a timing chart when the gate driving circuit provided by the present disclosure includes the shift register unit shown in FIG. 6.
  • a gate driving circuit including at least one set of clock signal lines and cascaded multi-stage shift register units (shown in FIG. 3)
  • each set of clock signal lines includes two of said clock signal lines, and said plurality of shift register units are divided into at least one set of shift register units, and each The group of clock signal lines corresponds to a group of the shift register units, wherein a clock signal line of each group of clock signal lines and a last shift of a group of shift register units corresponding to the group of clock signal lines are shifted
  • the reset signal input of the register unit is connected to provide a reset signal to the start of the reset phase.
  • the clock signal generating circuit that supplies the clock signal is located outside the display panel, and thus does not affect the narrow bezel design of the display device including the gate driving circuit.
  • the number of groups of shift register units is the same as the number of groups of clock signal lines.
  • the gate driving circuit provided by the present disclosure is configured to include n sets of clock signal lines, the gate driving circuit also includes n sets of shift register units, and the last stage shift register unit in each set of shift register units is used as A reset unit of the group of shift register units.
  • a clock signal input through a clock signal line supplies a reset signal to a shift register unit serving as a reset unit, thereby eliminating the need to add an additional reset unit or an additional thin film transistor in the gate drive circuit, thereby simplifying
  • the overall structure of the gate drive circuit facilitates the implementation of a narrow bezel design of a display device including the gate drive circuit.
  • a gate driving circuit for a display panel includes an even-numbered shift register unit.
  • the gate driving circuit includes an odd-array clock signal line and an even-array clock signal line, and two sets of clock signal lines, and the odd-array clock signal line includes a first odd-numbered clock signal line CLK1.
  • the even-array clock signal line includes a first even-numbered clock signal line CLK2 and a second even-numbered clock signal line CLK4, and the multi-stage shift register unit is divided into odd numbers corresponding to the odd-array gate lines a group shift register unit and an even array shift register unit corresponding to an even row gate line, and a last stage shift register unit of the odd array shift register unit is used as an odd array reset unit, and the last one of the even array shift register unit
  • the stage shift register unit is used as an even array reset unit, the first even clock signal line CLK2 is connected to the reset signal input end of the odd array reset unit, and the second odd clock signal line CLK3 and the reset signal of the even array reset unit The inputs are connected.
  • an output end of the odd array reset unit is connected to an input end of the even array reset unit.
  • the output of the odd array reset unit is also connected to the shift register unit corresponding to the last row of odd row gate lines
  • the reset terminals are connected, and the output terminal of the even array reset unit is connected to the reset terminal of the shift register unit corresponding to the last row of even-numbered gate lines.
  • the first stage shift register unit 100_1, the second stage shift register unit 100_2, the third stage shift register unit 100_3, ... the Nth stage shift register unit 100_N, the Nth are shown in FIG.
  • N is an even number.
  • the second odd-numbered clock signal line CLK3 is connected to the reset terminal RESET of the shift register unit 100_N+2 as the even-array reset unit in the even-array shift register unit, and is supplied with a reset signal;
  • the first even-numbered clock signal line CLK2 It is connected to the reset terminal RESET of the shift register unit 100_N+1 which is an odd-array reset unit in the odd-array shift register unit, and is supplied with a reset signal.
  • the specific structure of the shift register unit is not limited.
  • the shift register unit may have a 9T1C structure, specifically, The shift register unit includes a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3, a fourth thin film transistor M4, a fifth thin film transistor M5, a sixth thin film transistor M6, a seventh thin film transistor M7, and an eighth The thin film transistor M8, the ninth thin film transistor M9, and the storage capacitor C.
  • the gate and the first electrode of the first thin film transistor M1 are connected to the signal input terminal IN of the shift register unit, and the second electrode of the first thin film transistor M1 is connected to the first electrode of the second thin film transistor M2.
  • the gate of the second thin film transistor M2 is connected to the reset signal input terminal RESET of the shift register unit, and the second electrode of the second thin film transistor M2 is connected to the low level input terminal VGL.
  • a first pole of the third thin film transistor M3 is connected to the first clock signal input end, a gate of the third thin film transistor M3 is connected to a second pole of the first thin film transistor M1, and a second pole of the third thin film transistor M3 is The output terminal OUTPUT of the shift register unit is connected.
  • the first electrode of the fourth thin film transistor M4 is connected to the second clock signal input terminal, the second electrode of the fourth thin film transistor M4 is connected to the first electrode of the fifth thin film transistor M5, and the gate and the seventh of the fourth thin film transistor M4 are connected.
  • the second electrode of the thin film transistor M7 is connected, the gate of the fifth thin film transistor M5 is connected to the gate of the third thin film transistor M3, and the second electrode of the fifth thin film transistor M5 is connected to the low level input terminal VGL, and the sixth thin film transistor M6 grid
  • the pole is connected to the gate of the fifth thin film transistor M5, the first pole of the sixth thin film transistor M6 is connected to the gate of the fourth thin film transistor M4, and the second pole of the sixth thin film transistor M6 is connected to the low level input terminal VGL.
  • the gate of the seventh thin film transistor M7 is connected to the second clock signal input terminal, and the first electrode of the seventh thin film transistor M7 is connected to the gate of the seventh thin film transistor M7.
  • the gate of the eighth thin film transistor M8 is connected to the gate of the ninth thin film transistor M9, and is connected to the first electrode of the fifth thin film transistor M5, and the first electrode of the eighth thin film transistor M8 and the first of the second thin film transistor M2
  • the poles are connected, and the second pole of the eighth thin film transistor M8 is connected to the low level input terminal VGL.
  • a first electrode of the ninth thin film transistor M9 is connected to a signal output terminal OUTPUT of the shift register unit, and a second electrode of the ninth thin film transistor M9 is connected to a low level input terminal VGL, and a gate of the ninth thin film transistor Connected to the gate of the eighth thin film transistor.
  • the first end of the storage capacitor C is connected to the gate of the third thin film transistor M3, and the second end of the storage capacitor C is connected to the signal output terminal OUTPUT of the shift register unit.
  • the first end of the storage capacitor C is formed as a pull-up node PU, the second electrode of the first thin film transistor M1, the gate of the third thin film transistor M3, and the fifth
  • the gate of the thin film transistor M5 and the gate of the sixth thin film transistor M6 are both connected to the pull-up node PU.
  • the first electrode of the fifth thin film transistor M5 is formed as a pull-down node PD, and the second electrode of the fourth thin film transistor M4, the gate of the eighth thin film transistor M8, and the gate of the ninth thin film transistor M9 are both connected to the pull-down node PD.
  • the gate of the fourth thin film transistor M4 is formed as a pull-down control node PD, and the first poles of the second and sixth thin film transistors M6 of the seventh thin film transistor M7 are connected to the pull-down control node PD.
  • first clock signal input end is connected to the first odd clock signal line CLK1 or the first even clock signal line CLK2, and the second clock signal input end and the second odd clock signal line CLK3 or the second even clock signal line. CLK4 is connected.
  • the shift register unit shown in FIG. 4 includes only 9 thin film transistors and one storage capacitor, and therefore takes up less space.
  • FIG. 5 Shown in FIG. 5 is a timing chart of a gate driving circuit including the shift register unit shown in FIG. This will be described in detail below, and will not be described here.
  • Shown in Fig. 6 is a shift register unit having a 10T1C structure.
  • the shift register unit shown in FIG. 6 further includes a tenth thin film transistor M10, as compared with the shift register unit shown in FIG.
  • the first pole of the tenth thin film transistor M10 is connected to the first pole of the ninth thin film transistor M9
  • the second pole of the tenth thin film transistor M10 is connected to the second pole of the ninth thin film transistor M9
  • the gate of the tenth thin film transistor M10 The pole is connected to the reset signal input terminal RESET. After the tenth thin film transistor M10 is added, the discharge speed of the output terminal OUTPUT of the shift register unit can be increased.
  • an array substrate including a gate driving circuit, wherein the gate driving circuit is the above-described gate driving circuit provided by the present disclosure.
  • the gate driving circuit provided by the present disclosure, there is no need to additionally add a component for resetting the last-stage shift register unit. Therefore, the gate driving circuit has a simple structure and is easy to implement the narrow array substrate. Border design.
  • a display device including an array substrate, wherein the array substrate is the above array substrate provided by the present disclosure.
  • the display device Since the array substrate easily realizes a narrow bezel design, the display device also has a narrow bezel.
  • a gate circuit driving method for driving a gate driving circuit including a plurality of driving periods, each of which includes a display phase And a reset phase, the reset phase includes a reset unit output phase, a reset cell output discharge phase, and a reset cell pull-up node discharge phase:
  • a high level signal is input to the first clock signal input end of the reset unit, so that the reset unit outputs high power to the reset end of the shift register unit of the reset unit Flat signal
  • the second clock signal input terminal inputs a high level signal to discharge the pull-up node of the reset unit.
  • other shift register units other than the shift register unit serving as the reset unit output scan signals to the gate lines in the array substrate for displaying an image.
  • a reset signal is supplied to the shift register unit serving as the reset unit by the clock signal line to reset the reset unit, and the signal outputted from the output terminal of the reset unit is provided to the shift register unit of the upper stage of the reset unit. Reset the signal to reset.
  • the reset unit output terminal is spaced apart from the reset unit discharge phase by a predetermined time.
  • the shift register unit of the upper stage of the reset unit is a shift register unit connected to the corresponding gate line for supplying a scan signal to the gate line.
  • each shift register unit serving as a reset unit has been pulled up to the high level before entering the reset phase.
  • the structure of each shift register unit serving as a reset unit is the same as that of other shift register units, and thus the reset unit also includes an output module, which typically includes a thin film transistor and a storage capacitor.
  • the gate of the thin film transistor in the output module is connected to the pull-up node, and the first pole of the thin film transistor of the output module is connected to the first clock signal input end, and the second pole of the thin film transistor of the output module and the output of the shift register unit of the current stage
  • the terminals are connected, the first end of the storage capacitor is connected to the pull-up node, and the second end of the storage capacitor is connected to the output end of the shift register unit of the current stage.
  • the pull-up node of the reset unit is at a high level. Therefore, the thin film transistor of the output module is turned on.
  • the first clock signal input terminal is connected to the high level
  • the output of the reset unit is high.
  • Level signal output The reset output outputs a high level signal to the reset terminal of the shift register unit of the previous stage, thereby resetting the shift register unit of the previous stage.
  • a low level signal is input to the first clock signal input end of the reset unit, and since the pull-up node of the reset unit still maintains a high level, the reset unit can utilize the output module The thin film transistor is discharged.
  • the input terminal of the reset unit inputs a high-level signal, so that the pull-up node potential of the reset unit can be pulled low by the reset module inside the reset unit. How the reset module discharges the pull-up node is well known in the art and will not be described again here.
  • the reset signal is supplied to the shift register unit serving as the reset unit through the clock signal line, it is not necessary to add other components, which is advantageous in simplifying the structure of the gate drive circuit.
  • the display panel includes an even number of gate lines, and therefore, the gate driving circuit includes an even-numbered shift register unit.
  • the gate driving circuit includes an odd array clock signal line and an even array clock signal line
  • the odd array clock signal line includes the An odd-numbered clock signal line and a second odd-numbered clock signal line
  • the even-array clock signal line includes a first even-numbered clock signal line and a second even-numbered clock signal line
  • the plurality of stages of the shift register unit are divided into corresponding odd-numbered gate lines
  • the last stage shift register unit is used as an even array reset unit.
  • the first even clock signal line provides a reset signal for the odd array reset unit
  • the second odd clock signal line provides a reset signal for the even array reset unit.
  • an output end of the odd array reset unit is connected to an input end of the even array reset unit.
  • the reset output stage includes:
  • An odd-array reset unit output stage inputting a high-level signal to a first clock signal input end of the odd-array reset unit to shift the odd-array reset unit to a register-level register unit of the odd-level reset unit
  • the reset terminal outputs a high level signal
  • Even array reset unit output stage inputting a high level signal to the first clock signal input end of the even array reset unit, so that the even array reset unit shifts the register unit to the upper stage of the even array reset unit
  • the reset terminal outputs a high level signal.
  • the upper shift register unit of the odd array reset unit refers to the shift register unit connected to the last row of odd gate lines
  • the shift register unit of the even array reset unit refers to A shift register unit connected to the last row of even-numbered gate lines.
  • the discharge phase of the output of the reset unit includes:
  • An odd-array reset unit output terminal discharge phase in the discharge phase of the odd-array reset unit output terminal, a low-level signal is input to the first clock signal input end and the second clock signal input end of the odd-array reset unit, Discharging the output of the odd-array reset unit;
  • Even array reset unit output discharge stage in the discharge stage of the even array reset unit output stage, inputting a low level signal to the first clock signal input end and the second clock signal input end of the even array reset unit, Discharging the output of the even array reset unit;
  • the even array reset unit pull-up node discharge phase includes:
  • An odd array reset unit pull-up node discharge phase in the odd-array reset unit pull-up node discharge phase, a low-level signal is input to the first clock signal input end of the odd-array reset unit, and an even-array clock signal line is utilized Inputting high power to the reset signal input terminal of the odd array reset unit Flat signal to discharge the pull-up node of the odd-array reset unit;
  • Even array reset unit pull-up node discharge phase in the even-array reset unit pull-up node discharge phase, input a low-level signal to the first clock signal input end of the even-array reset unit, and use an odd-array clock signal line And inputting a high level signal to the reset signal input end of the even array reset unit to discharge the pull-up node of the even array reset unit.
  • the odd array reset unit and the even array reset unit are respectively reset. It should be understood that the odd array reset unit output stage, the odd array reset unit output discharge stage, and the odd array reset unit pull up node discharge stage are continuous. Similarly, the even array reset unit output stage, the even array reset unit output stage discharge stage, and the even array reset unit pull up node discharge stage are continuous.
  • the odd array reset unit If the odd array reset unit is the upper stage of the even array reset unit, then the odd array reset unit pull-up node discharge phase ends after the even array reset unit output stage, the even array reset unit output discharge stage, and the even array reset unit. Pull the node discharge phase. Conversely, if the even array reset unit is the upper stage of the odd array reset unit, then the even array reset unit pulls up the node after the discharge phase ends, after the odd array reset unit output stage, the odd array reset unit output discharge stage, and the odd array reset. The unit pulls up the node discharge phase.
  • FIG. 5 Shown in FIG. 5 is a timing chart for driving a gate driving circuit including the shift register unit shown in FIG.
  • each phase before phase S1, phase S2, and phase S1 is a display phase
  • phase S3 to phase S7 are reset phases
  • the reset phase is from The display phase begins at the end of the display phase.
  • the driving method includes, during the same driving cycle:
  • a high-level signal is supplied to the first even-numbered clock signal line to the first odd-numbered clock signal line, the second odd-numbered clock signal line, and
  • the second even clock signal line provides a low level signal to pass through the odd array reset unit pull-up node discharge phase while passing through the output stage of the even array reset unit;
  • the odd-array reset unit pulls up the node discharge phase beam, to the first odd clock signal line, the first even clock signal line, the second odd clock signal line, and the second even clock signal
  • the line provides a high and low level signal to pass through the discharge stage of the output of the even array reset unit
  • N is an even number
  • the shift register includes an even number of shift register units
  • the shift register unit 100_N+1 shown in Fig. 3 is an odd array.
  • a reset unit for resetting the shift register unit of the odd array ie, the N-1th shift register unit
  • the shift register unit 100_N+2 is an even array reset unit for shifting the even array
  • the register unit i.e., the Nth stage shift register unit
  • the output terminal Output N-1 of the N-1th shift register unit outputs a scan signal to the N-1th scan line, and the scan signal of the N-1th scan line is also used as the odd array reset unit.
  • the output terminal Output N of the Nth stage shift register unit outputs a scan signal to the Nth row scan line, and the scan signal of the Nth row scan line is also used as the input of the shift register unit 100_N+2 of the reset unit.
  • the signal therefore, the pull-up node 100_N+2PU of the shift register unit 100_N+2 starts charging, at which time the shift register unit 100_N+1 is charged and remains high.
  • the stage S3 is an odd-array reset unit output stage, and in the S3 stage, the first odd-numbered clock signal corresponding to the shift register unit 100_N+1 (provided by the first odd-numbered clock signal line CLK1) becomes a high level, and thus the shift register unit 100_N+1 starts outputting, and the pull-up node of the shift register unit of the (N-1)th row is reset.
  • Stage S4 is an output stage of the odd-array reset unit output stage.
  • the first odd-numbered clock signal (provided by the first odd-numbered clock signal line CLK1) becomes a low level, but the N-1th line shifts.
  • the pull-up node of the register unit remains high, and the output of the shift register unit 100_N+1 is discharged through the third thin film transistor M3 and pulled down to a low level.
  • the third thin film transistor M3 is the thin film transistor of the output module described above.
  • the stage S5 is an odd-array reset unit pull-up node discharge phase, and at the same time, the stage S5 is an odd-array reset unit output stage.
  • the first even-numbered clock signal CLK2 corresponding to the shift register unit 100_N+1 becomes a high level. Therefore, the output terminal Output N+1 of the shift register unit 100_N+1 starts to be output, and the pull-up node PU of the N-th stage shift register unit 100_N is reset.
  • the N-1th shift register unit and the Nth stage The shift register unit 100_N is smoothly reset.
  • the first even clock signal CLK2 resets the pull-up node PU point of the shift register unit 100_N+1 to a low level.
  • Stage S6 is an output stage of the even array reset unit output stage.
  • the first even clock signal (provided by the first even clock signal line CLK2) becomes a low level, but the pull-up node of the shift register unit 100_N+2
  • the PU remains at a high level, and the output terminal of the shift register unit 100_N+2 is discharged to a low level by the third thin film transistor M3.
  • Stage S7 is an even array reset unit pull-up node discharge phase, and in stage S7, the second odd clock signal (provided by the second odd-numbered clock signal line CLK3) becomes a high level, and the pull-up register unit 100_N+2 is pulled up.
  • the node PU is reset to a low level. At this point, each shift register unit is normally reset, and one frame ends.
  • the driving method further includes, during the same driving period:
  • the reset phase includes:
  • the pull-up node of the even-array reset unit After charging the pull-up node of the even-array reset unit, providing a high-level signal to the first even-numbered clock signal line, to the first odd-numbered clock signal line, the second odd-numbered clock signal line, and The second even clock signal line provides a low level signal, such that the second thin film transistor and the tenth thin film transistor of the odd array reset unit are turned on to simultaneously pass through the odd array reset unit pull-up node a pull-down phase and a pull-down phase of the odd-array reset unit output;
  • a high-level signal is supplied to the second odd-numbered clock signal line to the first odd-numbered clock signal a line, the first even clock signal line, and the second even clock signal line provide a low level signal such that the second thin film transistor and the tenth thin film transistor of the even array reset unit are turned on to
  • the even-array reset unit pull-up node pull-down phase and the even-array reset unit output pull-down phase are performed.
  • N is an even number, that is, the shift register includes an even number of shift register units
  • the shift register unit 100_N+1 shown in FIG. 3 is an odd array reset unit for The shift register unit of the odd array is reset
  • the shift register unit 100_N+2 is an even array reset unit for resetting the shift register unit of the even array in the same display period:
  • the S1 phase from the half pulse time before the end of the display phase is the pull-up node charging phase of the odd-array reset unit, and in the S1 phase, the first odd-numbered clock signal line CLK1 outputs a low-level signal, and the second odd-numbered clock signal
  • the line CLK3 and the second even clock signal line CLK4 output a high level signal
  • the output terminal Output N of the Nth stage shift register unit 100_N is an input signal of the shift register unit 100_N+1 serving as a reset unit, Therefore, the pull-up node 100_N+1PU of the shift register unit 100_N+1 starts charging;
  • the S2 phase after the end of the S1 phase is an odd-array reset cell output phase and a pull-up node charging phase of the even-array reset cell.
  • the first odd-numbered clock signal line CLK1 outputs a high-level signal
  • the first even-numbered clock signal line CLK2 the second odd clock signal line CLK3 and the second even number
  • the clock signal line CLK4 outputs a low level signal
  • the output terminal Reset output 1 of the shift register unit 100_N+1 serving as the reset unit starts to output a high level, and therefore, the N-1th shift register unit is normally reset, and at the same time
  • the high-level signal outputted by the shift register unit 100_N+1 serving as the reset unit is also an input signal of the shift register unit 100_N+2 serving as the reset unit, and thus the pull-up node 100_N+ of the shift register unit 100_N+2 2PU starts charging;
  • the S3 stage is an even array reset unit output stage, an odd array reset unit output pull-down stage, and an odd array reset unit pull-up node pull-down stage.
  • the first even clock signal line CLK2 outputs a high level signal
  • the first odd clock signal The line CLK1, the second odd-numbered clock signal line CLK3, and the second even-numbered clock signal line CLK4 simultaneously output a low-level signal
  • the output terminal Reset output2 of the shift register unit 100_N+2 serving as the reset unit starts to output a high level, therefore,
  • the output terminal of the Nth stage shift register unit 100_N is normally reset, since the first even clock signal line CLK2 is connected to the reset terminal of the shift register unit 100_N+1 serving as the reset unit, the second thin film transistor M2 and the tenth thin film The transistor M10 is turned on.
  • the pull-up node 100_N+1PU and the output terminal of the shift register unit 100_N+1 serving as the reset unit are simultaneously pulled down to the low level VGL, so that the shift register unit 100_N+1 serving as the reset unit is used. Is reset normally;
  • the S4 phase is a pull-up node discharge phase of the even-array reset unit and an output discharge phase of the even-array reset cell
  • the second odd-numbered clock signal line CLK3 outputs a high-level signal in the S4 phase
  • the first odd-numbered clock signal line CLK1 the first The even clock signal line CLK2 and the second even clock signal line CLK4 output a low level signal
  • the second odd clock signal line CLK3 is connected to the reset terminal of the shift register unit 100_N+2 serving as the reset unit
  • the second film The transistor M2 and the tenth thin film transistor M10 are turned on, and thus the pull-up node 100_N+2PU and the output terminal of the shift register unit 100_N+2 serving as the reset unit are simultaneously pulled down to the low level VGL, so that the shift function is used as the reset unit.
  • the bit register unit 100_N+2 is normally reset. At this point, each shift register unit is normally reset, and one frame ends.
  • the pulse width of the reset phase clock signal is half of the width of the display phase pulse signal. Since the reset unit does not need to consider charging the pixel, it is only necessary to consider resetting the pull-up node of the previous shift register unit, so it is completely feasible to set the output width to be halved.
  • 100_3 third-stage shift register unit 100_N: N-th shift register unit
  • M1 first thin film transistor
  • M2 second thin film transistor
  • M3 third thin film transistor
  • M4 fourth thin film transistor

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Abstract

一种栅极驱动电路、阵列基板、显示装置和该栅极驱动电路的驱动方法，该栅极驱动电路包括至少一组时钟信号线和级联的多级移位寄存单元（100_1、100_2…100_N+2），每组时钟信号线包括两条时钟信号线，多级所述移位寄存单元（100_1、100_2…100_N+2）被划分为至少一组，并且每组时钟信号线对应一组所述移位寄存单元，每组时钟信号线中的一条时钟信号线连接到与该组时钟信号线对应的一组移位寄存单元中的最后一级移位寄存单元的复位信号输入端（RESET）。

Description

栅极驱动电路及其驱动方法、阵列基板、显示装置
相关申请的交叉引用
本申请主张在2015年2月12日在中国提交的中国专利申请号No.201510075641.8的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示装置领域，并且具体地涉及一种栅极驱动电路、该栅极驱动电路的驱动方法、包括所述栅极驱动电路的阵列基板和显示装置。
背景技术
栅极驱动电路实现的是移位寄存功能，栅极驱动电路包括多组移位寄存单元，对于每组移位寄存单元中连续的三个移位寄存单元而言，第二个移位寄存单元用于对第三个移位寄存单元进行输入，并且用于对第一个移位寄存单元进行复位，以实现顺序输出的功能。因此，第一个移位寄存单元需要增加额外的开始信号STV，来进行每一帧的初始输入，而最后一个移位寄存单元也需要进行额外的复位控制，来实现正常的关闭。
图1和图2为目前常用的栅极驱动电路级联原理图(以4个时钟信号CLK1、CLK2、CLK3、CLK4为例)。在图1和图2中，输出信号栅极输出(Gate output)N对应的移位寄存单元11为最后一行像素提供扫描信号输出。为了保证各行扫描信号输出的一致，会使用正常额外一组普通的移位寄存单元对最后一个用于输出扫描信号的移位寄存单元进行复位，如图中的输出信号复位输出(Reset output)1和输出信号Reset output 2对应的移位寄存单元。
而为了保证第一个用于复位的移位寄存单元输出的正常关闭，需要对其进行复位操作，如图1的方法，是使用额外两个具备自复位功能的移位寄存单元对与输出信号Reset output1对应的移位寄存单元和与输出信号Reset output 2对应的移位寄存单元进行复位。具体地，如图1中所示，一个具有自复位功能的移位寄存单元输出的Reset Output 3用于对输出的Reset output 1的复位单元进行复位，而另一个具有自复位功能的移位寄存单元输出的Reset  Output 4用于对输出的Reset output 2的复位单元进行复位。具有自复位功能的移位寄存单元需要增加额外的TFT器件，这样会增加栅极驱动电路占用的空间，不利于窄边框设计，还可能影响画面品质。
在如图2所述的方法中，是从驱动IC直接输入复位信号(即，增加复位信号线RST)的，对与输出信号Reset output 1对应的移位寄存单元和与输出信号Reset output 2对应的移位寄存单元进行复位。这样同样会增加边框宽度和IC成本。
如何在不增加边框宽度的前提下实现对栅极驱动电路中的移位寄存单元的复位成为本领域亟待解决的技术问题。
发明内容
本公开的一个目的在于提供一种栅极驱动电路、该栅极驱动电路的驱动方法包括所述栅极驱动电路的阵列基板和包括所述阵列基板的显示装置，所述栅极驱动电路能够在不增加元件的情况下实现对最后一级移位寄存单元的复位。
为了实现上述目的，作为本公开的一个方面，提供一种栅极驱动电路，所述栅极驱动电路包括至少一组时钟信号线和级联的多级移位寄存单元，所述至少一组时钟信号线中的每组时钟信号线包括两条所述时钟信号线，多级所述移位寄存单元被划分为至少一组，并且所述每组所述时钟信号线对应一组所述移位寄存单元，其中，所述每组时钟信号线中的一条时钟信号线连接到与该组时钟信号线对应的一组移位寄存单元中的最后一级移位寄存单元的复位信号输入端，以在复位阶段开始时向一组移位寄存单元中的最后一级移位寄存单元的复位信号输入端提供复位信号。
可选地，所述栅极驱动电路包括偶数级移位寄存单元，所述栅极驱动电路包括奇数组时钟信号线和偶数组时钟信号线，奇数组时钟信号线包括第一奇数时钟信号线和第二奇数时钟信号线，偶数组时钟信号线包括第一偶数时钟信号线和第二偶数时钟信号线，多级所述移位寄存单元被划分为对应于奇数行栅线的奇数组移位寄存单元和对应于偶数行栅线的偶数组移位寄存单元，奇数组移位寄存单元的最后一级移位寄存单元用作奇数组复位单元，偶 数组移位寄存单元的最后一级移位寄存单元用作偶数组复位单元，第一偶数时钟信号线与所述奇数组复位单元的复位信号输入端相连，第二奇数时钟信号线与所述偶数组复位单元的复位信号输入端相连，所述奇数组复位单元的输出端与所述偶数组复位单元的输入端相连，所述奇数组复位单元的输出端与对应于最后一行奇数行栅线的奇数组移位寄存单元的复位端相连，所述偶数组复位单元的输出端与对应于最后一行偶数行栅线的偶数组移位寄存单元的复位端相连。
可选地，所述移位寄存单元包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管和存储电容，所述第一薄膜晶体管的栅极和第一极与所述移位寄存单元的信号输入端相连，所述第一薄膜晶体管的第二极与所述第二薄膜晶体管的第一极相连，所述第二薄膜晶体管的栅极与所述移位寄存单元的复位信号输入端相连，所述第二薄膜晶体管的第二极与低电平输入端相连，所述第三薄膜晶体管的第一极与第一时钟信号输入端相连，所述第三薄膜晶体管的栅极与所述第一薄膜晶体管的第二极相连，所述第三薄膜晶体管的第二极与所述移位寄存单元的输出端相连，所述第四薄膜晶体管的第一极与第二时钟信号输入端相连，所述第四薄膜晶体管的第二极与所述第五薄膜晶体管的第一极相连，所述第四薄膜晶体管的栅极与所述第七薄膜晶体管的第二极相连，所述第五薄膜晶体管的栅极与所述第三薄膜晶体管的栅极相连，所述第五薄膜晶体管的第二极与所述低电平输入端相连，所述第六薄膜晶体管的栅极与所述第五薄膜晶体管的栅极相连，所述第六薄膜晶体管的第一极与所述第四薄膜晶体管的栅极相连，所述第六薄膜晶体管的第二极与所述低电平输入端相连，所述第七薄膜晶体管的栅极与所述第二时钟信号输入端相连，所述第七薄膜晶体管的第一极与该第七薄膜晶体管的栅极相连，所述第八薄膜晶体管的栅极与所述第九薄膜晶体管的栅极相连，且与所述第五薄膜晶体管的第一极相连，所述第八薄膜晶体管的第一极与所述第二薄膜晶体管的第一极相连，所述第八薄膜晶体管的第二极与所述低电平输入端相连，所述第九薄膜晶体管的第一极与所述移位寄存单元的信号输出端相连，所述第九薄膜晶体管的第二极与所述低电平输入端相 连，所述存储电容的第一端与所述第三薄膜晶体管的栅极相连，所述存储电容的第二端与所述移位寄存单元的信号输出端相连。
可选地，所述移位寄存单元包括还包括第十薄膜晶体管，所述第十薄膜晶体管的第一极与所述第九薄膜晶体管的第一极相连，所述第十薄膜晶体管的第二极与所述第九薄膜晶体管的第二极相连，所述第十薄膜晶体管的栅极与所述复位信号输入端相连。
作为本公开的另一个方面，提供一种阵列基板，包括本公开所提供的上述栅极驱动电路。
作为本公开的还一个方面，提供一种显示装置，包括本公开所提供的上述阵列基板。
作为本公开的又一个方面，提供一种栅极驱动电路的驱动方法，其中，所述栅极驱动电路为权利要求1所述的栅极驱动电路，所述栅极电路驱动方法包括多个驱动周期，每个驱动周期都包括显示阶段和复位阶段，所述复位阶段包括复位单元输出阶段、复位单元输出端放电阶段和复位单元上拉节点放电阶段：
在所述复位单元输出阶段，向所述复位单元的第一时钟信号输入端输入高电平信号，以使所述复位单元向该复位单元的上一级移位寄存单元的复位端输出高电平信号；
在所述复位单元输出端放电阶段，向所述复位单元的所述第一时钟信号输入端和第二时钟信号输入端输入低电平信号，以对所述复位单元的输出端进行放电；
在所述复位单元上拉节点放电阶段，向所述复位单元的第一时钟信号输入端输入低电平信号，并且利用时钟信号线向所述复位单元的复位信号输入端和所述复位单元的第二时钟信号输入端输入高电平信号，以对所述复位单元的上拉节点进行放电。
可选地，所述栅极驱动电路包括奇数组时钟信号线和偶数组时钟信号线，奇数组时钟信号线包括第一奇数时钟信号线和第二奇数时钟信号线，偶数组时钟信号线包括第一偶数时钟信号线和第二偶数时钟信号线，多级所述移位寄存单元被划分为对应于奇数行栅线的奇数组移位寄存单元和对应于偶数行 栅线的偶数组移位寄存单元，奇数组移位寄存单元的最后一级移位寄存单元用作奇数组复位单元，偶数组移位寄存单元的最后一级移位寄存单元用作偶数组复位单元，在所述奇数组复位单元与所述偶数组复位单元中，位于前级的一者的输出端与位于后一级的一者的输入端相连，所述奇数组复位单元的输出端与对应于最后一行奇数行栅线的奇数组移位寄存单元的复位端相连，所述偶数组复位单元的输出端与对应于最后一行偶数行栅线的偶数组移位寄存单元的复位端相连，第二奇数时钟信号线为所述奇数组复位单元提供复位信号，第一偶数时钟信号线为所述偶数组复位单元提供复位信号，
所述复位输出阶段包括：
奇数组复位单元输出阶段：向所述奇数组复位单元的第一时钟信号输入端输入高电平信号，以使所述奇数组复位单元向该奇数组复位单元的上一级移位寄存单元的复位端输出高电平信号；和
偶数组复位单元输出阶段：向所述偶数组复位单元的第一时钟信号输入端输入高电平信号，以使所述偶数组复位单元向该偶数组复位单元的上一级移位寄存单元的复位端输出高电平信号；
所述复位单元输出端放电阶段包括：
奇数组复位单元输出端放电阶段：在所述奇数组复位单元输出端放电阶段，向所述奇数组复位单元的所述第一时钟信号输入端和所述第二时钟信号输入端输入低电平信号，以对所述奇数组复位单元的输出端进行放电；和
偶数组复位单元输出端放电阶段：在所述偶数组复位单元输出端放电阶段，向所述偶数组复位单元的所述第一时钟信号输入端和所述第二时钟信号输入端输入低电平信号，以对所述偶数组复位单元的输出端进行放电；
所述复位单元上拉节点放电阶段包括：
奇数组复位单元上拉节点放电阶段：在所述奇数组复位单元上拉节点放电阶段，向所述奇数组复位单元的第一时钟信号输入端输入低电平信号，并且利用所述偶数组时钟信号线向所述奇数组复位单元的复位信号输入端输入高电平信号，以对所述奇数组复位单元的上拉节点进行放电；
偶数组复位单元上拉节点放电阶段：在所述偶数组复位单元上拉节点放电阶段，向所述偶数组复位单元的第一时钟信号输入端输入低电平信号，并 且利用所述奇数组时钟信号线向所述偶数组复位单元的复位信号输入端输入高电平信号，以对所述偶数组复位单元的上拉节点进行放电。
可选地，所述奇数组复位单元输出阶段、奇数组复位单元输出端放电阶段和奇数组复位单元上拉节点放电阶段是连续的。
可选地，所述偶数组复位单元输出阶段、偶数组复位单元输出端放电阶段和偶数组复位单元上拉节点放电阶段是连续的。
可选地，所述移位寄存单元包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管和存储电容，所述第一薄膜晶体管的栅极和第一极与所述移位寄存单元的信号输入端相连，所述第一薄膜晶体管的第二极与所述第二薄膜晶体管的第一极相连，所述第二薄膜晶体管的栅极与所述移位寄存单元的复位信号输入端相连，所述第二薄膜晶体管的第二极与低电平输入端相连，所述第三薄膜晶体管的第一极与第一时钟信号输入端相连，所述第三薄膜晶体管的栅极与所述第一薄膜晶体管的第二极相连，所述第三薄膜晶体管的第二极与所述移位寄存单元的输出端相连，所述第四薄膜晶体管的第一极与第二时钟信号输入端相连，所述第四薄膜晶体管的第二极与所述第五薄膜晶体管的第一极相连，所述第四薄膜晶体管的栅极与所述第七薄膜晶体管的第二极相连，所述第五薄膜晶体管的栅极与所述第三薄膜晶体管的栅极相连，所述第五薄膜晶体管的第二极与所述低电平输入端相连，所述第六薄膜晶体管的栅极与所述第五薄膜晶体管的栅极相连，所述第六薄膜晶体管的第一极与所述第四薄膜晶体管的栅极相连，所述第六薄膜晶体管的第二极与所述低电平输入端相连，所述第七薄膜晶体管的栅极与所述第二时钟信号输入端相连，所述第七薄膜晶体管的第一极与该第七薄膜晶体管的栅极相连，所述第八薄膜晶体管的栅极与所述第九薄膜晶体管的栅极相连，且与所述第五薄膜晶体管的第一极相连，所述第八薄膜晶体管的第一极与所述第二薄膜晶体管的第一极相连，所述第八薄膜晶体管的第二极与所述低电平输入端相连，所述第九薄膜晶体管的第一极与所述移位寄存单元的信号输出端相连，所述第九薄膜晶体管的第二极与所述低电平输入端相连，所述存储电容的第一端与所述第三薄膜晶体管的栅极相连，所述存储电 容的第二端与所述移位寄存单元的信号输出端相连，
所述驱动方法包括，在同一个驱动周期内：
所述显示周期结束后，向所述第一奇数时钟信号线提供高电平信号，向所述第一偶数时钟信号线、所述第二奇数时钟信号线以及所述第二偶数时钟信号线提供低电平信号，以经过所述奇数组复位单元输出阶段；
在所述奇数组复位单元输出阶段结束后，向所述第一奇数时钟信号线、第一偶数时钟信号线、第二奇数时钟信号线和所述第二偶数时钟信号线提供低电平信号，以经过所述奇数组复位单元输出端放电阶段；
在所述奇数组复位单元输出端放电阶段结束后，向所述第一偶数时钟信号线提供高电平信号，向所述第一奇数时钟信号线、所述第二奇数时钟信号线和所述第二偶数时钟信号线提供低电平信号，以经过所述奇数组复位单元上拉节点放电阶段，同时经过所述偶数组复位单元的输出阶段；
在所述奇数组复位单元上拉节点放电阶段束后，向所述第一奇数时钟信号线、所述第一偶数时钟信号线、所述第二奇数时钟信号线和所述第二偶数时钟信号线提供低电平信号，以经过所述偶数组复位单元输出端放电阶段；
在所述偶数组复位单元输出端放电阶段结束后，向所述第二奇数时钟信号线提供高电平信号，向所述第一奇数时钟信号线、所述第一偶数时钟信号线和所述第二偶数时钟信号线提供低电平信号，以经过所述偶数组复位单元上拉节点放电阶段。
可选地，所述移位寄存单元包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管和存储电容，所述第一薄膜晶体管的栅极和第一极与所述移位寄存单元的信号输入端相连，所述第一薄膜晶体管的第二极与所述第二薄膜晶体管的第一极相连，所述第二薄膜晶体管的栅极与所述移位寄存单元的复位信号输入端相连，所述第二薄膜晶体管的第二极与低电平输入端相连，所述第三薄膜晶体管的第一极与第一时钟信号输入端相连，所述第三薄膜晶体管的栅极与所述第一薄膜晶体管的第二极相连，所述第三薄膜晶体管的第二极与所述移位寄存单元的输出端相连，所述第四薄膜晶体管的第一极与第二时钟信号输入端相连， 所述第四薄膜晶体管的第二极与所述第五薄膜晶体管的第一极相连，所述第四薄膜晶体管的栅极与所述第七薄膜晶体管的第二极相连，所述第五薄膜晶体管的栅极与所述第三薄膜晶体管的栅极相连，所述第五薄膜晶体管的第二极与所述低电平输入端相连，所述第六薄膜晶体管的栅极与所述第五薄膜晶体管的栅极相连，所述第六薄膜晶体管的第一极与所述第四薄膜晶体管的栅极相连，所述第六薄膜晶体管的第二极与所述低电平输入端相连，所述第七薄膜晶体管的栅极与所述第二时钟信号输入端相连，所述第七薄膜晶体管的第一极与该第七薄膜晶体管的栅极相连，所述第八薄膜晶体管的栅极与所述第九薄膜晶体管的栅极相连，且与所述第五薄膜晶体管的第一极相连，所述第八薄膜晶体管的第一极与所述第二薄膜晶体管的第一极相连，所述第八薄膜晶体管的第二极与所述低电平输入端相连，所述第九薄膜晶体管的第一极与所述移位寄存单元的信号输出端相连，所述第九薄膜晶体管的第二极与所述低电平输入端相连，所述第十薄膜晶体管的第一极与所述第九薄膜晶体管的第一极相连，所述第十薄膜晶体管的第二极与所述第九薄膜晶体管的第二极相连，所述第十薄膜晶体管的栅极与所述复位信号输入端相连，所述存储电容的第一端与所述第三薄膜晶体管的栅极相连，所述存储电容的第二端与所述移位寄存单元的信号输出端相连，
所述驱动方法还包括，在同一个所述驱动周期内：
从所述显示阶段结束前的半个脉冲时刻开始，向所述第一奇数时钟信号线和所述第一偶数时钟信号线提供低电平信号，向所述第二奇数时钟信号线以及所述第二偶数时钟信号线提供高电平信号，以对所述奇数组复位单元的上拉节点进行充电；
在对所述奇数组复位单元的上拉节点充电完毕后，经过所述奇数组复位单元输出阶段，并向所述第一奇数时钟信号线和所述第二偶数时钟信号线提供高电平信号，向所述第一偶数时钟信号线和所述第二奇数时钟信号线提供低电平信号，以对所述偶数组复位单元的上拉节点进行充电；
在对所述偶数组复位单元的上拉节点充电完毕后，经过所述偶数组复位单元输出阶段，并向所述第一偶数时钟信号线提供高电平信号，向所述第一奇数时钟信号线、所述第二奇数时钟信号线和所述第二偶数时钟信号线提供 低电平信号，使得所述奇数组复位单元的所述第二薄膜晶体管和所述第十薄膜晶体管导通，以同时经过所述奇数组复位单元上拉节点下拉阶段和所述奇数组复位单元输出端下拉阶段；
所述奇数组复位单元的上拉节点下拉阶段和所述奇数组复位单元的输出端下拉阶段结束后，向所述第二奇数时钟信号线提供高电平信号，向所述第一奇数时钟信号线、所述第一偶数时钟信号线和所述第二偶数时钟信号线提供低电平信号，使得所述偶数组复位单元的所述第二薄膜晶体管和所述第十薄膜晶体管导通，以同时经过所述偶数组复位单元上拉节点下拉阶段和所述偶数组复位单元输出端下拉阶段。
可选地，复位阶段时钟信号的脉冲宽度为显示阶段脉冲信号宽度的一半。
在本公开中，通过时钟信号线输入的时钟信号为用作复位单元的移位寄存单元提供复位信号，因此，无需在栅极驱动电路中增加额外的复位单元或额外的薄膜晶体管，从而简化了栅极驱动电路的总体结构，有利于实现包括所述栅极驱动电路的显示装置的窄边框设计。
附图说明
为了更清楚地说明本公开文本的实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开文本的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是现有的一种能够实现复位的栅极驱动电路的示意图；
图2是现有的另一种能够实现复位的栅极驱动电路的示意图；
图3是本公开所提供的栅极驱动电路的示意图；
图4是图3中所示的栅极驱动电路中移位寄存单元的一种实施方式的电路图；
图5是当本公开所提供的栅极驱动电路包括图4中所示的移位寄存单元时的时序图；
图6是图3中所示的栅极驱动电路中移位寄存单元的另一种实施方式的 电路图；以及
图7是当本公开所提供的栅极驱动电路包括图6中所示的移位寄存单元时的时序图。
具体实施方式
下面结合附图和实施例，对本公开文本的具体实施方式做进一步描述。以下实施例仅用于说明本公开文本，但不用来限制本公开文本的范围。
为使本公开文本的实施例的目的、技术方案和优点更加清楚，下面将结合本公开文本的实施例的附图，对本公开文本的实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开文本的一部分实施例，而不是全部的实施例。基于所描述的本公开文本的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开文本保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开文本所属领域内具有一般技能的人士所理解的通常意义。本公开文本专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
下面将结合本公开文本的实施例中的附图，对本公开文本的实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开文本一部分实施例，而不是全部的实施例。基于本公开文本中的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开文本保护的范围。
如图3所示，作为本公开的一个方面，提供一种栅极驱动电路，栅极驱动电路包括至少一组时钟信号线和级联的多级移位寄存单元(图3中示出了第一级移位寄存单元100_1、第二级移位寄存单元100_2、第三级移位寄存单元100_3……第N级移位寄存单元100_N、第N+1级移位寄存单元100_N+1 和第N+2级移位寄存单元100_N+2)，每组时钟信号线包括两条所述时钟信号线，多级所述移位寄存单元被划分为至少一组移位寄存单元，并且每组所述时钟信号线对应一组所述移位寄存单元，其中，每组时钟信号线中的一条时钟信号线与该组时钟信号线对应的一组移位寄存单元中的最后一级移位寄存单元的复位信号输入端相连，以在复位阶段开始时向其提供复位信号。提供时钟信号的时钟信号发生电路位于显示面板的外部，因此并不会影响包括所述栅极驱动电路的显示装置的窄边框设计。
在本公开中，移位寄存单元的组数与时钟信号线的组数相同。设定本公开所提供的栅极驱动电路包括n组时钟信号线，所述栅极驱动电路也包括n组移位寄存单元，每组移位寄存单元中的最后一级移位寄存单元用作该组移位寄存单元的复位单元。在本公开中，通过时钟信号线输入的时钟信号为用作复位单元的移位寄存单元提供复位信号，因此，无需在栅极驱动电路中增加额外的复位单元或额外的薄膜晶体管，从而简化了栅极驱动电路的总体结构，有利于实现包括所述栅极驱动电路的显示装置的窄边框设计。
应当指出的是，为了通过时钟信号线为复位单元提供复位信号，需要对时钟信号的时序进行重新设计，下文中将对本公开中时钟信号的时序进行详细的描述，这里先不赘述。
通常，用于显示面板的栅极驱动电路包括偶数级移位寄存单元。在图3中所示的具体实施方式中，所述栅极驱动电路包括奇数组时钟信号线和偶数组时钟信号线共两组时钟信号线，奇数组时钟信号线包括第一奇数时钟信号线CLK1和第二奇数时钟信号线CLK3，偶数组时钟信号线包括第一偶数时钟信号线CLK2和第二偶数时钟信号线CLK4，多级所述移位寄存单元被划分为对应于奇数组栅线的奇数组移位寄存单元和对应于偶数行栅线的偶数组移位寄存单元，奇数组移位寄存单元的最后一级移位寄存单元用作奇数组复位单元，偶数组移位寄存单元的最后一级移位寄存单元用作偶数组复位单元，第一偶数时钟信号线CLK2与所述奇数组复位单元的复位信号输入端相连，第二奇数时钟信号线CLK3与所述偶数组复位单元的复位信号输入端相连。并且，所述奇数组复位单元的输出端与所述偶数组复位单元的输入端相连。奇数组复位单元的输出端还与对应于最后一行奇数行栅线的移位寄存单元的 复位端相连，偶数组复位单元的输出端与对应于最后一行偶数行栅线的移位寄存单元的复位端相连。容易理解的是，奇数组复位单元与偶数组复位单元是相邻的两级移位寄存单元。需要指出的是，此处奇数组复位单元与偶数组复位单元之间的关系并不能称之为级联。
如上文中所述，图3中示出了第一级移位寄存单元100_1、第二级移位寄存单元100_2、第三级移位寄存单元100_3……第N级移位寄存单元100_N、第N+1级移位寄存单元100_N+1和第N+2级移位寄存单元100_N+2。在图3中所示出的实施例中，N为偶数。因此，第二奇数时钟信号线CLK3与偶数组移位寄存单元中作为偶数组复位单元的移位寄存单元100_N+2的复位端RESET相连，并为其提供复位信号；第一偶数时钟信号线CLK2与奇数组移位寄存单元中作为奇数组复位单元的移位寄存单元100_N+1的复位端RESET相连，并为其提供复位信号。
在本公开中，对移位寄存单元的具体结构并不做限定，作为本公开的一种可选实施方式，如图4所示，所述移位寄存单元可以具有9T1C结构，具体地，所述移位寄存单元包括第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第五薄膜晶体管M5、第六薄膜晶体管M6、第七薄膜晶体管M7、第八薄膜晶体管M8、第九薄膜晶体管M9和存储电容C。
第一薄膜晶体管M1的栅极和第一极与所述移位寄存单元的信号输入端IN相连，第一薄膜晶体管M1的第二极与第二薄膜晶体管M2的第一极相连。第二薄膜晶体管M2的栅极与所述移位寄存单元的复位信号输入端RESET相连，第二薄膜晶体管M2的第二极与低电平输入端VGL相连。第三薄膜晶体管M3的第一极与第一时钟信号输入端相连，第三薄膜晶体管M3的栅极与第一薄膜晶体管M1的第二极相连，第三薄膜晶体管M3的第二极与所述移位寄存单元的输出端OUTPUT相连。第四薄膜晶体管M4的第一极与第二时钟信号输入端相连，第四薄膜晶体管M4的第二极与第五薄膜晶体管M5的第一极相连，第四薄膜晶体管M4的栅极与第七薄膜晶体管M7的第二极相连，第五薄膜晶体管M5的栅极与第三薄膜晶体管M3的栅极相连，第五薄膜晶体管M5的第二极与低电平输入端VGL相连，第六薄膜晶体管M6的栅 极与第五薄膜晶体管M5的栅极相连，第六薄膜晶体管M6的第一极与第四薄膜晶体管M4的栅极相连，第六薄膜晶体管M6的第二极与低电平输入端VGL相连，第七薄膜晶体管M7的栅极与所述第二时钟信号输入端相连，第七薄膜晶体管M7的第一极与该第七薄膜晶体管M7的栅极相连。第八薄膜晶体管M8的栅极与第九薄膜晶体管M9的栅极相连，且与第五薄膜晶体管M5的第一极相连，第八薄膜晶体管M8的第一极与第二薄膜晶体管M2的第一极相连，第八薄膜晶体管M8的第二极与低电平输入端VGL相连。第九薄膜晶体管M9的第一极与所述移位寄存单元的信号输出端OUTPUT相连，第九薄膜晶体管M9的第二极与低电平输入端VGL相连，所述第九薄膜晶体管的栅极与所述第八薄膜晶体管的栅极相连。存储电容C的第一端与第三薄膜晶体管M3的栅极相连，存储电容C的第二端与所述移位寄存单元的信号输出端OUTPUT相连。
在图4中所示的9T1C的移位寄存单元中，存储电容C的第一端形成为上拉节点PU，第一薄膜晶体管M1的第二极、第三薄膜晶体管M3的栅极、第五薄膜晶体管M5的栅极、第六薄膜晶体管M6的栅极均与上拉节点PU相连。第五薄膜晶体管M5的第一极形成为下拉节点PD，第四薄膜晶体管M4的第二极、第八薄膜晶体管M8的栅极和第九薄膜晶体管M9的栅极均与下拉节点PD相连。第四薄膜晶体管M4的栅极形成为下拉控制节点PD，第七薄膜晶体管M7的第二极、第六薄膜晶体管M6的第一极均与下拉控制节点PD相连。
需要指出的是，第一时钟信号输入端与第一奇数时钟信号线CLK1或第一偶数时钟信号线CLK2相连，第二时钟信号输入端与第二奇数时钟信号线CLK3或第二偶数时钟信号线CLK4相连。
图4中所示的移位寄存单元中仅包括9个薄膜晶体管和1个存储电容，因此，占用较小的空间。
图5中所示的是包括图4中所示的移位寄存单元的栅极驱动电路的时序图。下文中将对其进行详细的描述，这里先不赘述。
图6中所示的是具有10T1C结构的移位寄存单元。与图4中所示的移位寄存单元相比，图6中所示的所述移位寄存单元还包括第十薄膜晶体管M10， 该第十薄膜晶体管M10的第一极与第九薄膜晶体管M9的第一极相连，第十薄膜晶体管M10的第二极与第九薄膜晶体管M9的第二极相连，第十薄膜晶体管M10的栅极与复位信号输入端RESET相连。在增加了第十薄膜晶体管M10之后，可以加快移位寄存单元的输出端OUTPUT的放电速度。
作为本公开的另一个方面，提供一种阵列基板，所述阵列基板包括栅极驱动电路，其中，所述栅极驱动电路为本公开所提供的上述栅极驱动电路。
由于在本公开所提供的栅极驱动电路中，无需额外增设用于对最后一级移位寄存单元进行复位的元器件，因此，所述栅极驱动电路结构较简单，容易实现阵列基板的窄边框设计。
作为本公开的再一个方面，提供一种显示装置，所述显示装置包括阵列基板，其中，所述阵列基板为本公开所提供的上述阵列基板。
由于所述阵列基板容易实现窄边框设计，因此，所述显示装置也具有较窄的边框。
作为本公开的又一个方面，提供一种用于驱动本公开所提供的栅极驱动电路的栅极电路驱动方法，该栅极电路驱动方法包括多个驱动周期，每个驱动周期都包括显示阶段和复位阶段，所述复位阶段包括复位单元输出阶段、复位单元输出端放电阶段和复位单元上拉节点放电阶段：
在所述复位单元输出阶段，向所述复位单元的第一时钟信号输入端输入高电平信号，以使所述复位单元向该复位单元的上一级移位寄存单元的复位端输出高电平信号；
在所述复位单元输出端放电阶段，向所述复位单元的所述第一时钟信号输入端和第二时钟信号输入端输入低电平信号，以对所述复位单元的输出端进行放电；
在所述复位单元上拉节点放电阶段，向所述复位单元的第一时钟信号输入端输入低电平信号，并且利用时钟信号线向所述复位单元的复位信号输入端和所述复位单元的第二时钟信号输入端输入高电平信号，以对所述复位单元的上拉节点进行放电。
在显示阶段，在栅极驱动电路中，除了用作复位单元的移位寄存单元之外的其他移位寄存单元向阵列基板中的栅线输出扫描信号，以用于显示图像。 在复位阶段，利用时钟信号线向用作复位单元的移位寄存单元提供复位信号，以对复位单元进行复位，复位单元的输出端输出的信号为该复位单元上一级的移位寄存单元提供复位信号以进行复位。所述复位单元输出极端与所述复位单元放电阶段之间间隔预定时刻。需要指出的是，复位单元上一级的移位寄存单元是与相应的栅线相连的、用于为该栅线提供扫描信号的移位寄存单元。
容易理解的是，在进入复位阶段之前，用作复位单元的移位寄存单元的上拉节点已经被上拉至高电平。每个用作复位单元的移位寄存单元的结构与其他移位寄存单元的结构相同，因此所述复位单元也包括输出模块，通常输出模块包括薄膜晶体管和存储电容。输出模块中的薄膜晶体管栅极与上拉节点相连，输出模块的薄膜晶体管的第一极与第一时钟信号输入端相连，输出模块的薄膜晶体管的第二极与本级移位寄存单元的输出端相连，存储电容的第一端与上拉节点相连，存储电容的第二端与本级移位寄存单元的输出端相连。在复位单元输出阶段，复位单元的上拉节点处于高电平，因此，输出模块的薄膜晶体管是导通的，当第一时钟信号输入端接入高电平时，复位单元的输出端会有高电平信号输出。复位输出端将高电平信号输出至上一级移位寄存单元的复位端，从而对上一级移位寄存单元进行复位。
在复位单元输出端放电阶段，向复位单元的第一时钟信号输入端输入低电平信号，由于此时复位单元的上拉节点仍然保持高电平，因此，所述复位单元可以利用输出模块的薄膜晶体管进行放电。
在所述复位单元上拉节点放电阶段，所述复位单元的输入端输入了高电平信号，从而可以通过复位单元内部的复位模块将复位单元的上拉节点电位拉低。关于复位模块如何对上拉节点进行放电是本领域公知的，这里不再赘述。
由于通过时钟信号线向用作复位单元的移位寄存单元提供复位信号，因此，不需要增加其他的元器件，有利于简化栅极驱动电路的结构。
通常，显示面板包括偶数条栅线，因此，所述栅极驱动电路包括偶数级移位寄存单元。如上文中所述，作为本公开的可选实施方式，所述栅极驱动电路包括奇数组时钟信号线和偶数组时钟信号线，奇数组时钟信号线包括第 一奇数时钟信号线和第二奇数时钟信号线，偶数组时钟信号线包括第一偶数时钟信号线和第二偶数时钟信号线，多级所述移位寄存单元被划分为对应于奇数行栅线的奇数组移位寄存单元和对应于偶数行栅线的偶数组移位寄存单元，奇数组移位寄存单元的最后一级移位寄存单元用作奇数组复位单元，偶数组移位寄存单元的最后一级移位寄存单元用作偶数组复位单元。在这种实施方式中，第一偶数时钟信号线为所述奇数组复位单元提供复位信号，第二奇数时钟信号线为所述偶数组复位单元提供复位信号。并且，所述奇数组复位单元的输出端与所述偶数组复位单元的输入端相连。
具体地，所述复位输出阶段包括：
奇数组复位单元输出阶段：向所述奇数组复位单元的第一时钟信号输入端输入高电平信号，以使所述奇数组复位单元向该奇数组复位单元的上一级移位寄存单元的复位端输出高电平信号；和
偶数组复位单元输出阶段：向所述偶数组复位单元的第一时钟信号输入端输入高电平信号，以使所述偶数组复位单元向该偶数组复位单元的上一级移位寄存单元的复位端输出高电平信号。
需要解释的是，此处，奇数组复位单元的上一级移位寄存单元是指与最后一行奇数行栅线相连的移位寄存单元，偶数组复位单元的上一级移位寄存单元是指与最后一行偶数行栅线相连的移位寄存单元。
所述复位单元输出端放电阶段包括：
奇数组复位单元输出端放电阶段：在所述奇数组复位单元输出端放电阶段，向所述奇数组复位单元的所述第一时钟信号输入端和第二时钟信号输入端输入低电平信号，以对所述奇数组复位单元的输出端进行放电；和
偶数组复位单元输出端放电阶段：在所述偶数组复位单元输出端放电阶段，向所述偶数组复位单元的所述第一时钟信号输入端和第二时钟信号输入端输入低电平信号，以对所述偶数组复位单元的输出端进行放电；
所述偶数组复位单元上拉节点放电阶段包括：
奇数组复位单元上拉节点放电阶段：在所述奇数组复位单元上拉节点放电阶段，向所述奇数组复位单元的第一时钟信号输入端输入低电平信号，并且利用偶数组时钟信号线向所述奇数组复位单元的复位信号输入端输入高电 平信号，以对所述奇数组复位单元的上拉节点进行放电；
偶数组复位单元上拉节点放电阶段：在所述偶数组复位单元上拉节点放电阶段，向所述偶数组复位单元的第一时钟信号输入端输入低电平信号，并且利用奇数组时钟信号线向所述偶数组复位单元的复位信号输入端输入高电平信号，以对所述偶数组复位单元的上拉节点进行放电。
在本公开中，分别对奇数组复位单元和偶数组复位单元进行复位。应当理解的是，奇数组复位单元输出阶段、奇数组复位单元输出端放电阶段和奇数组复位单元上拉节点放电阶段是连续的。同样地，偶数组复位单元输出阶段、偶数组复位单元输出端放电阶段和偶数组复位单元上拉节点放电阶段是连续的。
如果奇数组复位单元为偶数组复位单元的上一级，那么奇数组复位单元上拉节点放电阶段结束后依次经过偶数组复位单元输出阶段、偶数组复位单元输出端放电阶段和偶数组复位单元上拉节点放电阶段。反之，如果偶数组复位单元为奇数组复位单元的上一级，那么偶数组复位单元上拉节点放电阶段结束后依次经过奇数组复位单元输出阶段、奇数组复位单元输出端放电阶段和奇数组复位单元上拉节点放电阶段。
下面介绍如何利用本公开所提供的驱动方法驱动具有图4中所示的9T1C结构的栅极驱动电路。
图5中所示的是驱动包括图4中所示的移位寄存单元的栅极驱动电路的时序图。
如图中所示，在一个显示周期中，阶段S1、阶段S2以及阶段S1之前的各个阶段均为显示阶段，阶段S3至阶段S7为复位阶段，在同一个显示周期内，所述复位阶段从所述显示阶段结束时开始。
所述驱动方法包括，在同一个驱动周期内：
所述显示周期结束后，向所述第一奇数时钟信号线提供高电平信号，向所述第一偶数时钟信号线、所述第二奇数时钟信号线以及所述第二偶数时钟信号线提供低电平信号，以经过所述奇数组复位单元输出阶段；
在所述奇数组复位单元输出阶段结束后，向所述第一奇数时钟信号线、第一偶数时钟信号线、第二奇数时钟信号线和所述第二偶数时钟信号线提供 低电平信号，以经过所述奇数组复位单元输出端放电阶段；
在所述奇数组复位单元输出端放电阶段结束后，向所述第一偶数时钟信号线提供高电平信号，向所述第一奇数时钟信号线、所述第二奇数时钟信号线和所述第二偶数时钟信号线提供低电平信号，以经过所述奇数组复位单元上拉节点放电阶段，同时经过所述偶数组复位单元的输出阶段；
在所述奇数组复位单元上拉节点放电阶段束后，向所述第一奇数时钟信号线、所述第一偶数时钟信号线、所述第二奇数时钟信号线和所述第二偶数时钟信号线提供高低平信号，以经过所述偶数组复位单元输出端放电阶段；
在所述偶数组复位单元输出端放电阶段结束后，向所述第二奇数时钟信号线提供高电平信号，向所述第一奇数时钟信号线、所述第一偶数时钟信号线和所述第二偶数时钟信号线提供低电平信号，以经过所述偶数组复位单元上拉节点放电阶段。
下面结合图5详细描述这种驱动方法，其中，N为偶数，也就是说，所述移位寄存器包括偶数个移位寄存单元，图3中所示的移位寄存单元100_N+1为奇数组复位单元，用于为奇数组的移位寄存单元(即，第N-1级移位寄存单元)进行复位，移位寄存单元100_N+2为偶数组复位单元，用于为偶数组的移位寄存单元(即，第N级移位寄存单元)进行复位。
在S1阶段，第N-1级移位寄存单元的输出端Output N-1向第N-1行扫描线输出扫描信号，第N-1行扫描线的扫描信号同时还是用作奇数组复位单元的移位寄存单元100_N+1的输入信号，因此移位寄存单元100_N+1的上拉节点100_N+1PU开始充电。
在S2阶段，第N级移位寄存单元的输出端Output N向第N行扫描线输出扫描信号，第N行扫描线的扫描信号同时还是用作复位单元的移位寄存单元100_N+2的输入信号，因此移位寄存单元100_N+2的上拉节点100_N+2PU开始充电，此时移位寄存单元100_N+1充电完成，保持高电平。
阶段S3为奇数组复位单元输出阶段，在S3阶段，移位寄存单元100_N+1对应的第一奇数时钟信号(由第一奇数时钟信号线CLK1提供)变为高电平，因此移位寄存单元100_N+1开始输出，对第N-1行移位寄存单元的上拉节点进行复位。
阶段S4为奇数组复位单元输出端放电阶段，在S4阶段，如上所述，第一奇数时钟信号(由第一奇数时钟信号线CLK1提供)变为低电平，但第N-1行移位寄存单元的上拉节点仍保持高电平，移位寄存单元100_N+1的输出端通过第三薄膜晶体管M3放电，被下拉为低电平。容易理解的是，第三薄膜晶体管M3即为上文中所述的输出模块的薄膜晶体管。
阶段S5为奇数组复位单元上拉节点放电阶段，同时，阶段S5为奇数组复位单元输出阶段，在阶段S5，移位寄存单元100_N+1对应的第一偶数时钟信号CLK2变为高电平，因此移位寄存单元100_N+1的输出端Output N+1开始输出，对第N级移位寄存单元100_N的上拉节点PU进行复位，至此，第N-1级移位寄存单元和第N级移位寄存单元100_N均都顺利复位。同时，第一偶数时钟信号CLK2将移位寄存单元100_N+1的上拉节点PU点复位为低电平。
阶段S6为偶数组复位单元输出端放电阶段，在阶段S6，第一偶数时钟信号(由第一偶数时钟信号线CLK2提供)变为低电平，但移位寄存单元100_N+2的上拉节点PU仍保持高电平，移位寄存单元100_N+2的输出端通过第三薄膜晶体管M3放电为低电平。
阶段S7为偶数组复位单元上拉节点放电阶段，在阶段S7，第二奇数时钟信号(由第二奇数时钟信号线CLK3提供)变为高电平，将移位寄存单元100_N+2的上拉节点PU复位为低电平。至此各移位寄存单元均被正常复位，一帧结束。
容易理解的是，当移位寄存单元具有图4中所示的9T1C结构时，显示阶段结束后才开始复位阶段。
所述驱动方法还包括，在同一个所述驱动周期内：
从所述显示阶段结束前的半个脉冲时刻开始，向所述第一奇数时钟信号线和所述第一偶数时钟信号线提供低电平信号，向所述第二奇数时钟信号线以及所述第二偶数时钟信号线提供高电平信号，以对所述奇数组复位单元的上拉节点进行充电；和
在对所述奇数组复位单元的上拉节点充电完毕后，向所述第一奇数时钟信号线提供高电平信号，向所述第一偶数时钟信号线、所述第二奇数时钟信 号线和所述第二偶数时钟信号线提供低电平信号，以对所述偶数复位单元的上拉节点进行充电；
所述复位阶段包括：
在对所述偶数组复位单元的上拉节点充电完毕后，向所述第一偶数时钟信号线提供高电平信号，向所述第一奇数时钟信号线、所述第二奇数时钟信号线和所述第二偶数时钟信号线提供低电平信号，使得所述奇数组复位单元的所述第二薄膜晶体管和所述第十薄膜晶体管导通，以同时经过所述奇数组复位单元上拉节点下拉阶段和所述奇数组复位单元输出端下拉阶段；
所述奇数组复位单元的上拉节点下拉阶段和所述奇数组复位单元的输出端下拉阶段结束后，向所述第二奇数时钟信号线提供高电平信号，向所述第一奇数时钟信号线、所述第一偶数时钟信号线和所述第二偶数时钟信号线提供低电平信号，使得所述偶数组复位单元的所述第二薄膜晶体管和所述第十薄膜晶体管导通，以同时经过所述偶数组复位单元上拉节点下拉阶段和所述偶数组复位单元输出端下拉阶段。
下面介绍移位寄存单元具有图6中所示的10T1C结构时，所述驱动方法的具体步骤。
如图7中所示，N为偶数，也就是说，所述移位寄存器包括偶数个移位寄存单元，图3中所示的移位寄存单元100_N+1为奇数组复位单元，用于为奇数组的移位寄存单元进行复位，移位寄存单元100_N+2为偶数组复位单元，用于为偶数组的移位寄存单元进行复位，在同一个显示周期内：
从所述显示阶段结束前的半个脉冲时刻开始的S1阶段为奇数组复位单元的上拉节点充电阶段，在S1阶段，第一奇数时钟信号线CLK1输出低电平信号，第二奇数时钟信号线CLK3和第二偶数时钟信号线CLK4输出高电平信号，第N级移位寄存单元100_N的输出端Output N输出，该输出是用作复位单元的移位寄存单元100_N+1的输入信号，因此移位寄存单元100_N+1的上拉节点100_N+1PU开始充电；
S1阶段结束后的S2阶段为奇数组复位单元输出阶段和偶数组复位单元的上拉节点充电阶段，在S2阶段，第一奇数时钟信号线CLK1输出高电平信号，第一偶数时钟信号线CLK2、第二奇数时钟信号线CLK3和第二偶数时 钟信号线CLK4输出低电平信号，用作复位单元的移位寄存单元100_N+1的输出端Reset output 1开始输出高电平，因此，第N-1级移位寄存单元被正常复位，同时，用作复位单元的移位寄存单元100_N+1输出的高电平信号也是用作复位单元的移位寄存单元100_N+2的输入信号，因此移位寄存单元100_N+2的上拉节点100_N+2PU开始充电；
S3阶段为偶数组复位单元输出阶段、奇数组复位单元输出端下拉阶段以及奇数组复位单元上拉节点下拉阶段，在S3阶段第一偶数时钟信号线CLK2输出高电平信号，第一奇数时钟信号线CLK1、第二奇数时钟信号线CLK3和第二偶数时钟信号线CLK4同时输出低电平信号，用作复位单元的移位寄存单元100_N+2的输出端Reset output2开始输出高电平，因此，第N级移位寄存单元100_N的输出端被正常复位，由于第一偶数时钟信号线CLK2连接了用作复位单元的移位寄存单元100_N+1的复位端，第二薄膜晶体管M2和第十薄膜晶体管M10导通因此，用作复位单元的移位寄存单元100_N+1的上拉节点100_N+1PU和输出端同时被下拉至低电平VGL，使得用作复位单元的移位寄存单元100_N+1被正常复位；
S4阶段为偶数组复位单元的上拉节点放电阶段和偶数组复位单元的输出端放电阶段，在S4阶段第二奇数时钟信号线CLK3输出高电平信号，第一奇数时钟信号线CLK1、第一偶数时钟信号线CLK2和第二偶数时钟信号线CLK4输出低电平信号，由于第二奇数时钟信号线CLK3连接了用作复位单元的移位寄存单元100_N+2的复位端，因此，第二薄膜晶体管M2和第十薄膜晶体管M10导通，因此用作复位单元的移位寄存单元100_N+2的上拉节点100_N+2PU和输出端同时被下拉至低电平VGL，使得用作复位单元的移位寄存单元100_N+2被正常复位。至此，各移位寄存单元均被正常复位，一帧结束。
可选地，复位阶段时钟信号的脉冲宽度为显示阶段脉冲信号宽度的一半。而由于复位单元不需要考虑对像素进行充电，只需要考虑对前一个移位寄存单元的上拉节点进行复位即可，因此设置输出宽度减半完全可行。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而 言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。
附图标记说明
100_1：第一级移位寄存单元    100_2：第二级移位寄存单元
100_3：第三级移位寄存单元    100_N：第N级移位寄存单元
100_N+1：第N+1级移位寄存单元
100_N+2：第N+2级移位寄存单元
M1：第一薄膜晶体管      M2：第二薄膜晶体管
M3：第三薄膜晶体管      M4：第四薄膜晶体管
M5：第五薄膜晶体管      M6：第六薄膜晶体管
M7：第七薄膜晶体管      M8：第八薄膜晶体管
M9：第九薄膜晶体管      M10：第十薄膜晶体管
C：存储电容

Claims (13)

  1. 一种栅极驱动电路，所述栅极驱动电路包括至少一组时钟信号线和级联的多级移位寄存单元，所述至少一组时钟信号线中的每组时钟信号线包括两条所述时钟信号线，多级所述移位寄存单元被划分为至少一组，并且所述每组所述时钟信号线对应一组所述移位寄存单元，其中，所述每组时钟信号线中的一条时钟信号线连接到与该组时钟信号线对应的一组移位寄存单元中的最后一级移位寄存单元的复位信号输入端，以在复位阶段开始时向一组移位寄存单元中的最后一级移位寄存单元的复位信号输入端提供复位信号。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述栅极驱动电路包括偶数级移位寄存单元，所述栅极驱动电路包括奇数组时钟信号线和偶数组时钟信号线，奇数组时钟信号线包括第一奇数时钟信号线和第二奇数时钟信号线，偶数组时钟信号线包括第一偶数时钟信号线和第二偶数时钟信号线，多级所述移位寄存单元被划分为对应于奇数行栅线的奇数组移位寄存单元和对应于偶数行栅线的偶数组移位寄存单元，奇数组移位寄存单元的最后一级移位寄存单元用作奇数组复位单元，偶数组移位寄存单元的最后一级移位寄存单元用作偶数组复位单元，第一偶数时钟信号线与所述奇数组复位单元的复位信号输入端相连，第二奇数时钟信号线与所述偶数组复位单元的复位信号输入端相连，所述奇数组复位单元的输出端与所述偶数组复位单元的输入端相连，所述奇数组复位单元的输出端与对应于最后一行奇数行栅线的奇数组移位寄存单元的复位端相连，所述偶数组复位单元的输出端与对应于最后一行偶数行栅线的偶数组移位寄存单元的复位端相连。
  3. 根据权利要求1或2所述的栅极驱动电路，其中，所述移位寄存单元包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管和存储电容，所述第一薄膜晶体管的栅极和第一极与所述移位寄存单元的信号输入端相连，所述第一薄膜晶体管的第二极与所述第二薄膜 晶体管的第一极相连，所述第二薄膜晶体管的栅极与所述移位寄存单元的复位信号输入端相连，所述第二薄膜晶体管的第二极与低电平输入端相连，所述第三薄膜晶体管的第一极与第一时钟信号输入端相连，所述第三薄膜晶体管的栅极与所述第一薄膜晶体管的第二极相连，所述第三薄膜晶体管的第二极与所述移位寄存单元的输出端相连，所述第四薄膜晶体管的第一极与第二时钟信号输入端相连，所述第四薄膜晶体管的第二极与所述第五薄膜晶体管的第一极相连，所述第四薄膜晶体管的栅极与所述第七薄膜晶体管的第二极相连，所述第五薄膜晶体管的栅极与所述第三薄膜晶体管的栅极相连，所述第五薄膜晶体管的第二极与所述低电平输入端相连，所述第六薄膜晶体管的栅极与所述第五薄膜晶体管的栅极相连，所述第六薄膜晶体管的第一极与所述第四薄膜晶体管的栅极相连，所述第六薄膜晶体管的第二极与所述低电平输入端相连，所述第七薄膜晶体管的栅极与所述第二时钟信号输入端相连，所述第七薄膜晶体管的第一极与该第七薄膜晶体管的栅极相连，所述第八薄膜晶体管的栅极与所述第九薄膜晶体管的栅极相连，且与所述第五薄膜晶体管的第一极相连，所述第八薄膜晶体管的第一极与所述第二薄膜晶体管的第一极相连，所述第八薄膜晶体管的第二极与所述低电平输入端相连，所述第九薄膜晶体管的第一极与所述移位寄存单元的信号输出端相连，所述第九薄膜晶体管的第二极与所述低电平输入端相连，所述存储电容的第一端与所述第三薄膜晶体管的栅极相连，所述存储电容的第二端与所述移位寄存单元的信号输出端相连。
  4. 根据权利要求3所述的栅极驱动电路，其中，所述移位寄存单元包括还包括第十薄膜晶体管，所述第十薄膜晶体管的第一极与所述第九薄膜晶体管的第一极相连，所述第十薄膜晶体管的第二极与所述第九薄膜晶体管的第二极相连，所述第十薄膜晶体管的栅极与所述复位信号输入端相连。
  5. 一种阵列基板，包括根据权利要求1至4中任意一项所述的栅极驱动电路。
  6. 一种显示装置，包括根据权利要求5所述的阵列基板。
  7. 一种栅极驱动电路的驱动方法，其中，所述栅极驱动电路为权利要求1所述的栅极驱动电路，所述栅极电路驱动方法包括多个驱动周期，每个驱动周期都包括显示阶段和复位阶段，所述复位阶段包括复位单元输出阶段、复位单元输出端放电阶段和复位单元上拉节点放电阶段：
    在所述复位单元输出阶段，向所述复位单元的第一时钟信号输入端输入高电平信号，以使所述复位单元向该复位单元的上一级移位寄存单元的复位端输出高电平信号；
    在所述复位单元输出端放电阶段，向所述复位单元的所述第一时钟信号输入端和第二时钟信号输入端输入低电平信号，以对所述复位单元的输出端进行放电；
    在所述复位单元上拉节点放电阶段，向所述复位单元的第一时钟信号输入端输入低电平信号，并且利用时钟信号线向所述复位单元的复位信号输入端和所述复位单元的第二时钟信号输入端输入高电平信号，以对所述复位单元的上拉节点进行放电。
  8. 根据权利要求7所述的驱动方法，其中，所述栅极驱动电路包括奇数组时钟信号线和偶数组时钟信号线，奇数组时钟信号线包括第一奇数时钟信号线和第二奇数时钟信号线，偶数组时钟信号线包括第一偶数时钟信号线和第二偶数时钟信号线，多级所述移位寄存单元被划分为对应于奇数行栅线的奇数组移位寄存单元和对应于偶数行栅线的偶数组移位寄存单元，奇数组移位寄存单元的最后一级移位寄存单元用作奇数组复位单元，偶数组移位寄存单元的最后一级移位寄存单元用作偶数组复位单元，所述奇数组复位单元与所述偶数组复位单元级联，所述奇数组复位单元的输出端与对应于最后一行奇数行栅线的奇数组移位寄存单元的复位端相连，所述偶数组复位单元的输出端与对应于最后一行偶数行栅线的偶数组移位寄存单元的复位端相连，第二奇数时钟信号线为所述奇数组复位单元提供复位信号，第一偶数时钟信号线为所述偶数组复位单元提供复位信号，
    所述复位输出阶段包括：
    奇数组复位单元输出阶段：向所述奇数组复位单元的第一时钟信号输入端输入高电平信号，以使所述奇数组复位单元向该奇数组复位单元的上一级移位寄存单元的复位端输出高电平信号；和
    偶数组复位单元输出阶段：向所述偶数组复位单元的第一时钟信号输入端输入高电平信号，以使所述偶数组复位单元向该偶数组复位单元的上一级移位寄存单元的复位端输出高电平信号；
    所述复位单元输出端放电阶段包括：
    奇数组复位单元输出端放电阶段：在所述奇数组复位单元输出端放电阶段，向所述奇数组复位单元的所述第一时钟信号输入端和所述第二时钟信号输入端输入低电平信号，以对所述奇数组复位单元的输出端进行放电；和
    偶数组复位单元输出端放电阶段：在所述偶数组复位单元输出端放电阶段，向所述偶数组复位单元的所述第一时钟信号输入端和所述第二时钟信号输入端输入低电平信号，以对所述偶数组复位单元的输出端进行放电；
    所述复位单元上拉节点放电阶段包括：
    奇数组复位单元上拉节点放电阶段：在所述奇数组复位单元上拉节点放电阶段，向所述奇数组复位单元的第一时钟信号输入端输入低电平信号，并且利用所述偶数组时钟信号线向所述奇数组复位单元的复位信号输入端输入高电平信号，以对所述奇数组复位单元的上拉节点进行放电；
    偶数组复位单元上拉节点放电阶段：在所述偶数组复位单元上拉节点放电阶段，向所述偶数组复位单元的第一时钟信号输入端输入低电平信号，并且利用所述奇数组时钟信号线向所述偶数组复位单元的复位信号输入端输入高电平信号，以对所述偶数组复位单元的上拉节点进行放电。
  9. 根据权利要求8所述的驱动方法，其中，所述奇数组复位单元输出阶段、奇数组复位单元输出端放电阶段和奇数组复位单元上拉节点放电阶段是连续的。
  10. 根据权利要求8或9所述的驱动方法，其中，所述偶数组复位单元 输出阶段、偶数组复位单元输出端放电阶段和偶数组复位单元上拉节点放电阶段是连续的。
  11. 根据权利要求8所述的驱动方法，其中，所述移位寄存单元包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管和存储电容，所述第一薄膜晶体管的栅极和第一极与所述移位寄存单元的信号输入端相连，所述第一薄膜晶体管的第二极与所述第二薄膜晶体管的第一极相连，所述第二薄膜晶体管的栅极与所述移位寄存单元的复位信号输入端相连，所述第二薄膜晶体管的第二极与低电平输入端相连，所述第三薄膜晶体管的第一极与第一时钟信号输入端相连，所述第三薄膜晶体管的栅极与所述第一薄膜晶体管的第二极相连，所述第三薄膜晶体管的第二极与所述移位寄存单元的输出端相连，所述第四薄膜晶体管的第一极与第二时钟信号输入端相连，所述第四薄膜晶体管的第二极与所述第五薄膜晶体管的第一极相连，所述第四薄膜晶体管的栅极与所述第七薄膜晶体管的第二极相连，所述第五薄膜晶体管的栅极与所述第三薄膜晶体管的栅极相连，所述第五薄膜晶体管的第二极与所述低电平输入端相连，所述第六薄膜晶体管的栅极与所述第五薄膜晶体管的栅极相连，所述第六薄膜晶体管的第一极与所述第四薄膜晶体管的栅极相连，所述第六薄膜晶体管的第二极与所述低电平输入端相连，所述第七薄膜晶体管的栅极与所述第二时钟信号输入端相连，所述第七薄膜晶体管的第一极与该第七薄膜晶体管的栅极相连，所述第八薄膜晶体管的栅极与所述第九薄膜晶体管的栅极相连，且与所述第五薄膜晶体管的第一极相连，所述第八薄膜晶体管的第一极与所述第二薄膜晶体管的第一极相连，所述第八薄膜晶体管的第二极与所述低电平输入端相连，所述第九薄膜晶体管的第一极与所述移位寄存单元的信号输出端相连，所述第九薄膜晶体管的第二极与所述低电平输入端相连，所述存储电容的第一端与所述第三薄膜晶体管的栅极相连，所述存储电容的第二端与所述移位寄存单元的信号输出端相连，
    所述驱动方法包括，在同一个驱动周期内：
    所述显示周期结束后，向所述第一奇数时钟信号线提供高电平信号，向所述第一偶数时钟信号线、所述第二奇数时钟信号线以及所述第二偶数时钟信号线提供低电平信号，以经过所述奇数组复位单元输出阶段；
    在所述奇数组复位单元输出阶段结束后，向所述第一奇数时钟信号线、第一偶数时钟信号线、第二奇数时钟信号线和所述第二偶数时钟信号线提供低电平信号，以经过所述奇数组复位单元输出端放电阶段；
    在所述奇数组复位单元输出端放电阶段结束后，向所述第一偶数时钟信号线提供高电平信号，向所述第一奇数时钟信号线、所述第二奇数时钟信号线和所述第二偶数时钟信号线提供低电平信号，以经过所述奇数组复位单元上拉节点放电阶段，同时经过所述偶数组复位单元的输出阶段；
    在所述奇数组复位单元上拉节点放电阶段束后，向所述第一奇数时钟信号线、所述第一偶数时钟信号线、所述第二奇数时钟信号线和所述第二偶数时钟信号线提供低电平信号，以经过所述偶数组复位单元输出端放电阶段；
    在所述偶数组复位单元输出端放电阶段结束后，向所述第二奇数时钟信号线提供高电平信号，向所述第一奇数时钟信号线、所述第一偶数时钟信号线和所述第二偶数时钟信号线提供低电平信号，以进过所述偶数组复位单元上拉节点放电阶段。
  12. 根据权利要求8所述的驱动方法，其中，所述移位寄存单元包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管和存储电容，所述第一薄膜晶体管的栅极和第一极与所述移位寄存单元的信号输入端相连，所述第一薄膜晶体管的第二极与所述第二薄膜晶体管的第一极相连，所述第二薄膜晶体管的栅极与所述移位寄存单元的复位信号输入端相连，所述第二薄膜晶体管的第二极与低电平输入端相连，所述第三薄膜晶体管的第一极与第一时钟信号输入端相连，所述第三薄膜晶体管的栅极与所述第一薄膜晶体管的第二极相连，所述第三薄膜晶体管的第二极与所述移位寄存单元的输出端相连，所述第四薄膜晶体管的第一极与第二时钟信号输入端相连，所述第四薄膜晶体管的第二极与所述第 五薄膜晶体管的第一极相连，所述第四薄膜晶体管的栅极与所述第七薄膜晶体管的第二极相连，所述第五薄膜晶体管的栅极与所述第三薄膜晶体管的栅极相连，所述第五薄膜晶体管的第二极与所述低电平输入端相连，所述第六薄膜晶体管的栅极与所述第五薄膜晶体管的栅极相连，所述第六薄膜晶体管的第一极与所述第四薄膜晶体管的栅极相连，所述第六薄膜晶体管的第二极与所述低电平输入端相连，所述第七薄膜晶体管的栅极与所述第二时钟信号输入端相连，所述第七薄膜晶体管的第一极与该第七薄膜晶体管的栅极相连，所述第八薄膜晶体管的栅极与所述第九薄膜晶体管的栅极相连，且与所述第五薄膜晶体管的第一极相连，所述第八薄膜晶体管的第一极与所述第二薄膜晶体管的第一极相连，所述第八薄膜晶体管的第二极与所述低电平输入端相连，所述第九薄膜晶体管的第一极与所述移位寄存单元的信号输出端相连，所述第九薄膜晶体管的第二极与所述低电平输入端相连，所述第十薄膜晶体管的第一极与所述第九薄膜晶体管的第一极相连，所述第十薄膜晶体管的第二极与所述第九薄膜晶体管的第二极相连，所述第十薄膜晶体管的栅极与所述复位信号输入端相连，所述存储电容的第一端与所述第三薄膜晶体管的栅极相连，所述存储电容的第二端与所述移位寄存单元的信号输出端相连，
    所述驱动方法还包括，在同一个所述驱动周期内：
    从所述显示阶段结束前的半个脉冲时刻开始，向所述第一奇数时钟信号线和所述第一偶数时钟信号线提供低电平信号，向所述第二奇数时钟信号线以及所述第二偶数时钟信号线提供高电平信号，以对所述奇数组复位单元的上拉节点进行充电；
    在对所述奇数组复位单元的上拉节点充电完毕后，经过所述奇数组复位单元输出阶段，并向所述第一奇数时钟信号线和所述第二偶数时钟信号线提供高电平信号，向所述第一偶数时钟信号线和所述第二奇数时钟信号线提供低电平信号，以对所述偶数组复位单元的上拉节点进行充电；
    在对所述偶数组复位单元的上拉节点充电完毕后，经过所述偶数组复位单元输出阶段，并向所述第一偶数时钟信号线提供高电平信号，向所述第一奇数时钟信号线、所述第二奇数时钟信号线和所述第二偶数时钟信号线提供低电平信号，使得所述奇数组复位单元的所述第二薄膜晶体管和所述第十薄 膜晶体管导通，以同时经过所述奇数组复位单元上拉节点下拉阶段和所述奇数组复位单元输出端下拉阶段；
    所述奇数组复位单元的上拉节点下拉阶段和所述奇数组复位单元的输出端下拉阶段结束后，向所述第二奇数时钟信号线提供高电平信号，向所述第一奇数时钟信号线、所述第一偶数时钟信号线和所述第二偶数时钟信号线提供低电平信号，使得所述偶数组复位单元的所述第二薄膜晶体管和所述第十薄膜晶体管导通，以同时经过所述偶数组复位单元上拉节点下拉阶段和所述偶数组复位单元输出端下拉阶段。
  13. 根据权利要求7至12中任意一项所述的驱动方法，其中，复位阶段时钟信号的脉冲宽度为显示阶段脉冲信号宽度的一半。
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