WO2017154432A1 - 多層積層板及びこれを用いた多層プリント配線板の製造方法 - Google Patents
多層積層板及びこれを用いた多層プリント配線板の製造方法 Download PDFInfo
- Publication number
- WO2017154432A1 WO2017154432A1 PCT/JP2017/003966 JP2017003966W WO2017154432A1 WO 2017154432 A1 WO2017154432 A1 WO 2017154432A1 JP 2017003966 W JP2017003966 W JP 2017003966W WO 2017154432 A1 WO2017154432 A1 WO 2017154432A1
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- layer
- dielectric layer
- dielectric
- conductive layer
- multilayer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B32B7/02—Physical, chemical or physicochemical properties
- B32B7/025—Electric or magnetic properties
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
- B32B15/08—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/0047—Drilling of holes
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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- H05K3/4608—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated comprising an electrically conductive base or core
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- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- B32B3/26—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer
- B32B3/266—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer characterised by an apertured layer, the apertures going through the whole thickness of the layer, e.g. expanded metal, perforated layer, slit layer regular cells B32B3/12
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- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
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- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
- H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
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Definitions
- the present invention relates to a multilayer laminate. Moreover, this invention relates to the manufacturing method of the multilayer printed wiring board using this multilayer laminated board.
- a technique is known in which a capacitor structure is formed in a printed wiring board, particularly a multilayer printed wiring board, in the same manner as a circuit shape is formed using a copper clad laminate, and this is used as a built-in capacitor. Yes.
- the capacitor structure in the inner layer portion of the multilayer printed wiring board, the capacitor disposed on the outer layer surface can be omitted, and the outer layer circuit can be miniaturized and the density can be increased. As a result, the number of surface-mounted components is reduced, and it becomes easy to manufacture a printed wiring board having a fine pitch circuit.
- a seven-layer capacitive laminate in which conductive layers and dielectric layers are alternately arranged is known.
- this capacitive laminate as seen from the cross-sectional structures of FIGS. 6 to 9 of the document, a circuit pattern is formed in the conductive layer and a conductive via is formed in a portion where the circuit pattern is not formed.
- it is manufactured by repeating the steps of forming a circuit pattern on a conductive layer, forming a dielectric layer thereon, further forming a conductive layer thereon, and further forming a dielectric layer thereon. It is thought that.
- the capacitive laminate described in Patent Document 1 is produced by the process as described above, and in particular, by forming a dielectric layer on the conductive layer on which the circuit pattern is formed. Thus, it is not easy to make the thickness of the dielectric layer constant. In other words, it is not easy to make the capacitance of the dielectric layer constant. Further, the capacitive laminate described in the same document has a total of seven structures including four conductive layers, and due to the layer structure, the conductive layer that exposes the conductive layer located inside is provided It is not easy to connect.
- an object of the present invention is to improve a multilayer laminated board having a built-in capacitor, and more specifically, to provide a multilayer laminated board having a small variation in capacitance of the capacitor.
- the present invention includes a central conductive layer, a first dielectric layer and a second dielectric layer directly disposed on each surface of the central conductive layer, and a first outer surface disposed directly outside the first dielectric layer.
- a multilayer laminate comprising a conductive layer and a second outer conductive layer disposed directly outside the second dielectric layer, In the multilayer laminate, the first outer conductive layer and the second outer conductive layer constitute the outer surface of the multilayer laminate,
- the central conductive layer is formed in a solid state over the entire area in the in-plane direction of the multilayer laminate,
- the present invention provides a multilayer laminate in which the variation in the thickness of the first dielectric layer and the variation in the thickness of the second dielectric layer are each 15% or less.
- the present invention provides the above multilayer laminate, Forming a first through hole penetrating the multilayer laminate in the thickness direction; A non-conductive filler is completely filled in the formed first through hole, A method of manufacturing a multilayer printed wiring board having a step, wherein a second through hole having a smaller diameter than the first through hole is formed at a position filled with the filler so as to penetrate in a thickness direction of the multilayer laminated board. It is to provide.
- FIG. 1 is a cross-sectional view schematically showing a structure along the thickness direction of the multilayer laminate of the present invention.
- FIG. 2 is a schematic view showing a manufacturing process of the multilayer laminate shown in FIG. 3 (a) to 3 (c) are schematic views sequentially showing steps of manufacturing a multilayer printed wiring board using the multilayer laminate board shown in FIG. 4 (a) to 4 (c) are schematic views sequentially showing steps for manufacturing a multilayer printed wiring board, continuing from FIG. 3 (c).
- 5 (a) to 5 (c) are schematic diagrams sequentially showing steps for manufacturing a multilayer printed wiring board, continuing from FIG. 4 (c).
- 6 (a) and 6 (b) are schematic diagrams sequentially showing steps for manufacturing a multilayer printed wiring board, continuing from FIG. 5 (c).
- FIGS. 8A to 8C are schematic views sequentially showing steps for manufacturing a multilayer printed wiring board, continuing from FIG. 7C.
- 9 (a) and 9 (b) are schematic views sequentially showing steps for manufacturing a multilayer printed wiring board, continuing from FIG. 8 (c).
- FIG. 1 schematically shows a cross-sectional structure along the thickness direction of a multilayer laminate 10 according to an embodiment of the present invention.
- the multilayer laminated board 10 has a five-layer structure.
- the multilayer laminate 10 has a central conductive layer 11a at the center in the thickness direction.
- a first dielectric layer 12a and a second dielectric layer 12b are disposed on each surface of the central conductive layer 11a.
- the first dielectric layer 12a and the second dielectric layer 12b are directly disposed on the surface of the central conductive layer 11a.
- no layer is interposed between the central conductive layer 11a and the first dielectric layer 12a.
- no layer is interposed between the central conductive layer 11a and the second dielectric layer 12b.
- the outer surface of the first dielectric layer 12a that is, the surface located on the side of the two main surfaces of the first dielectric layer 12a that does not face the central conductive layer 11a, is the first outer conductive layer 13a. Is arranged.
- the second outer conductive layer 13b is disposed on the outer surface of the second dielectric layer 12b.
- the first outer conductive layer 13a is directly disposed on the outer surface of the first dielectric layer 12a. In other words, no layer is interposed between the first outer conductive layer 13a and the first dielectric layer 12a.
- the second outer conductive layer 13b is disposed directly on the outer surface of the second dielectric layer 12b, and no layer is interposed between the second outer conductive layer 13b and the second dielectric layer 12b. Is not intervening.
- the first outer conductive layer 13 a and the second outer conductive layer 13 b form the outer surface of the multilayer laminate 10.
- the outer surface of the first outer conductive layer 13a that is, the surface located on the side not facing the first dielectric layer 12a out of the two main surfaces of the first outer conductive layer 13a
- the layers are also not laminated.
- the outer surface of the second outer conductive layer 13b that is, the surface located on the side not facing the second dielectric layer 12b of the two main surfaces of the first outer conductive layer 13b, no layer is formed. Is not laminated. Since the multilayer laminate 10 has the above configuration, the multilayer laminate 10 has a five-layer structure as a whole as described above.
- the first dielectric layer 12a in the multilayer laminate 10 is preferably composed of the same material at any position of the dielectric layer 12a.
- a first material arbitrarily defined and a second region arbitrarily defined different from the first region may be a constituent material. May be different.
- the constituent material of the first dielectric layer 12a and the second dielectric layer 12b These constituent materials may be the same or different.
- first outer conductive layer 13a and the second outer conductive layer 13b are preferably made of the same material at any position.
- the constituent material is composed of an arbitrarily defined first region and an arbitrarily defined second region different from the first region. It may be different.
- the constituent material of the first outer surface conductive layer 13a and the second outer surface conductive layer 13b may be the same or different.
- the central conductive layer 11 a located in the central area in the thickness direction is formed in a “solid state” over the entire area in the in-plane direction of the multilayer laminate 10.
- the central conductive layer 11a is viewed in a plan view, there is no missing portion such as a hole (through hole) or a notch in the entire thickness direction at any position.
- the central conductive layer 11a has no defect in the entire thickness direction.
- These dielectric layers 12a and 12b can be formed so that their thickness is uniform. As a result, it is possible to effectively suppress variations in the capacitances of the dielectric layers 12a and 12b.
- the degree of thickness variation is measured by the method described below.
- the multilayer laminate 10 is preferably manufactured by the method shown in FIG. Specifically, first, the central conductive layer 11a is prepared. At the same time, a first element 14a and a second element 14b are prepared. The first element 14a is formed by forming a first dielectric layer 12a on one surface of the first outer conductive layer 13a. The second element 14b is formed by forming a second dielectric layer 12b on one surface of the second outer conductive layer 13b.
- the 1st element 14a and the 2nd element 14b are arrange
- the first dielectric layer 12a in the first element 14a is opposed to the central conductive layer 11a
- the second dielectric layer 12b in the second element 14b is opposed to the central conductive layer 11a.
- Elements 14a and 14b are arranged.
- the three members are pressurized under heating in the state.
- the first element 14a and the second element 14b are pressure-bonded to each surface of the central conductive layer 11a, and the multilayer laminated board 10 formed by integrating these three elements is obtained.
- the multilayer laminate 10 can be obtained by a simple operation of simply bonding the first element 14a and the second element 14b manufactured in advance to each surface of the central conductive layer 11a, the first dielectric Variations in thickness are less likely to occur in the body layer 12a and the second dielectric layer 12b. This makes it difficult for the first dielectric layer 12a and the second dielectric layer 12b to vary in capacitance.
- Each of the first element 14a and the second element 14b is formed by applying a resin composition containing dielectric particles and a resin to one surface of each of the first outer conductive layer 13a and the second outer conductive layer 13b. It is preferably manufactured by forming the first dielectric layer 12a and the second dielectric layer 12b.
- the resin composition may be applied.
- a thermosetting resin is used as the resin
- a resin composition containing a thermosetting resin and dielectric particles in an A-stage state and in a varnish-like fluid state is used. What is necessary is just to apply.
- the 1st element 14a and the 2nd element 14b are obtained by giving a heat
- the first element 14a and the second element 14b by such a method, the first dielectric layer 12a and the second dielectric layer 12b having a uniform thickness can be successfully formed.
- thermosetting resin As the resin contained in the first dielectric layer 12a and the second dielectric layer 12b, it is preferable to use a thermosetting resin as described above, and it is particularly preferable to use a highly insulating resin.
- a thermosetting resin the thing similar to what was used until now in the technical field of a printed wiring board can be used.
- the thermosetting resin include epoxy resin, polyimide resin, polyamide resin, polyphenylene ether resin, cyanate resin, maleimide resin, phenol resin, phenoxy resin, and styrene-butadiene resin.
- the thermosetting resin is preferably in the A stage or B stage state when in the state of the first element 14a and the second element 14b, and in the state of the C stage when in the state of the multilayer laminate 10. It is preferable.
- the first dielectric layer 12a and the second dielectric layer 12b are made of a fibrous material such as a glass woven fabric, a glass nonwoven fabric and paper for reinforcing the dielectric layers 12a and 12b, or a polyimide resin, for example.
- the film-like material, that is, the reinforcing material may be included, but it is preferable that the reinforcing material is not included.
- the reinforcing material is a useful material from the viewpoint of imparting strength to the dielectric layers 12a and 12b. On the other hand, however, the use of a reinforcing material has the disadvantage that the thickness of these dielectric layers 12a and 12b increases.
- a central conductive layer 11a and metal foils to be the first and second outer conductive layers 13a and 13b are prepared, and the first and second dielectric layers 12a and 12b are prepared.
- Two dielectric resin layers are prepared, and each dielectric edge resin layer is disposed between the central conductive layer 11a and the first outer conductive layer 13a and between the central conductive layer 11a and the second outer conductive layer 13b.
- a method of obtaining the multilayer laminate 10 by heating and pressurizing under these conditions and integrating them.
- the dielectric resin layer used in this method is obtained by dispersing dielectric particles in a thermosetting resin in a B-stage state.
- the dielectric resin layer can be composed of a sheet or film containing a thermosetting resin and dielectric particles.
- the dielectric edge resin layer needs to contain a thermosetting resin and impregnate a fibrous material such as glass woven fabric, glass nonwoven fabric and paper with a thermosetting resin in a B-stage state. It may be a laminated sheet or a laminated film in which a number of sheets are stacked. A film may be used instead of the fibrous material.
- the dielectric resin layer may contain an inorganic filler.
- the dielectric resin layer is in any form, for example, an epoxy resin, a cyanate resin, a maleimide resin, a polyphenylene ether resin, a phenol resin, a polyimide resin, or the like can be used as the thermosetting resin. .
- the relative dielectric constant of the first dielectric layer 12a and the second dielectric layer 12b is preferably 10 or more, more preferably 20 or more, and still more preferably 40 or more. By setting the relative dielectric constant to be equal to or higher than these values, it is possible to easily increase the capacitance while making the dielectric layers 12a and 12b thinner. These dielectric layers 12a and 12b preferably have a higher relative dielectric constant, but considering the adhesion to the central conductive layer 11a and the first and second outer conductive layers and the strength of the dielectric layers 12a and 12b. 300 or less, more preferably 200 or less, and even more preferably 100 or less.
- the relative permittivity mentioned here is a value measured by the split post dielectric resonance method (use frequency: 1 GHz).
- the dielectric layers 12a and 12b may include the above-described dielectric particles.
- the dielectric particles those having a relative dielectric constant of 50 to 20000 are preferably used.
- a composite oxide having a perovskite structure such as a ceramic based, a lead zirconate based ceramic, a barium zirconate based ceramic, or a calcium zirconate based ceramic can be used.
- barium titanate-based ceramics are preferably used in order to obtain a high dielectric constant, but may be selectively used according to the design quality of the multilayer laminate 10.
- the dielectric particles preferably have a particle size of 0.01 ⁇ m or more and 1.0 ⁇ m or less because the dielectric constant of the dielectric layer 11 can be kept constant regardless of location.
- the particle size referred to here is the volume cumulative particle size D 50 at a cumulative volume of 50% according to the laser diffraction scattering type particle size distribution measurement method.
- the ratio of the dielectric particles contained in the first dielectric layer 12a and the second dielectric layer 12b is independent from the viewpoint of balancing the improvement in capacitance and the strength of the dielectric layers 12a and 12b. It is preferably 60% by mass to 95% by mass, more preferably 60% by mass to 90% by mass, and still more preferably 70% by mass to 90% by mass. The ratio of the dielectric particles contained in these dielectric layers 12a and 12b can be measured from the mass of the remaining particles by sublimating the resin content in the dielectric layers 12a and 12b.
- a dielectric layer that does not contain a reinforcing material and is filled with a high concentration of dielectric particles is very brittle, so when the stress at the time of lamination is high, it cannot withstand that stress and cracks. May occur.
- stacking is possible without damaging the dielectric layer.
- breaking strain energy In the stress ⁇ -strain ⁇ curve in the tensile test of the resin film forming the dielectric layer, the breaking strain energy U (unit: MJ (megajoule)) is calculated by the following integral formula.
- epsilon b shows the strain at break.
- the breaking strain energy U of the dielectric layer is more typically 1.2 MJ or less, more typically 0.8 MJ or less, and further 0.5 MJ or less.
- the lower limit value of the breaking strain energy U is not particularly limited, but if it is 0.01 MJ or more, more preferably 0.02 MJ or more, the thickness uniformity of the dielectric layers 12a and 12b in the multilayer laminate of the present invention is as follows. It can be secured sufficiently.
- the value of the breaking strain energy U is preferably satisfied by one of the dielectric layers 12a and 12b in the multilayer laminate of the present invention, and more preferably by both.
- the dielectric layer having a low breaking strain energy has a property of lowering the tensile strength.
- the tensile strength of the dielectric layer exhibiting a high relative dielectric constant is typically 60.0 MPa or less, more preferably 55.0 MPa or less, and particularly 50.0 MPa or less. The effect is exhibited more advantageously.
- the tensile strength of the dielectric layer is preferably 5.0 MPa or more, more preferably 8.0 MPa or more, from the viewpoint of sufficiently ensuring the adhesion between the dielectric layer and the conductive layer. This tensile strength value is preferably satisfied by one of the dielectric layers 12a and 12b in the multilayer laminate of the present invention, and more preferably by both.
- the dielectric layer has a low tensile elongation at break (breaking strain) of 5.0% or less, further 4.0% or less, and particularly 1.0% or less, the effect of the present invention is further enhanced. It is beneficial.
- the tensile breaking elongation (breaking strain) of the dielectric layer is preferably 0.05% or more from the viewpoint of maintaining flexibility sufficient to withstand handling at the time of manufacturing a printed wiring board. More preferably, it is 0.2% or more.
- the tensile elongation at break is preferably satisfied by one of the dielectric layers 12a and 12b in the multilayer laminate of the present invention, and more preferably by both.
- breaking strain energy, tensile strength and tensile breaking elongation are in accordance with JIS K 7161 (1994) “Plastics—Testing method for tensile properties”, measuring temperature is 25 ° C., distance between gauge points is 50 mm, and tensile speed. The value obtained from the stress-strain curve when measured at 1.0 mm / min (2% / min as the strain rate) is adopted as the standard condition. In addition, when the sample length of a dielectric material layer is remarkably short and the distance between the above-mentioned reference points cannot be taken, it can also measure by the method set to 2% / min of strain rates.
- Indentation elastic modulus Eit Another physical property value indicating the brittleness of the dielectric layer is the indentation elastic modulus Eit.
- Indentation modulus Eit dielectric layer 4800N / mm 2 or more, further 6000 N / mm 2 or more, in particular 8000 N / mm 2 or more and becomes higher the typical.
- This indentation elastic modulus Eit a value measured by a nanoindentation method in accordance with ISO14577 (2015) is adopted.
- the value of the indentation elastic modulus Eit is preferably satisfied by one of the dielectric layers 12a and 12b in the multilayer laminate of the present invention, and more preferably satisfied by both.
- the thicknesses of these dielectric layers 12a and 12b are determined at the stage of product design and circuit design, and are determined in consideration of the required level in the market. In the present invention, the thicknesses of the first dielectric layer 12a and the second dielectric layer 12b are each independently preferably 30 ⁇ m or less, more preferably 16 ⁇ m or less, particularly preferably 12 ⁇ m or less, and most preferably 8 ⁇ m or less.
- the thickness of these dielectric layers 12a and 12b there is no limitation on the lower limit of the thickness of these dielectric layers 12a and 12b, as long as the adjacent conductive layers are not short-circuited.
- it is preferably 0.1 ⁇ m or more independently, and more preferably 0.5 ⁇ m or more in order to prevent the above-described short circuit more reliably.
- the first dielectric layer 12a and the second dielectric layer 12b each have a small variation in thickness measured at a plurality of arbitrary positions, provided that the first dielectric layer 12a and the second dielectric layer 12b have a thickness in the above-described range. This is because variation in the thickness of the capacitors formed from these dielectric layers 12a and 12b is less likely to occur due to the small variation in thickness. From this viewpoint, the dielectric layers 12a and 12b each have a thickness variation of preferably 15% or less, more preferably 10% or less, and still more preferably 8% or less.
- the variation in the thickness of these dielectric layers 12a and 12b is a cross section in the thickness direction of the center of the first dielectric layer 12a or the second dielectric layer 12b and its end portions (for example, four corners if the dielectric layer is rectangular).
- Magnified observation for example, magnification of 500 times or more to measure a total of at least 10 points, find the maximum value, minimum value, and average value, numerical values (units) represented by the following (1) and (2) :%) Is a value defined by a numerical value with a large value. [100 ⁇ (maximum value ⁇ average value) / average value] (1) [100 ⁇ (average value ⁇ minimum value) / average value] (2)
- each of the first dielectric layer 12a and the second dielectric layer 12b has a small thickness variation.
- the first dielectric layer 12a and the second dielectric layer 12b may have the same thickness or may be different.
- the difference between the relative dielectric constant of the first dielectric layer 12a and the relative dielectric constant of the second dielectric layer 12b is preferably small.
- the difference between the relative dielectric constant ⁇ a of the first dielectric layer 12a and the relative dielectric constant ⁇ b of the second dielectric layer 12b is preferably 10% or less, more preferably 5% or less, and 3%. More preferably, it is as follows.
- the difference between the relative dielectric constants ⁇ a and ⁇ b of both the dielectric layers 12a and 12b is small, the design when manufacturing the multilayer printed wiring board using the multilayer laminated board 10 becomes easy. From this viewpoint, it is particularly preferable that the first dielectric layer 12a and the second dielectric layer 12b have the same thickness. It is particularly preferable that the first dielectric layer 12a and the second dielectric layer 12b have the same composition (composition of the resin composition) constituting them.
- the difference between the relative dielectric constants ⁇ a and ⁇ b of both dielectric layers 12a and 12b is defined by [(
- the central conductive layer 11a, the first outer conductive layer 13a, and the second outer conductive layer 13b sandwiching the first dielectric layer 12a and the second dielectric layer 12b are not particularly limited in thickness, and may be thin or thick. Also good.
- the thicknesses of these conductive layers 11a, 13a, and 13b are preferably set independently from, for example, 0.1 ⁇ m to 70 ⁇ m.
- the thicknesses and / or types of the conductive layers 11a, 13a, and 13b may be the same or different.
- these conductive layers 11a, 13a, and 13b are preferably made of metal foil from the viewpoint of the manufacturing process. Such metal foil may be any of rolled foil, electrolytic foil, and vapor phase foil.
- the metal foil is a copper foil, but other metal foils may be used.
- the conductive layers 13a and 13b may be provided with an electric resistance layer (for example, a layer made of Ni-P, Ni-Cr, etc.) on the surface facing the dielectric layer 12.
- the dielectric layer The roughness of the surface facing 12a, 12b is preferably low. From this point of view, the opposing surfaces of the first and second dielectric layers 12a, 12b in the conductive layers 11a, 13a, 13b have their surface roughness expressed by a ten-point average roughness Rz (JIS B0601-1994). Rz is preferably 1.5 ⁇ m or less, more preferably 1.0 ⁇ m or less, and even more preferably no roughening treatment.
- the central conductive layer 11a preferably has a difference in Rz between both surfaces of 1.0 ⁇ m or less, and more preferably 0.5 ⁇ m or less. Since the central conductive layer 11a faces both the dielectric layers 12a and 12b, the thickness of the first and second dielectric layers 12a and 12b is reduced by reducing the difference in roughness between the both surfaces of the central conductive layer 11a. Can be made more uniform.
- the multilayer laminated board 10 having the configuration as described above is suitably used as a material for manufacturing a multilayer printed wiring board. Accordingly, a preferred method for manufacturing a multilayer printed wiring board using the multilayer laminate 10 will be described below.
- first through holes 15 penetrating the multilayer laminated plate 10 over the entire thickness direction are formed at predetermined positions in the multilayer laminated plate 10.
- a drilling means known in the technical field such as a drill can be used as appropriate.
- an appropriate value is selected according to the specific use of the target multilayer printed wiring board.
- a filler 16 is filled into the first through hole 15 formed by perforation.
- a non-conductive material is preferably used.
- the non-conductive material here means a volume resistivity of the material is 1 ⁇ 10 7 ⁇ ⁇ cm or more at 25 ° C..
- it is easy to use a resin and it is particularly preferable to use various thermosetting resins exemplified as the resins constituting the dielectric layers 12a and 12b.
- the first through hole 15 is filled with a thermosetting resin in an A-stage state, and this is then cured.
- a filler 16 made of a cured resin is formed in the first through hole 15.
- the first through hole 15 is completely filled with the filler 16.
- the second through hole 17 is formed as shown in FIG.
- the second through hole 17 is formed at a position where the filler 16 is filled.
- the second through-hole 17 is formed so as to penetrate the multilayer laminate 10 in the thickness direction.
- the shape of the second through hole 17 is preferably similar to the shape of the first through hole 15.
- the second through hole 17 and the first through hole 15 are both circular (true circles).
- the second through hole 17 has a smaller diameter than the first through hole 15.
- the second through hole 17 is preferably formed so that the centroid of the first through hole 15 and the centroid of the second through hole 17 coincide with each other in plan view of the multilayer laminate 10.
- the second through hole 17 and the first through hole 15 in the plan view of the multilayer laminate 10 are both circular
- the second through hole is so arranged that the through holes 17 and 15 are concentric. 17 is preferably formed.
- the shape of the filler 16 after the second through hole 17 is formed changes from a columnar shape to a cylindrical shape. Therefore, the inner wall of the second through hole 17 is made of a nonconductive material.
- the third conductive layers 18a and 18b are formed on the outer surfaces of the first and second outer conductive layers 13a and 13b in the multilayer laminate 10.
- a fourth conductive layer 19 is formed on the inner wall of the second through hole 17.
- the fourth conductive layer 19 is formed so as to be electrically connected to the two third conductive layers 18a and 18b. Since the 4th conductive layer 19 is formed in the surface of the filler 16 comprised from a nonelectroconductive material, the 4th conductive layer 19 and the center conductive layer 11a are insulated with a filler, and become non-conducting.
- an electroless plating method is used to form the third conductive layers 18a and 18b and the fourth conductive layer 19, but the method is not limited thereto.
- patterning for circuit formation is performed on the multilayer laminate 10.
- a process of forming a circuit by patterning the first and second outer conductive layers 13a and 13b including the third conductive layers 18a and 18b is shown.
- various lithography methods known in the art can be appropriately used.
- the third conductive layers 18a and 18b and the first and second outer conductive layers 13a and 13b are partially removed for patterning, the first conductive layer 13a is at least one of the removed portions on the first outer conductive layer 13a side. It is preferable to perform patterning so that the first missing portion Ra and the second missing portion Rb, which is at least one of the removed portions on the second outer surface conductive layer 13b side, overlap in a plan view of the multilayer laminate 10. .
- the insulating resin layer 20 is laminated on each surface of the multilayer laminate 10 as shown in FIG.
- the resin contained in the insulating resin layer 20 serves as a filler, so that the inside of the second through hole 17 is completely filled, and each surface of the multilayer laminate 10 is completely covered with the insulating resin layer 20.
- the insulating resin layer 20 those known in the technical field can be used without particular limitation. Since the insulating resin layer 20 generally includes a B-stage thermosetting resin as a non-conductive material, in the lamination using the insulating resin layer 20, the insulating resin layer 20 is heated to produce the insulating resin layer 20.
- the layer 20 is preferably bonded to the multilayer laminate 10.
- the insulating resin layer may be (a) a required number of prepregs impregnated with an insulating resin in a fibrous material such as glass woven fabric, glass nonwoven fabric and paper.
- the insulating resin to be impregnated include epoxy resin, cyanate resin, maleimide resin, polyphenylene ether resin, phenol resin, and polyimide resin.
- an insulating resin layer (that is, a layer not including a fibrous material) made of an insulating resin such as an epoxy resin, a polyimide resin, or a polyester resin may be used.
- the inorganic filler in the insulating resin layer can be contained.
- the filler filled in the second through hole 17 is an insulating resin and an inorganic filler.
- the fifth conductive layers 21a and 21b are formed on each surface of the insulating resin layer 20, respectively.
- Both the fifth conductive layers 21a and 21b can be made of, for example, a metal foil.
- the insulating resin layers 20 and 20 and the fifth conductive layers 21a and 21b can be stacked by various methods. For example, first, the semi-cured B-stage insulating resin layers 20 and 20 are laminated on each surface of the multilayer laminate 10, and the fifth conductive layers 21a and 21b are laminated thereon. Then, the insulating resin layer 20 is cured by pressing under heating, and these three are joined and integrated. Further, instead of separately preparing the insulating resin layers 20 and 20 and the fifth conductive layers 21a and 21b, these layers may be laminated with a metal foil with resin.
- patterning is performed on the fifth conductive layer 21b. This patterning is performed in order to form a conformal mask for drilling the insulating resin layer 20. A part of the fifth conductive layer 21b is removed by patterning to form a third missing portion Rc.
- the insulating resin layer 20 is punched with a laser beam through the missing portion Rc removed by the patterning in the fifth conductive layer 21b. Drilling the insulating resin layer 20 is performed so that the third conductive layer 18b is exposed.
- the third through hole 22 penetrating over the entire thickness direction is formed as shown in FIG. 5C.
- the third through hole 22 is formed by removing the conductive layers 13a and 13b from the circuit pattern formed on the first outer conductive layers 13a and 13b in the step shown in FIG. This is performed for the first missing portion Ra and the second missing portion Rb, which are the formed portions.
- sixth conductive layers 23a and 23b are formed on the outer surfaces of the fifth conductive layers 21a and 21b as shown in FIG.
- the sixth conductive layer 23b is also formed on the side surface of the hole 25 formed in the fifth conductive layer 21b and the insulating resin layer 20, and connects the sixth conductive layer 23b and the exposed third conductive layer 18b.
- a seventh conductive layer 24 is formed on the inner wall of the third through hole 22.
- the seventh conductive layer 24 is formed so as to be electrically connected to the two sixth conductive layers 23a and 23b.
- the seventh conductive layer 24 is formed on the side surface of the third through hole 22 so as to be electrically connected to the fifth conductive layers 21a and 21b and the central conductive layer 11a.
- an electroless plating method is used to form the sixth conductive layers 23a and 23b and the seventh conductive layer 24, but the method is not limited thereto.
- the connection between the sixth conductive layer 23b and the seventh conductive layer 24 is disconnected.
- the cutting can be performed, for example, by patterning the sixth conductive layer 23b.
- the cut portion is on the fifth conductive layer 21b.
- known means such as laser light irradiation or etching can be used.
- a hole 26 is formed in the sixth conductive layer 23b and the fifth conductive layer 21b in the thickness direction so that the surface of the insulating resin layer 20 is exposed. As a result, the connection between the sixth conductive layer 23b and the fifth conductive layer 21b and the seventh conductive layer 24 is disconnected.
- the first and second dielectric layers 12a and 12b are respectively composed of the central conductive layer 11a and the first and second outer conductive layers.
- a built-in capacitor is formed by being disposed between 13a and 13b.
- the central conductive layer 11 a is connected to the sixth conductive layer 23 a exposed on one surface of the multilayer printed wiring board 100 through the seventh conductive layer 24.
- the first and second outer conductive layers 13 a and 13 b are connected to the sixth conductive layer 23 b exposed on the other surface of the multilayer printed wiring board 100 through the third conductive layers 18 a and 18 b and the fourth conductive layer 19. Connected. Therefore, the built-in capacitor can function by applying a voltage between the sixth conductive layers 23a and 23b.
- the multilayer printed wiring board 100 having the built-in capacitors can be obtained without impairing the thickness uniformity of the first and second dielectric layers 12 a and 12 b. Therefore, this built-in capacitor has a suppressed variation in its capacitance. Further, the central conductive layer 11a and the first and second outer conductive layers 13a and 13b in the multilayer laminate 10 can be easily connected to an external conductive layer.
- the manufacturing method of this embodiment is the same process up to FIG. 3A in the above-described embodiment. Then, after the step shown in FIG. 3A, patterning for circuit formation is performed on the multilayer laminate 10 as shown in FIG. 7A. In the figure, a step of patterning the first and second outer conductive layers 13a and 13b to form a circuit is shown.
- the first missing portion Ra which is at least one of the removed portions on the first outer conductive layer 13a side
- the second missing portion Rb which is at least one of the removed portions on the outer surface conductive layer 13b side
- the insulating resin layer 20 is laminated on each surface of the multilayer laminate 10 as shown in FIG. Thereby, the resin contained in the insulating resin layer 20 serves as a filler, and the first through hole 15 is completely filled, and each surface of the multilayer laminate 10 is completely covered with the insulating resin layer 20.
- the insulating resin layer 20 can contain an inorganic filler as in the embodiment shown in FIG.
- the filler filled in the first through hole 15 is an insulating resin and an inorganic filler.
- the fifth conductive layers 21a and 21b are patterned. This patterning is performed in order to form a conformal mask for drilling the insulating resin layer 20. Part of the fifth conductive layers 21a and 21b is removed by patterning to form a third missing portion Rc.
- a laser is applied to the insulating resin layer 20 through the third missing portion Rc (see FIG. 7C) of the fifth conductive layers 21a and 21b removed by the patterning. Drilling with light. Drilling into the insulating resin layer 20 is performed so that the first and second outer conductive layers 13a and 13b are exposed.
- the second through hole 17 is formed.
- the second through hole 17 is formed at a position where the first through hole 15 is filled with the insulating resin layer 20.
- the second through hole 17 is formed so as to penetrate through the multilayer laminated plate 10 in the entire thickness direction.
- the second through hole 17 has a smaller diameter than the first through hole 15.
- the second through hole 17 is preferably formed so that the centroid of the first through hole 15 and the centroid of the second through hole 17 coincide with each other in plan view of the multilayer laminate 10.
- the shape of the insulating resin layer 20 in the first through hole 15 after the second through hole 17 is formed changes from a columnar shape to a cylindrical shape. Therefore, the inner wall of the second through hole 17 is made of a non-conductive material.
- the third through hole 22 is formed.
- the third through hole 22 is formed so as to penetrate through the entire thickness direction of the multilayer laminate 10.
- the formation of the third through hole 22 is performed, for example, by removing the conductive layers 13a and 13b from the circuit pattern formed on the first outer conductive layers 13a and 13b in the step shown in FIG. This is performed for the first missing portion Ra and the second missing portion Rb, which are the formed portions.
- the diameter of the third through hole 22 is preferably the same as the diameter of the second through hole 17 formed previously.
- the third conductive layers 18a and 18b are formed on the outer surfaces of the fifth conductive layers 21a and 21b as shown in FIG. 9A.
- the third conductive layers 18a and 18b are also formed on the side surfaces of the holes 25 formed in the fifth conductive layer 21b and the insulating resin layer 20, and the third conductive layers 18a and 18b and the exposed first and first conductive layers are formed.
- the outer surface conductive layers 13a and 13b are connected.
- the fourth conductive layer 19 is formed on the inner wall of the second through hole 17, and the seventh conductive layer 24 is formed on the inner wall of the third through hole 22.
- the fourth conductive layer 19 is formed so as to be electrically connected to the two third conductive layers 18a and 18b.
- the seventh conductive layer 24 is formed to be electrically connected to the two third conductive layers 18a and 18b. Since the fourth conductive layer 19 is formed on the surface of the insulating resin layer 20 made of a nonconductive material, the fourth conductive layer 19 and the central conductive layer 11a are insulated by the insulating resin layer 20 and become non-conductive. . On the other hand, since the seventh conductive layer 24 is formed directly on the inner wall of the third through hole 22, the central conductive layer 11a exposed on the inner wall of the third through hole 22 and the seventh conductive layer 24 are electrically connected. .
- the connection between the third conductive layers 18a and 18b and the seventh conductive layer 24 is disconnected.
- the cutting can be performed, for example, by patterning the third conductive layers 18a and 18b by etching or the like.
- the locations where these connections are disconnected are on the fifth conductive layers 21a and 21b.
- holes 26 are formed in the third conductive layers 18a and 18b and the fifth conductive layers 21a and 21b in the thickness direction so that the surface of the insulating resin layer 20 is exposed. To do.
- the connection between the third conductive layers 18 a and 18 b and the fifth conductive layers 21 a and 21 b and the seventh conductive layer 24 is disconnected.
- the first and second dielectric layers 12a and 12b are respectively composed of the central conductive layer 11a and the first and second outer conductive layers.
- a built-in capacitor is formed by being disposed between 13a and 13b.
- the central conductive layer 11 a is connected to the third conductive layers 18 a ′ and 18 b ′ exposed on the outer surface of the multilayer printed wiring board 100 through the seventh conductive layer 24.
- the first and second outer conductive layers 13a and 13b are directly connected to the third conductive layers 18a "and 18b". Therefore, the built-in capacitor can function by applying a voltage between the third conductive layers 18a 'and 18b' and the third conductive layers 18a "and 18b".
- the use of the multilayer laminated board 10 makes it possible to incorporate the first and second dielectric layers 12a and 12b without impairing the thickness uniformity.
- a multilayer printed wiring board 100 having a capacitor is obtained. Therefore, this built-in capacitor has a suppressed variation in its capacitance.
- the third missing portion Rc is formed by removing a part of the fifth conductive layers 21a and 21b in order to form a conformal mask.
- the third missing portion Rc may not be formed.
- the third through hole 22 is formed after the second through hole 17 is formed, but this order may be reversed. Alternatively, the second through hole 17 and the third through hole 22 may be formed simultaneously. These through holes 17 and 22 can generally be formed using a drill.
- a multilayer laminated board in which the variation in the capacitance of the built-in capacitor is suppressed.
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Abstract
Description
前記多層積層板においては、第1外面導電層及び第2外面導電層が、該多層積層板の外面をなし、
前記中央導電層は、前記多層積層板の面内方向の全域にわたり、べた状態で形成されており、
第1誘電体層の厚みのばらつき及び第2誘電体層の厚みのばらつきが、それぞれ独立に15%以下である、多層積層板を提供するものである。
前記多層積層板をその厚み方向に貫通する第1スルーホールを形成し、
形成された第1スルーホール内に非導電性の充填剤を完全充填し、
第1スルーホールよりも小径の第2スルーホールを、前記充填剤が充填された位置に、前記多層積層板の厚み方向に貫通するように形成する、工程を有する多層プリント配線板の製造方法を提供するものである。
前記脆さを示す物性値としては、破断ひずみエネルギーを採用することが好適である。誘電体層を形成する樹脂フィルムの引張試験における応力σ-ひずみε曲線において、破断ひずみエネルギーU(単位:MJ(メガジュール))は、下記積分式によって算出される。なお、εbは破断時のひずみを示す。
一方で、誘電体層と、導電層との密着性を十分に確保する点では、誘電体層の引張強度は、5.0MPa以上であることが好ましく、より好ましくは8.0MPa以上である。
この引張強度の値は、本発明の多層積層板における誘電体層12a,12bのいずれか一方で満たされることが好ましく、双方で満たされることが更に好ましい。
一方で、プリント配線板製造時のハンドリングに最低限耐え得るだけの可撓性を保持する点では、誘電体層の引張破断伸び率(破断ひずみ)は、0.05%以上であることが好ましく、より好ましくは0.2%以上である。
この引張破断伸び率の値は、本発明の多層積層板における誘電体層12a,12bのいずれか一方で満たされることが好ましく、双方で満たされることが更に好ましい。
なお、上述した破断ひずみエネルギー、引張強度及び引張破断伸び率は、JISK7161(1994)「プラスチック-引張特性の試験方法」に準拠し、測定温度を25℃、標点間の距離を50mm、引張速度を1.0mm/min(ひずみ速度として2%/min)で測定したときの応力ひずみ曲線から求めた値を標準条件として採用するものとする。なお、誘電体層の試料長が著しく短く、上述した標点間の距離が取れない場合は、ひずみ速度2%/minとした方法で測定することも可能である。
これらの誘電体層12a,12bの厚みのばらつきは、第1誘電体層12a又は第2誘電体層12bの中心とその端部(例えば誘電体層が矩形であれば四隅)の厚み方向の断面を拡大観察(例えば500倍以上に拡大)することで合計で最低10点を測定し、その最大値、最小値及び平均値を求め、下記(1)及び(2)で表される数値(単位:%)のうち、値の大きい数値によって定義される値である。
〔100×(最大値-平均値)/平均値〕 (1)
〔100×(平均値-最小値)/平均値〕 (2)
絶縁樹脂層20,20及び第5導電層21a,21bの積層は種々の方法で行うことができる。例えば、まず多層積層板10の各面に対して、半硬化のBステージ状態の絶縁樹脂層20,20を積層するとともに、その上に第5導電層21a,21bを積層する。そして、加熱下にプレスすることで絶縁樹脂層20が硬化してこれら三者が接合一体化される。また、絶縁樹脂層20,20及び第5導電層21a,21bを別途用意することに代えて、これらの積層を樹脂付金属箔によって行ってもよい。
11a 中央導電層
12a 第1誘電体層
12b 第2誘電体層
13a 第1外面導電層
13b 第2外面導電層
14a 第1エレメント
14b 第2エレメント
15 第1スルーホール
16 充填剤
17 第2スルーホール
18a,18b 第3導電層
19 第4導電層
20 絶縁樹脂層
21a,21b 第5導電層
22 第3スルーホール
23a,23b 第6導電層
24 第7導電層
25,26 穴
100 多層プリント配線板
Ra 第1欠落部
Rb 第2欠落部
Rc 第3欠落部
Claims (9)
- 中央導電層と、該中央導電層の各面にそれぞれ直接配置された第1誘電体層及び第2誘電体層と、第1誘電体層の外側に直接配置された第1外面導電層と、第2誘電体層の外側に直接配置された第2外面導電層とを備えた多層積層板であって、
前記多層積層板においては、第1外面導電層及び第2外面導電層が、該多層積層板の外面をなし、
前記中央導電層は、前記多層積層板の面内方向の全域にわたり、べた状態で形成されており、
第1誘電体層の厚みのばらつき及び第2誘電体層の厚みのばらつきが、それぞれ独立に15%以下である、多層積層板。 - 第1誘電体層の比誘電率と第2誘電体層の比誘電率との差が10%以下である請求項1に記載の多層積層板。
- 第1誘電体層の厚み及び第2誘電体層の厚みが、それぞれ独立に0.1μm以上30μm以下である請求項1又は2に記載の多層積層板。
- 第1誘電体層の厚みと第2誘電体層の厚みとが同じである請求項3に記載の多層積層板。
- 第1誘電体層及び第2誘電体層がそれぞれ誘電体粒子及び樹脂を含み、これらの誘電体層に占める該誘電体粒子の割合が、それぞれ独立に60質量%以上95質量%以下である請求項1ないし4のいずれか一項に記載の多層積層板。
- 第1誘電体層の組成と第2の誘電体層の組成とが同じである請求項5に記載の多層積層板。
- 第1誘電体層及び第2誘電体層の応力σ-ひずみε曲線における破断ひずみエネルギーが、それぞれ1.8MJ以下である、請求項1ないし6のいずれか一項に記載の多層積層板。
- 前記各導電層がいずれも銅箔からなり、その厚みがそれぞれ独立に0.1μm以上70μm以下である請求項1ないし7のいずれか一項に記載の多層積層板。
- 請求項1に記載の多層積層板を用意し、
前記多層積層板をその厚み方向に貫通する第1スルーホールを形成し、
形成された第1スルーホール内に非導電性の充填剤を完全充填し、
第1スルーホールよりも小径の第2スルーホールを、前記充填剤が充填された位置に、前記多層積層板の厚み方向に貫通するように形成する、工程を有する多層プリント配線板の製造方法。
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| MYPI2018702988A MY191270A (en) | 2016-03-10 | 2017-02-03 | Multilayer laminate and method for producing multilayer printed wiring board using same |
| CN201780015169.6A CN108781517B (zh) | 2016-03-10 | 2017-02-03 | 多层层叠板以及使用其的多层印刷电路板的制造方法 |
| KR1020187024746A KR102737460B1 (ko) | 2016-03-10 | 2017-02-03 | 다층 적층판 및 이것을 이용한 다층 프린트 배선판의 제조 방법 |
| US16/082,393 US11285700B2 (en) | 2016-03-10 | 2017-02-03 | Multilayer laminate and method for producing multilayer printed wiring board using same |
| JP2018504056A JP6916165B2 (ja) | 2016-03-10 | 2017-02-03 | 多層積層板及びこれを用いた多層プリント配線板の製造方法 |
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| PCT/JP2016/057563 WO2017154167A1 (ja) | 2016-03-10 | 2016-03-10 | 多層積層板及びこれを用いた多層プリント配線板の製造方法 |
| JPPCT/JP2016/057563 | 2016-03-10 |
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| WO2017154432A1 true WO2017154432A1 (ja) | 2017-09-14 |
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| PCT/JP2017/003966 Ceased WO2017154432A1 (ja) | 2016-03-10 | 2017-02-03 | 多層積層板及びこれを用いた多層プリント配線板の製造方法 |
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| US (1) | US11285700B2 (ja) |
| JP (1) | JP6916165B2 (ja) |
| KR (1) | KR102737460B1 (ja) |
| CN (1) | CN108781517B (ja) |
| MY (1) | MY191270A (ja) |
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| CN117120536A (zh) * | 2021-03-24 | 2023-11-24 | 松下知识产权经营株式会社 | 树脂组合物、预浸料、带树脂的膜、带树脂的金属箔、覆金属箔层压板、以及布线板 |
| EP4081005A1 (en) | 2021-04-23 | 2022-10-26 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier |
| WO2023218801A1 (ja) * | 2022-05-13 | 2023-11-16 | 株式会社村田製作所 | コンデンサ |
| US12250771B2 (en) | 2022-07-21 | 2025-03-11 | Rockwell Collins, Inc. | Capacitor bank assembly |
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| Publication number | Publication date |
|---|---|
| TW201732849A (zh) | 2017-09-16 |
| MY191270A (en) | 2022-06-13 |
| JPWO2017154432A1 (ja) | 2019-01-10 |
| CN108781517B (zh) | 2021-10-26 |
| CN108781517A (zh) | 2018-11-09 |
| US20190110364A1 (en) | 2019-04-11 |
| KR20180120682A (ko) | 2018-11-06 |
| TWI702621B (zh) | 2020-08-21 |
| WO2017154167A1 (ja) | 2017-09-14 |
| JP6916165B2 (ja) | 2021-08-11 |
| US11285700B2 (en) | 2022-03-29 |
| KR102737460B1 (ko) | 2024-12-04 |
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