WO2014178356A1 - ハイブリッド基板の製造方法及びハイブリッド基板 - Google Patents
ハイブリッド基板の製造方法及びハイブリッド基板 Download PDFInfo
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- WO2014178356A1 WO2014178356A1 PCT/JP2014/061807 JP2014061807W WO2014178356A1 WO 2014178356 A1 WO2014178356 A1 WO 2014178356A1 JP 2014061807 W JP2014061807 W JP 2014061807W WO 2014178356 A1 WO2014178356 A1 WO 2014178356A1
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Images
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
Definitions
- the present invention relates to a method for manufacturing a hybrid substrate having an SOI (Silicon on Insulator) structure and a hybrid substrate.
- SOI Silicon on Insulator
- B-SOS Bionded-Silicon on Sapphire
- a “hydrogen ion implantation method” using hydrogen ion implantation is known.
- Surface activated, hydrogen ion-implanted silicon substrate and sapphire substrate are bonded together, and appropriate mechanical means such as water jet injection, light irradiation, etc. are driven into the hydrogen ion-implanted interface.
- a method of forming a thin silicon film by mechanical peeling at the interface is known.
- the point is how far the silicon substrate is ground or how to trim the outer periphery of the bonded substrate.
- the trimming technique is the main.
- the trimming timing after grinding the bonded wafer, the outer periphery is trimmed, and after trimming, the outer periphery is obtained by chemical etching.
- a method has been proposed for processing both the part and the effective part. Conventionally, trimming was performed before grinding and thinning, but it is effective to trim after thinning by grinding. It is said that there is.
- hybrid substrates are a combination of materials having a different coefficient of thermal expansion relative to Si used as a semiconductor layer. It is known that production is difficult due to the difference in expansion coefficient.
- the following methods are known.
- hydrogen ions are implanted into a silicon wafer on which an oxide film has been formed by thermal oxidation, etc., bonded to a support substrate, subjected to a bonding heat treatment, and then heat is applied to perform thermal separation.
- the implanted gas is formed as a microbubble layer inside the substrate by performing a heat treatment at a high temperature, and the bubble layer is expanded to be peeled off. For this reason, high-temperature heat treatment is essential, and it is difficult to apply to a substrate having a difference in thermal expansion coefficient.
- the part where the stress is applied locally is the outer peripheral part and the peeling end part where the bonding surface of the bonded substrate is interrupted, and the edge of the silicon thin film becomes jagged or fine pits (small film thickness fluctuations). ) May occur.
- hydrogen ions are implanted, and separation (separation) is performed from a defect layer generated from the hydrogen ions (ion implantation separation method).
- separation is performed from a defect layer generated from the hydrogen ions (ion implantation separation method).
- a defect spreading from the defect layer or a defect due to diffusion of hydrogen gas species. May cause problems.
- defects may occur in high temperature processing such as thermal oxidation processing.
- the present invention has been made in view of the above circumstances, and is a method for manufacturing a hybrid substrate by bonding an SOI substrate, an SOI substrate such as a sapphire substrate, and a support substrate having a different coefficient of thermal expansion.
- the manufacturing method of an SOI structure hybrid substrate having a high-quality silicon active layer without a defect such as partial delamination of the silicon active layer in the outer periphery of the substrate without trimming the periphery of the substrate An object is to provide a hybrid substrate.
- the present invention provides the following method for manufacturing a hybrid substrate and a hybrid substrate.
- An SOI substrate is prepared in which a first silicon oxide film and a silicon active layer are stacked in this order on a silicon substrate, and a terrace portion having no silicon active layer is formed on the outer peripheral portion of the silicon substrate surface.
- the thickness of the silicon substrate after the final grinding thinning treatment is reduced to 60 ⁇ m at the minimum, and the above-described bonding heat treatment and grinding thinning treatment are performed.
- the thinned silicon substrate is removed by etching to expose the first silicon oxide film, Furthermore, the exposed first silicon oxide film is removed by etching to obtain a hybrid substrate having a silicon active layer on the support substrate via the silicon oxide film.
- the bonding heat treatment temperature for increasing the bonding force between the SOI substrate and the support substrate is a temperature obtained by adding 0 to 100 ° C. to the bonding temperature (however, less than 250 ° C.) [1] Or the manufacturing method of the hybrid substrate of [2]. [4] The method for manufacturing a hybrid substrate according to any one of [1] to [3], wherein the second and subsequent bonding heat treatment temperatures are higher than the previous bonding heat treatment temperature. [5] The hybrid substrate according to any one of [1] to [3], wherein when the temperature of the first bonding heat treatment is 200 ° C. or higher and lower than 250 ° C., the second and subsequent bonding heat treatments are omitted. Manufacturing method.
- a method for manufacturing a hybrid substrate [10] The method for manufacturing a hybrid substrate according to any one of [1] to [9], wherein the support substrate is made of quartz glass, borosilicate glass, or sapphire. [11] The hybrid substrate according to any one of [1] to [10], wherein the support substrate is subjected to heat treatment in a reducing atmosphere before the SOI substrate and the support substrate are bonded to each other. Production method. [12] The hybrid substrate according to any one of [1] to [11], wherein an outer peripheral region having a predetermined width of a surface to be bonded to the SOI substrate of the support substrate is thinned so as to be recessed from a central portion. Manufacturing method. [13] A hybrid substrate produced by the method for producing a hybrid substrate according to any one of [1] to [12], having a silicon active layer on a support substrate via a silicon oxide film.
- the heat treatment temperature is increased by an amount corresponding to heating and bonding to a predetermined temperature, thereby increasing the bonding force between the SOI substrate and the support substrate.
- the grinding conditions it is possible to thin the silicon substrate while preventing problems such as peeling of the silicon active layer on the outer periphery of the substrate by grinding. This also makes it possible to omit the conventional trimming of the outer periphery of the substrate.
- the thickness of the silicon active layer can be accurately controlled by using the first silicon oxide film of the SOI substrate as an etching stop layer.
- FIG. 7 is an external view showing a peeled state of a silicon active layer in the outer periphery of a sapphire substrate of Test Example 1.
- FIG. 14 is an external view showing a state where a silicon active layer is peeled off and floated on the outer periphery of a sapphire substrate of Test Example 6.
- FIG. It is an external view which shows the example which does not have an island-like silicon part in a sapphire substrate outer peripheral part.
- the method for manufacturing a hybrid substrate according to the present invention includes an SOI substrate preparation step (step 1), a support substrate preparation step (step 2), an SOI substrate and / or a support substrate surface activation process.
- Process Process (Process 3), Bonding process of SOI substrate and support substrate (Process 4), Bonding heat treatment process (Process 5), Grinding thinning process of silicon substrate (Process 6), Thinned silicon substrate removing process (Process 7)
- the first silicon oxide film removing step (step 8) is performed in this order.
- An SOI substrate is prepared by laminating the first silicon oxide film 2 and the silicon active layer 3 in this order on the silicon substrate 1. At this time, it is preferable to form a terrace portion having no silicon active layer 3 on the outer peripheral portion (outer edge portion) of the silicon substrate 1 surface.
- the silicon substrate 1 is not particularly limited.
- the silicon substrate 1 is obtained by slicing a single crystal grown by the Czochralski (CZ) method.
- the diameter is 100 to 300 mm
- the conductivity type is P type.
- an N type and a thing with a resistivity of about 10 ohm * cm are mentioned.
- the thickness of the silicon substrate 1 is preferably 450 to 775 ⁇ m, more preferably 500 to 600 ⁇ m, in consideration of the handleability and the time required for the grinding thinning process described later.
- the description of “XXX to YYY” indicating the numerical range includes the upper and lower limits.
- “100 to 300 mm” means “100 mm to 300 mm”.
- the first silicon oxide film 2 is a silicon dioxide (SiO 2 ) insulating film called a so-called Box layer, and serves as an etching stop layer in the final process.
- the thickness of the first silicon oxide film 2 can be obtained from the Si thickness removed by etching (thickness of the thinned silicon substrate) and the selective etching ratio of Si and SiO 2 of the etching solution used. Is calculated from the selective etching ratio, and is set including a margin for in-plane thickness unevenness and etching unevenness. For example, if the thickness of Si removed by etching is about 80 ⁇ m, the thickness of the first silicon oxide film 2 is preferably 300 nm or more, and preferably in the range of 300 to 500 nm.
- the silicon active layer 3 is free from vacancy-type defects (COP (Crystal Originated Particle) defect-free) and does not generate oxidation-induced stacking faults (OSF (Oxidation Induced Stacking Fault) defects) due to thermal oxidation. Is preferred.
- the silicon active layer 3 is a thin film made of single crystal silicon, and finally becomes an SOI layer (semiconductor layer) on the support substrate.
- the film thickness of the silicon active layer 3 is preferably, for example, 100 to 500 nm, and more preferably 100 to 300 nm.
- Such an SOI substrate is preferably manufactured by an ion implantation separation method.
- a layer that is damaged by ion implantation and causes crystal defects in the surface layer of the silicon thin film after separation is wet-etched or dried. It is assumed that it has been removed by etching.
- the silicon substrate 1 on which the first silicon oxide film 2 is formed and the other silicon substrate on which the ion implantation region is formed at a predetermined depth are bonded together, and then the ion implantation region is used. Another silicon substrate is peeled off to obtain the SOI substrate.
- the edge roll-off region of the silicon substrate 1 (polishing sagging in the wafer CMP process during the manufacture of the silicon substrate) be a terrace portion, and the silicon on which the first silicon oxide film 2 is formed in the ion implantation delamination method.
- the substrate 1 and another silicon substrate on which an ion implantation region is formed are bonded to each other, they are not in contact with each other at this terrace portion. Therefore, a silicon thin film (a thin film that becomes the silicon active layer 3) is formed in this region of the silicon substrate 1. ) Is not transferred (that is, it does not have the silicon active layer 3).
- the terrace portion may be formed so as to be adjusted to the edge roll-off of the silicon substrate 1 so as to have a width of 1 to 3 mm, more preferably 2 to 3 mm, from the end (outer edge) of the silicon substrate.
- the SOI substrate and the supporting substrate are not in contact with each other and the silicon active layer 3 is not present in the terrace portion of the SOI substrate (that is, the outer peripheral portion width of 1 to 3 mm) at the bonding stage. Therefore, it is possible to further prevent the silicon active layer 3 from being locally separated at the stage of grinding and thinning the silicon substrate described later.
- the width of the terrace portion is less than 1 mm, even if the SOI substrate and the support substrate are bonded together and subjected to a bonding heat treatment, a local stress is applied to the outer peripheral portion at the stage of grinding and thinning the silicon substrate. There is a possibility that the silicon active layer is partially peeled off. Moreover, it is not preferable that the width of the terrace portion exceeds 3 mm because the area of the silicon active layer becomes small.
- the supporting substrate to be bonded is thinned so that the outer peripheral portion of the surface bonded to the SOI substrate is recessed at least by the width of the terrace portion from the central portion.
- the outer peripheral portion can be prevented, and troubles at locally joined portions can be avoided.
- the trouble is that grinding unevenness occurs between the joined and non-peripheral parts during grinding, and the grindstone is caught at the boundary and damages the Si substrate on the outer circumference. Will hurt you. The same effect can be obtained when the terrace portion is provided on the SOI substrate.
- a second silicon oxide film 4 is formed on the surface of the silicon active layer 3 of the prepared SOI substrate (FIG. 1A).
- the second silicon oxide film 4 may be formed by thermally oxidizing the silicon active layer 3.
- the second silicon oxide film 4 is for firmly bonding the SOI substrate and the support substrate, and the film thickness is preferably 50 to 300 nm.
- the film thickness is less than 50 nm, the water confined at the bonding interface cannot be diffused and agglomerates during the heat treatment to form a blister.
- the film thickness exceeds 300 nm, it is necessary to increase the thickness of the silicon active layer 3 before oxidation. There is a risk that the oxidation treatment time may be extended and the productivity and cost may be affected.
- the support substrate is an insulating transparent substrate that serves as a handle substrate of the hybrid substrate, and is preferably made of, for example, quartz glass, borosilicate glass, or sapphire.
- the support substrate has a coefficient of thermal expansion different from that of the SOI substrate.
- a sapphire substrate 5 is prepared as an example (FIG. 1B).
- the support substrate (sapphire substrate 5) preferably has the same outer dimensions from the relationship of being bonded to the SOI substrate, and when the SOI substrate (silicon substrate 1) has an orientation flat (OF) or notch. The same orientation flat or notch should be added to the support substrate.
- the sapphire substrate 5 may be heat-treated in a reducing atmosphere before the SOI substrate and the support substrate are bonded to each other.
- the sapphire substrate 5 is preliminarily heat-treated in a reducing atmosphere and then bonded to the SOI substrate, the number of defects in the silicon active layer 3 can be further reduced, and metal impurities on the sapphire substrate 5 are removed without cleaning, and the semiconductor manufacturing line is thus obtained. It is possible to make the input level possible.
- the reducing atmosphere at this time is, for example, a reducing gas composed of a gas species selected from carbon monoxide, hydrogen sulfide, sulfur dioxide, hydrogen, formaldehyde, or a combination thereof, or a mixture of the reducing gas and an inert gas.
- An atmosphere made of a gas can be mentioned, and among them, an atmosphere containing at least hydrogen, that is, an atmosphere made of only hydrogen or an inert gas containing hydrogen, more preferably an atmosphere made of only hydrogen.
- the lower limit of the heat treatment temperature is preferably 600 ° C or higher, more preferably 700 ° C or higher. If the heat treatment temperature is less than 600 ° C., the metal removal effect on the surface of the sapphire substrate 5 may be insufficient.
- the upper limit of the heat treatment temperature is preferably 1,100 ° C. or less, and preferably 900 ° C. or less. If the heat treatment temperature exceeds 1,100 ° C., the number of defects on the surface of the silicon active layer 3 of the hybrid substrate increases conversely, which may make it unsuitable as a hybrid substrate.
- the heat treatment time is preferably 10 seconds to 12 hours, more preferably 1 minute to 1 hour. If the heat treatment time is shorter than 10 seconds, metal removal on the surface of the sapphire substrate 5 may be insufficient, or the number of defects on the surface of the silicon active layer 3 of the hybrid substrate may be insufficient. If longer than 12 hours, Heat treatment costs may increase.
- Step 3 Surface activation treatment step of SOI substrate and / or support substrate
- a surface activation process is performed on both or one of the surface of the second silicon oxide film 4 of the SOI substrate and the surface of the sapphire substrate 5.
- activation is achieved by exposing highly reactive dangling bonds (dangling bonds) to the substrate surface, or by adding OH groups to the dangling bonds. It is performed by processing or processing by ion beam irradiation.
- the surface is exposed to high frequency plasma of about 100 W for about 5 to 30 seconds.
- Plasma treatment As a plasma gas, when processing an SOI substrate, when oxidizing the surface, plasma of oxygen gas, when not oxidizing, hydrogen gas, argon gas, or a mixed gas thereof or a mixed gas of hydrogen gas and helium gas Etc.
- hydrogen gas, argon gas, nitrogen gas, or a mixed gas thereof is used.
- organic substances on the surface of the SOI substrate and / or the sapphire substrate 5 are oxidized and removed, and the OH groups on the surface are increased and activated.
- the treatment by ion beam irradiation is a treatment of irradiating the surface of the SOI substrate and / or sapphire substrate 5 with an ion beam using a gas used in the plasma treatment to expose unbonded hands on the surface, It is possible to increase the binding force.
- the SOI substrate and the sapphire substrate 5 are bonded together via the second silicon oxide film 4 at a temperature higher than room temperature (25 ° C.) (FIG. 1C).
- this bonded body is referred to as a bonded substrate.
- the bonding temperature is 100 ° C. or higher and lower than 250 ° C., preferably 100 ° C. or higher and 225 ° C. or lower, more preferably 150 ° C. or higher and 225 ° C. or lower. If the bonding temperature is less than 100 ° C., the SOI substrate and the sapphire substrate 5 may not be bonded well. If the bonding temperature is 250 ° C. or more, the silicon activation layer is peeled off due to the difference in thermal expansion coefficient between the SOI substrate and the sapphire substrate 5. In some cases, the bonded substrate may be damaged.
- Step 5 Bonding heat treatment step
- heat is applied to the bonded substrate to perform heat treatment (bonding heat treatment).
- bonding heat treatment the bond between the SOI substrate and the sapphire substrate 5 is strengthened.
- the heat treatment temperature at this time is a temperature obtained by adding 0 to 100 ° C. to the above bonding temperature, and the temperature at which the bonded substrate is not damaged due to the difference (thermal stress) in the thermal expansion coefficient between the SOI substrate and the sapphire substrate 5 ( That is, it is preferably selected from 150 ° C. to less than 250 ° C., preferably 150 ° C. to 225 ° C., more preferably 150 ° C. to 200 ° C.
- the heat treatment time is, for example, 1 to 24 hours.
- the silicon substrate 1 in the bonded substrate is thinned by grinding. (FIG. 1 (d)).
- the thickness is preferably at most 60 ⁇ m.
- peeling of the silicon active layer 3 occurs on the outer peripheral side of the bonded substrate due to the action of local stress during grinding on the bonded substrate. There is a fear.
- a back grinding apparatus for example, PG200, manufactured by Tokyo Seimitsu Co., Ltd.
- polishing after grinding may be performed to remove damage on the surface layer.
- the grinding tool to be used is selected from the grinding amount and the damage thickness, and it is preferable to perform grinding in two stages by changing the count in order to further reduce the damage layer. For example, in order to obtain a grinding speed, a # 320 to 600 grinding tool is used in the first stage, and 2/3 to 3/4 of the thickness to be ground is performed. In the second stage, grinding is performed using a # 1200 to 2000 grinding tool while leaving a polishing allowance. Finally, polishing is performed to such an extent that the second stage grinding damage can be removed, or to a mirror finish. Finally, by performing polishing, it is possible to prevent damage during the next bonding heat treatment.
- step 5 at least two combinations of the bonding heat treatment (step 5) for increasing the bonding force between the SOI substrate and the support substrate and the grinding thinning process (step 6) for grinding and thinning the silicon substrate 1 of the bonded substrate are performed. It is preferable that the second heat treatment temperature be higher than the first heat treatment temperature. Specifically, the following procedure is recommended.
- Step 5 (1) The bonded substrate is heated to 150 ° C. or higher and lower than 200 ° C. to perform the first bonding heat treatment.
- the heat treatment time is 1 to 24 hours.
- Step 6 (1) The silicon substrate 1 in the bonded substrate is thinned by grinding (first grinding thinning process).
- the thickness of the silicon substrate after the first grinding thinning treatment is preferably 130 to 200 ⁇ m, more preferably 130 to 170 ⁇ m. At this time, it is preferable to perform the above-described two-stage grinding (first-stage grinding-second-stage grinding-polishing).
- Step 5 (2) The bonded substrate is heated to 200 ° C.
- Step 6 (2) The silicon substrate 1 in the bonded substrate is further thinned by grinding (second grinding thinning process).
- the thickness of the silicon substrate after the second thinning process is preferably 60 to 100 ⁇ m, more preferably 60 to 85 ⁇ m. Grinding conditions at this time will affect the stability during the etching of the next process if a processing mark or damage is left. Therefore, the above-mentioned two-stage grinding is performed, and a grinding tool of # 600 or more is used in the first stage. Use a grinding tool of # 2000 or higher for the second stage.
- the bonding force between the SOI substrate and the supporting substrate is increased by a higher temperature bonding heat treatment each time the thinning is performed, so that the silicon active layer 3 is peeled off by grinding or the bonded substrate is damaged. It becomes possible to prevent more reliably.
- Process 7 Thinned silicon substrate removal process
- the thinned silicon substrate 1 ′ is removed by etching to expose the first silicon oxide film 2 (FIG. 1E).
- Etching is preferably performed by a spin etching apparatus using a mixed acid for the electronics industry made of nitric acid, hydrofluoric acid or the like as a silicon wafer etching solution.
- Step 8 First silicon oxide film removal step
- the exposed first silicon oxide film 2 is removed by etching with an aqueous hydrogen fluoride solution to expose the silicon active layer 3 (FIG. 1F). Since the thickness distribution of the silicon active layer 3 obtained is equivalent to the thickness distribution of the original SOI substrate, it is comparable to that of the ion implantation separation method.
- by providing 1 to 3 mm of an outer peripheral portion without an active layer called a terrace portion on the SOI substrate to be used it is possible to prevent generation of Si islands due to extra bonding of the outer peripheral portion when a bonded substrate is used. A high-quality composite substrate can be obtained.
- the SOI substrate to be used is prepared so that the silicon active layer is defect-free (COP-free) and does not cause oxidation-induced stacking faults (OSF defects) due to thermal oxidation.
- COP-free defect-free
- OSF defects oxidation-induced stacking faults
- the silicon active layer 3 is finished and polished to a desired thickness and washed to obtain an SOI structure multilayer composite substrate (hybrid substrate) having the silicon active layer 3 on the support substrate (sapphire substrate 5) (FIG. 1 (g)).
- Step 1 A substrate with a diameter of 150 mm, a thickness of 525 ⁇ m, and a 47.5 mm OF was prepared as an SOI substrate.
- the thickness of the silicon active layer 3 and the like depends on the device to be manufactured, in this test example, from the surface layer, the second silicon oxide film 4 (SiO 2 ); 200 nm / silicon active layer 3; 380 nm / first silicon oxide Film 2 (SiO 2 ): 300 nm (FIG. 1A).
- the second silicon oxide film 4 is an oxide film obtained by thermally oxidizing the silicon active layer of the SOI substrate, and the first silicon oxide film 2 is a buried oxide film (Box layer) of the SOI substrate. In addition, a terrace portion was formed to have a width of 2 mm on the outer periphery of the SOI substrate.
- Step 2 As a support substrate, a sapphire substrate 5 with material: sapphire, diameter 150 mm, thickness 600 ⁇ m, 47.5 mm OF was prepared.
- Process 3 The activation process was performed by irradiating the surface to which the SOI substrate and the sapphire substrate 5 were bonded with 100 W plasma in a reduced-pressure nitrogen atmosphere.
- Step 4 The SOI substrate and the sapphire substrate 5 were bonded together at room temperature (25 ° C.). Next, a combination of a bonding heat treatment (step 5) for increasing the bonding force between the SOI substrate and the support substrate and a grinding thinning process (step 6) for grinding and thinning the silicon substrate 1 of the bonded substrate is performed twice. Repeatedly.
- Step 5 (1) The bonded substrate was subjected to bonding heat treatment at 150 ° C. for 24 hours. As a result, the appearance of the bonded substrate was good without any abnormality such as peeling.
- Step 6 (1) The silicon substrate 1 in the bonded substrate was ground to a thickness of 150 ⁇ m.
- Step 6 (1) was performed in the first-stage grinding-second-stage grinding-finish polishing procedure. Trimming processing of the outer periphery of the bonded substrate was not performed.
- Step 5 (2) The bonded substrate was subjected to bonding heat treatment at 150 ° C. for 24 hours. As a result, the appearance of the bonded substrate was good without any abnormality such as peeling.
- Step 6 (2) The silicon substrate 1 in the bonded substrate was ground to a thickness of 50 ⁇ m.
- Step 6 (2) processing was performed in the second grinding process (step 6 (2)) in the first-stage grinding-second-stage grinding procedure.
- Step 7 The silicon substrate 1 ′ after thinning was removed by spin etching using a mixed acid for electronic industry (mirror finishing solution Si etch E, manufactured by Nippon Kasei Co., Ltd.).
- Step 8) The first exposed silicon oxide film 2 was removed by etching with an aqueous hydrogen fluoride solution to expose the silicon active layer 3. As a result, as shown in FIG. 2, peeling was recognized at the outer peripheral portion of the silicon active layer 3.
- Test Example 2 In Test Example 1, a hybrid substrate was produced in the same manner as in Test Example 1 except that the second grinding process (Step 6 (2)) was not performed. As a result, peeling was recognized at the outer peripheral portion of the silicon active layer 3.
- Test Example 3 In Test Example 1, when the heat treatment temperature of the second bonding heat treatment (step 5 (2)) was set to 175 ° C., peeling of the silicon substrate 1 from the bonded portion was recognized at the outer peripheral portion of the bonded substrate, and the subsequent processing Did not do.
- Test Example 4 In Test Example 1, when the heat treatment temperature of the first bonding heat treatment (step 5 (1)) was set to 175 ° C., peeling of the silicon substrate 1 from the bonded portion was recognized at the outer peripheral portion of the bonded substrate, and the subsequent processing Did not do.
- Test Example 5 In Test Example 1, the processing after the outer periphery trimming was changed to the following conditions. The outer periphery of the bonded substrate was trimmed by 1 mm. (Step 5 (2)) The bonded substrate was subjected to a bonding heat treatment at 170 ° C. for 24 hours. As a result, the appearance of the bonded substrate was good without any abnormality such as peeling. (Step 6 (2)) The silicon substrate 1 in the bonded substrate was ground to a thickness of 50 ⁇ m. As a result, the appearance of the bonded substrate was good.
- Step 7 The silicon substrate 1 ′ after thinning was removed by spin etching using a mixed acid for electronic industry (mirror finishing solution Si etch E, manufactured by Nippon Kasei Co., Ltd.).
- Step 8) The first exposed silicon oxide film 2 was removed by etching with an aqueous hydrogen fluoride solution to expose the silicon active layer 3. As a result, the appearance of the silicon active layer 3 was good.
- the silicon active layer 3 was polished to a thickness of 280 nm to obtain a SOI substrate hybrid substrate.
- Test Example 6 In Test Example 1, the processing after the outer periphery trimming was changed to the following conditions. The outer periphery of the bonded substrate was trimmed by 1 mm. (Step 5 (2)) The bonded substrate was subjected to bonding heat treatment at 175 ° C. for 24 hours. As a result, peeling of the substrate was observed on the bonded substrate. (Step 6 (2)) The silicon substrate 1 in the bonded substrate was ground to a thickness of 50 ⁇ m. As a result, peeling of the silicon substrate 1 from the bonded portion was recognized at the outer peripheral portion of the bonded substrate.
- Step 7 The silicon substrate 1 ′ after thinning was removed by spin etching using a mixed acid for electronic industry (mirror finishing solution Si etch E, manufactured by Nippon Kasei Co., Ltd.).
- Step 8) The first exposed silicon oxide film 2 was removed by etching with an aqueous hydrogen fluoride solution to expose the silicon active layer 3. As a result, as shown in FIG. 3, peeling and floating were recognized in the outer peripheral portion of the silicon active layer 3.
- Test Example 7 In Test Example 1, the process after the bonding process (process 4) was changed to the following conditions.
- Step 4 The SOI substrate and the sapphire substrate 5 were brought into contact with each other while being heated to 100 ° C. and bonded together.
- step 5 a combination of a bonding heat treatment (step 5) for increasing the bonding force between the SOI substrate and the support substrate and a grinding thinning process (step 6) for grinding and thinning the silicon substrate 1 of the bonded substrate is performed twice.
- Step 5 (1) The bonded substrate was subjected to bonding heat treatment at 150 ° C. for 24 hours. As a result, the appearance of the bonded substrate was good without any abnormality such as peeling.
- Step 6 (1) The silicon substrate 1 in the bonded substrate was ground to a thickness of 150 ⁇ m. As a result, the appearance was good. Trimming processing of the outer periphery of the bonded substrate was not performed.
- Step 5 (2) The bonded substrate was subjected to bonding heat treatment at 175 ° C. for 24 hours. As a result, the appearance of the bonded substrate was good without any abnormality such as peeling.
- Step 6 (2) The silicon substrate 1 in the bonded substrate was ground to a thickness of 50 ⁇ m. As a result, peeling of the silicon substrate 1 from the bonded portion was recognized at the outer peripheral portion of the bonded substrate.
- Step 7 The silicon substrate 1 ′ after thinning was removed by spin etching using a mixed acid for electronic industry (mirror finishing solution Si etch E, manufactured by Nippon Kasei Co., Ltd.).
- Step 8) The first exposed silicon oxide film 2 was removed by etching with an aqueous hydrogen fluoride solution to expose the silicon active layer 3. As a result, peeling was recognized at the outer peripheral portion of the silicon active layer 3. It is presumed that the grinding wheel is caught during the grinding process, and stress that peels off the silicon substrate 1 acts.
- Test Example 8 In Test Example 7, the bonding heat treatment temperature in step 5 (2) was set to 200 ° C., and the silicon substrate 1 in the bonded substrate was ground to a thickness of 80 ⁇ m as the second grinding process (step 6 (2)). When processed, the appearance of the bonded substrate was good with no abnormalities such as peeling. Next, in steps 7 and 8, the silicon active layer 3 was exposed by etching in the same manner as in Test Example 7. As a result, the appearance of the silicon active layer 3 was good. Finally, the silicon active layer 3 was polished and thinned to a thickness of 280 nm to obtain an SOI structure hybrid substrate.
- Test Example 9 In Test Example 1, the process after the bonding process (process 4) was changed to the following conditions.
- Step 4 The SOI substrate and the sapphire substrate 5 were brought into contact with each other while being heated to 120 ° C. and bonded together.
- step 5 a combination of a bonding heat treatment (step 5) for increasing the bonding force between the SOI substrate and the support substrate and a grinding thinning process (step 6) for grinding and thinning the silicon substrate 1 of the bonded substrate is performed twice.
- Step 5 (1) The bonded substrate was subjected to bonding heat treatment at 150 ° C. for 24 hours. As a result, the appearance of the bonded substrate was good without any abnormality such as peeling.
- Step 6 (1) The silicon substrate 1 in the bonded substrate was ground to a thickness of 150 ⁇ m. As a result, the appearance was good. Trimming processing of the outer periphery of the bonded substrate was not performed.
- Step 5 (2) The bonded substrate was subjected to bonding heat treatment at 200 ° C. for 24 hours. As a result, the appearance of the bonded substrate was good without any abnormality such as peeling.
- Step 6 (2) The silicon substrate 1 in the bonded substrate was ground to a thickness of 80 ⁇ m. As a result, the appearance of the bonded substrate was good.
- Step 7 The silicon substrate 1 ′ after thinning was removed by spin etching using a mixed acid for electronic industry (mirror finishing solution Si etch E, manufactured by Nippon Kasei Co., Ltd.).
- Step 8) The first exposed silicon oxide film 2 was removed by etching with an aqueous hydrogen fluoride solution to expose the silicon active layer 3. As a result, the appearance of the silicon active layer 3 was good.
- the silicon active layer 3 was polished to a thickness of 280 nm to obtain a SOI substrate hybrid substrate.
- Test Example 10 In Test Example 1, the process after the bonding process (process 4) was changed to the following conditions. (Step 4) The SOI substrate and the sapphire substrate 5 were brought into contact with each other while being heated to 150 ° C. and bonded together. Next, a combination of a bonding heat treatment (step 5) for increasing the bonding force between the SOI substrate and the support substrate and a grinding thinning process (step 6) for grinding and thinning the silicon substrate 1 of the bonded substrate is performed twice. Repeatedly. (Step 5 (1)) The bonded substrate was subjected to bonding heat treatment at 175 ° C. for 24 hours. As a result, the appearance of the bonded substrate was good without any abnormality such as peeling.
- Step 6 (1) The silicon substrate 1 in the bonded substrate was ground to a thickness of 120 ⁇ m. As a result, peeling of the silicon substrate 1 from the bonded portion was recognized at the outer peripheral portion of the bonded substrate. Trimming processing of the outer periphery of the bonded substrate was not performed.
- Step 5 (2) The bonded substrate was subjected to bonding heat treatment at 200 ° C. for 24 hours. As a result, the appearance of the bonded substrate was good without any abnormality such as peeling.
- Step 6 (2) The silicon substrate 1 in the bonded substrate was ground to a thickness of 80 ⁇ m. As a result, peeling of the silicon substrate 1 from the bonded portion was recognized at the outer peripheral portion of the bonded substrate.
- Step 7 The silicon substrate 1 ′ after thinning was removed by spin etching using a mixed acid for electronic industry (mirror finishing solution Si etch E, manufactured by Nippon Kasei Co., Ltd.).
- Step 8) The first exposed silicon oxide film 2 was removed by etching with an aqueous hydrogen fluoride solution to expose the silicon active layer 3. As a result, peeling was recognized at the outer peripheral portion of the silicon active layer 3. It is presumed that the grinding wheel is caught during the grinding process, and stress that peels off the silicon substrate 1 acts.
- Step 6 (1) The silicon substrate 1 in the bonded substrate was ground to a thickness of 150 ⁇ m. As a result, the appearance was good. Trimming processing of the outer periphery of the bonded substrate was not performed.
- Step 5 (2) The bonded substrate was subjected to bonding heat treatment at 200 ° C. for 24 hours. As a result, the appearance of the bonded substrate was good without any abnormality such as peeling.
- Step 6 (2) The silicon substrate 1 in the bonded substrate was ground to a thickness of 60 ⁇ m. As a result, the appearance of the bonded substrate was good.
- Step 7 The silicon substrate 1 ′ after thinning was removed by spin etching using a mixed acid for electronic industry (mirror finishing solution Si etch E, manufactured by Nippon Kasei Co., Ltd.).
- Step 8) The first exposed silicon oxide film 2 was removed by etching with an aqueous hydrogen fluoride solution to expose the silicon active layer 3. As a result, the appearance of the silicon active layer 3 was good.
- the silicon active layer 3 was polished to a thickness of 280 nm to obtain a SOI substrate hybrid substrate.
- Step 6 (1) The silicon substrate 1 in the bonded substrate was ground until the thickness became 200 ⁇ m. As a result, the appearance was good. Trimming processing of the outer periphery of the bonded substrate was not performed.
- Step 5 (2) The bonded substrate was subjected to bonding heat treatment at 200 ° C. for 24 hours. As a result, the appearance of the bonded substrate was good without any abnormality such as peeling.
- Step 6 (2) The silicon substrate 1 in the bonded substrate was ground until the thickness became 75 ⁇ m. As a result, the appearance of the bonded substrate was good.
- Step 7 The silicon substrate 1 ′ after thinning was removed by spin etching using a mixed acid for electronic industry (mirror finishing solution Si etch E, manufactured by Nippon Kasei Co., Ltd.).
- Step 8) The first exposed silicon oxide film 2 was removed by etching with an aqueous hydrogen fluoride solution to expose the silicon active layer 3. As a result, the appearance of the silicon active layer 3 was good.
- the silicon active layer 3 was polished to a thickness of 280 nm to obtain a SOI substrate hybrid substrate.
- Test Example 13 In Test Example 1, the process after the bonding process (process 4) was changed to the following conditions.
- Step 4 The SOI substrate and the sapphire substrate 5 were brought into contact with each other while being heated to 175 ° C. and bonded together.
- step 5 a combination of a bonding heat treatment (step 5) for increasing the bonding force between the SOI substrate and the support substrate and a grinding thinning process (step 6) for grinding and thinning the silicon substrate 1 of the bonded substrate is performed twice.
- Step 5 (1) The bonded substrate was subjected to bonding heat treatment at 175 ° C. for 24 hours. As a result, the appearance of the bonded substrate was good without any abnormality such as peeling.
- Step 6 (1) The silicon substrate 1 in the bonded substrate was ground to a thickness of 150 ⁇ m. As a result, the appearance was good. Trimming processing of the outer periphery of the bonded substrate was not performed.
- Step 5 (2) The bonded substrate was subjected to bonding heat treatment at 200 ° C. for 24 hours. As a result, the appearance of the bonded substrate was good without any abnormality such as peeling.
- Step 6 (2) The silicon substrate 1 in the bonded substrate was ground to a thickness of 50 ⁇ m. As a result, there were a case where the appearance of the bonded substrate was good and a case where peeling of the silicon substrate 1 from the joint portion was recognized at the outer peripheral portion.
- Step 7 The silicon substrate 1 ′ after thinning was removed by spin etching using a mixed acid for electronic industry (mirror finishing solution Si etch E, manufactured by Nippon Kasei Co., Ltd.).
- Step 8) The first exposed silicon oxide film 2 was removed by etching with an aqueous hydrogen fluoride solution to expose the silicon active layer 3.
- the external appearance of the silicon active layer 3 was good when the appearance of the bonded substrate after grinding was good.
- peeling was recognized on the outer peripheral portion of the silicon active layer 3.
- the silicon active layer 3 was polished and thinned to a thickness of 280 nm to obtain an SOI structure hybrid substrate. From the results of Test Example 13, it is difficult to say that thinning up to 50 ⁇ m is stable (highly likely to cause separation of the floating part on the outer periphery during grinding), and it should be left thicker than 50 ⁇ m. Good. Preferably it is 60 micrometers or more.
- Test Example 14 In Test Example 13, as the second grinding process (step 6 (2)), when the silicon substrate 1 in the bonded substrate was ground until the thickness became 75 ⁇ m, the bonded substrate had an abnormal appearance such as peeling. Not good. Next, in steps 7 and 8, the silicon active layer 3 was exposed by etching in the same manner as in Test Example 13. As a result, the appearance of the silicon active layer 3 was good. Finally, the silicon active layer 3 was polished and thinned to a thickness of 280 nm to obtain an SOI structure hybrid substrate.
- Test Example 15 In Test Example 13, as the second grinding process (Step 6 (2)), when the silicon substrate 1 in the bonded substrate was ground until the thickness became 85 ⁇ m, the appearance of the bonded substrate was abnormal such as peeling. Not good. Next, in steps 7 and 8, the silicon active layer 3 was exposed by etching in the same manner as in Test Example 13. As a result, the appearance of the silicon active layer 3 was good. Finally, the silicon active layer 3 was polished and thinned to a thickness of 280 nm to obtain an SOI structure hybrid substrate.
- Test Example 16 In Test Example 13, a process of trimming the outer periphery of the bonded substrate by 1 mm was performed, and the other processes were performed up to the second grinding process (step 6 (2)) in the same manner as in Test Example 13. The appearance was good with no abnormality such as peeling. Next, in steps 7 and 8, the silicon active layer 3 was exposed by etching in the same manner as in Test Example 13. As a result, the appearance of the silicon active layer 3 was good. Finally, the silicon active layer 3 was polished and thinned to a thickness of 280 nm to obtain an SOI structure hybrid substrate. Trimming is advantageous because the outer peripheral portion of the silicon active layer 3 is not peeled off, which is advantageous. However, as in Test Examples 14 and 15, the bonding heat of the bonded substrate is increased by increasing the bonding heat treatment temperature. If an appropriate grinding process is performed, the outer periphery of the substrate will not peel off even if there is no trimming process.
- Test Example 17 In Test Example 1, the process after the bonding process (process 4) was changed to the following conditions.
- Step 4 The SOI substrate and the sapphire substrate 5 were brought into contact with each other while being heated to 225 ° C. and bonded together.
- step 5 a combination of a bonding heat treatment (step 5) for increasing the bonding force between the SOI substrate and the support substrate and a grinding thinning process (step 6) for grinding and thinning the silicon substrate 1 of the bonded substrate is performed twice. Repeatedly. Note that the second bonding heat treatment was omitted under the conditions of this test example.
- Step 5 (1) The bonded substrate was subjected to bonding heat treatment at 225 ° C. for 24 hours.
- Step 6 (1) The silicon substrate 1 in the bonded substrate was ground to a thickness of 150 ⁇ m. As a result, the appearance was good. Trimming processing of the outer periphery of the bonded substrate was not performed.
- Step 5 (2) Since it was found that sufficient bonding was obtained between the SOI substrate and the sapphire substrate 5 by the first bonding heat treatment, the second bonding heat treatment was omitted.
- Step 6 (2) The silicon substrate 1 in the bonded substrate was ground to a thickness of 50 ⁇ m. As a result, the appearance was good.
- Step 7 The silicon substrate 1 ′ after thinning was removed by spin etching using a mixed acid for electronic industry (mirror finishing solution Si etch E, manufactured by Nippon Kasei Co., Ltd.).
- Step 8 The first exposed silicon oxide film 2 was removed by etching with an aqueous hydrogen fluoride solution to expose the silicon active layer 3. As a result, the appearance of the silicon active layer 3 was good.
- the silicon active layer 3 was polished and thinned to a thickness of 280 nm to obtain an SOI structure hybrid substrate. The results are shown in Table 1.
- the SOI substrate does not have a terrace portion (a portion without a silicon active layer), for example, even under the conditions of Test Example 14, the bonded substrate peels off weakly at the bonding force with the portion bonded to the outer periphery.
- a part is formed and the part finally joined is left in an island shape. That is, in some cases, silicon remains in an island shape even in the partial bonding portion even in the hybrid substrate, and the island-like silicon portion may drop out in a later process, resulting in a decrease in yield.
- the outer peripheral region having a predetermined width of the surface to be bonded to the SOI substrate of the support substrate is thinner than the central portion so as not to be joined. Further, even when the terrace portion is provided on the SOI substrate, by making the width of the terrace portion of the SOI substrate and the unjoined portion of the sapphire substrate 5 (the portion where the thickness is reduced) as shown in FIG. The island-like silicon portion is not formed, and the problems occurring in the outer peripheral portion of the bonded substrate can be prevented more reliably. Further, as shown in Test Example 17, when the temperature of the first bonding heat treatment is 200 ° C.
- the SOI substrate and the support substrate can be sufficiently bonded only by the bonding heat treatment, so that the second bonding is performed.
- Heat treatment can be omitted.
- the combination of steps 5 and 6 (bonding heat treatment and grinding) is three or more times, the second and subsequent bonding heat treatments can be omitted.
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Abstract
Description
(1) まず、熱酸化などにより酸化膜を形成したシリコンウェハに水素イオンを注入し、それを支持基板に貼り合わせ、結合熱処理を行った後、更に熱を加えて熱剥離を行う、スマートカット法と呼ばれる方法がある。これは、高温で熱処理を行うことで、打ち込んだガスが基板内部で微小気泡層として形成され、その気泡層が膨張することで剥離が行われるものである。このため、高温熱処理が必須であり、熱膨張率差のある基板への適用が難しい。
(2) また、熱酸化などによって酸化膜を形成したシリコンウェハに水素イオンを注入し、それを支持基板に貼り合わせ、結合熱処理を行った後に、機械的に剥離を行うSiGen法がある。この方法では、内部での気泡層の凝集や膨張の作用を必要としないため、高温熱処理は不要で、貼り合わせ面をプラズマなどで活性化することで予め結合力を上げ、熱処理を低温化していることもあり、スマートカット法の様な高温にはさらされない。しかしながら、機械的剥離では、貼り合わせ基板において応力が局所的に掛かる部分がどうしても発生し、その部分でシリコン薄膜に欠陥が生じやすいという欠点がある。また、それを防止するために結合強度を上げようとして熱処理温度を上げると、スマートカット法と同様に熱膨張率の問題が生じることとなる。ちなみに、応力が局所的に掛かる部分とは、貼り合わせ基板の結合面が途切れる外周部や剥離終端部のことであり、シリコン薄膜の縁がギザギザになったり、細かなピット(微小な膜厚変動)が生じたりする。
上記2つの方法は、水素イオンを注入し、その水素イオンより生じる欠陥層から分離(剥離)を行っている(イオン注入剥離法)が、その欠陥層から拡がる欠陥や水素ガス種の拡散による欠陥増の問題を生じることがある。特に、熱酸化処理などの高温処理で欠陥が発生することがある。
〔1〕 シリコン基板上に第1シリコン酸化膜とシリコン活性層とをこの順番で積層してなり、該シリコン基板面外周部に上記シリコン活性層を有しないテラス部を形成したSOI基板を準備し、
該SOI基板のシリコン活性層表面に第2シリコン酸化膜を形成し、
上記SOI基板と該SOI基板と熱膨張率の異なる支持基板とを貼り合わせるに際し、該SOI基板及び/又は支持基板の貼り合わせる面を活性化処理し、
上記SOI基板と支持基板とを室温より高温で第2シリコン酸化膜を介して貼り合わせて貼り合わせ基板とし、
次いで、上記貼り合わせ基板についてSOI基板と支持基板の結合力を高める結合熱処理と、上記シリコン基板を研削して薄化する研削薄化処理との組み合わせを少なくとも2回繰り返して行うに際し、1回目の結合熱処理の温度を上記貼り合わせの温度以上とし、1回目の研削薄化処理後のシリコン基板の厚さを最も薄くとも130μmまでとし、最終回の結合熱処理の温度を200℃以上250℃未満とし、最終回の研削薄化処理後のシリコン基板の厚さを最も薄くとも60μmまでとして上記結合熱処理及び研削薄化処理を行い、
次に、上記薄化したシリコン基板をエッチングにより除去して第1シリコン酸化膜を露出させ、
更に、露出した第1シリコン酸化膜をエッチングにより除去して、支持基板上にシリコン酸化膜を介してシリコン活性層を有するハイブリッド基板を得ることを特徴とするハイブリッド基板の製造方法。
〔2〕 上記SOI基板と支持基板の貼り合わせ温度を、100℃以上250℃未満とすることを特徴とする〔1〕記載のハイブリッド基板の製造方法。
〔3〕 上記SOI基板と支持基板の結合力を高める結合熱処理温度を、上記貼り合わせ温度に0~100℃加算した温度(ただし、250℃未満とする)とすることを特徴とする〔1〕又は〔2〕記載のハイブリッド基板の製造方法。
〔4〕 2回目以降の結合熱処理温度をその1回前の結合熱処理温度よりも高くすることを特徴とする〔1〕~〔3〕のいずれかに記載のハイブリッド基板の製造方法。
〔5〕 上記1回目の結合熱処理の温度が200℃以上250℃未満の場合、2回目以降の結合熱処理を省略することを特徴とする〔1〕~〔3〕のいずれかに記載のハイブリッド基板の製造方法。
〔6〕 上記1回目の研削薄化処理後のシリコン基板の厚さを130μm以上200μm以下とすることを特徴とする〔1〕~〔5〕のいずれかに記載のハイブリッド基板の製造方法。
〔7〕 上記最終回の研削薄化処理後のシリコン基板の厚さを60μm以上100μm以下とすることを特徴とする〔1〕~〔6〕のいずれかに記載のハイブリッド基板の製造方法。
〔8〕 上記テラス部の幅は、1mm以上3mm以下であることを特徴とする〔1〕~〔7〕のいずれかに記載のハイブリッド基板の製造方法。
〔9〕 上記SOI基板のシリコン活性層は、空孔型欠陥がなく、熱酸化により酸化誘起積層欠陥が発生しないものであることを特徴とする〔1〕~〔8〕のいずれかに記載のハイブリッド基板の製造方法。
〔10〕 上記支持基板は、石英ガラス、ホウ珪酸ガラス又はサファイアからなることを特徴とする〔1〕~〔9〕のいずれかに記載のハイブリッド基板の製造方法。
〔11〕 上記SOI基板と支持基板との貼り合わせの前に、上記支持基板について還元性雰囲気中の熱処理を行うことを特徴とする〔1〕~〔10〕のいずれかに記載のハイブリッド基板の製造方法。
〔12〕 上記支持基板のSOI基板と貼り合わされる面の所定幅の外周領域を中央部よりも凹むように薄くすることを特徴とする〔1〕~〔11〕のいずれかに記載のハイブリッド基板の製造方法。
〔13〕 〔1〕~〔12〕のいずれかに記載のハイブリッド基板の製造方法により製造された、支持基板上にシリコン酸化膜を介してシリコン活性層を有するハイブリッド基板。
本発明に係るハイブリッド基板の製造方法は、図1に示すように、SOI基板の準備工程(工程1)、支持基板の準備工程(工程2)、SOI基板及び/又は支持基板の表面活性化処理工程(工程3)、SOI基板と支持基板の貼り合わせ工程(工程4)、結合熱処理工程(工程5)、シリコン基板の研削薄化工程(工程6)、薄化シリコン基板除去工程(工程7)、第1シリコン酸化膜除去工程(工程8)の順に処理を行うものである。
シリコン基板1上に第1シリコン酸化膜2とシリコン活性層3とをこの順番で積層したものをSOI基板として準備する。このとき、そのシリコン基板1面外周部(外縁部)に上記シリコン活性層3を有しないテラス部を形成することが好ましい。
ここで、数値範囲を示す「XXX~YYY」の記載はその上限下限を含むものである。例えば「100~300mm」は「100mm以上300mm以下」を意味する。
シリコン活性層3の膜厚は、例えば100~500nmが好ましく、100~300nmがより好ましい。
SOI基板にテラス部を設けた場合も同様の効果が得られる。
支持基板は、ハイブリッド基板のハンドル基板となる絶縁性の透明基板であり、例えば石英ガラス、ホウ珪酸ガラス又はサファイアからなるものが好ましい。この場合、支持基板は、SOI基板とは熱膨張率が異なるものとなる。ここでは、例としてサファイア基板5を準備する(図1(b))。
貼り合わせの前に、SOI基板の第2シリコン酸化膜4表面と、サファイア基板5の表面との双方もしくは片方に表面活性化処理を施す。
次に、SOI基板とサファイア基板5とを室温(25℃)より高温で、第2シリコン酸化膜4を介して貼り合わせる(図1(c))。以下、この接合体を貼り合わせ基板という。このとき、貼り合わせ温度を100℃以上250℃未満、好ましくは100℃以上225℃以下、より好ましくは150℃以上225℃以下とするとよい。貼り合わせ温度が100℃未満では、SOI基板とサファイア基板5とがうまく接合しないおそれがあり、250℃以上では、SOI基板とサファイア基板5との熱膨張率の差により、シリコン活性化層の剥がれや貼り合わせ基板の破損が発生する場合がある。
貼り合わせ後に、貼り合わせ基板に熱を加えて熱処理(結合熱処理)を行う。この熱処理により、SOI基板とサファイア基板5の結合が強化される。このときの熱処理温度は、上記貼り合わせ温度に0~100℃加算した温度であって、貼り合わせ基板がSOI基板とサファイア基板5の熱膨率の差の影響(熱応力)で破損しない温度(即ち、250℃未満とする)を選択することが好ましく、例えば、150℃以上250℃未満、好ましくは150℃以上225℃以下、より好ましくは150℃以上200℃以下である。熱処理時間は、例えば1~24時間である。
貼り合わせ基板におけるシリコン基板1を研削により薄化する。(図1(d))。その厚さは最も薄くとも60μmまでが好ましい。薄化後のシリコン基板1’の厚さを60μm未満とすると、貼り合わせ基板に対する研削加工時の局所的な応力の作用により、シリコン活性層3の剥離が貼り合わせ基板の外周部側に発生するおそれがある。
(工程6(1))貼り合わせ基板におけるシリコン基板1を研削により薄化する(1回目研削薄化処理)。1回目の研削薄化処理後のシリコン基板の厚さを好ましくは130~200μm、より好ましくは130~170μmとする。このとき、上述した2段階の研削加工(1段目の研削−2段目の研削−研磨)を行うことが好ましい。
(工程5(2))貼り合わせ基板を200℃以上250℃未満に加熱して、2回目(工程5、6の組み合わせが3回以上の場合は最終回)の結合熱処理を行う。熱処理時間は1~24時間である。
(工程6(2))貼り合わせ基板におけるシリコン基板1を研削により更に薄化する(2回目研削薄化処理)。2回目(工程5、6の組み合わせが3回以上の場合は最終回)の研削薄化処理後のシリコン基板の厚さを好ましくは60~100μm、より好ましくは60~85μmとする。このときの研削加工条件は、加工痕やダメージを残すと次工程のエッチング時の安定性に影響を及ぼすので、上述した2段階の研削を行い、その1段目を#600以上の研削ツールを使用し、2段目は#2000以上の研削ツールを使用する。ここでは、シリコン基板1の外周部の剥がれの危険性から研磨を行わず、この面からも細かい粒子の研削ツールを選択するのが好ましい。
上記のように薄化したシリコン基板1’をエッチングにより除去して第1シリコン酸化膜2を露出させる(図1(e))。エッチングは、シリコンウェハエッチング液として硝酸、フッ酸などからなる電子工業用の混酸を用いてスピンエッチング装置により行うことが好ましい。
次に、露出した第1シリコン酸化膜2をフッ化水素水溶液によりエッチングして除去してシリコン活性層3を露出させる(図1(f))。得られるシリコン活性層3の厚み分布は、元々のSOI基板の厚み分布と同等であるのでイオン注入剥離法のものと遜色ないものとなる。また、使用するSOI基板にテラス部と呼ぶ活性層のない外周部を1~3mm設けることで、貼り合わせ基板としたときの外周部の余計な接合に起因するSi島の生成を防止でき、より高品質な複合基板を得ることができる。更に、使用するSOI基板は、シリコン活性層を欠陥フリー(COPフリー)で、かつ熱酸化により酸化誘起積層欠陥(OSF欠陥)の生じないように作製されたものとするので、イオン注入剥離法では得られない良質なシリコン薄膜が得られる。
上述したハイブリッド基板の製造方法の工程1~工程8を以下の条件で行い、ハイブリッド基板を作製した。
(工程1)SOI基板として、直径150mm、厚さ525μm、47.5mmOF付きの基板を用意した。なお、シリコン活性層3等の厚さは作製するデバイスにもよるが、本試験例では表層から、第2シリコン酸化膜4(SiO2);200nm/シリコン活性層3;380nm/第1シリコン酸化膜2(SiO2);300nmとした(図1(a))。なお、第2シリコン酸化膜4は、SOI基板のシリコン活性層を熱酸化して得た酸化膜であり、第1シリコン酸化膜2は、SOI基板の埋め込み酸化膜(Box層)である。また、SOI基板の外周にテラス部を幅2mmとなるように形成した。
(工程2)支持基板として、材質:サファイア、直径150mm、厚さ600μm、47.5mmOF付きのサファイア基板5を用意した。
(工程3)SOI基板及びサファイア基板5の貼り合わせる面を減圧窒素雰囲気中にて100Wのプラズマを照射することで活性化処理を行った。
(工程4)SOI基板とサファイア基板5とを室温(25℃)で貼り合わせた。
次に、SOI基板と支持基板の結合力を高める結合熱処理(工程5)と、上記貼り合わせ基板のシリコン基板1を研削して薄化する研削薄化処理(工程6)との組み合わせを2回繰り返して行った。
(工程5(1))貼り合わせ基板を150℃、24時間の結合熱処理を施した。その結果、貼り合わせ基板の外観は剥離等の異常なく、良好であった。
(工程6(1))貼り合わせ基板におけるシリコン基板1を厚さが150μmになるまで研削加工した。このときの研削加工条件は、1段目の研削で180μmまで薄くし、2段目の研削で更に150μm近くまで薄くし、最後に研磨で150μmに仕上げた。その結果、外観は良好であった。
なお、以降の試験例においても1回目の研削加工(工程6(1))において1段目の研削−2段目の研削−仕上げ研磨の手順で処理を行った。
貼り合わせ基板の外周のトリミング加工は行わなかった。
(工程5(2))貼り合わせ基板を150℃、24時間の結合熱処理を施した。その結果、貼り合わせ基板の外観は剥離等の異常なく、良好であった。
(工程6(2))貼り合わせ基板におけるシリコン基板1を厚さが50μmになるまで研削加工した。このときの研削加工条件は、シリコン基板1の厚さとして、1段目の研削で100μmまで薄くし、2段目の研削で更に50μmへ仕上げた。
その結果、貼り合わせ基板の外周部分に接合部からのシリコン基板1の剥離が認められた。
なお、以降の試験例においても2回目の研削加工(工程6(2))において1段目の研削−2段目の研削の手順で処理を行った。
(工程7)薄化後のシリコン基板1’を電子工業用混酸(鏡面化処理液SiエッチE、日本化成(株)製)を用いて、スピンエッチングして除去した。
(工程8)最後に露出した第1シリコン酸化膜2をフッ化水素水溶液によりエッチングして除去し、シリコン活性層3を露出させた。その結果、図2に示すように、シリコン活性層3の外周部分に剥がれが認められた。
試験例1において、2回目の研削加工(工程6(2))を行わず、それ以外は試験例1と同様にして、ハイブリッド基板を作製した。その結果、シリコン活性層3の外周部分に剥がれが認められた。
試験例1において、2回目の結合熱処理(工程5(2))の熱処理温度を175℃にしたところ、貼り合わせ基板の外周部分に接合部からのシリコン基板1の剥がれが認められ、以降の処理を行わなかった。
試験例1において、1回目の結合熱処理(工程5(1))の熱処理温度を175℃にしたところ、貼り合わせ基板の外周部分に接合部からのシリコン基板1の剥がれが認められ、以降の処理を行わなかった。
試験例1において、外周トリミング以降の処理を以下の条件に変更して行った。
貼り合わせ基板の外周を1mmだけトリミングする加工を行った。
(工程5(2))貼り合わせ基板を170℃、24時間の結合熱処理を施した。その結果、貼り合わせ基板の外観は剥離等の異常なく、良好であった。
(工程6(2))貼り合わせ基板におけるシリコン基板1を厚さが50μmになるまで研削加工した。その結果、貼り合わせ基板の外観は良好であった。
(工程7)薄化後のシリコン基板1’を電子工業用混酸(鏡面化処理液SiエッチE、日本化成(株)製)を用いて、スピンエッチングして除去した。
(工程8)最後に露出した第1シリコン酸化膜2をフッ化水素水溶液によりエッチングして除去し、シリコン活性層3を露出させた。その結果、シリコン活性層3の外観は良好であった。
次いで、シリコン活性層3を厚さ280nmになるまで研磨して薄膜化し、SOI構造のハイブリッド基板を得た。
試験例1において、外周トリミング以降の処理を以下の条件に変更して行った。
貼り合わせ基板の外周を1mmだけトリミングする加工を行った。
(工程5(2))貼り合わせ基板を175℃、24時間の結合熱処理を施した。その結果、貼り合わせ基板に基板の剥がれが認められた。
(工程6(2))貼り合わせ基板におけるシリコン基板1を厚さが50μmになるまで研削加工した。その結果、貼り合わせ基板の外周部分に接合部からのシリコン基板1の剥離が認められた。
(工程7)薄化後のシリコン基板1’を電子工業用混酸(鏡面化処理液SiエッチE、日本化成(株)製)を用いて、スピンエッチングして除去した。
(工程8)最後に露出した第1シリコン酸化膜2をフッ化水素水溶液によりエッチングして除去し、シリコン活性層3を露出させた。その結果、図3に示すように、シリコン活性層3の外周部分に剥がれや浮きが認められた。
試験例1において、貼り合わせ工程(工程4)以降の処理を以下の条件に変更して行った。
(工程4)SOI基板とサファイア基板5とを100℃に加熱しながら、当接させ、貼り合わせた。
次に、SOI基板と支持基板の結合力を高める結合熱処理(工程5)と、上記貼り合わせ基板のシリコン基板1を研削して薄化する研削薄化処理(工程6)との組み合わせを2回繰り返して行った。
(工程5(1))貼り合わせ基板を150℃、24時間の結合熱処理を施した。その結果、貼り合わせ基板の外観は剥離等の異常なく、良好であった。
(工程6(1))貼り合わせ基板におけるシリコン基板1を厚さが150μmになるまで研削加工した。その結果、外観は良好であった。
貼り合わせ基板の外周のトリミング加工は行わなかった。
(工程5(2))貼り合わせ基板を175℃、24時間の結合熱処理を施した。その結果、貼り合わせ基板の外観は剥離等の異常なく、良好であった。
(工程6(2))貼り合わせ基板におけるシリコン基板1を厚さが50μmになるまで研削加工した。その結果、貼り合わせ基板の外周部分に接合部からのシリコン基板1の剥離が認められた。
(工程7)薄化後のシリコン基板1’を電子工業用混酸(鏡面化処理液SiエッチE、日本化成(株)製)を用いて、スピンエッチングして除去した。
(工程8)最後に露出した第1シリコン酸化膜2をフッ化水素水溶液によりエッチングして除去し、シリコン活性層3を露出させた。その結果、シリコン活性層3の外周部分に剥がれが認められた。研削加工時に研削ホイールが引っ掛かる状態となり、シリコン基板1を剥がす応力が作用するためと推定される。
試験例7において、工程5(2)の結合熱処理温度を200℃とし、2回目の研削加工処理(工程6(2))として、貼り合わせ基板におけるシリコン基板1を厚さが80μmになるまで研削加工したところ、貼り合わせ基板の外観は剥離等の異常なく、良好であった。次いで、工程7、8として、試験例7と同様に、エッチングしてシリコン活性層3を露出させた。その結果、シリコン活性層3の外観は良好であった。最後に、シリコン活性層3を厚さ280nmになるまで研磨して薄膜化し、SOI構造のハイブリッド基板を得た。
試験例1において、貼り合わせ工程(工程4)以降の処理を以下の条件に変更して行った。
(工程4)SOI基板とサファイア基板5とを120℃に加熱しながら、当接させ、貼り合わせた。
次に、SOI基板と支持基板の結合力を高める結合熱処理(工程5)と、上記貼り合わせ基板のシリコン基板1を研削して薄化する研削薄化処理(工程6)との組み合わせを2回繰り返して行った。
(工程5(1))貼り合わせ基板を150℃、24時間の結合熱処理を施した。その結果、貼り合わせ基板の外観は剥離等の異常なく、良好であった。
(工程6(1))貼り合わせ基板におけるシリコン基板1を厚さが150μmになるまで研削加工した。その結果、外観は良好であった。
貼り合わせ基板の外周のトリミング加工は行わなかった。
(工程5(2))貼り合わせ基板を200℃、24時間の結合熱処理を施した。その結果、貼り合わせ基板の外観は剥離等の異常なく、良好であった。
(工程6(2))貼り合わせ基板におけるシリコン基板1を厚さが80μmになるまで研削加工した。その結果、貼り合わせ基板の外観は良好であった。
(工程7)薄化後のシリコン基板1’を電子工業用混酸(鏡面化処理液SiエッチE、日本化成(株)製)を用いて、スピンエッチングして除去した。
(工程8)最後に露出した第1シリコン酸化膜2をフッ化水素水溶液によりエッチングして除去し、シリコン活性層3を露出させた。その結果、シリコン活性層3の外観は良好であった。
次いで、シリコン活性層3を厚さ280nmになるまで研磨して薄膜化し、SOI構造のハイブリッド基板を得た。
試験例1において、貼り合わせ工程(工程4)以降の処理を以下の条件に変更して行った。
(工程4)SOI基板とサファイア基板5とを150℃に加熱しながら、当接させ、貼り合わせた。
次に、SOI基板と支持基板の結合力を高める結合熱処理(工程5)と、上記貼り合わせ基板のシリコン基板1を研削して薄化する研削薄化処理(工程6)との組み合わせを2回繰り返して行った。
(工程5(1))貼り合わせ基板を175℃、24時間の結合熱処理を施した。その結果、貼り合わせ基板の外観は剥離等の異常なく、良好であった。
(工程6(1))貼り合わせ基板におけるシリコン基板1を厚さが120μmになるまで研削加工した。その結果、貼り合わせ基板の外周部分に接合部からのシリコン基板1の剥離が認められた。
貼り合わせ基板の外周のトリミング加工は行わなかった。
(工程5(2))貼り合わせ基板を200℃、24時間の結合熱処理を施した。その結果、貼り合わせ基板の外観は剥離等の異常なく、良好であった。
(工程6(2))貼り合わせ基板におけるシリコン基板1を厚さが80μmになるまで研削加工した。その結果、貼り合わせ基板の外周部分に接合部からのシリコン基板1の剥離が認められた。
(工程7)薄化後のシリコン基板1’を電子工業用混酸(鏡面化処理液SiエッチE、日本化成(株)製)を用いて、スピンエッチングして除去した。
(工程8)最後に露出した第1シリコン酸化膜2をフッ化水素水溶液によりエッチングして除去し、シリコン活性層3を露出させた。その結果、シリコン活性層3の外周部分に剥がれが認められた。研削加工時に研削ホイールが引っ掛かる状態となり、シリコン基板1を剥がす応力が作用するためと推定される。
試験例10において、工程6(1)以降の処理を以下の条件に変更して行った。
(工程6(1))貼り合わせ基板におけるシリコン基板1を厚さが150μmになるまで研削加工した。その結果、外観は良好であった。
貼り合わせ基板の外周のトリミング加工は行わなかった。
(工程5(2))貼り合わせ基板を200℃、24時間の結合熱処理を施した。その結果、貼り合わせ基板の外観は剥離等の異常なく、良好であった。
(工程6(2))貼り合わせ基板におけるシリコン基板1を厚さが60μmになるまで研削加工した。その結果、貼り合わせ基板の外観は良好であった。
(工程7)薄化後のシリコン基板1’を電子工業用混酸(鏡面化処理液SiエッチE、日本化成(株)製)を用いて、スピンエッチングして除去した。
(工程8)最後に露出した第1シリコン酸化膜2をフッ化水素水溶液によりエッチングして除去し、シリコン活性層3を露出させた。その結果、シリコン活性層3の外観は良好であった。
次いで、シリコン活性層3を厚さ280nmになるまで研磨して薄膜化し、SOI構造のハイブリッド基板を得た。
試験例10において、工程6(1)以降の処理を以下の条件に変更して行った。
(工程6(1))貼り合わせ基板におけるシリコン基板1を厚さが200μmになるまで研削加工した。その結果、外観は良好であった。
貼り合わせ基板の外周のトリミング加工は行わなかった。
(工程5(2))貼り合わせ基板を200℃、24時間の結合熱処理を施した。その結果、貼り合わせ基板の外観は剥離等の異常なく、良好であった。
(工程6(2))貼り合わせ基板におけるシリコン基板1を厚さが75μmになるまで研削加工した。その結果、貼り合わせ基板の外観は良好であった。
(工程7)薄化後のシリコン基板1’を電子工業用混酸(鏡面化処理液SiエッチE、日本化成(株)製)を用いて、スピンエッチングして除去した。
(工程8)最後に露出した第1シリコン酸化膜2をフッ化水素水溶液によりエッチングして除去し、シリコン活性層3を露出させた。その結果、シリコン活性層3の外観は良好であった。
次いで、シリコン活性層3を厚さ280nmになるまで研磨して薄膜化し、SOI構造のハイブリッド基板を得た。
試験例1において、貼り合わせ工程(工程4)以降の処理を以下の条件に変更して行った。
(工程4)SOI基板とサファイア基板5とを175℃に加熱しながら、当接させ、貼り合わせた。
次に、SOI基板と支持基板の結合力を高める結合熱処理(工程5)と、上記貼り合わせ基板のシリコン基板1を研削して薄化する研削薄化処理(工程6)との組み合わせを2回繰り返して行った。
(工程5(1))貼り合わせ基板を175℃、24時間の結合熱処理を施した。その結果、貼り合わせ基板の外観は剥離等の異常なく、良好であった。
(工程6(1))貼り合わせ基板におけるシリコン基板1を厚さが150μmになるまで研削加工した。その結果、外観は良好であった。
貼り合わせ基板の外周のトリミング加工は行わなかった。
(工程5(2))貼り合わせ基板を200℃、24時間の結合熱処理を施した。その結果、貼り合わせ基板の外観は剥離等の異常なく、良好であった。
(工程6(2))貼り合わせ基板におけるシリコン基板1を厚さが50μmになるまで研削加工した。その結果、貼り合わせ基板の外観が良好である場合と、外周部分に接合部からのシリコン基板1の剥離が認められる場合とがあった。
(工程7)薄化後のシリコン基板1’を電子工業用混酸(鏡面化処理液SiエッチE、日本化成(株)製)を用いて、スピンエッチングして除去した。
(工程8)最後に露出した第1シリコン酸化膜2をフッ化水素水溶液によりエッチングして除去し、シリコン活性層3を露出させた。その結果、研削加工後の貼り合わせ基板の外観が良好なものはシリコン活性層3の外観は良好であった。一方、研削加工後の貼り合わせ基板の外周に剥がれが認められたものは、シリコン活性層3の外周部分に剥がれが認められた。外周部分に剥がれが認められる場合には、研削加工時に研削ホイールが引っ掛かる状態となり、シリコン基板1を剥がす応力が作用するためと推定される。
シリコン活性層3の良好なものについて、シリコン活性層3を厚さ280nmになるまで研磨して薄膜化し、SOI構造のハイブリッド基板を得た。
この試験例13の結果より、50μmまでの薄化は(研削時に外周の浮いた部分が引っ掛かり剥離を起こす可能性が高く)安定しているとは言いがたく、50μmよりも厚く残した方がよい。好ましくは60μm以上である。
試験例13において、2回目の研削加工処理(工程6(2))として、貼り合わせ基板におけるシリコン基板1を厚さが75μmになるまで研削加工したところ、貼り合わせ基板の外観は剥離等の異常なく、良好であった。次いで、工程7、8として、試験例13と同様に、エッチングしてシリコン活性層3を露出させた。その結果、シリコン活性層3の外観は良好であった。最後に、シリコン活性層3を厚さ280nmになるまで研磨して薄膜化し、SOI構造のハイブリッド基板を得た。
試験例13において、2回目の研削加工処理(工程6(2))として、貼り合わせ基板におけるシリコン基板1を厚さが85μmになるまで研削加工したところ、貼り合わせ基板の外観は剥離等の異常なく、良好であった。次いで、工程7、8として、試験例13と同様に、エッチングしてシリコン活性層3を露出させた。その結果、シリコン活性層3の外観は良好であった。最後に、シリコン活性層3を厚さ280nmになるまで研磨して薄膜化し、SOI構造のハイブリッド基板を得た。
試験例13において、貼り合わせ基板の外周を1mmだけトリミングする加工を行い、それ以外は試験例13と同様に、2回目の研削加工処理(工程6(2))まで行ったところ、貼り合わせ基板の外観は剥離等の異常なく、良好であった。次いで、工程7、8として、試験例13と同様に、エッチングしてシリコン活性層3を露出させた。その結果、シリコン活性層3の外観は良好であった。最後に、シリコン活性層3を厚さ280nmになるまで研磨して薄膜化し、SOI構造のハイブリッド基板を得た。
トリミング加工があると、シリコン活性層3の外周部分の剥がれ等がなく、有利であるが、試験例14、15のように、結合熱処理温度を増加させることで貼り合わせ基板の結合力が上がり、適切な研削加工を行えば、トリミング加工がなくても、基板外周の剥がれは生じない。
試験例1において、貼り合わせ工程(工程4)以降の処理を以下の条件に変更して行った。
(工程4)SOI基板とサファイア基板5とを225℃に加熱しながら、当接させ、貼り合わせた。
次に、SOI基板と支持基板の結合力を高める結合熱処理(工程5)と、上記貼り合わせ基板のシリコン基板1を研削して薄化する研削薄化処理(工程6)との組み合わせを2回繰り返し行った。なお、本試験例の条件では2回目の結合熱処理を省略した。
(工程5(1))貼り合わせ基板を225℃、24時間の結合熱処理を施した。その結果、貼り合わせ基板の外観は剥離等の異常なく、良好であった。なお、貼り合わせ基板の反りが大きく、以降の研削加工が難しかったが加工可能であった。
(工程6(1))貼り合わせ基板におけるシリコン基板1を厚さが150μmになるまで研削加工した。その結果、外観は良好であった。
貼り合わせ基板の外周のトリミング加工は行わなかった。
(工程5(2))上記1回目の結合熱処理によってSOI基板とサファイア基板5との間で十分な結合が得られることが分かったため、2回目の結合熱処理を省略した。
(工程6(2))貼り合わせ基板におけるシリコン基板1を厚さが50μmになるまで研削加工した。その結果、外観は良好であった。
(工程7)薄化後のシリコン基板1’を電子工業用混酸(鏡面化処理液SiエッチE、日本化成(株)製)を用いて、スピンエッチングして除去した。
(工程8)最後に露出した第1シリコン酸化膜2をフッ化水素水溶液によりエッチングして除去し、シリコン活性層3を露出させた。その結果、シリコン活性層3の外観は良好であった。
最後に、シリコン活性層3を厚さ280nmになるまで研磨して薄膜化し、SOI構造のハイブリッド基板を得た。
以上の結果を表1に示す。
また、試験例17に示すように、1回目の結合熱処理の温度が200℃以上250℃未満の場合にはその結合熱処理だけでSOI基板と支持基板とを十分に結合できるため、2回目の結合熱処理を省略することができる。この場合、工程5、6(結合熱処理、研削加工)の組み合わせが3回以上のときは2回目以降の結合熱処理を省略することができる。
2 第1シリコン酸化膜(Box層)
3 シリコン活性層
4 第2シリコン酸化膜
5 サファイア基板(支持基板)
Claims (13)
- シリコン基板上に第1シリコン酸化膜とシリコン活性層とをこの順番で積層してなり、該シリコン基板面外周部に上記シリコン活性層を有しないテラス部を形成したSOI基板を準備し、
該SOI基板のシリコン活性層表面に第2シリコン酸化膜を形成し、
上記SOI基板と該SOI基板と熱膨張率の異なる支持基板とを貼り合わせるに際し、該SOI基板及び/又は支持基板の貼り合わせる面を活性化処理し、
上記SOI基板と支持基板とを室温より高温で第2シリコン酸化膜を介して貼り合わせて貼り合わせ基板とし、
次いで、上記貼り合わせ基板についてSOI基板と支持基板の結合力を高める結合熱処理と、上記シリコン基板を研削して薄化する研削薄化処理との組み合わせを少なくとも2回繰り返して行うに際し、1回目の結合熱処理の温度を上記貼り合わせの温度以上とし、1回目の研削薄化処理後のシリコン基板の厚さを最も薄くとも130μmまでとし、最終回の結合熱処理の温度を200℃以上250℃未満とし、最終回の研削薄化処理後のシリコン基板の厚さを最も薄くとも60μmまでとして上記結合熱処理及び研削薄化処理を行い、
次に、上記薄化したシリコン基板をエッチングにより除去して第1シリコン酸化膜を露出させ、
更に、露出した第1シリコン酸化膜をエッチングにより除去して、支持基板上にシリコン酸化膜を介してシリコン活性層を有するハイブリッド基板を得ることを特徴とするハイブリッド基板の製造方法。 - 上記SOI基板と支持基板の貼り合わせ温度を、100℃以上250℃未満とすることを特徴とする請求項1記載のハイブリッド基板の製造方法。
- 上記SOI基板と支持基板の結合力を高める結合熱処理温度を、上記貼り合わせ温度に0~100℃加算した温度(ただし、250℃未満とする)とすることを特徴とする請求項1又は2記載のハイブリッド基板の製造方法。
- 2回目以降の結合熱処理温度をその1回前の結合熱処理温度よりも高くすることを特徴とする請求項1~3のいずれか1項記載のハイブリッド基板の製造方法。
- 上記1回目の結合熱処理の温度が200℃以上250℃未満の場合、2回目以降の結合熱処理を省略することを特徴とする請求項1~3のいずれか1項記載のハイブリッド基板の製造方法。
- 上記1回目の研削薄化処理後のシリコン基板の厚さを130μm以上200μm以下とすることを特徴とする請求項1~5のいずれか1項記載のハイブリッド基板の製造方法。
- 上記最終回の研削薄化処理後のシリコン基板の厚さを60μm以上100μm以下とすることを特徴とする請求項1~6のいずれか1項記載のハイブリッド基板の製造方法。
- 上記テラス部の幅は、1mm以上3mm以下であることを特徴とする請求項1~7のいずれか1項記載のハイブリッド基板の製造方法。
- 上記SOI基板のシリコン活性層は、空孔型欠陥がなく、熱酸化により酸化誘起積層欠陥が発生しないものであることを特徴とする請求項1~8のいずれか1項記載のハイブリッド基板の製造方法。
- 上記支持基板は、石英ガラス、ホウ珪酸ガラス又はサファイアからなることを特徴とする請求項1~9のいずれか1項記載のハイブリッド基板の製造方法。
- 上記SOI基板と支持基板との貼り合わせの前に、上記支持基板について還元性雰囲気中の熱処理を行うことを特徴とする請求項1~10のいずれか1項記載のハイブリッド基板の製造方法。
- 上記支持基板のSOI基板と貼り合わされる面の所定幅の外周領域を中央部よりも凹むように薄くすることを特徴とする請求項1~11のいずれか1項記載のハイブリッド基板の製造方法。
- 請求項1~12のいずれか1項記載のハイブリッド基板の製造方法により製造された、支持基板上にシリコン酸化膜を介してシリコン活性層を有するハイブリッド基板。
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EP2993686B1 (en) | 2021-05-26 |
JP6168143B2 (ja) | 2017-07-26 |
EP2993686A1 (en) | 2016-03-09 |
EP2993686A4 (en) | 2016-11-30 |
CN105190835A (zh) | 2015-12-23 |
KR102229397B1 (ko) | 2021-03-17 |
CN105190835B (zh) | 2018-11-09 |
US9741603B2 (en) | 2017-08-22 |
JPWO2014178356A1 (ja) | 2017-02-23 |
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US20160071761A1 (en) | 2016-03-10 |
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