WO2013105634A1 - 熱酸化異種複合基板及びその製造方法 - Google Patents
熱酸化異種複合基板及びその製造方法 Download PDFInfo
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- WO2013105634A1 WO2013105634A1 PCT/JP2013/050387 JP2013050387W WO2013105634A1 WO 2013105634 A1 WO2013105634 A1 WO 2013105634A1 JP 2013050387 W JP2013050387 W JP 2013050387W WO 2013105634 A1 WO2013105634 A1 WO 2013105634A1
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- heterogeneous composite
- thermally oxidized
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- 239000000758 substrate Substances 0.000 title claims abstract description 85
- 239000002131 composite material Substances 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 238000010438 heat treatment Methods 0.000 claims abstract description 36
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 24
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229910052594 sapphire Inorganic materials 0.000 claims description 27
- 239000010980 sapphire Substances 0.000 claims description 27
- 230000003647 oxidation Effects 0.000 claims description 21
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 18
- 239000010453 quartz Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 229910052786 argon Inorganic materials 0.000 claims description 9
- 239000011521 glass Substances 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 239000001307 helium Substances 0.000 claims description 5
- 229910052734 helium Inorganic materials 0.000 claims description 5
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 5
- 239000011261 inert gas Substances 0.000 claims description 5
- 230000007547 defect Effects 0.000 abstract description 23
- 235000012431 wafers Nutrition 0.000 description 36
- 239000010408 film Substances 0.000 description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 239000000463 material Substances 0.000 description 6
- 238000012545 processing Methods 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000009279 wet oxidation reaction Methods 0.000 description 3
- 238000007689 inspection Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
Definitions
- the present invention relates to a thermally oxidized heterogeneous composite substrate obtained by thermally oxidizing a heterogeneous composite substrate in which a single crystal silicon film is formed on a handle substrate made of glass, quartz, sapphire or the like, and a method for manufacturing the same.
- Silicon on insulator (SOI) wafers are becoming widely used to reduce parasitic capacitance and measure device speed.
- SOI wafers wafers in which handle wafers of silicon on quartz (SOQ) and silicon on sapphire (SOS) are made of an insulating transparent wafer are attracting attention.
- SOQ is expected to be applied to optoelectronics utilizing the high transparency of quartz, or to high frequency devices utilizing low dielectric loss. Since SOS has a handle wafer made of sapphire, it has high thermal conductivity that cannot be obtained with quartz in addition to high transparency and low dielectric loss, so it is expected to be applied to high-frequency devices that generate heat. .
- bonded wafers made of different materials are concerned about defects induced during the process.
- a normal device process includes high-temperature processing exceeding 850 ° C. for forming a gate oxide film.
- dissimilar composite substrates the silicon thin film is subjected to strong compressive and tensile stresses by such a high temperature process, and various defects (such as minute cracks) may occur. is there.
- the heterogeneous composite substrate has a large difference in expansion coefficient between a support substrate called a handle substrate and an upper silicon thin film, which is an essential problem of the heterogeneous composite substrate.
- the present invention has been made in view of the above circumstances, and a thermally oxidized heterogeneous composite substrate in which defects such as microcracks are reduced as much as possible after performing high-temperature processing exceeding 850 ° C. in order to form an oxide film. And it aims at providing the manufacturing method.
- an insulating transparent wafer (quartz, glass, sapphire, etc.) to which a silicon thin film has been transferred is subjected to an intermediate process before being subjected to a high temperature process exceeding 850 ° C. It has been found that it is effective to add heat treatment to be called heat treatment and to set the temperature of this intermediate heat treatment to 650 ° C. or higher and 850 ° C. or lower.
- this intermediate heat treatment is a treatment for reducing defects that appear due to a high-temperature treatment exceeding 850 ° C. by interposing an intermediate heat treatment (650 ° C. or higher and 850 ° C. or lower). It can be said that the localized stress is averaged over the entire wafer surface. The cause of the localized stress is presumed to be the distortion and roughness of the material of the handle substrate, non-uniformity in the bonding process, and the like. In addition, this intermediate heat treatment sufficiently increases the bonding strength at the bonding interface before reaching the high temperature processing temperature, and does not cause peeling or misalignment even when the silicon thin film is subjected to strong stress. It is. Then, after the intermediate heat treatment, the number of defects after oxidation can be reduced by performing a high temperature treatment such as oxidation.
- the present invention provides the following thermally oxidized heterogeneous composite substrate and a method for manufacturing the same.
- It is a heterogeneous composite substrate having a single crystal silicon film on the handle substrate, and an intermediate heat treatment from 650 ° C. to 850 ° C. is performed before the thermal oxidation process exceeding 850 ° C., and then the temperature exceeds 850 ° C.
- Thermally oxidized heterogeneous composite substrate obtained by applying thermal oxidation treatment.
- a thermally oxidized heterogeneous composite substrate with a reduced number of defects after thermal oxidation can be obtained.
- the thermally oxidized heterogeneous composite substrate of the present invention is obtained by subjecting a heterogeneous composite substrate having a single crystal silicon film on a handle substrate to an intermediate heat treatment at 650 to 850 ° C., and then performing a thermal oxidation process at a temperature exceeding 850 ° C. can get.
- glass, quartz, sapphire and the like are the main subjects. These materials have a different expansion coefficient from silicon. The expansion coefficient is shown in Table 1 below.
- the SOQ that can be obtained by bonding silicon and quartz has a difference in expansion coefficient of 2.04 ppm.
- the minimum is 4.4 ppm and the maximum is 5.1 ppm.
- sapphire has a different expansion coefficient depending on the orientation, the effect of the present invention can be further improved by using a sapphire substrate having a small expansion coefficient in order to reduce the difference in expansion coefficient. Specifically, it is effective to avoid the use of an A-plane wafer having a large expansion coefficient and use the C-plane (7.0 ppm) or the R-plane (about 7.4 ppm).
- the thermal expansion coefficient of the handle substrate is preferably 0.54 to 7.4 ppm at 400 ° C. or less, and in the case of a sapphire wafer, the expansion coefficient is preferably 7.4 ppm or less from room temperature to 400 ° C. .
- the thickness of the handle substrate is preferably 500 to 800 ⁇ m, particularly 600 to 725 ⁇ m, and the thickness of the single crystal silicon film is preferably 50 to 500 nm, particularly 100 to 350 nm.
- the thickness is preferably 25 to 150 nm.
- the BOX oxide film may be formed by a method similar to that disclosed in Japanese Patent Laid-Open No. 2002-305292 for forming a buried oxide film on an SOI wafer.
- an intermediate heat treatment at 650 to 850 ° C., preferably 700 to 850 ° C. is performed.
- the atmosphere of the intermediate heat treatment is not particularly limited as long as it is easy to handle. Typical examples include argon, nitrogen, oxygen, hydrogen, helium and the like. Further, an inert gas such as argon or nitrogen and an oxidizing gas may be mixed.
- the time for the intermediate heat treatment is preferably 0.5 to 6 hours, particularly 1 to 3 hours. If it is too short, the object of the present invention may not be sufficiently achieved. If it is too long, the cost may increase.
- a thermal oxidation treatment is performed after the intermediate heat treatment.
- the heat treatment temperature is a temperature exceeding 850 ° C., preferably a temperature exceeding 900 ° C. to 1,000 ° C., particularly 950 to 1,000 ° C.
- the thickness is not particularly limited as long as a desired oxide film thickness is obtained.
- the intermediate heat treatment can be performed at 650 to 900 ° C., particularly 700 to 900 ° C.
- the heat treatment atmosphere is generally dry oxygen, water vapor or the like.
- the heat treatment time is not particularly limited as long as a desired oxide film thickness can be obtained.
- a thermally oxidized heterogeneous composite substrate having a significantly reduced number of defects can be obtained, but an HF immersion test can be applied to determine the number of defects in the composite substrate.
- the inspection can be easily performed. If it is too thin, HF will not penetrate, and if it is too thick, penetration of HF will be too fast, which may cause a disadvantage in inspection.
- Example 1 A plurality of SOS wafers using a sapphire wafer (R surface) having a diameter of 150 mm and a thickness of 600 ⁇ m as a supporting substrate were prepared.
- the thickness of silicon is 200 nm
- the thickness of the BOX layer is 200 nm.
- This wafer was subjected to intermediate heat treatment at 600 ° C., 650 ° C., 700 ° C., 800 ° C., 850 ° C., and 900 ° C.
- the atmosphere was argon gas and the holding time was 1 hour.
- One reference wafer without intermediate heat treatment was added, and a 200 nm oxide film was formed on these wafers by wet oxidation at 1,000 ° C.
- Example 2 A plurality of SOQ wafers using a quartz wafer having a diameter of 150 mm and a thickness of 625 ⁇ m as a supporting substrate were prepared.
- the thickness of silicon is 200 nm
- the thickness of the BOX layer is 200 nm.
- This wafer was subjected to intermediate heat treatment at 600 ° C., 650 ° C., 700 ° C., 800 ° C., 850 ° C., and 900 ° C.
- the atmosphere was argon gas and the holding time was 1 hour.
- One reference wafer without intermediate heat treatment was added, and a 200 nm oxide film was formed on these wafers by wet oxidation at 950 ° C.
- Example 3 A plurality of SOS wafers using a sapphire wafer having a diameter of 150 mm and a thickness of 600 ⁇ m as a supporting substrate were prepared.
- the thickness of silicon is 200 nm
- the thickness of the BOX layer is 200 nm.
- An intermediate heat treatment at 800 ° C. was applied to these wafers.
- the atmosphere was argon gas and the holding time was 1 hour.
- a 200 nm oxide film was formed on these wafers by wet oxidation at 1,000 ° C.
- This method has been described in an embodiment specific to quartz and sapphire, but is equally effective when a material having a thermal expansion coefficient (0.54 to 7.4 ppm) between quartz and sapphire is used as a handle substrate. is there.
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Abstract
Description
また、この中間の熱処理は、貼り合わせ界面の貼り合わせ強度を、上記高温処理温度に到達する前に十分に高め、シリコン薄膜が強い応力を受けた際にも剥がれやズレを生じさせないための処理である。
そして、この中間熱処理を経た後に酸化などの高温処理を施すことで、酸化後の欠陥数を低減することが可能となるものである。
〔1〕
ハンドル基板上に単結晶シリコン膜を有する異種複合基板であり、850℃を超えた熱酸化処理を施す前に650℃から850℃までの中間熱処理を加え、然る後に850℃を超えた温度で熱酸化処理を施すことで得られる熱酸化異種複合基板。
〔2〕
ハンドル基板がガラス、石英、サファイアのいずれかであることを特徴とする〔1〕に記載の熱酸化異種複合基板。
〔3〕
ハンドル基板と単結晶シリコン膜との間に埋め込み酸化膜が介在することを特徴とする〔1〕又は〔2〕に記載の熱酸化異種複合基板。
〔4〕
中間熱処理の雰囲気が、アルゴン、窒素、酸素、水素、ヘリウム、又は不活性ガスと酸素を混合した雰囲気であることを特徴とする〔1〕~〔3〕のいずれかに記載の熱酸化異種複合基板。
〔5〕
ハンドル基板の熱膨張係数が400℃以下で0.54ppm以上7.4ppm以下であることを特徴とする〔1〕~〔4〕のいずれかに記載の熱酸化異種複合基板。
〔6〕
ハンドル基板がサファイアであり、サファイアウェーハの膨張係数が室温から400℃で7.4ppm以下であることを特徴とする〔5〕に記載の熱酸化異種複合基板。
〔7〕
ハンドル基板上に単結晶シリコン膜を有する異種複合基板に対し650~850℃の中間熱処理を加えた後、850℃を超えた温度で熱酸化処理を施すことを特徴とする熱酸化異種複合基板の製造方法。
〔8〕
ハンドル基板がガラス、石英、サファイアのいずれかであることを特徴とする〔7〕に記載の熱酸化異種複合基板の製造方法。
〔9〕
異種複合基板が、ハンドル基板と単結晶シリコン膜との間に埋め込み酸化膜が介在するものであることを特徴とする〔7〕又は〔8〕に記載の熱酸化異種複合基板の製造方法。
〔10〕
中間熱処理の雰囲気が、アルゴン、窒素、酸素、水素、ヘリウム、又は不活性ガスと酸素を混合した雰囲気であることを特徴とする〔7〕~〔9〕のいずれかに記載の熱酸化異種複合基板の製造方法。
〔11〕
ハンドル基板の熱膨張係数が400℃以下で0.54ppm以上7.4ppm以下であることを特徴とする〔7〕~〔10〕のいずれかに記載の熱酸化異種複合基板の製造方法。
〔12〕
ハンドル基板がサファイアであり、サファイアウェーハの膨張係数が室温から400℃で7.4ppm以下であることを特徴とする〔11〕に記載の熱酸化異種複合基板の製造方法。
この場合、ハンドル基板と単結晶シリコン膜との間に埋め込み酸化膜(BOX層:Box=Buried oxide)を介在させることもできる。
また、上記ハンドル基板の厚さは500~800μm、特に600~725μmが好ましく、単結晶シリコン膜の厚さは50~500nm、特に100~350nmが好ましい。埋め込み酸化膜(BOX酸化膜)を介在させる場合、その厚さは25~150nmが好ましい。なお、BOX酸化膜は、特開2002-305292号公報において、SOIウェーハの埋め込み酸化膜の成膜について開示されているのと同様の方法で形成すればよい。
この中間熱処理の雰囲気は、扱いやすいものであれば、特に限定を受けることはない。代表的なものとして、アルゴン、窒素、酸素、水素、ヘリウム等が挙げられる。また、アルゴンや窒素などの不活性ガスと酸化ガスを混合しても構わない。
また、中間熱処理の時間は、0.5~6時間、特に1~3時間であることが好ましい。短すぎると、本発明の目的が十分達成されないおそれがあり、長すぎると、コストの上昇を招くおそれがある。
熱処理時間は、所望の酸化膜厚が得られれば特に限定はない。
直径150mm、厚さ600μmのサファイアウェーハ(R面)を支持基板とするSOSウェーハを複数枚用意した。シリコンの厚さは200nm、BOX層の厚さは200nmである。このウェーハに、600℃、650℃、700℃、800℃、850℃、900℃の中間熱処理を加えた。雰囲気はアルゴンガスとし、保持時間を1時間とした。中間熱処理を施さないリファレンスのウェーハ1枚を追加し、これらのウェーハに1,000℃でウェット酸化により、200nmの酸化膜を形成した。酸化後、これらのウェーハを10%HF溶液に30分間浸漬し、欠陥の数を数えたところ、図1の結果を得た。650℃から850℃までの中間熱処理を加えたものは、欠陥数が減少している。600℃の中間熱処理を加えたものは欠陥がそれほど減少していないのは、600℃が効果を発現させるには不十分な温度なためと思われる。また900℃で中間処理したものは、中間処理の時点で既に欠陥が発現してしまったためと思われる。最適な温度は650℃から850℃程度と考えられる。
直径150mm、厚さ625μmの石英ウェーハを支持基板とするSOQウェーハを複数枚用意した。シリコンの厚さは200nm、BOX層の厚さは200nmである。このウェーハに、600℃、650℃、700℃、800℃、850℃、900℃の中間熱処理を加えた。雰囲気はアルゴンガスとし、保持時間を1時間とした。中間熱処理を施さないリファレンスのウェーハ1枚を追加し、これらのウェーハに950℃でウェット酸化により、200nmの酸化膜を形成した。酸化後、これらのウェーハを10%HF溶液に30分間浸漬し、欠陥の数を数えたところ、図2の結果を得た。650℃から850℃までの中間熱処理を加えたものは、欠陥数が減少している。600℃の中間熱処理を加えたものは欠陥がそれほど減少していないのは、600℃が効果を発現させるには不十分な温度なためと思われる。また900℃で中間処理したものは、中間処理の時点で既に欠陥が発現してしまったためと思われる。最適な温度は650℃から850℃程度と考えられる。
直径150mm、厚さ600μmのサファイアウェーハを支持基板とするSOSウェーハを複数枚用意した。この時のサファイアの方位は、C面(熱膨張係数CTE=7.0ppm)、R面(熱膨張係数CTE=7.4ppm)、A面(熱膨張係数CTE=7.7ppm)とした。シリコンの厚さは200nm、BOX層の厚さは200nmである。これらのウェーハに、800℃の中間熱処理を加えた。雰囲気はアルゴンガスとし、保持時間を1時間とした。これらのウェーハに1,000℃でウェット酸化により、200nmの酸化膜を形成した。酸化後、これらのウェーハを10%HF溶液に30分間浸漬し、欠陥の数を数えたところ、図3の結果を得た。C面、R面はA面よりも効果的に欠陥の数が減少していることが分かった。
Claims (12)
- ハンドル基板上に単結晶シリコン膜を有する異種複合基板であり、850℃を超えた熱酸化処理を施す前に650℃から850℃までの中間熱処理を加え、然る後に850℃を超えた温度で熱酸化処理を施すことで得られる熱酸化異種複合基板。
- ハンドル基板がガラス、石英、サファイアのいずれかであることを特徴とする請求項1に記載の熱酸化異種複合基板。
- ハンドル基板と単結晶シリコン膜との間に埋め込み酸化膜が介在することを特徴とする請求項1又は2に記載の熱酸化異種複合基板。
- 中間熱処理の雰囲気が、アルゴン、窒素、酸素、水素、ヘリウム、又は不活性ガスと酸素を混合した雰囲気であることを特徴とする請求項1~3のいずれか1項に記載の熱酸化異種複合基板。
- ハンドル基板の熱膨張係数が400℃以下で0.54ppm以上7.4ppm以下であることを特徴とする請求項1~4のいずれか1項に記載の熱酸化異種複合基板。
- ハンドル基板がサファイアであり、サファイアウェーハの膨張係数が室温から400℃で7.4ppm以下であることを特徴とする請求項5に記載の熱酸化異種複合基板。
- ハンドル基板上に単結晶シリコン膜を有する異種複合基板に対し650~850℃の中間熱処理を加えた後、850℃を超えた温度で熱酸化処理を施すことを特徴とする熱酸化異種複合基板の製造方法。
- ハンドル基板がガラス、石英、サファイアのいずれかであることを特徴とする請求項7に記載の熱酸化異種複合基板の製造方法。
- 異種複合基板が、ハンドル基板と単結晶シリコン膜との間に埋め込み酸化膜が介在するものであることを特徴とする請求項7又は8に記載の熱酸化異種複合基板の製造方法。
- 中間熱処理の雰囲気が、アルゴン、窒素、酸素、水素、ヘリウム、又は不活性ガスと酸素を混合した雰囲気であることを特徴とする請求項7~9のいずれか1項に記載の熱酸化異種複合基板の製造方法。
- ハンドル基板の熱膨張係数が400℃以下で0.54ppm以上7.4ppm以下であることを特徴とする請求項7~10のいずれか1項に記載の熱酸化異種複合基板の製造方法。
- ハンドル基板がサファイアであり、サファイアウェーハの膨張係数が室温から400℃で7.4ppm以下であることを特徴とする請求項11に記載の熱酸化異種複合基板の製造方法。
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