CN104040686A - 热氧化异种复合基板及其制造方法 - Google Patents

热氧化异种复合基板及其制造方法 Download PDF

Info

Publication number
CN104040686A
CN104040686A CN201380005209.0A CN201380005209A CN104040686A CN 104040686 A CN104040686 A CN 104040686A CN 201380005209 A CN201380005209 A CN 201380005209A CN 104040686 A CN104040686 A CN 104040686A
Authority
CN
China
Prior art keywords
treatment
base plate
thermal oxidation
composite base
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201380005209.0A
Other languages
English (en)
Other versions
CN104040686B (zh
Inventor
秋山昌次
飞坂优二
永田和寿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Chemical Co Ltd
Original Assignee
Shin Etsu Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Chemical Co Ltd filed Critical Shin Etsu Chemical Co Ltd
Publication of CN104040686A publication Critical patent/CN104040686A/zh
Application granted granted Critical
Publication of CN104040686B publication Critical patent/CN104040686B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明涉及热氧化异种复合基板,是在处理基板上具有单晶硅膜的异种复合基板,通过在实施超过850℃的热氧化处理前施加650℃~850℃的中间热处理,然后在超过了850℃的温度下实施热氧化处理而得到,根据本发明,能够得到热氧化后的缺陷数减少的热氧化异种复合基板。

Description

热氧化异种复合基板及其制造方法
技术领域
本发明涉及通过对在玻璃、石英、蓝宝石等的处理基板上形成了单晶硅膜的异种复合基板进行热氧化处理而得到的热氧化异种复合基板及其制造方法。
背景技术
为了减少寄生电容,实现器件的高速化,已广泛使用绝缘体上硅(SOI(Silicon on insulator))晶片。该SOI晶片中,石英上硅(SOQ(Silicon on Quartz))、蓝宝石上硅(SOS(Silicon on Sapphire))这样的处理晶片由绝缘透明晶片构成的晶片受到关注。期待SOQ在利用了石英的高透明性的光电子学关系、或利用了低的介电损耗的高频器件中的应用。SOS由于处理晶片由蓝宝石构成,因此除了高透明性、低介电损耗以外,还具有对于石英未能获得的高热导率,因此期待在伴有发热的高频器件中的应用。
为了层叠具有高品质的单晶,由块体的硅晶片采用贴合-转印法形成硅薄膜是理想的。开发了在R面的蓝宝石上使硅层异质外延生长的方法,在玻璃上使非单晶硅生长、然后采用激光退火等提高结晶性的CG硅等,但可以说不存在胜过贴合法的方法。
但是,对于异种材料形成的贴合晶片(例:SOQ、SOS、SOG等),担心工艺中诱发的缺陷。具体地,通常的器件工艺中包含用于形成栅极氧化膜的超过850℃的高温处理等。对于这些异种材料贴合基板(以下称为异种复合基板),通过实施这样的高温工艺,硅薄膜受到强的压缩-拉伸应力,有时产生各种缺陷(微小的裂纹等)。其原因在于,异种复合基板在称为处理基板的支持基板与上层的硅薄膜之间存在大的膨胀系数之差,因此可以说是异种复合基板的本质上的问题。
发明内容
发明要解决的课题
本发明鉴于上述实际情况而进行,其目的在于提供为了形成氧化膜而进行了超过850℃的高温处理后使微小裂纹等缺陷尽可能减少的热氧化异种复合基板及其制造方法。
用于解决课题的手段
本发明人为了实现上述目的,反复深入研究,结果发现,在对转印了硅薄膜的绝缘透明晶片(石英、玻璃、蓝宝石等)施以超过850℃的高温工艺前,施加也应称为中间的热处理的热处理,使该中间的热处理的温度为650℃以上850℃以下是有效的。
即,该中间的热处理是用于通过将中间热处理(650℃以上850℃以下)介入从而使因超过850℃的高温处理而显现的缺陷减少的处理。也可称为使局部存在的应力在晶片全部表面中平均化的处理。对于局部存在的应力的原因,推测处理基板具有的材料的变形、疏密、贴合工艺的面内不均一等是原因所在。
此外,该中间的热处理是用于将贴合界面的贴合强度在到达上述高温处理温度前充分地提高,即使硅薄膜受到了强的应力时也不产生剥离、错位的处理。
而且,通过在经过该中间热处理后实施氧化等高温处理,能够减少氧化后的缺陷数。
因此,本发明提供下述热氧化异种复合基板及其制造方法。
[1]热氧化异种复合基板,是在处理基板上具有单晶硅膜的异种复合基板,通过在实施超过850℃的热氧化处理前施加650℃~850℃的中间热处理,然后在超过850℃的温度下实施热氧化处理而得到。
[2][1]所述的热氧化异种复合基板,其特征在于,处理基板为玻璃、石英、蓝宝石的任一种。
[3][1]或[2]所述的热氧化异种复合基板,其特征在于,在处理基板与单晶硅膜之间存在埋入氧化膜。
[4][1]~[3]的任一项所述的热氧化异种复合基板,其特征在于,中间热处理的气氛是氩、氮、氧、氢、氦、或将非活性气体与氧混合而成的气氛。
[5][1]~[4]的任一项所述的热氧化异种复合基板,其特征在于,处理基板的热膨胀系数在400℃以下为0.54ppm以上7.4ppm以下。
[6][5]所述的热氧化异种复合基板,其特征在于,处理基板为蓝宝石,蓝宝石晶片的膨胀系数在室温~400℃下为7.4ppm以下。
[7]热氧化异种复合基板的制造方法,其特征在于,对于在处理基板上具有单晶硅膜的异种复合基板施加650~850℃的中间热处理后,在超过850℃的温度下实施热氧化处理。
[8][7]所述的热氧化异种复合基板的制造方法,其特征在于,处理基板为玻璃、石英、蓝宝石的任一种。
[9][7]或[8]所述的热氧化异种复合基板的制造方法,其特征在于,异种复合基板在处理基板与单晶硅膜之间存在埋入氧化膜。
[10][7]~[9]的任一项所述的热氧化异种复合基板的制造方法,其特征在于,中间热处理的气氛为氩、氮、氧、氢、氦、或将非活性气体与氧混合而成的气氛。
[11][7]~[10]的任一项所述的热氧化异种复合基板的制造方法,其特征在于,处理基板的热膨胀系数在400℃以下为0.54ppm以上7.4ppm以下。
[12][11]所述的热氧化异种复合基板的制造方法,其特征在于,处理基板为蓝宝石,蓝宝石晶片的膨胀系数在室温~400℃下为7.4ppm以下。
发明的效果
根据本发明,能够得到热氧化后的缺陷数减少的热氧化异种复合基板。
附图说明
图1为表示在各种温度下进行中间热处理时的热氧化SOS晶片基板的HF缺陷数的坐标图。
图2为表示在各种温度下进行中间热处理时的热氧化SOQ晶片基板的HF缺陷数的坐标图。
图3为表示使用在各种蓝宝石方位具有单晶硅膜的SOS晶片进行中间热处理时的热氧化SOS晶片基板的HF缺陷数的坐标图。
具体实施方式
本发明的热氧化异种复合基板,通过对在处理基板上具有单晶硅膜的异种复合基板施加650~850℃的中间热处理后,在超过850℃的温度下实施热氧化处理而得到。
这种情况下,也能够在处理基板与单晶硅膜之间存在埋入氧化膜(BOX层:Box=Buried oxide(埋入氧化物))。
作为成为本发明的对象的复合基板的处理材料,玻璃、石英、蓝宝石等为主要的对象。这些材料具有与硅大不相同的膨胀系数。将其膨胀系数示于下述表1中。
[表1]
通过将硅与石英贴合而形成的SOQ的膨胀系数之差为2.04ppm,SOS的情形下,最小存在4.4ppm,最大存在5.1ppm。对于蓝宝石,膨胀系数因方位而不同,因此为了使膨胀系数差小,通过使用膨胀系数小的蓝宝石基板,能够进一步提高本发明的效果。具体地,避免使用膨胀系数大的A面晶片而使用C面(7.0ppm)或R面(7.4ppm左右)也是有效的。
因此,处理基板的热膨胀系数优选在400℃以下为0.54~7.4ppm,在蓝宝石晶片的情形下,优选其膨胀系数在室温~400℃下为7.4ppm以下。
此外,上述处理基板的厚度优选500~800μm,特别优选600~725μm,单晶硅膜的厚度优选50~500nm,特别优选100~350nm。中间存在埋入氧化膜(BOX氧化膜)的情况下,其厚度优选25~150nm。再有,BOX氧化膜可采用与在特开2002-305292号公报中对于SOI晶片的埋入氧化膜的成膜所公开的方法同样的方法形成。
对上述异种复合基板进行热氧化处理的情况下,首先实施650~850℃、优选地700~850℃的中间热处理。
该中间热处理的气氛只要容易处理,则并不会特别受到限定。作为代表性的气氛,可列举氩、氮、氧、氢、氦等。此外,也可将氩、氮等非活性气体与氧化气体混合。
此外,中间热处理的时间优选为0.5~6小时,特别优选为1~3小时。如果过短,有可能无法充分实现本发明的目的,如果过长,有可能招致成本的上升。
上述中间热处理后实施热氧化处理。作为该热氧化处理条件,可采用公知的条件,热处理温度为超过850℃的温度、优选地超过900℃的温度~1000℃,特别地为950~1000℃,只要是可获得所需的氧化膜厚的范围,则并无特别限定。再有,使热处理温度为超过900℃的温度的情形下,中间热处理能够为650~900℃、特别地为700~900℃。热处理气氛一般为干燥氧、水蒸汽等。
热处理时间,只要可获得所需的氧化膜厚,则并无特别限定。
根据本发明,可得到缺陷数显著减少的热氧化异种复合基板,对于复合基板的缺陷数的定量,能够应用HF浸渍试验。其为通过将SOQ或SOS浸渍于HF溶液,通过缺陷将内部的埋入氧化膜(BOX层:Box=Buried oxide)侵蚀而将尺寸扩大,使得即使用光学显微镜等也能简单地发现的试验。对于该试验,如果BOX氧化膜的厚度为25~500nm,可容易地进行检查。如果过薄,HF没有浸透,如果过厚,HF的浸透过快,有可能在检查上产生不利。
实施例
以下示出实施例,对本发明具体地说明,但本发明并不受下述的实施例限制。
[实施例1]
准备多张以直径150mm、厚600μm的蓝宝石晶片(R面)作为支持基板的SOS晶片。硅的厚度为200nm,BOX层的厚度为200nm。对该晶片施加600℃、650℃、700℃、800℃、850℃、900℃的中间热处理。气氛为氩气,使保持时间为1小时。追加没有实施中间热处理的参比的晶片1张,对这些晶片,在1000℃下通过湿式氧化,形成了200nm的氧化膜。氧化后,将这些晶片浸渍于10%HF溶液中30分钟,计数缺陷的数目,结果得到了图1的结果。通过施加650℃~850℃的中间热处理,缺陷数减少了。通过施加600℃的中间热处理,缺陷没有那么减少的原因,认为是600℃是不足以使效果显现的温度。此外,在900℃进行中间处理,认为在中间处理的时刻已发现了缺陷。最佳的温度认为是650℃~850℃左右。
[实施例2]
准备多张以直径150mm、厚625μm的石英晶片作为支持基板的SOQ晶片。硅的厚度为200nm,BOX层的厚度为200nm。对该晶片施加了600℃、650℃、700℃、800℃、850℃、900℃的中间热处理。气氛为氩气,使保持时间为1小时。追加没有实施中间热处理的参比的晶片1张,对这些晶片,在950℃下通过湿式氧化,形成了200nm的氧化膜。氧化后,将这些晶片浸渍于10%HF溶液中30分钟,计数缺陷的数目,结果得到了图2的结果。通过施加650℃~850℃的中间热处理,缺陷数减少了。在施加600℃的中间热处理的情况下,缺陷没有那么减少的原因,认为是600℃是不足以使效果显现的温度。此外,在900℃进行中间处理的情况下,认为在中间处理的时刻已发现了缺陷。最佳的温度认为是650℃~850℃左右。
[实施例3]
准备多张以直径150mm、厚600μm的蓝宝石晶片作为支持基板的SOS晶片。此时的蓝宝石的方位为C面(热膨胀系数CTE=7.0ppm)、R面(热膨胀系数CTE=7.4ppm)、A面(热膨胀系数CTE=7.7ppm)。硅的厚度为200nm,BOX层的厚度为200nm。对这些晶片施加了800℃的中间热处理。气氛为氩气,使保持时间为1小时。在这些晶片,在1000℃下通过湿式氧化,形成了200nm的氧化膜。氧化后,将这些晶片浸渍于10%HF溶液中30分钟,计数缺陷的数目,结果得到了图3的结果。可知C面、R面与A面相比,缺陷的数目有效地减少。
本方法记载了限定为石英和蓝宝石的实施例,但在以取石英和蓝宝石的中间的热膨胀系数(0.54~7.4ppm)的材料作为处理基板时也同样地有效。

Claims (12)

1.热氧化异种复合基板,是在处理基板上具有单晶硅膜的异种复合基板,通过在实施超过850℃的热氧化处理前施加650℃~850℃的中间热处理,然后在超过850℃的温度下实施热氧化处理而得到。
2.权利要求1所述的热氧化异种复合基板,其特征在于,处理基板为玻璃、石英、蓝宝石的任一种。
3.权利要求1或2所述的热氧化异种复合基板,其特征在于,在处理基板与单晶硅膜之间存在埋入氧化膜。
4.权利要求1~3的任一项所述的热氧化异种复合基板,其特征在于,中间热处理的气氛为氩、氮、氧、氢、氦、或将非活性气体与氧混合而成的气氛。
5.权利要求1~4的任一项所述的热氧化异种复合基板,其特征在于,处理基板的热膨胀系数在400℃以下为0.54ppm以上7.4ppm以下。
6.权利要求5所述的热氧化异种复合基板,其特征在于,处理基板为蓝宝石,蓝宝石晶片的膨胀系数在室温~400℃下为7.4ppm以下。
7.热氧化异种复合基板的制造方法,其特征在于,对于在处理基板上具有单晶硅膜的异种复合基板施加650~850℃的中间热处理后,在超过850℃的温度下实施热氧化处理。
8.权利要求7所述的热氧化异种复合基板的制造方法,其特征在于,处理基板为玻璃、石英、蓝宝石的任一种。
9.权利要求7或8所述的热氧化异种复合基板的制造方法,其特征在于,异种复合基板在处理基板与单晶硅膜之间存在埋入氧化膜。
10.权利要求7~9的任一项所述的热氧化异种复合基板的制造方法,其特征在于,中间热处理的气氛为氩、氮、氧、氢、氦、或将非活性气体与氧混合而成的气氛。
11.权利要求7~10的任一项所述的热氧化异种复合基板的制造方法,其特征在于,处理基板的热膨胀系数在400℃以下为0.54ppm以上7.4ppm以下。
12.权利要求11所述的热氧化异种复合基板的制造方法,其特征在于,处理基板为蓝宝石,蓝宝石晶片的膨胀系数在室温~400℃下为7.4ppm以下。
CN201380005209.0A 2012-01-12 2013-01-11 热氧化异种复合基板及其制造方法 Active CN104040686B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2012-003856 2012-01-12
JP2012003856 2012-01-12
PCT/JP2013/050387 WO2013105634A1 (ja) 2012-01-12 2013-01-11 熱酸化異種複合基板及びその製造方法

Publications (2)

Publication Number Publication Date
CN104040686A true CN104040686A (zh) 2014-09-10
CN104040686B CN104040686B (zh) 2017-05-24

Family

ID=48781576

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201380005209.0A Active CN104040686B (zh) 2012-01-12 2013-01-11 热氧化异种复合基板及其制造方法

Country Status (8)

Country Link
US (1) US10103021B2 (zh)
EP (1) EP2804202B1 (zh)
JP (2) JPWO2013105634A1 (zh)
KR (1) KR102055933B1 (zh)
CN (1) CN104040686B (zh)
SG (1) SG11201404039UA (zh)
TW (1) TWI576474B (zh)
WO (1) WO2013105634A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2993686B1 (en) 2013-05-01 2021-05-26 Shin-Etsu Chemical Co., Ltd. Method for producing hybrid substrate
JP6121357B2 (ja) * 2014-03-31 2017-04-26 信越化学工業株式会社 酸化膜付き異種soi基板の欠陥検出方法
JP6121356B2 (ja) * 2014-03-31 2017-04-26 信越化学工業株式会社 酸化膜付き異種soi基板の製造方法
JP7262421B2 (ja) * 2020-05-08 2023-04-21 信越化学工業株式会社 圧電体複合基板およびその製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040229444A1 (en) * 2003-02-18 2004-11-18 Couillard James G. Glass-based SOI structures
EP1981063A1 (en) * 2005-12-27 2008-10-15 Shin-Etsu Chemical Co., Ltd. Process for producing soi wafer and soi wafer
CN101383379A (zh) * 2007-09-05 2009-03-11 中国科学院微电子研究所 多介质复合隧穿层的纳米晶浮栅存储器及其制作方法
US20090203191A1 (en) * 2008-02-04 2009-08-13 Hideto Ohnuma Method for manufacturing soi substrate

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4178191A (en) * 1978-08-10 1979-12-11 Rca Corp. Process of making a planar MOS silicon-on-insulating substrate device
US4509990A (en) * 1982-11-15 1985-04-09 Hughes Aircraft Company Solid phase epitaxy and regrowth process with controlled defect density profiling for heteroepitaxial semiconductor on insulator composite substrates
JPS59159563A (ja) * 1983-03-02 1984-09-10 Toshiba Corp 半導体装置の製造方法
US5395788A (en) * 1991-03-15 1995-03-07 Shin Etsu Handotai Co., Ltd. Method of producing semiconductor substrate
US6312968B1 (en) * 1993-06-30 2001-11-06 The United States Of America As Represented By The Secretary Of The Navy Method for fabricating an electrically addressable silicon-on-sapphire light valve
JPH1140682A (ja) 1997-07-18 1999-02-12 Sony Corp 不揮発性半導体記憶装置及びその製造方法
JPH11145438A (ja) 1997-11-13 1999-05-28 Shin Etsu Handotai Co Ltd Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ
FR2777115B1 (fr) * 1998-04-07 2001-07-13 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
JPH11330438A (ja) 1998-05-08 1999-11-30 Shin Etsu Handotai Co Ltd Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ
US6417078B1 (en) 2000-05-03 2002-07-09 Ibis Technology Corporation Implantation process using sub-stoichiometric, oxygen doses at different energies
US6797604B2 (en) 2000-05-08 2004-09-28 International Business Machines Corporation Method for manufacturing device substrate with metal back-gate and structure formed thereby
JP4304879B2 (ja) 2001-04-06 2009-07-29 信越半導体株式会社 水素イオンまたは希ガスイオンの注入量の決定方法
US6649535B1 (en) 2002-02-12 2003-11-18 Taiwan Semiconductor Manufacturing Company Method for ultra-thin gate oxide growth
FR2855909B1 (fr) * 2003-06-06 2005-08-26 Soitec Silicon On Insulator Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat
KR100588647B1 (ko) 2003-12-30 2006-06-12 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
JP2005217288A (ja) * 2004-01-30 2005-08-11 Seiko Epson Corp 電気光学装置の製造方法
KR100898649B1 (ko) * 2004-05-28 2009-05-22 가부시키가이샤 섬코 Soi기판 및 그 제조방법
JP4407384B2 (ja) * 2004-05-28 2010-02-03 株式会社Sumco Soi基板の製造方法
JP2006032725A (ja) 2004-07-16 2006-02-02 Sumco Corp 半導体ウェーハの酸化膜形成方法
JP2006310661A (ja) 2005-04-28 2006-11-09 Toshiba Corp 半導体基板および製造方法
KR100638825B1 (ko) 2005-05-23 2006-10-27 삼성전기주식회사 수직구조 반도체 발광 소자 및 그 제조 방법
WO2008121262A2 (en) 2007-03-30 2008-10-09 Corning Incorporated Glass-ceramic-based semiconductor-on-insulator structures and method for making the same
JP2008263087A (ja) 2007-04-12 2008-10-30 Shin Etsu Chem Co Ltd Soi基板の製造方法
JP5289805B2 (ja) * 2007-05-10 2013-09-11 株式会社半導体エネルギー研究所 半導体装置製造用基板の作製方法
JP2009105315A (ja) * 2007-10-25 2009-05-14 Shin Etsu Chem Co Ltd 半導体基板の製造方法
SG183670A1 (en) * 2009-04-22 2012-09-27 Semiconductor Energy Lab Method of manufacturing soi substrate
JP2010278337A (ja) * 2009-05-29 2010-12-09 Shin-Etsu Chemical Co Ltd 表面欠陥密度が少ないsos基板
FR2954585B1 (fr) 2009-12-23 2012-03-02 Soitec Silicon Insulator Technologies Procede de realisation d'une heterostructure avec minimisation de contrainte
JP2011138818A (ja) 2009-12-25 2011-07-14 Panasonic Corp 半導体装置、高周波集積回路、高周波無線通信システムおよび半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040229444A1 (en) * 2003-02-18 2004-11-18 Couillard James G. Glass-based SOI structures
EP1981063A1 (en) * 2005-12-27 2008-10-15 Shin-Etsu Chemical Co., Ltd. Process for producing soi wafer and soi wafer
CN101383379A (zh) * 2007-09-05 2009-03-11 中国科学院微电子研究所 多介质复合隧穿层的纳米晶浮栅存储器及其制作方法
US20090203191A1 (en) * 2008-02-04 2009-08-13 Hideto Ohnuma Method for manufacturing soi substrate

Also Published As

Publication number Publication date
TW201341604A (zh) 2013-10-16
EP2804202A4 (en) 2015-09-16
WO2013105634A1 (ja) 2013-07-18
TWI576474B (zh) 2017-04-01
SG11201404039UA (en) 2014-10-30
US20140322546A1 (en) 2014-10-30
JP6288323B2 (ja) 2018-03-07
JP2017098577A (ja) 2017-06-01
CN104040686B (zh) 2017-05-24
JPWO2013105634A1 (ja) 2015-05-11
EP2804202A1 (en) 2014-11-19
US10103021B2 (en) 2018-10-16
KR102055933B1 (ko) 2019-12-13
KR20140112036A (ko) 2014-09-22
EP2804202B1 (en) 2021-02-24

Similar Documents

Publication Publication Date Title
JP6796162B2 (ja) 膜応力を制御可能なシリコン基板の上に電荷トラップ用多結晶シリコン膜を成長させる方法
CN101207009B (zh) Soi基板的制造方法
US20240022229A1 (en) Composite substrate
JP5064692B2 (ja) Soi基板の製造方法
KR102229397B1 (ko) 하이브리드 기판의 제조 방법 및 하이브리드 기판
US20060099773A1 (en) Fabrication of a low defect germanium film by direct wafer bonding
JP2010135764A (ja) シリコン薄膜転写絶縁性ウェーハの製造方法
JP2010538459A (ja) 熱処理を用いる剥離プロセスにおける半導体ウエハの再使用
JP6288323B2 (ja) 熱酸化異種複合基板の製造方法
US7605055B2 (en) Wafer with diamond layer
CN101188190B (zh) Soq基板以及soq基板的制造方法
US8367519B2 (en) Method for the preparation of a multi-layered crystalline structure
US10910258B2 (en) Engineered substrate structure and method of manufacture
KR20140104477A (ko) 산화물층을 포함하는 구조 내에 위치한 결합 인터페이스의 안정화 방법 및 획득된 구조
JP2018085536A (ja) 多層半導体デバイス作製時の低温層転写方法
US11393772B2 (en) Bonding method for semiconductor substrate, and bonded semiconductor substrate
JP2021518324A (ja) AlN材料の単結晶膜を生成するための方法、及びAlN材料の単結晶膜をエピタキシャル成長させるための基板
JP5424445B2 (ja) 半導体基板の製造方法および半導体基板
US10957539B2 (en) Method for bonding by direct adhesion
JP6121357B2 (ja) 酸化膜付き異種soi基板の欠陥検出方法
JPH029148A (ja) 集積回路用基板の製造方法
JP2011134852A (ja) GeOI基板の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant