TWI576474B - Composite substrate containing no thermal decomposition of SOI and its manufacturing method - Google Patents
Composite substrate containing no thermal decomposition of SOI and its manufacturing method Download PDFInfo
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- TWI576474B TWI576474B TW102101103A TW102101103A TWI576474B TW I576474 B TWI576474 B TW I576474B TW 102101103 A TW102101103 A TW 102101103A TW 102101103 A TW102101103 A TW 102101103A TW I576474 B TWI576474 B TW I576474B
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- 239000000758 substrate Substances 0.000 title claims description 83
- 239000002131 composite material Substances 0.000 title claims description 45
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 238000005979 thermal decomposition reaction Methods 0.000 title 1
- 239000000463 material Substances 0.000 claims description 45
- 238000010438 heat treatment Methods 0.000 claims description 38
- 229910052594 sapphire Inorganic materials 0.000 claims description 27
- 239000010980 sapphire Substances 0.000 claims description 27
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 18
- 230000003647 oxidation Effects 0.000 claims description 18
- 238000007254 oxidation reaction Methods 0.000 claims description 18
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 15
- 239000013078 crystal Substances 0.000 claims description 15
- 229910052707 ruthenium Inorganic materials 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 14
- 239000010453 quartz Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 229910052786 argon Inorganic materials 0.000 claims description 9
- 239000011521 glass Substances 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 239000001307 helium Substances 0.000 claims description 5
- 229910052734 helium Inorganic materials 0.000 claims description 5
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 5
- 239000011261 inert gas Substances 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 34
- 230000001590 oxidative effect Effects 0.000 description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 5
- 229910052732 germanium Inorganic materials 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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- Ceramic Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Thin Film Transistor (AREA)
Description
本發明為熱氧化異種材料複合基板及其製造方法相關內容,其經將玻璃、石英、藍寶石等操作基板上形成之單晶矽膜異種材料複合基板熱氧化處理而取得者。
為減少寄生容量,測量裝置高速化,Silicon on insulator(SOI)晶圓廣為運用。SOI晶圓中,尤以Silicon on Quartz(SOQ),Silicon on Sapphire(SOS)這類的操作晶圓因其結構為絕緣透明晶圓而備受矚目。SOQ由於能活用石英高透明性之光電特性亦或可活用其低誘點損失特性,在高周波裝置應用方面被深寄厚望。SOS由於其操作晶圓結構來自藍寶石,除高透明性外並有低誘電損失特性,其具有石英所無法取得之高熱傳導率,因此可期待其應用於發熱工程的高周波裝置領域。
將塊狀矽晶圓貼合,以轉寫法形成矽薄膜這樣的方式是將具高品質之單晶積層的理想方式。目前雖然可見於R面藍寶石上將矽層以異種基板未整合方式長晶,亦有於玻璃上讓非單晶矽成長後以雷射熱移轉結晶方格長
晶法等提高結晶度這樣的CG矽,但這些方法可說都不如貼合法。
然而在貼合異種材料過程(如SOQ、SOS、SOG等)中所導致的問題點堪憂。具體而言,一般裝置過程中為形成氧化膜閘門,其過程包含超過850℃的高溫處理。這些異種材料貼合基板(以下簡稱異種複合基板)由於受到高溫過程矽薄膜強烈壓縮及拉扯應力,有時會產生各種問題點(如微小裂縫等)。其原因為異種材料複合基板中,操作基板這樣的支撐基板及上層矽薄膜之間產生的膨脹係數差幅較大,而這也是異種材料複合基板其實質問題點。
本發明有鑑於上述緣由,以提供一種熱氧化異種材料複合基板及其製造方法為主要目的,此方法可減少形成氧化膜時以850℃以上高溫處理後造成的微小裂縫等問題點。
本發明相關人員為達成上述目的,在多次致力於相關研究後,得到的見解為:在將矽薄膜轉寫於絕緣透明晶圓時(石英、玻璃、藍寶石等)執行850℃以上高溫處理過程前,加上一道中間加熱處理,且此中間加熱處理的溫度以650℃以上850℃以下最為有效。
亦即此道中間加熱處理(650℃以上850℃以下)是為了減少850℃以上高溫處理造成的問題點。也可
說是一種讓局部應力可平均於施加整片晶圓的處理方式。產生局部應力的原因可推敲是來自於操作基板材料之扭曲或密度粗糙,造成貼合過程面無法均一。
另外,此中間加熱處理可讓貼合界面之貼合強度在進行高溫處理前就充分提高,如此矽薄膜受到強烈應力時也比較不會剝落或分岐。
透過該中間加熱處理後再進行氧化等高溫處理,則可能減少氧化後的問題點。
本發明提供下述熱氧化異種材料複合基板及其製造方法。
〔1〕一種操作基板上具有單晶矽膜的異種材料複合基板,在進行超過850℃以上熱氧化處理前先進行650℃-850℃間的中間加熱處理,之後再進行850℃以上的熱氧化處理所取得之熱氧化異種材料複合基板。
〔2〕如前項之熱氧化異種材料複合基板,其操作基板為玻璃、石英、藍寶石其中任一種材質。
〔3〕如上述〔1〕或〔2〕之熱氧化異種材料複合基板,操作基板及單晶矽膜之間有氧化膜為媒介。
〔4〕如上述〔1〕到〔3〕任一項之熱氧化異種材料複合基板,其中,中間加熱處理的環境為混合氬、氮、氧、氫、氦亦或非活性氣體與氧之環境。
〔5〕如上述〔1〕至〔4〕任一項之熱氧化異種材料
複合基板,其操作基板熱膨脹係數在400℃以下為0.54ppm以上,7.4ppm以下。
〔6〕如上述〔5〕所述之熱氧化異種材料複合基板,其操作基板為藍寶石,藍寶石晶圓膨脹係數為室溫至400℃,7.4ppm以下。
〔7〕一種熱氧化異種材料複合基板及其製造方法,其特徵為針對操作基板上具有單晶矽膜的異種材料複合基板在進行超過850℃以上熱氧化處理前先進行650℃-850℃間的中間加熱處理,之後再進行850℃以上的熱氧化處理。
〔8〕如第〔7〕項之熱氧化異種材料複合基板製造方法,其操作基板為玻璃、石英、藍寶石其中之一。
〔9〕如〔7〕或〔8〕之熱氧化異種材料複合基板製造方法,異種材料複合基板之操作基板與單晶矽膜間有氧化膜作為媒介。
〔10〕如〔7〕-〔9〕之熱氧化異種材料複合基板製造方法,其中間加熱處理的環境為混合氬、氮、氧、氫、氦或非活性氣體與氧之環境。
〔11〕如〔7〕-〔10〕任一項之熱氧化種材料複合基板製造方法,其操作基板熱膨脹係數在400℃以下為0.54ppm以上,7.4ppm以下。
〔12〕如第〔11〕項之熱氧化異種材料複合基板製造方法,其操作基板為藍寶石,藍寶石晶圓膨脹係數為室溫到400℃,7.4ppm以下。
經由本發明可取得熱氧化程序後缺陷問題點較少之熱氧化異種材料複合基板。
本發明所指之熱氧化異種材料複合基板為將操作基板上具單晶矽膜之異種材料複合基板以650-850℃中間加熱處理後再以超過850℃溫度進行熱氧化處理所取得之複合基板。
此狀況下,也可讓操作基板及單晶矽膜之間有氧化膜為媒介(BOX層:Box=Buried oxide)
本發明對象之複合基板操作材料主要以玻璃、石英、藍寶石為主。這些材料與矽有較大差膨脹係數差幅,其膨脹係數如下表1所示。
矽與石英貼合形成的SOQ其膨脹係數差幅有2.04ppm,SOS的情況則最小為4.4ppm,最大為5.1ppm。藍寶石則隨其方位不同膨脹係數也不同,因此為減少膨脹係數差幅,選擇使用膨脹係數較小之藍寶石基板,以期提高本發明效果。具體程序為,避免使用膨脹係數較大的A面晶圓,以使用C面(7.0ppm)或R面(7.4ppm左右)之效果較佳。
操作基板膨脹係數在400℃以下,0.54-7.4ppm為佳,藍寶石晶圓則以膨脹係數在室溫至400℃,7.4ppm以下為佳。
此外,上述操作基板之厚度以500-800μm,尤以600-725μm為佳,單晶矽膜厚度以50-500nm,尤以100-350nm為佳。若要充填媒介的氧化膜(BOX氧化膜),其厚度則以25-150nm為佳。此外BOX氧化膜相關內容於專利2002-305292號公報已針對SOI晶圓充填氧化膜成膜方法公開,可參考其內容成形氧化膜。
將上述異種材料複合基板熱氧化處理時,首先以650-850℃,尤以700-850℃為佳,進行中間加熱處理。
此中間加熱處理的環境氣氛,若為方便處理的環境則不受限制。代表性環境如氬、氮、氧、氫、氦等。或者是氬及氮等非活性氣體與氧化氣體之混合環境也可接受。
中間加熱處理的時間以0.5-6小時,尤以1-3小時為佳。若加熱時間太短則有可能無法完全達到本發明之目的,加熱時間太長則可能會導致成本提升問題。
進行上述中間加熱處理後再進行熱氧化處理。此熱氧化處理可採用目前眾所皆知的條件,但加熱處理溫度最好超過850℃,以超過900℃-1000℃,特別是950-1000℃為佳。但只要是能取得所需氧化膜厚度範圍,則沒有特殊限制。此外,若熱氧化處理溫度超過900℃,則其中間加熱處理以650-900℃,尤以700-900℃為佳。加熱處理的周邊環境以乾氧及水蒸氣等為一般條件。加熱處理所需時間則視所需氧化膜厚度調整,並無特殊限制。
本發明可取得問題點明顯減少之熱氧化異種材料複合基板,複合基板問題點之確認可以HF浸泡測試來計算。這是指將SOQ或SOS以HF溶液浸泡,若有問題點則會侵蝕內部充填的氧化膜(BOX層:BOX=Buried oxide),其增大的範圍可以光學顯微鏡等輕易發現的測試法。若BOX氧化膜厚度在25-500nm,則本測試可輕易檢查出問題點。若厚度太薄,則HF無法滲透,厚度太厚則HF浸泡速度可能會過快造成檢查不利條件。
〔圖1〕顯示於各種溫度進行中間加熱處理時,熱氧化SOS晶圓基板之HF問題點圖表。
〔圖2〕顯示於各種溫度進行中間加熱處理時,熱氧化SOQ晶圓基板之HF缺陷問題點圖表。
〔圖3〕顯示於各種藍寶石方位中,採用具有單晶矽膜之SOS晶圓進行中間加熱處理,其熱氧化SOS晶圓基板之HF問題點圖表。
以下針對實施方式具體詳述,但本發明不限於以下實施方式。
準備幾片直徑150mm,厚度600μm,以藍寶石晶圓(R面)作為支撐基板的SOS晶圓。矽厚度為200nm,BOX層厚度為200nm。將此晶圓以600℃,650℃,700℃,800℃,850℃,900℃溫度進行中間加熱處理。周邊氣氛以氬氣為主,維持1小時。並追加一片不進行中間加熱處理的參考晶圓,將這些晶圓以1000℃濕氧化形成200nm氧化膜。氧化後將這些晶圓以10%HF溶液浸泡30分,計算問題點,則可取得如圖1之結果。650℃至850℃間的中間加熱處理其問題點有減少現象。以600℃溫度進行中間加熱處理,其問題點減少狀況不彰的原因是由於600℃這樣的溫度不足以發現問題點。另外以900℃進行中間加熱處理的晶圓,在中間加熱處理時就已經發現問題點。因此判斷最適當溫度為650℃至850℃。
準備幾片直徑150mm,厚度625μm,以石英晶圓作為支撐基板的SOQ晶圓。矽厚度為200nm,BOX層厚度為200nm。將此晶圓以600℃,650℃,700℃,800℃,850℃,900℃溫度進行中間加熱處理。周邊氣氛以氬氣為主,維持1小時。並追加一片不進行中間加熱處理的參考
晶圓,將這些晶圓以950℃濕氧化形成200nm氧化膜。氧化後將這些晶圓以10%HF溶液浸泡30分,計算問題點,則可取得如圖2之結果。650℃至850℃間的中間加熱處理其問題點有減少現象。以600℃溫度進行中間加熱處理,其問題點減少狀況不彰的原因是由於600℃這樣的溫度不足以發現問題點。另外以900℃進行中間加熱處理的晶圓,在中間加熱處理時就已經發現問題點,因此判斷最適當溫度為650℃至850℃。
準備幾片直徑150mm,厚度600μm,以藍寶石晶圓為支撐基板之SOS晶圓。此時藍寶石方位為C面(熱膨脹係數CTE=7.0ppm),R面(熱膨脹係數CTE=7.4ppm),A面(熱膨脹係數CTE=7.7ppm)。矽厚為200nm,BOX層厚度為200nm,將這些晶圓以800℃溫度中間加熱處理。周邊氣氛已氬氣為主,維持1小時。將這些晶圓以1000℃濕氧化形成200nm氧化膜。氧化後將這些晶圓以10%HF溶液浸泡30分,計算其問題點,則可取得如圖3之結果。結果發現C面,R面比A面更有效減少問題點。
本方法主要針對石英及藍寶石描述實施例,但若採用與石英及藍寶石一樣的中間熱膨脹係數(0.54-7.4ppm)材料為操作基板,也可得到同樣效果。
Claims (12)
- 一種不含SOI之熱氧化異種材料複合基板,其係於貼合矽與矽而製成的操作基板上(handle substrate)具有單晶矽膜,其特徵為在實施超過850℃之熱氧化處理前,增加1~6小時、650℃至850℃的中間加熱處理,爾後以超過850℃溫度執行熱氧化處理所取得。
- 如申請專利範圍第1項之不含SOI之熱氧化異種材料複合基板,其中,操作基板為玻璃、石英、藍寶石等任何一種材料。
- 如申請專利範圍第1或2項之不含SOI之熱氧化異種材料複合基板,其中,於操作基板及單晶矽膜間充填氧化膜作為媒介。
- 如申請專利範圍第1或2項之不含SOI之熱氧化異種材料複合基板,其中,中間熱處理的環境為混合氬、氮、氧、氫、氦、或非活性氣體與氧的環境。
- 如申請專利範圍第1或2之不含SOI之熱氧化異種材料複合基板,其中,操作基板之膨脹係數在400℃以下,為0.54ppm以上,7.4ppm以下。
- 如申請專利範圍第5項之不含SOI之熱氧化異種材料複合基板,其中,操作基板為藍寶石,且藍寶石晶圓膨脹係數在室溫~400℃,為7.4ppm以下。
- 一種不含SOI之熱氧化異種材料複合基板之製造方法,其特徵為對操作基板上具有單晶矽膜的異種材料複合基板施加以650℃至850℃之中間熱處理後,以超過 850℃溫度進行熱氧化處理。
- 如申請專利範圍第7項之不含SOI之熱氧化異種材料複合基板之製造方法,其中,操作基板為玻璃、石英、藍寶石之任一。
- 如申請專利範圍第7或8項之不含SOI之熱氧化異種材料複合基板之製造方法,其中,異種複合材料基板即操作基板與單晶矽膜之間填入氧化膜為媒介的基板。
- 如上述申請專利範圍第7或8項之不含SOI之熱氧化異種材料複合基板之製造方法,其中,中間熱處理的環境為混合氬、氮、氧、氫、氦或非活性氣體與氧的環境。
- 如申請專利範圍第7或8項之不含SOI之熱氧化異種材料複合基板之製造方法,其中,操作基板之熱膨脹係數在400℃以下,為0.54ppm以上,7.4ppm以下。
- 如專利申請範圍第11項之不含SOI之熱氧化異種材料複合基板之製造方法,其中,操作基板為藍寶石,且藍寶石晶圓膨脹係數在室溫~400℃,為7.4ppm以下。
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