WO2014086250A1 - 一种用于 led 外延晶圆制程的石墨承载盘 - Google Patents

一种用于 led 外延晶圆制程的石墨承载盘 Download PDF

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WO2014086250A1
WO2014086250A1 PCT/CN2013/088264 CN2013088264W WO2014086250A1 WO 2014086250 A1 WO2014086250 A1 WO 2014086250A1 CN 2013088264 W CN2013088264 W CN 2013088264W WO 2014086250 A1 WO2014086250 A1 WO 2014086250A1
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wafer
led
groove
carrier disk
graphite
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PCT/CN2013/088264
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English (en)
French (fr)
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谢祥彬
南琦
潘磊
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厦门市三安光电科技有限公司
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Publication of WO2014086250A1 publication Critical patent/WO2014086250A1/zh
Priority to US14/588,384 priority Critical patent/US9725824B2/en

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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/12—Substrate holders or susceptors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B25—HAND TOOLS; PORTABLE POWER-DRIVEN TOOLS; MANIPULATORS
    • B25J—MANIPULATORS; CHAMBERS PROVIDED WITH MANIPULATION DEVICES
    • B25J11/00—Manipulators not otherwise provided for
    • B25J11/0095—Manipulators transporting wafers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
    • C23C16/4582—Rigid and flat substrates, e.g. plates or discs
    • C23C16/4583—Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68735—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge profile or support profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/6875—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a plurality of individual support members, e.g. support posts or protrusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68771—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by supporting more than one semiconductor substrate

Definitions

  • the invention relates to a graphite carrier disk used in an LED light emitting diode epitaxial (Epitax) wafer process ( Wafer carrier ).
  • Light Emitting Diode (English Light Emitting Diode, referred to as LED It is a solid-state semiconductor diode light-emitting device widely used in lighting fields such as indicator lights and display screens.
  • LED epitaxial wafers are chemically vapor deposited by metal organic compounds (English for Metal-organic).
  • Chemical Vapor Deposition is obtained as follows. The process is briefly described as follows: an epitaxial wafer substrate (such as a sapphire substrate) is placed in a graphite carrier (Wafer) The groove of the carrier is introduced into the MOCVD reaction chamber along with the graphite carrier, and the substrate is heated together with the graphite carrier to a high temperature of 1000. Around °C, the organometallic compound and the Group V gas are introduced into the reaction chamber, and after high temperature cracking, the LED epitaxial layer is re-polymerized on the wafer substrate.
  • MOCVD Chemical Vapor Deposition
  • the wafer substrate is directly supported on the graphite carrier. Therefore, the structure of the graphite carrier disk plays an important role in the epitaxial yield, which has become the focus of research in the industry.
  • the present invention aims to provide a graphite carrier disk for LED epitaxial wafer process, which is used for growing LED
  • the epitaxial wafer has a high overall yield and good wavelength uniformity.
  • the technical solution of the present invention is for an LED
  • the epitaxial wafer process graphite carrier disk comprises a plurality of wafer recesses disposed above the carrier disk for placing an epitaxial wafer substrate, wherein the inner edge of the wafer groove is a concave step and has a plurality of An inwardly extending support portion; further comprising an edge of the graphite carrier disk and a shaft hole disposed in the center of the graphite carrier disk.
  • Different numbers and sizes of grooves can be set according to the needs of different process parameters.
  • the inner edge structure of the wafer recess can reduce airflow interference and improve edge yield of the wafer during epitaxial growth.
  • the relationship between the diameter D1 of the wafer substrate and the step inner diameter D2 is: 0 ⁇ D1-D2 ⁇ 0.06mm.
  • the step width of the inner edge of the groove of the wafer is 0.2 mm to 1.5 mm, and the height is 0.03mm to 0.5mm.
  • the step width of the inner edge of the groove of the wafer is 0.2 mm to 0.5 mm, and the height is 0.03mm to 0.5mm.
  • the support portion of the inner edge of the wafer groove is a periodically distributed protrusion.
  • the protrusion has a width of 0.2 mm to 0.5 mm and a height of 0.03 mm. 0.5mm.
  • the step height of the edge of the wafer groove coincides with the height of the protrusion.
  • the bottom of the groove of the wafer is a flat surface, a convex surface or a concave surface.
  • the graphite carrier disk disclosed in the invention has a wafer groove with a stepped and inwardly extending edge of the support portion, and the epitaxial wafer substrate can be directly lifted, so that the epitaxial wafer substrate and the graphite carrier disk are directly contacted.
  • the epitaxial film is heated from the original contact type heating to the heat radiation type heating, effectively reducing the unevenness of the epitaxial wafer due to factors such as the quality and surface condition of the graphite carrier disk, wavelength uniformity and overall The condition of poor yield occurs; at the same time, it also effectively avoids the unfavorable factors caused by the hollowness of the bottom of the wafer being lifted, the airflow in the reaction chamber may be poured into the bottom of the wafer substrate, and the turbulence of the epitaxial wafer substrate becomes large. happened.
  • a graphite carrier for use in LED epitaxial wafer processes for MOCVD methods for LED epitaxial processes is provided.
  • Figure 1 is a cross-sectional view of a typical graphite carrier disk for LED epitaxy.
  • Figure 2 is a cross-sectional view of the wafer groove of the graphite carrier disk flat disk.
  • Figure 3 is a cross-sectional view of the wafer recess of the graphite carrier disk flat disk.
  • FIG. 4 is a cross-sectional view of a wafer groove of a stepped edge disk of a graphite carrier.
  • Figure 5 is a cross-sectional view of a wafer groove of a stepped edge disk of a graphite carrier.
  • Figure 6 is a cross-sectional view of the wafer recess of the graphite carrier disk projecting edge disk.
  • Figure 7 is a cross-sectional view of a wafer recess of a graphite carrier disk projecting edge disk.
  • Figure 8 is a cross-sectional view showing a groove of a wafer having a ring-shaped stepped edge graphite disk carrier disk according to Embodiment 1 of the present invention.
  • Figure 9 is a perspective view of a wafer groove having a ring-shaped stepped edge graphite disk carrier disk according to an embodiment of the present invention.
  • Figure 10 is a cross-sectional view showing a groove of a wafer having a ring-shaped stepped edge graphite disk carrier disk according to an embodiment of the present invention.
  • Figure 11 is a cross-sectional view showing a groove of a wafer having a ring-shaped stepped edge graphite disk carrier disk according to Embodiment 2 of the present invention.
  • Figure 12 is a cross-sectional view showing a groove of a wafer having a ring-shaped stepped edge graphite disk carrier disk according to Embodiment 3 of the present invention.
  • Figure 1 shows a typical cross section of a graphite carrier disk for LED epitaxy, which is distributed over a number of wafer recesses placed above the carrier disk 1 (English can be called Pocket Profile) for placing epitaxial wafer substrates.
  • the wafer groove 1 of the LED graphite disk flat plate ( Flat Disc), stepped edge disc (Rim disc) and raised edge disc (tab).
  • the flat groove has a flat and smooth cylindrical surface.
  • the substrate is in direct contact with the bottom of the graphite carrier, when heated in the reaction chamber,
  • the way in which thermal energy is conducted from the graphite carrier to the substrate is contact, and the characteristics of the contact surface of the graphite carrier and the substrate directly determine whether the substrate is heated uniformly.
  • Due to the single-wafer groove design of the flat disk, the epitaxial wafer substrate and the graphite carrier disk are directly in contact, and the heating method is contact heat transfer, and the uniformity of the epitaxial wafer substrate and the epitaxial yield are largely controlled.
  • the edge of the wafer groove of the stepped edge disk is designed with a step for directly lifting the wafer substrate, thereby avoiding direct contact between the wafer substrate and the bottom of the groove of the graphite carrier wafer, so that the wafer substrate is
  • the heating method becomes contact heat transfer, which effectively improves the uniformity of heating of the wafer substrate, but due to the influence of the step in the stepped edge disk, the portion of the substrate that is in contact with the step may be overheated due to direct contact with the graphite disk. Scrap will sacrifice a considerable portion of the core particles, which in turn affects the core yield.
  • the following embodiments propose a LED with a stepped and raised groove edge design.
  • Epitaxial wafer process graphite carrier disk, LED grown by the graphite carrier disk The overall yield of the epitaxial wafer is high, and the wavelength uniformity is good, which overcomes the disadvantage that the overall epitaxial wafer yield of the conventional graphite carrier is not high and the uneven distribution of the wavelength of the epitaxial wafer is unstable due to uneven heating.
  • the following embodiments disclose a graphite carrier disk comprising a plurality of wafer recesses disposed above the carrier disk for placing an epitaxial wafer substrate, the inner edge of the wafer groove being a concave step, and having A plurality of support portions extending inwardly.
  • the graphite carrier tray also includes an edge of the graphite carrier disk and a shaft hole disposed in the center of the graphite carrier disk. Different numbers and sizes of grooves can be set according to the needs of different process parameters.
  • an LED epitaxial wafer process graphite carrier disk includes: 12 wafer grooves 1.
  • Inner edge of wafer groove 1 12 has a step 13 and a protrusion 14 , and the bottom 15 of the groove 1 of the wafer is concave, and the depth H2 of the recess is 5 ⁇ m to 30 ⁇ m, and the protrusion 14 It is distributed periodically.
  • the wafer groove has a step width W of 0.2 mm and a height H1 of 0.03 mm.
  • the groove width of the wafer groove is 0.2mm and the height H1 is 0.03mm. .
  • the diameter D1 of the wafer substrate is the same as the step inner diameter D2 such that the wafer substrate 16 is placed just above the raised edge, i.e., by 12 periodically distributed inwardly extending supports 14
  • the support not only avoids the peripheral portion of the wafer substrate contacting the step, but also causes the temperature to be too high due to direct contact with the graphite carrier disk, and also prevents the airflow from flowing into the gap between the substrate and the groove of the graphite disk wafer, resulting in the wafer.
  • a severe turbulence is formed at the bottom of the substrate, causing the epitaxial wafer to warp severely.
  • the bottom portion 19 of the wafer groove of this embodiment is a flat type.
  • the step of the wafer groove 13 The width W is 1.0mm and the height H1 is 0.15mm.
  • the protrusion 14 of the wafer groove has a width W of 0.4 mm and a height H1 of 0.15 mm.
  • Wafer substrate diameter D1 is 0.04mm larger than the step inner diameter D2, and the number of periodic projections is 6
  • the wafer substrate is mostly placed over the raised edge, and a small portion of the periphery of the wafer substrate is placed over the stepped edge.
  • the bottom portion 20 of the wafer groove of the present embodiment is a convex type, and the convex height H3 is 5 ⁇ m ⁇ 30 ⁇ m.
  • the step 13 of the wafer groove has a width W of 1.5 mm and a height H1 of 0.5 mm.
  • the width of the protrusion 14 of the wafer groove is W 0.5mm, height H1 is 0.5mm.
  • the diameter D1 of the wafer substrate is 0.05 mm larger than the step inner diameter D2, and the number of periodically distributed protrusions is four.
  • the wafer substrate holder has a slightly larger portion on the concave step on the inner edge of the wafer groove, the number of protrusions can be further reduced, that is, reduced to four.
  • the periodic distribution can also achieve not only the reduction of the peripheral portion of the wafer substrate and the step contact, but also the overheating of the graphite due to the direct contact with the graphite carrier, and the flow of gas into the substrate and the graphite wafer groove can be avoided.
  • the gap between them causes severe turbulence at the bottom of the wafer substrate, causing the epitaxial wafer to warp severely.
  • the edge of the epitaxial wafer substrate can be directly lifted to expose the epitaxial wafer substrate except for the bumps of the wafer.
  • Most of the contacts (partial embodiments also include a small portion of the periphery of the wafer substrate), and the rest are suspended on the graphite carrier disk recess.
  • the epitaxial wafer substrate is heated by the original heat conduction method.
  • the heat radiation type heats up, greatly improves the uniformity of the heat transfer efficiency per unit area of the epitaxial wafer substrate when it is heated at a high temperature, thereby greatly improving the wavelength uniformity and the wavelength yield of the epitaxial wafer; on the other hand, the step of the wafer groove 13
  • the edge of the epitaxial wafer substrate can effectively prevent the flow of the reaction chamber into the gap 18 between the wafer substrate and the groove of the wafer, thereby effectively improving the epitaxial wavelength uniformity and the wavelength yield.
  • the graphite carrier disk proposed in the above embodiments is suitable for MOCVD of LED epitaxial process Method. It has been determined that, by the graphite carrier disk of the present invention, the inner edge structure of the wafer groove can reduce airflow interference and improve the edge yield of the wafer during epitaxial growth. Specifically, the epitaxial wavelength uniformity and the wavelength yield are improved compared to the growth of the conventional graphite carrier disk, and the average wavelength and the wavelength yield can be improved. More than 10%, greatly improving the yield of epitaxial products, and has significant effects on reducing the output cost of LED monoliths and improving the uniformity of epitaxial quality.

Abstract

提供一种用于LED外延晶圆制程的石墨承载盘，该石墨承载盘包括若干个设置在承载盘上方的晶圆凹槽（1），用于置放外延晶圆衬底（16），所述晶圆凹槽（1）的内边缘为下凹台阶（13），且具有复数个向内延伸的支撑部（14）；还包括石墨承载盘的边缘（2）以及设置在石墨承载盘中心的轴孔（3）。根据不同工艺参数的需要，可设置不同数量及不同尺寸的凹槽。所述结构能够降低反应室气流干扰、提高晶圆的边缘良率。

Description

一种用于 LED 外延晶圆制程的石墨承载盘
本申请主张如下优先权：中国发明专利申请号 201210506371.8，题为 ' 一种用于 LED 外延晶圆制程的石墨承载盘 ' ，于 2012 年 12 月 3 日提交。上述申请的全部内容通过引用结合在本申请中。
技术领域
本发明涉及一种 LED 发光二极管外延（ Epitaxy ）晶圆制程中使用的石墨承载盘（ Wafer carrier ）。
背景技术
发光二极管（英文为 Light Emitting Diode ，简称 LED ）是一种固态半导体二极管发光器件，被广泛用于指示灯、显示屏等照明领域。
目前， LED 外延晶圆很多通过金属有机化合物化学气相沉淀（英文为 Metal-organic Chemical Vapor Deposition ，简称 MOCVD ）获取，其制程简述如下：将外延晶圆衬底（如蓝宝石衬底）放入石墨承载盘（ Wafer carrier ）的凹槽上，连同石墨承载盘一起被传入 MOCVD 反应室内，衬底连同石墨承载盘被一起加热到高温 1000 ℃左右，反应室内通入有机金属化合物和五族气体，高温裂解后在晶圆衬底上重新聚合形成 LED 外延层。
LED 发光二极管外延（ Epitaxy ）晶圆制程中，晶圆衬底直接承载在石墨承载盘上，因此石墨承载盘的结构对外延的良率起到重要的影响，其成为业界研究的重点。
发明内容
本发明旨在提供一种用于 LED 外延晶圆制程的石墨承载盘，其用于生长的 LED 外延片整体良率高，波长均匀性好。
本发明的技术方案为一种用于 LED 外延晶圆制程的石墨承载盘，包括若干个设置在承载盘上方的晶圆凹槽，用于置放外延晶圆衬底，所述晶圆凹槽的内边缘为下凹台阶，且具有复数个向内延伸的支撑部；还包括石墨承载盘的边缘以及设置在石墨承载盘中心的轴孔。根据不同工艺参数的需要，可设置不同数量及不同尺寸的凹槽。
进一步地，根据本发明，在外延生长过程中，所述晶圆凹槽的内边缘结构能够降低气流干扰、提高晶圆的边缘良率。
进一步地，根据本发明，优选的是：所述晶圆衬底的直径 D1 与台阶内径 D2 的关系为： 0 ≤ D1-D2 ＜ 0.06mm 。
进一步地，根据本发明，优选的是：所述晶圆凹槽内边缘的台阶宽度为 0.2mm ～ 1.5mm ，高度为 0.03mm ～ 0.5mm 。
进一步地，根据本发明，优选的是：所述晶圆凹槽内边缘的台阶宽度为 0.2mm~0.5mm ，高度为 0.03mm ～ 0.5mm 。
进一步地，根据本发明，优选的是：所述晶圆凹槽内边缘的支撑部为周期性分布的突起。
进一步地，根据本发明，优选的是：所述突起宽度为 0.2mm ～ 0.5mm ，高度为 0.03mm ～ 0.5mm 。
进一步地，根据本发明，优选的是：所述晶圆凹槽边缘的台阶高度与突起高度一致。
进一步地，根据本发明，优选的是：所述晶圆凹槽底部为平面、凸面或者凹面。
本发明公开的石墨承载盘，具有台阶状和向内延伸的支撑部的边缘的晶圆凹槽，可以将外延晶圆衬底直接托起，使外延晶圆衬底和石墨承载盘由直接接触变为非直接接触，故而外延片受热方式由原有的接触式受热变为热辐射式受热，有效减少因石墨承载盘本身质量及表面状况等因素造成外延片受热不均匀，波长均匀性及整体良率差的状况发生；同时还有效地避免因晶圆底部被托起后造成中空，反应室内气流可能灌入晶圆衬底底部造成扰流导致外延晶圆衬底翘曲变大等不利因素的发生。
用于 LED 外延晶圆制程中的石墨承载盘，适用于 LED 外延制程的 MOCVD 方法。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明实施例一起用于解释本发明，并不构成对本发明的限制。此外，附图数据是描述概要，不是按比例绘制。
图 1 是典型的 LED 外延用石墨承载盘截面图。
图 2 是石墨承载盘平盘的晶圆凹槽的截面图。
图 3 是石墨承载盘平盘的晶圆凹槽的剖面图。
图 4 是石墨承载盘台阶状边缘盘的晶圆凹槽的截面图。
图 5 是石墨承载盘台阶状边缘盘的晶圆凹槽的剖面图。
图 6 是石墨承载盘突起状边缘盘的晶圆凹槽的截面图。
图 7 是石墨承载盘突起状边缘盘的晶圆凹槽的剖面图。
图 8 是本发明实施例 1 具有齿圈状台阶式边缘石墨盘承载盘的晶圆凹槽的截面图。
图 9 是本发明实施例 1 具有齿圈状台阶式边缘石墨盘承载盘的晶圆凹槽的立体图。
图 10 是本发明实施例 1 具有齿圈状台阶式边缘石墨盘承载盘的晶圆凹槽的剖面图。
图 11 是本发明实施例 2 具有齿圈状台阶式边缘石墨盘承载盘的晶圆凹槽的剖面图。
图 12 是本发明实施例 3 具有齿圈状台阶式边缘石墨盘承载盘的晶圆凹槽的剖面图。
符号说明
1 ：石墨承载盘上的晶圆凹槽；
2 ：石墨承载盘的边缘；
3 ：石墨承载盘中心的轴孔；
4 ：平盘晶圆凹槽的内边缘；
5 ：平盘晶圆凹槽的底面；
6 ：台阶状边缘盘晶圆凹槽的内边缘；
7 ：台阶状边缘盘台阶状边缘；
8 ：台阶状边缘盘晶圆凹槽底部；
9 ：突起状边缘盘晶圆凹槽的内边缘；
10 ：突起状边缘盘突起状边缘；
11 ：突起状边缘盘晶圆凹槽底部；
12 ：具有台阶状和突起状边缘的晶圆凹槽的内边缘；
13 ：具有台阶状和突起状边缘的晶圆凹槽的台阶；
14 ：具有台阶状和突起状边缘的晶圆凹槽的突起；
15 ：具有台阶状和突起状边缘的晶圆凹槽的下凹型底部；
16 ：外延晶圆衬底；
17 ：反应室内流经晶圆衬底和晶圆凹槽上方的气流；
18 ：晶圆衬底与晶圆凹槽之间的空隙；
19 ：具有台阶状和突起状边缘的晶圆凹槽的平面型底部；
20 ：具有台阶状和突起状边缘的晶圆凹槽的上凸型底部。
具体实施方式
以下结合附图和具体实施例对本发明作进一步的详细描述 , 有关本发明的相关技术内容，特点与功效，将可清楚呈现。
图 1 展示了典型的 LED 外延用石墨承载盘截面图，其上分布为若干个设置在承载盘上方的晶圆凹槽 1 （英文可称之为 Pocket Profile ），用于置放外延晶圆衬底。目前 LED 石墨盘的晶圆凹槽 1 设计主要有三种：平盘（ Flat 盘），台阶状边缘盘（ Rim 盘）和突起状边缘盘（ Tab 盘）。
请参考图 2~3 ，平盘的晶圆凹槽边缘为平整光滑的圆筒形表面，当外延晶圆衬底承载于其上时，衬底与石墨承载盘底部为直接接触，当在反应室室中加热时，热能从石墨承载盘传导到衬底的方式为接触式，石墨承载盘与衬底的接触面的特性直接决定衬底受热是否均匀。由于平盘的单片晶圆凹槽设计使得外延晶圆衬底和石墨承载盘直接接触，受热方式为接触式传热，外延晶圆衬底的受热均匀程度以及外延良率很大程度上受制于石墨承载盘本身质量以及表面等状况的影响。
请参考图 4~5 ，台阶状边缘盘的晶圆凹槽边缘设计有一圈台阶用于将晶圆衬底直接托起，避免了晶圆衬底和石墨承载盘晶圆凹槽底部直接接触，使晶圆衬底的受热方式变为接触式传热，有效地改善晶圆衬底的受热均匀程度，但是由于受台阶状边缘盘中台阶的影响，衬底与台阶接触的部分会由于直接接触石墨盘导致温度过高报废，会牺牲掉相当部分的芯粒，进而影响了芯粒良率。
请参考图 6~7 ，突起状边缘盘的晶圆凹槽边缘用突起状边缘盘代替台阶状边缘盘，但由于衬底边缘大部分则被暴露于反应室的气流干扰之下，气流会流入衬底与石墨盘晶圆凹槽之间的空隙，导致在晶圆衬底底部形成严重的扰流，使外延片翘曲严重，导致整体外延波长良率偏低。
现有的三种类型的石墨承载盘，在量产中均未能很好解决 LED 外延片外延波长及标准差（ STD ）良率问题，因此如何提升外延良率及减小石墨承载盘对外延制程的影响成为人们研究的重点。
针对上述石墨承载盘的不足，下面各实施例提出一种兼具台阶状和突起状凹槽边缘设计的用于 LED 外延晶圆制程的石墨承载盘，由该石墨承载盘所生长的 LED 外延片整体良率高，波长均匀性好，克服了传统石墨承载盘的整体外延片良率不高及受热不均匀造成的外延片波长均匀性分布不稳定的缺点。
下面各实施例公开了一种石墨承载盘，包括若干个设置在承载盘上方的晶圆凹槽，用于置放外延晶圆衬底，晶圆凹槽的内边缘为下凹台阶，且具有复数个向内延伸的支撑部。石墨承载盘还包括石墨承载盘的边缘以及设置在石墨承载盘中心的轴孔。根据不同工艺参数的需要，可设置不同数量及不同尺寸的凹槽。
下面结合实施例和附图对本发明的具体实施做进一步的说明。
实施例 1
参照图 1 及图 8~ 图 10 所示，一种 LED 外延晶圆制程的石墨承载盘，包括： 12 个晶圆凹槽 1 、石墨承载盘的边缘 2 以及设置在石墨承载盘中心的轴孔 3 ，其中，晶圆凹槽 1 设置在承载盘上方，用于置放外延晶圆衬底 16 。晶圆凹槽 1 的内边缘 12 具有台阶 13 和突起 14 ，晶圆凹槽 1 的底部 15 为凹面型，下凹深度 H2 为 5 μ m ～ 30 μ m ，突起 14 呈周期性分布。晶圆凹槽的台阶宽度 W 为 0.2mm ，高度 H1 为 0.03mm 。晶圆凹槽的突起宽度 L 为 0.2mm ，高度 H1 为 0.03mm 。晶圆衬底的直径 D1 与台阶内径 D2 相同，使得晶圆衬底 16 正好置于突起状边缘之上，即由 12 个周期性分布的向内延伸的支撑部 14 支撑，不仅避免晶圆衬底与台阶接触的外围部分会由于直接接触石墨承载盘导致温度过高报废，还可以避免气流流入衬底与石墨盘晶圆凹槽之间的空隙，导致在晶圆衬底底部形成严重的扰流，使外延片翘曲严重。
实施例 2
参照图 11 ，与实施例 1 不同的是：本实施例的晶圆凹槽底部 19 为平面型。其中，晶圆凹槽的台阶 13 宽度 W 为 1.0mm ，高度 H1 为 0.15mm 。晶圆凹槽的突起 14 宽度 W 为 0.4mm ，高度 H1 为 0.15mm 。晶圆衬底的直径 D1 比台阶内径 D2 大 0.04mm ，呈周期性分布突起数量为 6 个，使得晶圆衬底大部分置于突起状边缘之上，晶圆衬底的少部分外围置于台阶状边缘之上。为了既保证晶圆凹槽的内边缘下凹台阶和向内延伸的支撑部能够有效支撑住晶圆衬底，又尽量减少晶圆衬底与石墨承载盘的接触面积，因而与实施例 1 相比，晶圆凹槽的突起数量减少至 6 个，即可实现不仅尽可能减少晶圆衬底的外围部分与台阶接触会由于直接接触石墨承载盘导致温度过高报废，还可以避免气流流入衬底与石墨盘晶圆凹槽之间的空隙，导致在晶圆衬底底部形成严重的扰流，使外延片翘曲严重。
实施例 3
参照图 12 ，与实施例 2 不同的是：本实施例的晶圆凹槽底部 20 为凸面型，其上凸高度 H3 为 5 μ m ～ 30 μ m 。其中，晶圆凹槽的台阶 13 宽度 W 为 1.5mm ，高度 H1 为 0.5mm 。晶圆凹槽的突起 14 宽度 W 为 0.5mm ，高度 H1 为 0.5mm 。晶圆衬底的直径 D1 比台阶内径 D2 大 0.05mm ，呈周期性分布突起数量为 4 个。与实施例 2 相比，由于晶圆衬底架在晶圆凹槽的内边缘下凹台阶上的部分稍多，所以还可以进一步减少突起数量的设置，即减少至 4 个周期性分布，亦可实现不仅尽可能减少晶圆衬底的外围部分与台阶接触会由于直接接触石墨承载盘导致温度过高报废，还可以避免气流流入衬底与石墨盘晶圆凹槽之间的空隙，导致在晶圆衬底底部形成严重的扰流，使外延片翘曲严重。
上述兼具台阶状和突起状边缘的设置，一方面边缘的晶圆凹槽的突起 14 可以将外延晶圆衬底边缘直接托起，使外延晶圆衬底除了与晶圆凹槽的突起 14 接触的大部分（部分实施例还包括晶圆衬底外围的小部分），其余均悬空置于石墨承载盘凹槽上，在外延生长时，外延晶圆衬底由原来的热传导方式受热变为热辐射式受热，大大改善外延晶圆衬底在高温受热时在单位面积上受热效率的一致性，从而可以大大提升外延片波长均匀性及波长良率；另一方面，晶圆凹槽的台阶 13 在外延晶圆衬底边缘可以有效阻止反应室气流 17 流入晶圆衬底与晶圆凹槽之间的空隙 18 中造成扰流，进而有效改善外延波长均匀性及波长良率。
上述各实施例提出的石墨承载盘，适用于 LED 外延制程的 MOCVD 方法。经测定，藉由本发明的石墨承载盘，在外延生长过程中，晶圆凹槽的内边缘结构能够降低气流干扰、提高晶圆的边缘良率。具体来说，其外延波长均匀性及波长良率，相较传统石墨承载盘的成长的外延波长均匀性及波长良率平均可以提升 10% 以上，大大提升了外延产品良率，对于减少 LED 单片产出成本，提升外延质量均匀性有显著功效。
应当理解的是，上述具体实施方案为本发明的优选实施例，本发明的范围不限于该实施例，凡依本发明所做的任何变更，皆属本发明的保护范围之内。

Claims (10)

  1. 一种用于 LED 发光二极管外延制程中的石墨承载盘，其特征在于：包括若干个设置在承载盘上方的晶圆凹槽，用于置放外延晶圆衬底，所述晶圆凹槽的内边缘为下凹台阶，且具有复数个向内延伸的支撑部。
  2. 根据权利要求 1 所述的用于 LED 发光二极管外延制程中的石墨承载盘，其特征在于：在外延生长过程中，所述晶圆凹槽的内边缘结构能够降低气流干扰、提高晶圆的边缘良率。
  3. 根据权利要求 1 所述的用于 LED 发光二极管外延制程中的石墨承载盘，其特征在于：所述晶圆衬底的直径 D1 与台阶内径 D2 的关系为： 0 ≤ D1-D2 ＜ 0.06mm 。
  4. 根据权利要求 1 所述的用于 LED 发光二极管外延制程中的石墨承载盘，其特征在于：所述晶圆凹槽内边缘的台阶宽度为 0.2mm ～ 1.5mm 。
  5. 根据权利要求 4 所述的用于 LED 发光二极管外延制程中的石墨承载盘，其特征在于：所述晶圆凹槽内边缘的台阶宽度为 0.2mm~0.5mm 。
  6. 根据权利要求 1 所述的用于 LED 发光二极管外延制程中的石墨承载盘，其特征在于：所述晶圆凹槽内边缘的支撑部为周期性分布的突起。
  7. 根据权利要求 5 所述的用于 LED 发光二极管外延制程中的石墨承载盘，其特征在于：所述突起宽度为 0.2mm ～ 0.5mm 。
  8. 根据权利要求 5 或 6 所述的用于 LED 发光二极管外延制程中的石墨承载盘，其特征在于：所述晶圆凹槽边缘的台阶高度与突起高度一致。
  9. 根据权利要求 1 所述的用于 LED 发光二极管外延制程中的石墨承载盘，其特征在于：所述晶圆凹槽底部为平面、凸面或者凹面。
  10. 一种 LED 外延制程的 MOCVD 方法，其特征在于：使用权利要求 1 所述的用于 LED 发光二极管外延制程中的石墨承载盘，以所述晶圆凹槽的内边缘结构能够降低气流干扰、提高晶圆的边缘良率。
PCT/CN2013/088264 2012-12-03 2013-12-02 一种用于 led 外延晶圆制程的石墨承载盘 WO2014086250A1 (zh)

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