WO2013094213A1 - セラミックス銅回路基板とそれを用いた半導体装置 - Google Patents
セラミックス銅回路基板とそれを用いた半導体装置 Download PDFInfo
- Publication number
- WO2013094213A1 WO2013094213A1 PCT/JP2012/008178 JP2012008178W WO2013094213A1 WO 2013094213 A1 WO2013094213 A1 WO 2013094213A1 JP 2012008178 W JP2012008178 W JP 2012008178W WO 2013094213 A1 WO2013094213 A1 WO 2013094213A1
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- WIPO (PCT)
- Prior art keywords
- copper
- ceramic
- circuit board
- copper circuit
- substrate
- Prior art date
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- 239000010949 copper Substances 0.000 title claims abstract description 266
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 264
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 252
- 239000000919 ceramic Substances 0.000 title claims abstract description 152
- 239000004065 semiconductor Substances 0.000 title claims description 38
- 239000000758 substrate Substances 0.000 claims abstract description 116
- 229910052751 metal Inorganic materials 0.000 claims abstract description 52
- 239000002184 metal Substances 0.000 claims abstract description 50
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 18
- 229910052799 carbon Inorganic materials 0.000 claims description 16
- 229910052718 tin Inorganic materials 0.000 claims description 16
- 229910052738 indium Inorganic materials 0.000 claims description 15
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 13
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 13
- 229910052709 silver Inorganic materials 0.000 claims description 13
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 229910052735 hafnium Inorganic materials 0.000 claims description 6
- 238000005304 joining Methods 0.000 claims description 6
- 229910052758 niobium Inorganic materials 0.000 claims description 6
- 229910052726 zirconium Inorganic materials 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000012360 testing method Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 27
- 238000005219 brazing Methods 0.000 description 19
- 239000011135 tin Substances 0.000 description 13
- 239000010936 titanium Substances 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 11
- 238000013001 point bending Methods 0.000 description 10
- 238000005530 etching Methods 0.000 description 9
- 238000010438 heat treatment Methods 0.000 description 7
- 230000035882 stress Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- 239000010955 niobium Substances 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000005496 eutectics Effects 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000011247 coating layer Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010944 silver (metal) Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
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- C—CHEMISTRY; METALLURGY
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- C04B37/00—Joining burned ceramic articles with other burned ceramic articles or other articles by heating
- C04B37/02—Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles
- C04B37/023—Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles characterised by the interlayer used
- C04B37/026—Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles characterised by the interlayer used consisting of metals or metal salts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
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- C04B2237/126—Metallic interlayers wherein the active component for bonding is not the largest fraction of the interlayer
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- C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
- C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
- C04B2237/32—Ceramic
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- C04B2237/32—Ceramic
- C04B2237/36—Non-oxidic
- C04B2237/366—Aluminium nitride
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- C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
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- C04B2237/32—Ceramic
- C04B2237/36—Non-oxidic
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- C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
- C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
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- C04B2237/704—Forming laminates or joined articles comprising layers of a specific, unusual thickness of one or more of the ceramic layers or articles
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- C04B2237/50—Processing aspects relating to ceramic laminates or to the joining of ceramic articles with other articles by heating
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- C04B2237/50—Processing aspects relating to ceramic laminates or to the joining of ceramic articles with other articles by heating
- C04B2237/88—Joining of two substrates, where a substantial part of the joining material is present outside of the joint, leading to an outside joining of the joint
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/09145—Edge details
- H05K2201/09154—Bevelled, chamferred or tapered edge
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/098—Special shape of the cross-section of conductors, e.g. very thick plated conductors
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09827—Tapered, e.g. tapered hole, via or groove
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
- H05K2201/2009—Reinforced areas, e.g. for a specific part of a flexible printed circuit
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24479—Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness
- Y10T428/24488—Differential nonuniformity at margin
Definitions
- Embodiments described herein relate generally to a ceramic copper circuit board and a semiconductor device using the same.
- Conventional power module circuit boards include inexpensive aluminum oxide substrates, high thermal conductivity aluminum nitride substrates, ceramic substrates such as high-strength silicon nitride substrates, and metal plates such as copper plates with high thermal conductivity, molybdenum High melting point metal method using (Mo) or tungsten (W), DBC (Direct Bonding Copper) method using eutectic reaction between copper and oxygen, Active metal bonding method using active metal such as titanium (Ti)
- a bonded substrate bonded by, for example, is used.
- a circuit board is formed by patterning a metal plate bonded to a ceramic substrate, for example, by etching.
- the active metal bonding method is generally used because the bonding strength can be increased.
- TCT thermal cycle test
- a ceramic copper circuit board with improved TCT characteristics has been proposed by using a silicon nitride substrate as the ceramic substrate and controlling the composition of the brazing material protruding from the end of the copper plate.
- TCT when -50 ° C. ⁇ 30 minutes ⁇ room temperature ⁇ 10 minutes ⁇ 155 ° C. ⁇ 30 minutes ⁇ room temperature ⁇ 10 minutes is set to one cycle, TCT with more severe conditions is performed. It has been reported that cracks do not occur in the ceramic substrate at the 5000 cycle level.
- the operating temperature of the Si element has been predicted to rise to about 160 to 190 ° C., compared to about 100 to 130 ° C. until now. Further, it is predicted that the operating temperature of SiC elements will increase to 200 to 250 ° C. In order to cope with such high power semiconductor chips and high operating temperatures, ceramic copper circuit boards are required to improve TCT characteristics under more severe conditions.
- TCT characteristics are improved by using a silicon nitride substrate as the ceramic substrate.
- the durability of only about 300 to 400 cycles is obtained with an aluminum nitride substrate or an aluminum oxide substrate.
- the silicon nitride substrate can have a three-point bending strength as high as 600 MPa or more.
- a silicon nitride substrate is generally more expensive than an aluminum nitride substrate or an aluminum oxide substrate. Will increase. For this reason, there is a need for a ceramic copper circuit board that can improve TCT characteristics even when an aluminum nitride substrate or an aluminum oxide substrate is used.
- a bonder / mounter device When a semiconductor chip is mounted on a ceramic copper circuit board, a bonder / mounter device is generally used.
- the surface of the copper plate is image-recognized to detect the position, and after positioning the semiconductor chip with respect to the position-detected copper plate, the semiconductor chip is mounted on the copper plate.
- the position detection of the copper plate is performed by detecting the position of the end of the copper plate using a detector such as a CCD camera.
- the end portion of the copper plate becomes a gently inclined surface.
- Such a gently inclined surface causes a problem that the detection accuracy of the end portion of the copper plate by the detector is lowered.
- the area where the semiconductor chip can be mounted is smaller than the area of the copper plate. For this reason, the restrictions on the design of the semiconductor device increase.
- a problem to be solved by the present invention is to provide a ceramic copper circuit board capable of improving the position detection accuracy of a copper plate and the positioning accuracy of a semiconductor chip based thereon while improving TCT characteristics, and a semiconductor device using the same Is to provide.
- the ceramic copper circuit board of the embodiment includes a ceramic substrate having a first surface and a second surface, at least one active metal element selected from Ti, Zr, Hf, Al, and Nb, and Ag, Cu, Sn.
- a first copper plate bonded to the first surface of the ceramic substrate via a first bonding layer containing at least one element selected from In, C, Ti, Zr, Hf, Al, and Through the second bonding layer containing at least one active metal element selected from Nb and at least one element selected from Ag, Cu, Sn, In, and C, the second surface of the ceramic substrate is provided. And a joined second copper plate.
- the joining end of the copper plate and the ceramic substrate is point A
- the direction from the point A toward the inside of the upper surface of the copper plate is 45 ° with the interface between the copper plate and the ceramic substrate
- the cross-sectional area that protrudes from the straight line AB connecting the point A and the point B toward the outer side of the copper plate is an area C and the right triangle is a hypotenuse with the straight line AB as the hypotenuse.
- the area of the corresponding cross section is defined as area D
- the end portions of the first and second copper plates have a shape in which the ratio of area C to area D (C / D) is in the range of 0.2 to 0.6.
- R portions are respectively provided at the end portions of the upper surfaces of the first and second copper plates corresponding to the corner portions of the area C, and the length of the R portion as viewed from above the first and second copper plates.
- the depth F is 100 ⁇ m or less.
- FIG. 1 is a cross-sectional view showing a configuration of a ceramic copper circuit board according to an embodiment.
- 1 is a ceramic copper circuit board
- 2 is a ceramic board
- 3 is a copper circuit board (first copper board)
- 4 is a back side copper board (second copper board).
- FIG. 1 shows an example in which two copper plates are bonded to the ceramic substrate 2 as the copper circuit plate 3
- the number of copper circuit boards 3 can be increased or decreased as appropriate.
- the first copper plate is not limited to the back side copper plate 4 used for mounting, heat dissipation, or the like, but may be a copper circuit board.
- a copper circuit board (first copper board) 3 is bonded to the first surface 2 a of the ceramic substrate 2 via a first bonding layer 5.
- a back-side copper plate (second copper plate) 4 is bonded to the second surface 2 b of the ceramic substrate 2 via a second bonding layer 6.
- the first and second bonding layers 5 and 6 include at least one active metal element selected from titanium (Ti), zirconium (Zr), hafnium (Hf), aluminum (Al), and niobium (Nb); And at least one element selected from silver (Ag), copper (Cu), tin (Sn), indium (In), and carbon (C).
- the ceramic copper circuit board 1 of the embodiment is configured by bonding copper plates 3 and 4 to both surfaces 2a and 2b of a ceramic substrate 2 by an active metal bonding method.
- the active metal bonding method includes an active metal brazing containing at least one active metal element selected from Ti, Zr, Hf, Al and Nb and at least one element selected from Ag, Cu, Sn, In and C.
- the active metal brazing material is 1 to 6% by mass of active metal element, 50 to 80% by mass of Ag, 15 to 30 when the total of active metal elements, Ag, Cu, Sn, In and C is 100% by mass. It is preferable to contain Cu of mass%, Sn of 15 mass% or less (including zero), In of 15 mass% or less (including zero), and carbon of 2 mass% or less (including zero).
- the active metal brazing material preferably further contains an active metal element, Ag, Cu, and at least one selected from Sn, In and C.
- the content of at least one element selected from Sn, In and C is preferably in the range of 1 to 15% by mass.
- the active metal element is a component that improves the bonding strength between the ceramic substrate 2 and the copper plates 3 and 4 by reacting with the ceramic substrate 2 to form a reaction phase.
- Ti is used as the active metal element, a Ti oxide phase is formed if the ceramic substrate 2 is an aluminum oxide substrate.
- a silicon nitride substrate or an aluminum nitride substrate is used as the ceramic substrate 2, a Ti nitride phase is formed.
- Ti and Zr are preferably used because they easily form a reaction phase with the ceramic substrate 2. In particular, Ti is preferably used.
- the bonding layers 5 and 6 are a combination that generates a eutectic.
- the bonding layers 5 and 6 are strengthened.
- the thermal expansion coefficient and the flexibility of the bonding layers 5 and 6 can be controlled by containing at least one selected from Sn, In and C. Cracks generated in the ceramic substrate 2 when the ceramic copper circuit board 1 is subjected to TCT are caused by stress due to a difference in thermal expansion between the ceramic substrate 2 and the copper plates 3 and 4.
- Sn, In and C are effective components for adjusting the thermal expansion coefficient without inhibiting the formation of Ag—Cu eutectic. Furthermore, the softness
- the ceramic copper circuit board 1 of the embodiment has an end shape shown below when the end portions of the copper plates 3 and 4 are observed in cross section. That is, in the cross section of the end portion of the copper plates 3 and 4, the joining end of the copper plate and the ceramic substrate is point A, and the direction from the point A to the inside of the upper surface of the copper plate is 45 ° with the interface between the copper plate and the ceramic substrate.
- the first and second copper plates 3 and 4 are end shapes in which the ratio of area C to area D (C / D) is in the range of 0.2 to 0.6.
- R portions are provided at the end portions of the upper surfaces of the first and second copper plates 3 and 4 corresponding to the corner portions of the area C, and the first and second copper plates 3 and 4 of the R portion are provided.
- the length F seen from above is 100 ⁇ m or less.
- FIGS. 2 and 3 show the shapes of the end portions of the copper plates 3 and 4 in the ceramic copper circuit board 1 of the embodiment.
- the points A, B, straight line AB, area C, area D, length E, and length F will be described with reference to FIGS.
- the cross section of the edge part of arbitrary copper plates is observed.
- This observation cross section is a cross section in the thickness direction of the copper plate.
- 2 and 3 mainly show an end portion of the copper circuit board (first copper board) 3.
- the end of the back-side copper plate (second copper plate) 4 also has the same shape as the copper circuit board (first copper plate) 3.
- the end shapes shown below indicate the shapes of the end portions of the copper circuit board (first copper plate) 3 and the back side copper plate (second copper plate) 4.
- the point A is the joining end of the copper plate 3 and the ceramic substrate 2.
- the bonding layer 5 is not shown.
- a straight line is drawn from the point A toward the inside of the upper surface of the copper plate 3 in the direction of 45 ° with the interface between the copper plate 3 and the ceramic substrate 2, and a point where this straight line and the upper surface of the copper plate 3 intersect is defined as a point B.
- the area of the cross section that protrudes from the straight line AB connecting the point A and the point B toward the outer side of the copper plate 2 is defined as area C
- the area of the cross section corresponding to the right triangle having the straight line AB as the hypotenuse is defined as area D.
- the copper plate 3 (4) in the embodiment has an end shape in which the ratio of the area C to the area D (C / D) is in the range of 0.2 to 0.6.
- the area ratio (C / D) is more preferably in the range of 0.3 to 0.5.
- the reason for adopting a 45 ° straight line with respect to the interface as a reference for the area D is that it assumes a 45 ° heat dissipation simulation of the ceramic copper circuit board.
- R portions are provided at the end portions of the upper surface of the copper plate 3 (4).
- the end of the upper surface of the copper plate 3 (4) corresponds to the corner of the area C.
- the R portion has a shape in which the length F of the R portion as viewed from above the copper plate 3 (4) is 100 ⁇ m or less. That the length F is 100 ⁇ m or less means that the R portion has a shape with a small radius of curvature R.
- the length F is 100 ⁇ m or less, the position detection accuracy of the copper plate 3 (4) to which image recognition is applied is improved.
- the length F exceeds 100 ⁇ m, the R shape becomes loose, and the accuracy in detecting the end of the copper plate 3 (4) by applying image recognition varies.
- Positioning in a bonder / mounter device or the like is performed by recognizing an image of the copper plate 3 (4) using a detector such as a CCD camera. If the image of the end of the copper plate 3 (4) cannot be accurately recognized, the positioning accuracy of the copper plate 3 (4) is lowered, and the positioning accuracy of the mounting location of the semiconductor chip is deteriorated based on this.
- the length F is preferably 50 ⁇ m or less. However, if the length F is too short, stress concentration tends to occur. Therefore, the length F is preferably 10 ⁇ m or more, and more preferably 20 ⁇ m or more.
- FIG. 4 is a plan view of the ceramic copper circuit board 1 viewed from the copper circuit board 3 side
- FIG. 5 is a back view of the ceramic copper circuit board 1 viewed from the back copper board 4 side.
- a semiconductor chip (not shown) is mounted on a part of the copper circuit board 3 shown in FIG. The mounting position of the semiconductor chip is recognized based on the distance from the end of the copper circuit board 3 detected by image recognition. For this reason, it is necessary that the end of the copper circuit board 3 has a shape that allows easy image recognition.
- the copper circuit board 3 in this embodiment has an R shape with a length F of 100 ⁇ m or less as a shape in which an end portion is easy to recognize an image.
- the semiconductor chip is not shown.
- the semiconductor device of this embodiment is configured by mounting a semiconductor chip on a part of the copper circuit board 3.
- the content of the active metal element per 10 mm 2 formation area of the bonding layer is preferably in the range of 0.5 mg to 0.8 m.
- the active metal element reacts with the ceramic substrate 2 to form a reaction phase.
- the content of the active metal element per 10 mm 2 formation area of the bonding layers 5 and 6 is less than 0.5 mg (milligram), the amount of the active metal element is insufficient and the bonding strength is lowered.
- the content of the active metal element exceeds 0.8 mg, not only a further effect cannot be obtained, but also a factor for increasing the manufacturing cost of the ceramic copper circuit board 1.
- the content of the active metal element per 10 mm 2 formation area of the bonding layers 5 and 6 can be adjusted by, for example, the content of the active metal element in the active metal brazing material and the thickness of the coating layer of the active metal brazing material. it can.
- the bonding layers 5 and 6 protrude from the ends of the copper plates 3 and 4.
- the protruding length E of the bonding layers 5 and 6 from the ends of the copper plates 3 and 4 is preferably in the range of 10 ⁇ m to 150 ⁇ m.
- the protruding length E of the bonding layers 5 and 6 is the width of the bonding layers 5 and 6 protruding outward from the point A as shown in FIG. According to the bonding layers 5 and 6 having the protruding length E of 10 ⁇ m or more, the stress generated at the ends of the copper plates 3 and 4 can be relaxed.
- the protrusion length E is more preferably in the range of 10 to 100 ⁇ m. However, in some cases, the bonding layers 5 and 6 may not protrude from the end portions of the copper plates 3 and 4.
- the ceramic substrate 2 is preferably a silicon nitride substrate made of a silicon nitride sintered body, an aluminum nitride substrate made of an aluminum nitride sintered body, or an aluminum oxide substrate made of an aluminum oxide sintered body.
- the silicon nitride substrate has a high strength such that the three-point bending strength is 600 MPa or more.
- the aluminum nitride substrate has a high thermal conductivity such that the thermal conductivity is 170 W / m ⁇ K or more.
- Aluminum oxide substrates are inexpensive. Based on the superiority of these substrates, the ceramic substrate 2 is selected according to the purpose. As described in Japanese Patent No.
- a silicon nitride substrate having a three-point bending strength of 700 MPa or more and a thermal conductivity of 80 W / m ⁇ K or more has been developed.
- a silicon nitride substrate having high strength and high thermal conductivity can improve TCT characteristics while improving heat dissipation.
- the thickness of the ceramic substrate 2 is preferably in the range of 0.2 to 1 mm.
- the thickness of the copper plates 3 and 4 is preferably in the range of 0.1 to 1 mm. If the thickness of the ceramic substrate 2 is less than 0.2 mm, the strength may decrease and the TCT characteristics may also decrease. If the ceramic substrate 2 is thin, insulation cannot be ensured, and a leakage current may occur. When the thickness of the ceramic substrate 2 exceeds 1 mm, it becomes a thermal resistor, and there is a possibility that the heat dissipation is reduced. When the thickness of the copper plates 3 and 4 is less than 0.1 mm, the current density as a circuit decreases. The strength as the copper plates 3 and 4 also decreases.
- the thickness of the copper plates 3 and 4 is more preferably in the range of 0.2 to 0.6 mm.
- the TCT characteristics of the ceramic copper circuit board 1 can be greatly improved.
- TCT has a low temperature region ⁇ room temperature ⁇ high temperature region ⁇ room temperature as one cycle.
- problems such as cracks in the ceramic substrate 2 and peeling of the copper plates 3 and 4 occur.
- This is a durability test to check the number of cycles to be performed.
- Ceramic copper circuit board 1 is ceramic even after 1000 cycles in TCT with -40 ° C. ⁇ 30 minutes ⁇ room temperature (25 ° C.) ⁇ 10 minutes ⁇ 175 ° C. ⁇ 30 minutes ⁇ room temperature (25 ° C.) ⁇ 10 minutes. It has the characteristic that the substrate 2 does not crack.
- TCT in which one cycle is -50 ° C. ⁇ 30 minutes ⁇ room temperature (25 ° C.) ⁇ 10 minutes ⁇ 250 ° C. ⁇ 30 minutes ⁇ room temperature (25 ° C.) ⁇ 10 minutes.
- TCT has, for example, a maximum temperature (high temperature region) of 125 ° C. or a maximum temperature (high temperature region) of 150 ° C.
- the ceramic copper circuit board 1 according to the embodiment exhibits excellent characteristics such that cracks do not occur in the ceramic substrate even when TCT having a maximum temperature (high temperature region) of 170 ° C. or higher is performed 1000 cycles.
- Specific TCT conditions are as described above. That is, the ceramic copper circuit board 1 of the embodiment has excellent characteristics even under more severe conditions, such as a TCT having a temperature difference of 210 ° C. or higher between the low temperature region and the high temperature region, and a TCT having a temperature difference of 300 ° C. Indicates.
- the reliability of a semiconductor device configured by mounting a semiconductor chip on the copper circuit board 3 can be greatly improved. Therefore, the reliability of the ceramic copper circuit board 1 can be maintained even if the operating temperature becomes 170 ° C. due to the high power of the Si element. Similarly, the TCT characteristics of the ceramic copper circuit board 1 can be maintained even when a semiconductor chip having an operating temperature of 200 to 250 ° C. is mounted like a SiC element. In other words, the ceramic copper circuit board 1 is effective as a circuit board on which a semiconductor chip having an operating temperature of 170 ° C. or higher is mounted.
- the ceramic copper circuit board 1 of the embodiment only needs to have the above-described structure, and its manufacturing method is not particularly limited. As a method for efficiently obtaining the ceramic copper circuit board 1 of the embodiment, the following manufacturing method may be mentioned.
- the ceramic substrate 2 is prepared.
- An active metal braze paste is prepared.
- the ratio of the active metal element, Ag, Cu, Sn, In, and C in the active metal brazing material is as described above.
- An active metal brazing paste is applied onto the ceramic substrate 2.
- the coating thickness of the active metal brazing paste is preferably in the range of 10 to 40 ⁇ m. If the coating thickness is less than 10 ⁇ m, the bonding strength may decrease. The function of the bonding layers 5 and 6 as a thermal stress relaxation layer is also lowered. When the coating thickness exceeds 40 ⁇ m, not only a further effect cannot be obtained, but also the manufacturing cost of the ceramic copper circuit board 1 is increased.
- the copper plate 3 is placed on the area where the active metal brazing paste is applied. At this time, the active metal brazing paste is applied to the back surface of the ceramic substrate 2 and the copper plates 3 and 4 are disposed on both surfaces.
- the copper plates 3 and 4 are preferably oxygen-free copper plates.
- the copper plates 3 and 4 may be processed into a circuit pattern shape in advance, or may have the same vertical and horizontal sizes as the ceramic substrate 2.
- the ceramic substrate 2 and the copper plates 3 and 4 are joined by heating. Heating is preferably performed in a vacuum or in an inert gas atmosphere such as nitrogen gas.
- the heating conditions are preferably 700 to 900 ° C. ⁇ 10 to 120 minutes. When the heating temperature is less than 700 ° C.
- the heating time is less than 10 minutes, the reaction phase between the active metal element and the ceramic substrate 2 is not sufficiently formed, and the bonding strength may be reduced. If the heating temperature exceeds 900 ° C. or the heating time exceeds 120 minutes, the copper plates 3 and 4 are excessively deformed and cause defects.
- the copper plates 3 and 4 are etched as necessary to form a circuit pattern, for example.
- the end portions of the copper plates 3 and 4 may be obtained by bonding the copper plates 3 and 4 whose ends are processed in advance to the target shape to the ceramic substrate 2, or so as to have a target shape after the bonding.
- the copper plates 3 and 4 may be obtained by etching. When etching is applied, the shape of the ends of the copper plates 3 and 4 can be adjusted depending on the strength of the etching conditions. For adjusting the protruding length E of the bonding layers 5 and 6, it is effective to use masking as shown in, for example, International Publication No. 2011/034075.
- a silicon nitride substrate having a thickness of 0.635 mm thermal conductivity: 90 W / m ⁇ K, three-point bending strength: 730 MPa
- an aluminum nitride substrate having a thickness of 0.635 mm thermal conductivity: 180 W.
- an aluminum oxide substrate having a thickness of 0.635 mm thermal conductivity: 15 W / m ⁇ K, 3-point bending strength: 500 MPa
- an active metal brazing material having the composition shown in Table 1 was prepared, pasted, and applied onto a ceramic substrate.
- the coating thickness of the active metal brazing paste is as shown in Table 1.
- a copper plate (oxygen-free copper plate) having a plate thickness of 0.3 mm was prepared.
- the shape of the copper plate was unified as 45 mm long x 25 mm wide.
- a copper plate having a thickness of 0.3 mm was used, and in Examples 10 to 11, a copper plate having a thickness of 0.5 mm was used.
- a copper plate was placed on the printed active metal brazing paste.
- the ceramic plate on which the copper plate was placed was heated in a vacuum at 800 to 840 ° C. for 20 to 40 minutes to bond the copper plate to both sides of the ceramic substrate.
- the two circuit patterns shown in FIG. 4 were formed by etching the copper plate on the surface side using an FeCl 3 etching solution.
- the circuit pattern has a structure in which two 20 mm long ⁇ 20 mm wide patterns are formed with an interval of 2 mm.
- the end portion of the copper plate was processed into a shape satisfying the conditions shown in Table 2 by changing the etching conditions.
- the edge part shape of the copper board shown in Table 2 was provided in both the copper circuit board and the back side copper board.
- the bonding strength of the copper plate, the withstand voltage failure rate, the TCT characteristics, and the positioning accuracy by image recognition were examined.
- the bonding strength was measured by peel strength.
- the withstand voltage failure rate means that the lower the value, the less the failure occurs.
- Condition 1 was set to one cycle of ⁇ 40 ° C. ⁇ 30 minutes ⁇ room temperature (25 ° C.) ⁇ 10 minutes ⁇ 125 ° C. ⁇ 30 minutes ⁇ room temperature (25 ° C.) ⁇ 10 minutes.
- Condition 2 was -40 ° C. ⁇ 30 minutes ⁇ room temperature (25 ° C.) ⁇ 10 minutes ⁇ 175 ° C. ⁇ 30 minutes ⁇ room temperature (25 ° C.) ⁇ 10 minutes.
- Condition 3 was set to one cycle of ⁇ 50 ° C. ⁇ 30 minutes ⁇ room temperature (25 ° C.) ⁇ 10 minutes ⁇ 250 ° C. ⁇ 30 minutes ⁇ room temperature (25 ° C.) ⁇ 10 minutes.
- the presence or absence of cracks in the ceramic substrate after 1000 cycles was examined by the soundness rate ⁇ (%).
- the soundness ratio ⁇ (%) is an examination of the ratio of cracks formed around the joint edge of the copper plate of the ceramic copper circuit board. When the perimeter of the joining end of the copper plate is 100%, the ratio at which cracks did not occur is measured. A soundness rate ⁇ (%) of 100% means that no cracks occurred. A soundness rate ⁇ (%) of 0% means that cracks occurred in the peripheral lengths of the joining ends of all the copper plates.
- the ceramic copper circuit boards of the examples all had excellent TCT characteristics. No misalignment occurred due to the bonder / mounter device (image recognition type by CCD camera). Furthermore, since the end shape of the copper plate is improved, a large mounting area of the semiconductor chip on the copper circuit board can be secured.
- Example 12 The ceramic copper circuit board of Example 9 was changed to Example 12, and the ceramic copper circuit board of Example 9 was changed to a copper plate thickness of 0.5 mm as Example 13.
- condition 2 (1 cycle: ⁇ 40 ° C. ⁇ 30 minutes ⁇ room temperature (25 ° C.) ⁇ 10 minutes ⁇ 175 ° C. ⁇ 30 minutes ⁇ room temperature (25 ° C.) ⁇ 10 minutes ), And the number of cycles in which cracks occurred in the ceramic substrate was examined. The results are shown in Table 4.
- the ceramic copper circuit board of the example has a durability of 6000 cycles or more, even for a TCT having a maximum temperature exceeding 170 ° C.
- the ceramic substrate 1 is a silicon nitride substrate (thermal conductivity: 93 W / m ⁇ K, three-point bending strength: 700 MPa) with a plate thickness of 0.320 mm.
- the ceramic substrate 2 is a silicon nitride substrate (thermal conductivity: 100 W / m ⁇ K, three-point bending strength: 600 MPa) with a plate thickness of 0.320 mm.
- the ceramic substrate 3 is an aluminum nitride substrate (thermal conductivity: 200 W / m ⁇ K, 3-point bending strength: 320 MPa) having a thickness of 0.635 mm.
- the ceramic substrate 4 is an aluminum oxide substrate (thermal conductivity: 12 W / m ⁇ K, three-point bending strength: 400 MPa) having a thickness of 0.635 mm.
- the shape of the ceramic substrate was unified to be 50 mm long ⁇ 30 mm wide.
- an active metal brazing material having a composition shown in Table 5 was prepared, pasted, printed on a ceramic substrate, and applied.
- a copper plate of 45 mm long ⁇ 20 mm wide ⁇ 0.3 mm thick was prepared.
- a copper plate was placed on the coating layer of the active metal brazing paste.
- the ceramic plate on which the copper plate was placed was heated in a vacuum at 800 to 840 ° C. for 20 to 40 minutes to bond the copper plate to both sides of the ceramic substrate.
- the copper plate on the surface side was etched using an FeCl 3 etching solution to form two circuit patterns shown in FIG.
- the circuit pattern has a structure in which two 20 mm long ⁇ 20 mm wide patterns are formed with an interval of 2 mm.
- the end of the copper plate was processed into a shape satisfying the conditions shown in Table 6 by changing the etching conditions.
- the edge part shape of the copper board shown in Table 6 was provided in both the copper circuit board and the back side copper board.
- each of Examples 14 to 16 using a silicon nitride substrate had a durability of 5000 cycles or more.
- the durability of Example 17 using the aluminum nitride substrate and Example 18 using the aluminum oxide substrate was about 1400 to 1500 cycles, which was inferior to that of Examples 14 to 16, but the conventional aluminum nitride substrate and Compared to a ceramic copper circuit board using an aluminum oxide substrate, it was confirmed to have excellent TCT characteristics. From the results of Examples 14 to 18, it can be seen that the use of the silicon nitride substrate further improves the TCT characteristics of the ceramic copper circuit board.
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Abstract
Description
セラミックス基板として、板厚が0.635mmの窒化珪素基板(熱伝導率:90W/m・K、3点曲げ強度:730MPa)と、板厚が0.635mmの窒化アルミニウム基板(熱伝導率:180W/m・K、3点曲げ強度:400MPa)と、板厚が0.635mmの酸化アルミニウム基板(熱伝導率:15W/m・K、3点曲げ強度:500MPa)とを用意した。セラミックス基板の形状は縦50mm×横30mmで統一した。
実施例9のセラミックス銅回路基板を実施例12、実施例9のセラミックス銅回路基板の銅板厚さを0.5mmに変えたものを実施例13とした。実施例12および実施例13のセラミックス銅回路基板について、条件2(1サイクル:-40℃×30分→室温(25℃)×10分→175℃×30分→室温(25℃)×10分)でTCTを実施し、セラミックス基板にクラックが発生するサイクル数を調べた。その結果を表4に示す。
セラミックス基板として以下のものを用意した。セラミックス基板1は板厚が0.320mmの窒化珪素基板(熱伝導率:93W/m・K、3点曲げ強度:700MPa)である。セラミックス基板2は板厚が0.320mmの窒化珪素基板(熱伝導率:100W/m・K、3点曲げ強度:600MPa)である。セラミックス基板3は板厚が0.635mmの窒化アルミニウム基板(熱伝導率:200W/m・K、3点曲げ強度:320MPa)である。セラミックス基板4は板厚が0.635mmの酸化アルミニウム基板(熱伝導率:12W/m・K、3点曲げ強度:400MPa)である。なお、セラミックス基板の形状は縦50mm×横30mmで統一した。
Claims (12)
- 第1の面と第2の面とを有するセラミックス基板と、
Ti、Zr、Hf、AlおよびNbから選ばれる少なくとも1種の活性金属元素とAg、Cu、Sn、InおよびCから選ばれる少なくとも1種の元素とを含む第1の接合層を介して、前記セラミックス基板の第1の面に接合された第1の銅板と、
Ti、Zr、Hf、AlおよびNbから選ばれる少なくとも1種の活性金属元素とAg、Cu、Sn、InおよびCから選ばれる少なくとも1種の元素とを含む第2の接合層を介して、前記セラミックス基板の第2の面に接合された第2の銅板とを具備し、
前記第1および第2の銅板の端部の断面において、前記銅板と前記セラミックス基板との接合端を点A、前記点Aから前記銅板の上面の内側に向けて前記銅板と前記セラミックス基板との界面と45°となる方向に引いた直線と前記銅板上面とが交わる点を点B、前記点Aと前記点Bとを結ぶ直線ABより前記銅板の外側方向に向けてはみ出す断面の面積を面積C、前記直線ABを斜辺とする直角三角形に相当する断面の面積を面積Dとしたとき、前記第1および第2の銅板の端部は前記面積Dに対する前記面積Cの割合(C/D)が0.2以上0.6以下の範囲である形状を有し、
前記面積Cの角部に相当する前記第1および第2の銅板の前記上面の端部には、それぞれR部が設けられており、かつ前記R部の前記第1および第2の銅板の上方から見た長さFが100μm以下であることを特徴とするセラミックス銅回路基板。 - 前記第1および第2の接合層の10mm2の形成面積当たりにおける前記活性金属元素の含有量が0.5mg以上0.8mg以下の範囲である、請求項1に記載のセラミックス銅回路基板。
- 前記第1および第2の接合層の端部は、それぞれ前記第1および第2の銅板の端部からはみ出しており、前記第1および第2の接合層の端部の前記第1および第2の銅板の端部からのはみ出し長さEが10μm以上150μm以下の範囲である、請求項1に記載のセラミックス銅回路基板。
- 前記第1および第2の接合層は、前記活性金属元素と、Agと、Cuと、Sn、InおよびCから選ばれる少なくとも1種の元素とを含有する、請求項1に記載のセラミックス銅回路基板。
- 前記第1および第2の接合層は、前記活性金属元素、Ag、Cu、Sn、InおよびCを含有する、請求項1に記載のセラミックス銅回路基板。
- 前記セラミックス基板は、窒化珪素基板、窒化アルミニウム基板、または酸化アルミニウム基板である、請求項1に記載のセラミックス銅回路基板。
- 前記セラミックス基板の厚さが0.2mm以上1mm以下の範囲である、請求項1に記載のセラミックス銅回路基板。
- 前記第1および第2の銅板の厚さがそれぞれ0.1mm以上1mm以下の範囲である、請求項1に記載のセラミックス銅回路基板。
- 前記セラミックス銅回路基板に対して最大温度が170℃以上の熱サイクル試験を1000サイクル実施したときに、前記セラミックス基板にクラックが生じない、請求項1に記載のセラミックス銅回路基板。
- 前記熱サイクル試験は、-40℃×30分→室温(25℃)×10分→175℃×30分→室温(25℃)×10分を1サイクルとして実施される、請求項9に記載のセラミックス銅回路基板。
- 請求項1に記載のセラミックス銅回路基板と、
前記セラミックス銅回路基板の前記第1の銅板上に搭載された半導体チップと
を具備することを特徴とする半導体装置。 - 前記半導体チップはSiC素子を備える、請求項11に記載の半導体装置。
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KR101659194B1 (ko) | 2016-09-22 |
JP2016174165A (ja) | 2016-09-29 |
JP5976678B2 (ja) | 2016-08-24 |
KR20140112029A (ko) | 2014-09-22 |
JP6125691B2 (ja) | 2017-05-10 |
JP2017130686A (ja) | 2017-07-27 |
CN104011852A (zh) | 2014-08-27 |
US20140291699A1 (en) | 2014-10-02 |
US9357643B2 (en) | 2016-05-31 |
JPWO2013094213A1 (ja) | 2015-04-27 |
CN104011852B (zh) | 2016-12-21 |
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