WO2012160704A1 - 半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置 - Google Patents
半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置 Download PDFInfo
- Publication number
- WO2012160704A1 WO2012160704A1 PCT/JP2011/062134 JP2011062134W WO2012160704A1 WO 2012160704 A1 WO2012160704 A1 WO 2012160704A1 JP 2011062134 W JP2011062134 W JP 2011062134W WO 2012160704 A1 WO2012160704 A1 WO 2012160704A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- mol
- junction
- semiconductor device
- semiconductor
- content
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 182
- 239000011521 glass Substances 0.000 title claims abstract description 131
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 53
- 239000000203 mixture Substances 0.000 title claims abstract description 51
- ODINCKMPIJJUCX-UHFFFAOYSA-N calcium oxide Inorganic materials [Ca]=O ODINCKMPIJJUCX-UHFFFAOYSA-N 0.000 claims abstract description 19
- XLOMVQKBTHCTTD-UHFFFAOYSA-N zinc oxide Inorganic materials [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 15
- 229910052787 antimony Inorganic materials 0.000 claims abstract description 14
- 229910052744 lithium Inorganic materials 0.000 claims abstract description 14
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 14
- 229910052745 lead Inorganic materials 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims description 60
- 238000000034 method Methods 0.000 claims description 30
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 22
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 20
- 229910052796 boron Inorganic materials 0.000 claims description 11
- 230000001681 protective effect Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 18
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052593 corundum Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 2
- 238000011156 evaluation Methods 0.000 description 26
- 238000009792 diffusion process Methods 0.000 description 24
- 230000015572 biosynthetic process Effects 0.000 description 14
- 238000010304 firing Methods 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000002161 passivation Methods 0.000 description 7
- 238000007747 plating Methods 0.000 description 7
- 239000000126 substance Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 6
- 239000002994 raw material Substances 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000001962 electrophoresis Methods 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000007788 roughening Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C3/00—Glass compositions
- C03C3/04—Glass compositions containing silica
- C03C3/062—Glass compositions containing silica with less than 40% silica by weight
- C03C3/064—Glass compositions containing silica with less than 40% silica by weight containing boron
- C03C3/066—Glass compositions containing silica with less than 40% silica by weight containing boron containing zinc
-
- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C3/00—Glass compositions
- C03C3/04—Glass compositions containing silica
- C03C3/076—Glass compositions containing silica with 40% to 90% silica, by weight
- C03C3/089—Glass compositions containing silica with 40% to 90% silica, by weight containing boron
- C03C3/091—Glass compositions containing silica with 40% to 90% silica, by weight containing boron containing aluminium
- C03C3/093—Glass compositions containing silica with 40% to 90% silica, by weight containing boron containing aluminium containing zinc or zirconium
-
- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C8/00—Enamels; Glazes; Fusion seal compositions being frit compositions having non-frit additions
- C03C8/02—Frit compositions, i.e. in a powdered or comminuted form
- C03C8/04—Frit compositions, i.e. in a powdered or comminuted form containing zinc
-
- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C8/00—Enamels; Glazes; Fusion seal compositions being frit compositions having non-frit additions
- C03C8/24—Fusion seal compositions being frit compositions having non-frit additions, i.e. for use as seals between dissimilar materials, e.g. glass and metal; Glass solders
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3178—Coating or filling in grooves made in the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a glass composition for protecting a semiconductor junction, a method for manufacturing a semiconductor device, and a semiconductor device.
- a semiconductor device manufacturing method is known in which a passivation glass layer is formed so as to cover a pn junction exposed portion in the process of manufacturing a mesa type semiconductor device (see, for example, Patent Document 1).
- FIGS. 6 and 7 are views for explaining such a conventional method of manufacturing a semiconductor device.
- 6 (a) to 6 (d) and FIGS. 7 (a) to 7 (d) are process diagrams.
- the conventional semiconductor device manufacturing method includes a “semiconductor substrate forming step”, a “groove forming step”, a “glass layer forming step”, a “photoresist forming step”, and an “oxide removal”. Step, “roughened region forming step”, “electrode forming step” and “semiconductor substrate cutting step” are included in this order.
- a conventional method for manufacturing a semiconductor device will be described in the order of steps.
- n + -type diffusion layer 912 is diffused from one surface of n ⁇ -type semiconductor substrate (n ⁇ -type silicon substrate) 910, and n-type impurities from the other surface are diffused.
- An n + -type diffusion layer 914 is formed by diffusion to form a semiconductor substrate in which a pn junction parallel to the main surface is formed.
- oxide films 916 and 918 are formed on the surfaces of the p + type diffusion layer 912 and the n + type diffusion layer 914 by thermal oxidation (see FIG. 6A).
- the step of forming the groove 920 exceeding the pn junction from one surface of the semiconductor substrate on which the pn junction parallel to the main surface is formed (FIG. 6A and FIG.
- a step of forming a passivation glass layer 924 so as to cover the exposed portion of the pn junction inside the groove 920 (see FIG. 6C). Therefore, according to the conventional method for manufacturing a semiconductor device, a high-breakdown-voltage mesa semiconductor device can be manufactured by forming a passivation glass layer 924 in the groove 920 and then cutting the semiconductor substrate. .
- glass material used for the glass layer for passivation (a) it can be fired at an appropriate temperature (for example, 900 ° C. or less), (b) can withstand chemicals used in the process, and (c) thermal expansion close to silicon. It is necessary to satisfy the requirements of having a coefficient (especially an average coefficient of thermal expansion at 50 ° C. to 500 ° C. is close to that of silicon) and (d) having an excellent insulating property. “Glass materials as components” are widely used.
- glass material based on lead silicate contains lead with a large environmental impact, and in the near future, the use of such “glass material based on lead silicate” is prohibited. It is thought that it will go.
- the present invention has been made in view of the above circumstances, and uses a glass material that does not contain lead, as in the case of using the conventional “glass material mainly composed of lead silicate”. It is an object of the present invention to provide a glass composition for protecting a semiconductor junction, a method for manufacturing a semiconductor device, and a semiconductor device, which make it possible to manufacture the semiconductor device.
- the glass composition for protecting a semiconductor junction of the present invention contains at least SiO 2 , Al 2 O 3 , ZnO, CaO, and 3 mol% to 10 mol% B 2 O 3 , and Pb And P, As, Sb, Li, Na, and K are substantially not contained.
- the content of SiO 2 is in the range of 32 mol% to 48 mol%, and the content of Al 2 O 3 is in the range of 9 mol% to 13 mol%.
- the ZnO content is in the range of 18 mol% to 28 mol%
- the CaO content is in the range of 15 mol% to 23 mol%
- the content of B 2 O 3 is in the range of 3 mol% to 10 mol%. It is preferable that it exists in.
- a method of manufacturing a semiconductor device includes a first step of preparing a semiconductor element having a pn junction exposed portion where a pn junction is exposed, and a second step of forming a glass layer so as to cover the pn junction exposed portion.
- the second step at least SiO 2 , Al 2 O 3 , ZnO, CaO, and 3 mol% to 10 mol% B 2 O 3 are included in this order.
- the glass layer is formed using a glass composition for protecting a semiconductor junction that contains substantially no Pb, P, As, Sb, Li, Na, and K. It is characterized by.
- the first step includes a step of preparing a semiconductor substrate having a pn junction parallel to the main surface, and the pn junction is exceeded from one surface of the semiconductor substrate. Forming the pn junction exposed portion in the groove by forming a groove having a depth, and the second step covers the pn junction exposed portion in the groove. It is preferable to include a step of forming a layer.
- the second step includes a step of forming the glass layer so as to directly cover the exposed portion of the pn junction inside the groove.
- forming the glass layer so as to cover the pn junction exposed portion “directly” means forming the glass layer so as to cover the pn junction exposed portion “directly without an insulating layer or the like”.
- the second step includes a step of forming an insulating film on the pn junction exposed portion in the trench, and the pn junction exposure through the insulating film. And forming the glass layer so as to cover the portion.
- the first step includes a step of forming the pn junction exposed portion on the surface of the semiconductor substrate
- the second step includes the step on the surface of the semiconductor substrate. It is preferable to include a step of forming the glass layer so as to cover the pn junction exposed portion.
- the second step includes a step of forming the glass layer so as to directly cover the pn junction exposed portion on the surface of the semiconductor substrate.
- forming the glass layer so as to cover the pn junction exposed portion “directly” means forming the glass layer so as to cover the pn junction exposed portion “directly without an insulating layer or the like”.
- the second step includes a step of forming an insulating film on the pn junction exposed portion on the surface of the semiconductor substrate, and the pn junction via the insulating film. And a step of forming the glass layer so as to cover the exposed portion.
- the glass composition for protecting a semiconductor junction has a SiO 2 content in the range of 32 mol% to 48 mol% and an Al 2 O 3 content of 9 mol. % To 13 mol%, the content of ZnO is in the range of 18 mol% to 28 mol%, the content of CaO is in the range of 15 mol% to 23 mol%, and the content of B 2 O 3 is It is preferably in the range of 3 mol% to 10 mol%.
- a semiconductor device is a semiconductor device comprising a semiconductor element having a pn junction exposed portion from which a pn junction is exposed, and a glass layer formed so as to cover the pn junction exposed portion, wherein the glass The layer contains at least SiO 2 , Al 2 O 3 , ZnO, CaO, 3 mol% to 10 mol% B 2 O 3 , and Pb, P, As, Sb, and Li And it is formed using the glass composition for semiconductor junction protection which does not contain Na and K substantially, It is characterized by the above-mentioned.
- the content of SiO 2 is in the range of 32 mol% to 48 mol%
- the content of Al 2 O 3 is in the range of 9 mol% to 13 mol%
- the content of ZnO Preferably, the amount is in the range of 18 mol% to 28 mol%
- the content of CaO is in the range of 15 mol% to 23 mol%
- the content of B 2 O 3 is in the range of 3 mol% to 10 mol%.
- a glass material containing no lead is used, A high breakdown voltage semiconductor device can be manufactured in the same manner as in the case of using “a glass material having a main component”.
- the firing temperature is lower than that in the case of a glass composition not containing B 2 O 3 (for example, 900 ° C. or less), and glass easily A layer can be formed. Furthermore, since the content of B 2 O 3 is set to 10 mol% or less, boron is not diffused into the semiconductor substrate in the step of firing the glass layer, and the insulating property is not lowered.
- Pb, P, As, Sb, Li, Na, and K are substantially free of Pb, P, As, It means that Sb, Li, Na, and K are not contained as components, and does not exclude a glass composition in which the above is mixed as an impurity in the raw materials of each component constituting the glass. The same applies to the semiconductor device manufacturing method and the semiconductor device of the present invention.
- Pb is not substantially contained because the purpose of the present invention is to use a conventional “glass material containing lead silicate as a main component using a glass material not containing lead”. Similarly, it is possible to manufacture a semiconductor device having a high breakdown voltage ”.
- P, As, and Sb are substantially not contained is advantageous in terms of the firing temperature when these components are contained, but these components are contained in the semiconductor during firing. This is because the insulating property may be lowered due to diffusion to the substrate.
- Li, Na, and K are not substantially contained is advantageous in terms of the average coefficient of thermal expansion and the firing temperature when these components are contained. This is because it may decrease.
- a glass composition containing at least SiO 2 , Al 2 O 3 , ZnO, CaO, and 3 mol% to 10 mol% of B 2 O 3 may be used as a glass composition for protecting a semiconductor junction.
- a conventional “glass material mainly composed of lead silicate” using a glass material not containing lead can be manufactured as in the case of using it.
- FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the second embodiment.
- FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the second embodiment.
- FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the third embodiment.
- FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the third embodiment. It is a graph which shows the result of an Example. It is a figure shown in order to demonstrate the manufacturing method of the conventional semiconductor device. It is a figure shown in order to demonstrate the manufacturing method of the conventional semiconductor device.
- Embodiment 1 is an embodiment according to a glass composition for protecting a semiconductor junction.
- the glass composition for protecting a semiconductor junction according to Embodiment 1 contains at least SiO 2 , Al 2 O 3 , ZnO, CaO, 3 mol% to 10 mol% B 2 O 3 , and Pb , P, As, Sb, Li, Na, and K are not substantially contained.
- the content of SiO 2 is in the range of 32 mol% to 48 mol% (eg, 40 mol%), and the content of Al 2 O 3 is in the range of 9 mol% to 13 mol% (eg, 11 mol%).
- the content of ZnO is in the range of 18 mol% to 28 mol% (eg, 23 mol%), the content of CaO is in the range of 15 mol% to 23 mol% (eg, 19 mol%), and the content of B 2 O 3 Is in the range of 3 mol% to 10 mol% (for example, 7 mol%).
- a conventional “glass material mainly composed of lead silicate” using a glass material not containing lead can be manufactured in the same manner as in the case of using.
- the reason why the SiO 2 content is in the range of 32 mol% to 48 mol% is that when the SiO 2 content is less than 32 mol%, the chemical resistance is lowered or the insulation is lowered. This is because if the content of SiO 2 exceeds 48 mol%, the firing temperature tends to increase.
- the content of Al 2 O 3 is set within the range of 9 mol% to 13 mol% because when the content of Al 2 O 3 is less than 9 mol%, the chemical resistance decreases or the insulating property This is because the firing temperature tends to increase when the Al 2 O 3 content exceeds 13 mol%.
- the reason why the ZnO content is in the range of 18 mol% to 28 mol% is that when the ZnO content is less than 18 mol%, the firing temperature tends to increase. This is because when the content exceeds 28 mol%, chemical resistance may be lowered or insulation properties may be lowered.
- the reason why the CaO content is in the range of 15 mol% to 23 mol% is that the firing temperature tends to increase when the CaO content is less than 15 mol%. This is because when the amount exceeds 23 mol%, chemical resistance may be lowered or insulation may be lowered.
- the reason why the content of B 2 O 3 is in the range of 3 mol% to 10 mol% is that the firing temperature tends to increase when the content of B 2 O 3 is less than 3 mol%. This is because if the content of B 2 O 3 exceeds 10 mol%, the insulating property may be lowered.
- the glass composition for protecting a semiconductor junction according to Embodiment 1 can be manufactured as follows. That is, the raw materials (SiO 2 , Al (OH) 3 , ZnO, CaO, H 3 BO 3 ) were prepared so as to have the above-described composition ratio (molar ratio), stirred well with a mixer, and then the mixed raw materials Is placed in a platinum crucible raised to a predetermined temperature in an electric furnace and melted for a predetermined time. Thereafter, the melt is poured into a water-cooled roll to obtain flaky glass flakes. Thereafter, the glass flakes are pulverized with a ball mill or the like until a predetermined average particle diameter is obtained to obtain a powdery glass composition.
- the second embodiment is an embodiment according to a method for manufacturing a semiconductor device.
- the manufacturing method of the semiconductor device includes a first step of preparing a semiconductor element having a pn junction exposed portion where a pn junction is exposed, and a second step of forming a glass layer so as to cover the pn junction exposed portion.
- a first step of preparing a semiconductor element having a pn junction exposed portion where a pn junction is exposed and a second step of forming a glass layer so as to cover the pn junction exposed portion.
- at least SiO 2 , Al 2 O 3 , ZnO, CaO, and 3 mol% to 10 mol% B 2 O 3 are contained, and Pb, P, and As are contained.
- forming a glass layer using a glass composition for protecting a semiconductor junction that does not substantially contain Sb, Li, Na, and K (the glass composition for protecting a semiconductor junction according to Embodiment 1). Yes.
- the first step a semiconductor substrate having a pn junction parallel to the main surface is prepared, and a groove having a depth exceeding the pn junction is formed from one surface of the semiconductor substrate to expose the pn junction inside the groove.
- the second step includes a step of forming a glass layer so as to directly cover the pn junction exposed portion inside the groove.
- FIGS. 1 and 2 are views for explaining a method of manufacturing a semiconductor device according to the second embodiment.
- FIGS. 2A to 2D are process diagrams.
- the method for manufacturing a semiconductor device according to the second embodiment includes a “semiconductor substrate forming step”, a “groove forming step”, a “glass layer forming step”, a “photoresist forming step”, “ The “oxide film removing step”, “roughened region forming step”, “electrode forming step”, and “semiconductor substrate cutting step” are performed in this order.
- the semiconductor device manufacturing method according to the second embodiment will be described below in the order of steps.
- p + -type diffusion layer 112 is diffused by diffusion of p-type impurities from one surface of n ⁇ -type semiconductor substrate (n ⁇ -type silicon substrate) 110, and n-type impurities from the other surface.
- An n + -type diffusion layer 114 is formed by diffusion to form a semiconductor substrate in which a pn junction parallel to the main surface is formed.
- oxide films 116 and 118 are formed on the surfaces of the p + type diffusion layer 112 and the n + type diffusion layer 114 by thermal oxidation (see FIG. 1A).
- (F) Roughened region forming step Next, a roughened surface for increasing the adhesion between the Ni-plated electrode and the semiconductor substrate by performing a roughening treatment on the surface of the semiconductor substrate in the portion 130 where the Ni-plated electrode film is formed.
- the formation region 132 is formed (see FIG. 2B).
- Electrode forming step Ni plating is performed on the semiconductor substrate to form the anode electrode 134 on the roughened region 132 and the cathode electrode 136 is formed on the other surface of the semiconductor substrate (FIG. 2C). )reference.).
- a high-voltage mesa semiconductor device semiconductor device according to Embodiment 2
- semiconductor device semiconductor device according to Embodiment 2
- the third embodiment is an embodiment according to a method for manufacturing a semiconductor device.
- the method for manufacturing a semiconductor device according to the third embodiment includes a first step of preparing a semiconductor element having a pn junction exposed portion where the pn junction is exposed, and pn junction exposure. And a second step of forming a glass layer so as to cover the part in this order.
- the second step at least SiO 2 , Al 2 O 3 , ZnO, CaO, and 3 mol% to 10 mol% B 2 O 3 are contained, and Pb, P, and As are contained.
- forming a glass layer using a glass composition for protecting a semiconductor junction that does not substantially contain Sb, Li, Na, and K (the glass composition for protecting a semiconductor junction according to Embodiment 1).
- the first step includes a step of forming a pn junction exposed portion on the surface of the semiconductor substrate, and the second step includes a pn on the surface of the semiconductor substrate. Forming a glass layer so as to directly cover the joint exposed portion.
- FIGS. 3 and 4 are views for explaining the semiconductor device manufacturing method according to the third embodiment.
- 3A to FIG. 3C and FIG. 4A to FIG. 4C are process diagrams.
- the method for manufacturing a semiconductor device according to the third embodiment includes a “semiconductor substrate preparation step”, a “p + -type diffusion layer formation step”, an “n + -type diffusion layer formation step”, “ The “glass layer forming step”, “glass layer etching step” and “electrode forming step” are performed in this order.
- the semiconductor device manufacturing method according to the third embodiment will be described below in the order of steps.
- a p-type impurity for example, boron ions
- a p + type diffusion layer 214 is formed by thermal diffusion (see FIG. 3B).
- n + -type diffusion layer forming step Next, after removing the mask M1 and forming the mask M2, an n - type is formed on the surface of the n ⁇ -type epitaxial layer 212 via the mask M2 by ion implantation. Impurities (for example, arsenic ions) are introduced. Thereafter, an n + -type diffusion layer 216 is formed by thermal diffusion (see FIG. 3C).
- a high breakdown voltage planar semiconductor device semiconductor device according to Embodiment 3
- semiconductor device semiconductor device according to Embodiment 3
- Example 1 Sample Adjustment FIG. 5 is a chart showing the results of Examples.
- the raw materials were prepared so as to have the composition ratios shown in Example 1 and Comparative Examples 1 and 2 (see FIG. 5), stirred well with a mixer, and then the mixed raw materials were raised to 1550 ° C. in an electric furnace. It was put in a platinum crucible and melted for 2 hours. Thereafter, the melt was poured into a water-cooled roll to obtain flaky glass flakes. The glass flakes were pulverized with a ball mill until the average particle size became 5 ⁇ m to obtain a powdery glass composition.
- raw materials used in the examples are SiO 2, Al (OH) 3 , ZnO, CaO, H 3 BO 3, PbO.
- Evaluation method 1 (environmental load)
- the object of the present invention is “to make it possible to manufacture a semiconductor device having a high withstand voltage using a glass material containing no lead as in the case of using a conventional“ glass material mainly composed of lead silicate ”. Therefore, when the lead component is not included, an evaluation of “ ⁇ ” is given, and when the lead component is included, an evaluation of “x” is given.
- Evaluation method 5 (insulating property) A semiconductor device (pn diode) was manufactured by the same method as the method for manufacturing a semiconductor device according to Embodiment 2, and the reverse characteristics of the manufactured semiconductor device were measured. As a result, an evaluation of “ ⁇ ” was given when the reverse direction characteristic of the semiconductor device was normal, and an evaluation of “x” was given when the reverse direction characteristic of the semiconductor device was abnormal.
- the glass composition according to Comparative Example 1 was evaluated as “x” in Evaluation Item 1.
- the glass composition according to Comparative Example 2 was evaluated as “x” in Evaluation Item 3.
- the glass composition according to Example 1 was evaluated as “ ⁇ ” for any of the evaluation items (evaluation items 1 to 5).
- the glass composition according to Embodiment 1 is (a) capable of firing at an appropriate temperature (for example, 900 ° C. or less) and (b) can withstand chemicals used in the process, while being a glass material not containing lead. And (c) a glass composition satisfying all the conditions of having a thermal expansion coefficient close to that of silicon (particularly having an average coefficient of thermal expansion close to that of silicon at 50 ° C. to 500 ° C.) and (d) having excellent insulating properties. It turns out that.
- the glass layer is formed in the second step so as to directly cover the exposed pn junction in the groove, but the present invention is not limited to this.
- an insulating film may be formed on the pn junction exposed portion inside the trench, and then a glass layer may be formed so as to cover the pn junction exposed portion via the insulating film.
- the glass layer is formed in the second step so as to directly cover the exposed pn junction on the surface of the semiconductor substrate, but the present invention is not limited to this.
- an insulating film may be formed on the exposed pn junction on the surface of the semiconductor substrate, and then a glass layer may be formed so as to cover the exposed pn junction via the insulating film.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Organic Chemistry (AREA)
- Materials Engineering (AREA)
- Life Sciences & Earth Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Geochemistry & Mineralogy (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Glass Compositions (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
従来の半導体装置の製造方法は、図6及び図7に示すように、「半導体基体形成工程」、「溝形成工程」、「ガラス層形成工程」、「フォトレジスト形成工程」、「酸化膜除去工程」、「粗面化領域形成工程」、「電極形成工程」及び「半導体基体切断工程」をこの順序で含む。以下、従来の半導体装置の製造方法を工程順に説明する。
まず、n-型半導体基板(n-型シリコン基板)910の一方の表面からのp型不純物の拡散によりp+型拡散層912、他方の表面からのn型不純物の拡散によりn+型拡散層914を形成して、主面に平行なpn接合が形成された半導体基体を形成する。その後、熱酸化によりp+型拡散層912及びn+型拡散層914の表面に酸化膜916,918を形成する(図6(a)参照。)。
次に、フォトエッチング法によって、酸化膜916の所定部位に所定の開口部を形成する。酸化膜のエッチング後、引き続いて半導体基体のエッチングを行い、半導体基体の一方の表面からpn接合を超える深さの溝920を形成する(図6(b)参照。)。
次に、溝920の表面に、電気泳動法により溝920の内面及びその近傍の半導体基体表面に半導体接合保護用ガラス組成物からなる層を形成するとともに、当該半導体接合保護用ガラス組成物からなる層を焼成することにより、パッシベーション用のガラス層924を形成する(図6(c)参照。)。
次に、ガラス層912の表面を覆うようにフォトレジスト926を形成する(図6(d)参照。)。
次に、フォトレジスト926をマスクとして酸化膜916のエッチングを行い、Niめっき電極膜を形成する部位930における酸化膜916を除去する(図7(a)参照。)。
次に、Niめっき電極膜を形成する部位930における半導体基体表面の粗面化処理を行い、Niめっき電極と半導体基体との密着性を高くするための粗面化領域932を形成する(図7(b)参照。)。
次に、半導体基体にNiめっきを行い、粗面化領域932上にアノード電極934を形成するとともに、半導体基体の他方の表面にカソード電極936を形成する(図7(c)参照。)。
次に、ダイシング等により、ガラス層924の中央部において半導体基体を切断して半導体基体をチップ化して、メサ型半導体装置(pnダイオード)を作成する(図7(d)参照。)。
実施形態1は、半導体接合保護用ガラス組成物に係る実施形態である。
実施形態2は、半導体装置の製造方法に係る実施形態である。
実施形態2に係る半導体装置の製造方法は、図1及び図2に示すように、「半導体基体形成工程」、「溝形成工程」、「ガラス層形成工程」、「フォトレジスト形成工程」、「酸化膜除去工程」、「粗面化領域形成工程」、「電極形成工程」及び「半導体基体切断工程」をこの順序で実施する。以下、実施形態2に係る半導体装置の製造方法を工程順に説明する。
まず、n-型半導体基板(n-型シリコン基板)110の一方の表面からのp型不純物の拡散によりp+型拡散層112、他方の表面からのn型不純物の拡散によりn+型拡散層114を形成して、主面に平行なpn接合が形成された半導体基体を形成する。その後、熱酸化によりp+型拡散層112及びn+型拡散層114の表面に酸化膜116,118を形成する(図1(a)参照。)。
次に、フォトエッチング法によって、酸化膜116の所定部位に所定の開口部を形成する。酸化膜のエッチング後、引き続いて半導体基体のエッチングを行い、半導体基体の一方の表面からpn接合を超える深さの溝120を形成する(図1(b)参照。)。
次に、溝120の表面に、電気泳動法により溝120の内面及びその近傍の半導体基体表面に実施形態1に係る半導体接合保護用ガラス組成物からなる層を形成するとともに、当該半導体接合保護用ガラス組成物からなる層を焼成することにより、パッシベーション用のガラス層124を形成する(図1(c)参照。)。従って、溝120の内部におけるpn接合露出部はガラス層124に直接覆われた状態となる。
次に、ガラス層112の表面を覆うようにフォトレジスト126を形成する(図1(d)参照。)。
次に、フォトレジスト126をマスクとして酸化膜116のエッチングを行い、Niめっき電極膜を形成する部位130における酸化膜116を除去する(図2(a)参照。)。
次に、Niめっき電極膜を形成する部位130における半導体基体表面の粗面化処理を行い、Niめっき電極と半導体基体との密着性を高くするための粗面化領域132を形成する(図2(b)参照。)。
次に、半導体基体にNiめっきを行い、粗面化領域132上にアノード電極134を形成するとともに、半導体基体の他方の表面にカソード電極136を形成する(図2(c)参照。)。
次に、ダイシング等により、ガラス層124の中央部において半導体基体を切断して半導体基体をチップ化して、メサ型半導体装置(pnダイオード)を作成する(図2(d)参照。)。
実施形態3は、半導体装置の製造方法に係る実施形態である。
実施形態3に係る半導体装置の製造方法は、図3及び図4に示すように、「半導体基体準備工程」、「p+型拡散層形成工程」、「n+型拡散層形成工程」、「ガラス層形成工程」、「ガラス層エッチング工程」及び「電極形成工程」をこの順序で実施する。以下、実施形態3に係る半導体装置の製造方法を工程順に説明する。
まず、n+型シリコン基板210上にn-型エピタキシャル層212が積層された半導体基体を準備する(図3(a)参照。)。
次に、マスクM1を形成した後、当該マスクM1を介してn-型エピタキシャル層212の表面における所定領域にイオン注入法によりp型不純物(例えばボロンイオン)を導入する。その後、熱拡散することにより、p+型拡散層214を形成する(図3(b参照。)。
次に、マスクM1を除去するとともにマスクM2を形成した後、当該マスクM2を介してn-型エピタキシャル層212の表面における所定領域にイオン注入法によりn型不純物(例えばヒ素イオン)を導入する。その後、熱拡散することにより、n+型拡散層216を形成する(図3(c)参照。)。
次に、マスクM2を除去した後、n-型エピタキシャル層212の表面に、スピンコート法により、実施形態1に係る半導体接合保護用ガラス組成物からなる層を形成し、その後、当該半導体接合保護用ガラス組成物からなる層を焼成することにより、パッシベーション用のガラス層215を形成する(図4(a)参照。)。
次に、ガラス層215の表面にマスクM3を形成した後、ガラス層のエッチングを行う(図4(b)参照。)。これにより、n-型エピタキシャル層212の表面における所定領域にガラス層216が形成されることとなる。
次に、マスクM3を除去した後、半導体基体の表面におけるガラス層216で囲まれた領域にアノード電極218を形成するとともに、半導体基体の裏面にカソード電極220を形成する(図4(c)参照。)。
1.試料の調整
図5は、実施例の結果を示す図表である。実施例1並びに比較例1及び2に示す組成比(図5参照。)になるように原料を調合し、混合機でよく攪拌した後、その混合した原料を電気炉中で1550℃まで上昇させた白金ルツボに入れ、2時間溶融させた。その後、融液を水冷ロールに流し出して薄片状のガラスフレークを得た。このガラスフレークをボールミルで平均粒径が5μmとなるまで粉砕して、粉末状のガラス組成物を得た。
本発明の目的が「鉛を含まないガラス材料を用いて、従来の『珪酸鉛を主成分としたガラス材料』を用いた場合と同様に高耐圧の半導体装置を製造することを可能とする」ことにあるため、鉛成分を含まない場合に「○」の評価を与え、鉛成分を含む場合に「×」の評価を与えた。
焼成温度が高すぎると製造中の半導体装置に与える影響が大きくなるため、焼成温度が900℃以下である場合に「○」の評価を与え、焼成温度が900℃~1000℃の範囲内にある場合に「△」の評価を与え、焼成温度が1000℃を超える場合に「×」の評価を与えた。
ガラス組成物が王水、めっき液及びフッ酸のすべてに対して難溶性を示す場合に「○」の評価を与え、王水、めっき液及びフッ酸のいずれかに対して溶解性を示す場合に「×」の評価を与えた。
50℃~550℃におけるガラス組成物の平均熱膨張率とシリコンの平均熱膨張率(3.73×10-6)との差が「0.5×10-6」以下の場合に「○」の評価を与え、当該差が「0.5×10-6~1.0×10-6」の範囲内にある場合に「△」の評価を与え、当該差が「1.0×10-6」を超える場合に「×」の評価を与えた。
実施形態2に係る半導体装置の製造方法と同様の方法によって半導体装置(pnダイオード)を作製し、作製した半導体装置の逆方向特性を測定した。その結果、半導体装置の逆方向特性が正常である場合に「○」の評価を与え、半導体装置の逆方向特性が異常である場合に「×」の評価を与えた。
上記した評価方法1~5についての各評価がすべて「○」の場合に「○」の評価を与え、各評価のうち1つでも「△」がある場合に「△」の評価を与え、各評価のうち1つでも「×」がある場合に「×」の評価を与えた。
図5からも分かるように、比較例1に係るガラス組成物は、評価項目1で「×」の評価が得られた。また、比較例2に係るガラス組成物は、評価項目3で「×」の評価が得られた。これに対して、実施例1に係るガラス組成物は、いずれの評価項目(評価項目1~5)についても「○」の評価が得られた。その結果、実施形1に係るガラス組成物は、鉛を含まないガラス材料でありながら、(a)適正な温度(例えば900℃以下)で焼成できること、(b)工程で使用する薬品に耐えること、(c)シリコンに近い熱膨張係数を有すること(特に50℃~500℃における平均熱膨張率がシリコンに近いこと)及び(d)優れた絶縁性を有することという条件をすべて満たすガラス組成物であることが分かった。
Claims (12)
- 少なくともSiO2と、Al2O3と、ZnOと、CaOと、3mol%~10mol%のB2O3とを含有し、かつ、Pbと、Pと、Asと、Sbと、Liと、Naと、Kとを実質的に含有しないことを特徴とする半導体接合保護用ガラス組成物。
- SiO2の含有量が32mol%~48mol%の範囲内にあり、
Al2O3の含有量が9mol%~13mol%の範囲内にあり、
ZnOの含有量が18mol%~28mol%の範囲内にあり、
CaOの含有量が15mol%~23mol%の範囲内にあり、
B2O3の含有量が3mol%~10mol%の範囲内にあることを特徴とする請求項1に記載の半導体接合保護用ガラス組成物。 - pn接合が露出するpn接合露出部を有する半導体素子を準備する第1工程と、
前記pn接合露出部を覆うようにガラス層を形成する第2工程とをこの順序で含む半導体装置の製造方法であって、
前記第2工程においては、少なくともSiO2と、Al2O3と、ZnOと、CaOと、3mol%~10mol%のB2O3とを含有し、かつ、Pbと、Pと、Asと、Sbと、Liと、Naと、Kとを実質的に含有しない半導体接合保護用ガラス組成物を用いて前記ガラス層を形成することを特徴とする半導体装置の製造方法。 - 前記第1工程は、主面に平行なpn接合を備える半導体基体を準備する工程と、前記半導体基体の一方の表面から前記pn接合を超える深さの溝を形成することにより、前記溝の内部に前記pn接合露出部を形成する工程とを含み、
前記第2工程は、前記溝の内部における前記pn接合露出部を覆うように前記ガラス層を形成する工程を含むことを特徴とする請求項3に記載の半導体装置の製造方法。 - 前記第2工程は、前記溝の内部における前記pn接合露出部を直接覆うように前記ガラス層を形成する工程を含むことを特徴とする請求項4に記載の半導体装置の製造方法。
- 前記第2工程は、前記溝の内部における前記pn接合露出部上に絶縁膜を形成する工程と、前記絶縁膜を介して前記pn接合露出部を覆うように前記ガラス層を形成する工程とを含むことを特徴とする請求項4に記載の半導体装置の製造方法。
- 前記第1工程は、半導体基体の表面に前記pn接合露出部を形成する工程を含み、
前記第2工程は、前記半導体基体の表面における前記pn接合露出部を覆うように前記ガラス層を形成する工程を含むことを特徴とする請求項3に記載の半導体装置の製造方法。 - 前記第2工程は、前記半導体基体の表面における前記pn接合露出部を直接覆うように前記ガラス層を形成する工程を含むことを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記第2工程は、前記半導体基体の表面における前記pn接合露出部上に絶縁膜を形成する工程と、前記絶縁膜を介して前記pn接合露出部を覆うように前記ガラス層を形成する工程とを含むことを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記半導体接合保護用ガラス組成物は、
SiO2の含有量が32mol%~48mol%の範囲内にあり、
Al2O3の含有量が9mol%~13mol%の範囲内にあり、
ZnOの含有量が18mol%~28mol%の範囲内にあり、
CaOの含有量が15mol%~23mol%の範囲内にあり、
B2O3の含有量が3mol%~10mol%の範囲内にあることをを特徴とする請求項3~9のいずれかに記載の半導体装置の製造方法。 - pn接合が露出するpn接合露出部を有する半導体素子と、
前記pn接合露出部を覆うように形成されたガラス層とを備える半導体装置であって、
前記ガラス層は、少なくともSiO2と、Al2O3と、ZnOと、CaOと、3mol%~10mol%のB2O3とを含有し、かつ、Pbと、Pと、Asと、Sbと、Liと、Naと、Kとを実質的に含有しない半導体接合保護用ガラス組成物を用いて形成されたものであることを特徴とする半導体装置。 - 前記半導体接合保護用ガラス組成物は、
SiO2の含有量が32mol%~48mol%の範囲内にあり、
Al2O3の含有量が9mol%~13mol%の範囲内にあり、
ZnOの含有量が18mol%~28mol%の範囲内にあり、
CaOの含有量が15mol%~23mol%の範囲内にあり、
B2O3の含有量が3mol%~10mol%の範囲内にあることを特徴とする請求項11に記載の半導体装置。
Priority Applications (11)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201180004599.0A CN102781861B (zh) | 2011-05-26 | 2011-05-26 | 半导体接合保护用玻璃合成物、半导体装置及其制造方法 |
EP11857966.3A EP2717299B1 (en) | 2011-05-26 | 2011-05-26 | Glass composition for semiconductor junction protection, production method for semiconductor device, and semiconductor device |
PCT/JP2011/062134 WO2012160704A1 (ja) | 2011-05-26 | 2011-05-26 | 半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置 |
JP2011546466A JP4927237B1 (ja) | 2011-05-26 | 2011-05-26 | 半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置 |
US13/582,215 US9159549B2 (en) | 2011-05-26 | 2011-05-26 | Glass composition for protecting semiconductor junction, method of manufacturing semiconductor device and semiconductor device |
JP2013516273A JP5655139B2 (ja) | 2011-05-23 | 2012-05-08 | 半導体装置の製造方法及び半導体装置 |
JP2013516274A JP5655140B2 (ja) | 2011-05-23 | 2012-05-08 | 半導体装置の製造方法及び半導体装置 |
PCT/JP2012/061780 WO2012160962A1 (ja) | 2011-05-23 | 2012-05-08 | 半導体装置の製造方法及び半導体装置 |
PCT/JP2012/061779 WO2012160961A1 (ja) | 2011-05-23 | 2012-05-08 | 半導体装置の製造方法及び半導体装置 |
TW101118618A TWI424472B (zh) | 2011-05-26 | 2012-05-25 | Method for fabricating glass for semiconductor bonding, method for manufacturing semiconductor device, and semiconductor device |
US13/980,435 US9941112B2 (en) | 2011-05-26 | 2012-11-28 | Method of manufacturing semiconductor device and semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2011/062134 WO2012160704A1 (ja) | 2011-05-26 | 2011-05-26 | 半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2012160704A1 true WO2012160704A1 (ja) | 2012-11-29 |
Family
ID=46261513
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2011/062134 WO2012160704A1 (ja) | 2011-05-23 | 2011-05-26 | 半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置 |
Country Status (6)
Country | Link |
---|---|
US (2) | US9159549B2 (ja) |
EP (1) | EP2717299B1 (ja) |
JP (1) | JP4927237B1 (ja) |
CN (1) | CN102781861B (ja) |
TW (1) | TWI424472B (ja) |
WO (1) | WO2012160704A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2016067477A1 (ja) * | 2014-10-31 | 2017-06-01 | 新電元工業株式会社 | 半導体装置の製造方法及びレジストガラス |
JP2020055724A (ja) * | 2018-10-04 | 2020-04-09 | 日本電気硝子株式会社 | 半導体素子被覆用ガラス及びこれを用いた半導体被覆用材料 |
WO2021060001A1 (ja) * | 2019-09-24 | 2021-04-01 | 日本電気硝子株式会社 | 半導体素子被覆用ガラス及びこれを用いた半導体被覆用材料 |
WO2024101356A1 (ja) * | 2022-11-09 | 2024-05-16 | 日本電気硝子株式会社 | ガラス |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5508547B1 (ja) | 2012-05-08 | 2014-06-04 | 新電元工業株式会社 | 半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置 |
JP5827397B2 (ja) * | 2012-05-08 | 2015-12-02 | 新電元工業株式会社 | 樹脂封止型半導体装置及び樹脂封止型半導体装置の製造方法 |
JP5848821B2 (ja) * | 2012-05-08 | 2016-01-27 | 新電元工業株式会社 | 半導体接合保護用ガラス組成物、半導体装置の製造方法、半導体装置及び半導体接合保護用ガラス組成物の製造方法 |
JP5631497B1 (ja) * | 2013-03-29 | 2014-11-26 | 新電元工業株式会社 | 半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置 |
WO2016075787A1 (ja) | 2014-11-13 | 2016-05-19 | 新電元工業株式会社 | 半導体装置の製造方法及びガラス被膜形成装置 |
CN109121423B (zh) * | 2017-04-19 | 2020-05-19 | 新电元工业株式会社 | 半导体装置的制造方法 |
JP7218531B2 (ja) * | 2018-10-04 | 2023-02-07 | 日本電気硝子株式会社 | 半導体素子被覆用ガラス及びこれを用いた半導体被覆用材料 |
US11677023B2 (en) * | 2021-05-04 | 2023-06-13 | Infineon Technologies Austria Ag | Semiconductor device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5645055A (en) * | 1979-09-21 | 1981-04-24 | Toshiba Corp | Semiconductor device |
JPS57202742A (en) * | 1981-06-09 | 1982-12-11 | Toshiba Corp | Glass for semiconductor coating |
JP2004087955A (ja) | 2002-08-28 | 2004-03-18 | Shindengen Electric Mfg Co Ltd | 半導体装置の製造方法及び半導体装置 |
JP2006221942A (ja) * | 2005-02-10 | 2006-08-24 | Nippon Electric Glass Co Ltd | プラズマディスプレイパネル基板作製用ガラスセット |
JP2009203154A (ja) * | 2008-01-31 | 2009-09-10 | Ohara Inc | ガラス |
Family Cites Families (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1180908A (en) | 1966-11-17 | 1970-02-11 | English Electric Co Ltd | Improvements in or relating to processes for Forming an Insulating Coating on Silicon, and to Coated Silicon |
JPS5240071A (en) * | 1975-09-26 | 1977-03-28 | Hitachi Ltd | Semiconductor device |
DE2730130C2 (de) | 1976-09-14 | 1987-11-12 | Mitsubishi Denki K.K., Tokyo | Verfahren zum Herstellen von Halbleiterbauelementen |
JPS5951137B2 (ja) | 1976-09-16 | 1984-12-12 | 三菱電機株式会社 | 半導体装置の製造方法 |
JPS5393783A (en) | 1977-01-26 | 1978-08-17 | Nec Home Electronics Ltd | Mesa type semiconductor device |
JPS5526656A (en) | 1978-08-17 | 1980-02-26 | Hitachi Ltd | Semiconductor element coverd with glass |
FR2458144A1 (fr) * | 1979-05-29 | 1980-12-26 | Thomson Csf | Structure de passivation d'un affleurement de jonction semi-conductrice et son procede de fabrication |
FR2487576A1 (fr) * | 1980-07-24 | 1982-01-29 | Thomson Csf | Procede de fabrication de diodes mesa glassivees |
DE3247938A1 (de) * | 1982-12-24 | 1984-07-05 | SEMIKRON Gesellschaft für Gleichrichterbau u. Elektronik mbH, 8500 Nürnberg | Halbleiterbauelement hoher sperrspannungsbelastbarkeit |
JPS59174544A (ja) * | 1983-03-25 | 1984-10-03 | Nippon Electric Glass Co Ltd | 半導体被覆用ガラス |
US4714687A (en) * | 1986-10-27 | 1987-12-22 | Corning Glass Works | Glass-ceramics suitable for dielectric substrates |
US5298330A (en) * | 1987-08-31 | 1994-03-29 | Ferro Corporation | Thick film paste compositions for use with an aluminum nitride substrate |
JPH0186629U (ja) | 1987-11-30 | 1989-06-08 | ||
JPH02163938A (ja) | 1988-12-16 | 1990-06-25 | Fuji Electric Co Ltd | 半導体素子の製造方法 |
US5047369A (en) | 1989-05-01 | 1991-09-10 | At&T Bell Laboratories | Fabrication of semiconductor devices using phosphosilicate glasses |
DE4124515A1 (de) | 1991-07-24 | 1993-01-28 | Vdo Schindling | Verfahren zum ueberwachen und verstellanordnung fuer die betaetigung eines verstellorgans einer steuerung einer verbrennungskraftmaschine |
US5433794A (en) * | 1992-12-10 | 1995-07-18 | Micron Technology, Inc. | Spacers used to form isolation trenches with improved corners |
US5652176A (en) * | 1995-02-24 | 1997-07-29 | Motorola, Inc. | Method for providing trench isolation and borderless contact |
JP3339549B2 (ja) * | 1996-10-14 | 2002-10-28 | 株式会社日立製作所 | ガラス被覆半導体装置及びその製造方法 |
JP3780061B2 (ja) | 1997-04-17 | 2006-05-31 | 株式会社日立製作所 | 面実装型半導体装置 |
JPH1186629A (ja) | 1997-09-12 | 1999-03-30 | Mitsubishi Electric Corp | イオン伝導性材料、その製造方法およびそれを用いた電池 |
US5998037A (en) * | 1997-12-22 | 1999-12-07 | Ferro Corporation | Porcelain enamel composition for electronic applications |
US6171987B1 (en) | 1997-12-29 | 2001-01-09 | Ben-Gurion University Of The Negev | Cadmium-free and lead-free glass compositions, thick film formulations containing them and uses thereof |
US6214699B1 (en) * | 1998-04-01 | 2001-04-10 | Texas Instruments Incorporated | Method for forming an isolation structure in a substrate |
US6620996B2 (en) | 2000-05-29 | 2003-09-16 | Kyocera Corporation | Photoelectric conversion device |
JP2002016272A (ja) | 2000-06-30 | 2002-01-18 | Kyocera Corp | 光電変換装置 |
JP3943341B2 (ja) * | 2001-02-23 | 2007-07-11 | 日本電気硝子株式会社 | ガラスセラミックス組成物 |
US7740899B2 (en) | 2002-05-15 | 2010-06-22 | Ferro Corporation | Electronic device having lead and cadmium free electronic overglaze applied thereto |
JP4299021B2 (ja) * | 2003-02-19 | 2009-07-22 | ヤマト電子株式会社 | 封着加工材及び封着加工用ペースト |
CN100368340C (zh) * | 2003-04-21 | 2008-02-13 | 旭硝子株式会社 | 制电介质用无铅玻璃、制电介质用玻璃陶瓷组合物、电介质及层积电介质的制造方法 |
US7030048B2 (en) * | 2003-08-05 | 2006-04-18 | E. I. Du Pont De Nemours And Company | Thick film dielectric compositions for use on aluminum nitride substrates |
JP4736342B2 (ja) | 2004-04-09 | 2011-07-27 | 株式会社村田製作所 | ガラスセラミック原料組成物、ガラスセラミック焼結体およびガラスセラミック多層基板 |
JP2006253669A (ja) | 2005-02-09 | 2006-09-21 | Ngk Spark Plug Co Ltd | 配線基板 |
TWI414218B (zh) | 2005-02-09 | 2013-11-01 | Ngk Spark Plug Co | 配線基板及配線基板內建用之電容器 |
JP2006221941A (ja) * | 2005-02-09 | 2006-08-24 | Nissin Ion Equipment Co Ltd | イオン注入装置およびイオン注入方法 |
JP4697397B2 (ja) | 2005-02-16 | 2011-06-08 | サンケン電気株式会社 | 複合半導体装置 |
WO2007023708A1 (ja) * | 2005-08-25 | 2007-03-01 | Asahi Glass Company, Limited | 膜付き基体および膜形成用ガラス |
US20070154713A1 (en) * | 2005-12-30 | 2007-07-05 | 3M Innovative Properties Company | Ceramic cutting tools and cutting tool inserts, and methods of making the same |
DE102006023115A1 (de) | 2006-05-16 | 2007-11-22 | Schott Ag | Backlightsystem mit IR-Absorptionseigenschaften |
DE102006062428B4 (de) | 2006-12-27 | 2012-10-18 | Schott Ag | Verfahren zur Herstellung eines mit einem bleifreien Glas passiviertenelektronischen Bauelements sowie elektronisches Bauelement mit aufgebrachtem bleifreien Glas und dessen Verwendung |
GB2464052A (en) * | 2007-08-01 | 2010-04-07 | Asahi Glass Co Ltd | Lead-free glass |
JP5128203B2 (ja) | 2007-08-22 | 2013-01-23 | 日本山村硝子株式会社 | 封着用ガラス組成物 |
TW200933899A (en) * | 2008-01-29 | 2009-08-01 | Sanyo Electric Co | Mesa type semiconductor device and method for making the same |
JP5138401B2 (ja) * | 2008-01-30 | 2013-02-06 | Hoya株式会社 | 光学ガラス、プレス成形用ガラスゴブおよび光学素子とその製造方法ならびに光学素子ブランクの製造方法 |
EP2448007A4 (en) | 2009-06-25 | 2012-11-28 | Mitsubishi Electric Corp | DISTRIBUTION BOX FOR A SOLAR CELL MODULE |
JP5526656B2 (ja) | 2009-08-25 | 2014-06-18 | 株式会社Ihi | 防護装置及び燃焼試験設備 |
JP2011060857A (ja) | 2009-09-07 | 2011-03-24 | Hitachi Maxell Ltd | 集光型光発電モジュール及び集光型光発電モジュールの製造方法 |
WO2011093177A1 (ja) * | 2010-01-28 | 2011-08-04 | 日本電気硝子株式会社 | 半導体被覆用ガラスおよびそれを用いてなる半導体被覆用材料 |
TW201143152A (en) * | 2010-03-31 | 2011-12-01 | Asahi Glass Co Ltd | Substrate for light-emitting element and light-emitting device employing it |
CN103189990A (zh) | 2011-10-28 | 2013-07-03 | 松下电器产业株式会社 | 薄膜半导体器件及其制造方法 |
JP2015511205A (ja) * | 2011-12-22 | 2015-04-16 | ヘレウス プレシャス メタルズ ノース アメリカ コンショホーケン エルエルシー | 低抵抗接点の太陽電池ペースト |
JP5184717B1 (ja) | 2012-01-31 | 2013-04-17 | 新電元工業株式会社 | 半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置 |
JP5827397B2 (ja) | 2012-05-08 | 2015-12-02 | 新電元工業株式会社 | 樹脂封止型半導体装置及び樹脂封止型半導体装置の製造方法 |
CN103890919B (zh) | 2012-05-08 | 2016-07-06 | 新电元工业株式会社 | 半导体接合保护用玻璃复合物、半导体装置的制造方法以及半导体装置 |
-
2011
- 2011-05-26 CN CN201180004599.0A patent/CN102781861B/zh active Active
- 2011-05-26 WO PCT/JP2011/062134 patent/WO2012160704A1/ja active Application Filing
- 2011-05-26 US US13/582,215 patent/US9159549B2/en active Active
- 2011-05-26 JP JP2011546466A patent/JP4927237B1/ja active Active
- 2011-05-26 EP EP11857966.3A patent/EP2717299B1/en active Active
-
2012
- 2012-05-25 TW TW101118618A patent/TWI424472B/zh active
- 2012-11-28 US US13/980,435 patent/US9941112B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5645055A (en) * | 1979-09-21 | 1981-04-24 | Toshiba Corp | Semiconductor device |
JPS57202742A (en) * | 1981-06-09 | 1982-12-11 | Toshiba Corp | Glass for semiconductor coating |
JP2004087955A (ja) | 2002-08-28 | 2004-03-18 | Shindengen Electric Mfg Co Ltd | 半導体装置の製造方法及び半導体装置 |
JP2006221942A (ja) * | 2005-02-10 | 2006-08-24 | Nippon Electric Glass Co Ltd | プラズマディスプレイパネル基板作製用ガラスセット |
JP2009203154A (ja) * | 2008-01-31 | 2009-09-10 | Ohara Inc | ガラス |
Non-Patent Citations (1)
Title |
---|
See also references of EP2717299A4 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2016067477A1 (ja) * | 2014-10-31 | 2017-06-01 | 新電元工業株式会社 | 半導体装置の製造方法及びレジストガラス |
JP2020055724A (ja) * | 2018-10-04 | 2020-04-09 | 日本電気硝子株式会社 | 半導体素子被覆用ガラス及びこれを用いた半導体被覆用材料 |
WO2020071093A1 (ja) * | 2018-10-04 | 2020-04-09 | 日本電気硝子株式会社 | 半導体素子被覆用ガラス及びこれを用いた半導体被覆用材料 |
JP7185181B2 (ja) | 2018-10-04 | 2022-12-07 | 日本電気硝子株式会社 | 半導体素子被覆用ガラス及びこれを用いた半導体被覆用材料 |
WO2021060001A1 (ja) * | 2019-09-24 | 2021-04-01 | 日本電気硝子株式会社 | 半導体素子被覆用ガラス及びこれを用いた半導体被覆用材料 |
CN114450257A (zh) * | 2019-09-24 | 2022-05-06 | 日本电气硝子株式会社 | 半导体元件包覆用玻璃及使用该玻璃的半导体包覆用材料 |
WO2024101356A1 (ja) * | 2022-11-09 | 2024-05-16 | 日本電気硝子株式会社 | ガラス |
Also Published As
Publication number | Publication date |
---|---|
JPWO2012160704A1 (ja) | 2014-07-31 |
US9941112B2 (en) | 2018-04-10 |
US20130075873A1 (en) | 2013-03-28 |
US20140312472A1 (en) | 2014-10-23 |
CN102781861B (zh) | 2016-07-06 |
US9159549B2 (en) | 2015-10-13 |
CN102781861A (zh) | 2012-11-14 |
EP2717299B1 (en) | 2016-07-27 |
EP2717299A1 (en) | 2014-04-09 |
TW201248687A (en) | 2012-12-01 |
EP2717299A4 (en) | 2015-04-08 |
TWI424472B (zh) | 2014-01-21 |
JP4927237B1 (ja) | 2012-05-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4927237B1 (ja) | 半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置 | |
JP5548276B2 (ja) | 半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置 | |
JP5827398B2 (ja) | 半導体接合保護用ガラス組成物の製造方法、半導体装置の製造方法及び半導体装置 | |
WO2013168314A1 (ja) | 半導体装置の製造方法及び半導体装置 | |
JP5184717B1 (ja) | 半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置 | |
JP5508547B1 (ja) | 半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置 | |
WO2012160962A1 (ja) | 半導体装置の製造方法及び半導体装置 | |
JP4993399B1 (ja) | 半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置 | |
JP5833112B2 (ja) | ガラス組成物の製造方法 | |
JP5139596B2 (ja) | 半導体接合保護用ガラス組成物、半導体装置の製造方法及び半導体装置 | |
JP5655140B2 (ja) | 半導体装置の製造方法及び半導体装置 | |
JP5848821B2 (ja) | 半導体接合保護用ガラス組成物、半導体装置の製造方法、半導体装置及び半導体接合保護用ガラス組成物の製造方法 | |
JP5655139B2 (ja) | 半導体装置の製造方法及び半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 201180004599.0 Country of ref document: CN |
|
ENP | Entry into the national phase |
Ref document number: 2011546466 Country of ref document: JP Kind code of ref document: A |
|
REEP | Request for entry into the european phase |
Ref document number: 2011857966 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2011857966 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13582215 Country of ref document: US |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 11857966 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |