WO2011071954A1 - Configurable digital-analog phase locked loop - Google Patents

Configurable digital-analog phase locked loop Download PDF

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Publication number
WO2011071954A1
WO2011071954A1 PCT/US2010/059338 US2010059338W WO2011071954A1 WO 2011071954 A1 WO2011071954 A1 WO 2011071954A1 US 2010059338 W US2010059338 W US 2010059338W WO 2011071954 A1 WO2011071954 A1 WO 2011071954A1
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WO
WIPO (PCT)
Prior art keywords
digital
analog loop
filter
analog
pll device
Prior art date
Application number
PCT/US2010/059338
Other languages
English (en)
French (fr)
Inventor
Jeremy D. Dunworth
Gary J. Ballantyne
Bhushan S. Asuri
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Priority to KR1020127017816A priority Critical patent/KR101470938B1/ko
Priority to CN201080055240.1A priority patent/CN102648581B/zh
Priority to EP10795515.5A priority patent/EP2510621B1/en
Priority to JP2012543215A priority patent/JP5661793B2/ja
Publication of WO2011071954A1 publication Critical patent/WO2011071954A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop

Definitions

  • the present invention relates generally to phase locked loops, and more specifically to hybrid analog-digital phase locked loops.
  • Phase-locked loops generate signals relative to a reference signal.
  • the phase- locked loop circuit adjusts a frequency of a PLL output signal based on differences in phase and/or frequency of the reference signal and the output signal. The frequency of the output signal is increased or decreased based on the difference.
  • the phase-locked loop is, therefore, a control system using negative feedback.
  • Phase-locked loops are used in electronics such as radios, telecommunication circuits, and computers as well as other devices.
  • PLLs often use a resonant-tuned voltage controlled oscillator (VCO) to generate the PLL output signal.
  • VCO voltage controlled oscillator
  • a resonant tuned VCO often includes a capacitive device and a resonant inductor-capacitor (LC) circuit.
  • the capacitive device typically includes at least one varactor having a capacitance that responds to a tuning voltage to change the frequency of the PLL output signal.
  • Some conventional PLL include one more digital components. Such PLLs have advantages over analog loops in some respects. Unfortunately, these PLLs also have some disadvantages. Accordingly, there is need for a PLL that has advantages of both analog and digital loops
  • a phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop.
  • PLL phase locked loop
  • In an analog mode at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop.
  • In a digital mode at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.
  • VCO voltage controlled oscillator
  • TDC time to digital converter
  • DAC digital to analog converter
  • FIG. 1 is a block diagram of a hybrid analog-digital phase locked loop device (PLL device) in accordance with an exemplary embodiment of the invention.
  • PLL device phase locked loop device
  • FIG. 2 is a block diagram of the PLL device where the switching mechanism configures filter elements to form an integrator during the digital mode.
  • FIG. 3 is schematic illustration of a switching mechanism connected to the charge pump and the current DAC where the switching element is a transistor.
  • FIG. 4 is a schematic diagram of the analog loop filter formed when the switching mechanism is in the analog mode.
  • FIG. 5 is a graphical representation of the filter response of the exemplary loop filter in a complex plane.
  • FIG. 6 is a schematic diagram of the integrator formed when the switching mechanism is in the digital mode.
  • FIG. 7 is a block diagram of a dual mode PLL with two point modulation having a lower frequency port in the reference path.
  • FIG. 8 is block diagram of a dual mode PLL with two point modulation having a lower frequency port in the feedback path.
  • FIG. 9 is a block diagram of a dual mode PLL with two point modulation having a lower frequency port using delta signal modulation in the feedback path.
  • FIG. 10 is a flow chart of a method of managing a PLL device in accordance with the exemplary embodiment of the invention.
  • FIG. 1 1 is a flow chart of method of configuring the PLL device in the analog mode.
  • FIG. 12 is a flow chart of method of configuring the PLL device in the digital mode.
  • FIG. 13 is a schematic representation of a current steering DAC with a current source output stage.
  • FIG. 14 is a schematic representation of a current steering DAC with a current source output stage in accordance with another configuration.
  • FIG. 15 is a schematic representation of exemplary current pulse DAC with a current source output stage.
  • FIG. 1 is a block diagram of a configurable analog-digital phase locked loop device (PLL device) 100 in accordance with an exemplary embodiment of the invention.
  • PLL device phase locked loop device
  • the functional blocks discussed with reference to FIG. 1 may be implemented using any suitable combination of devices, circuits and/or code. Accordingly, the functions of the blocks may be implemented in hardware, software and/or firmware. The functions of several blocks may be performed by a single circuit or device and functions described as performed by a single block may be performed by several devices or circuits.
  • the PLL device includes a switching mechanism 102 that configures the PLL device 100 into an analog PLL or into a hybrid digital-analog PLL that includes digital as well as analog signals and components.
  • the PLL device 100 is configured in the PLL loop that includes at least a phase detector 104, analog loop filter 106, voltage controlled oscillator (VCO) 108 and feedback 110.
  • the PLL device 100 is configured in the hybrid digital-analog loop to include at least a phase to digital converter (PDC) 112, a digital loop filter 1 14, a digital to analog converter (DAC) 1 16, the VCO 108 and the feedback 1 10.
  • PDC phase to digital converter
  • DAC digital to analog converter
  • a detector 1 17 includes the phase detector 104 and the PDC 112 where the PDC 112 is formed by the phase detector 104 and a time to digital converter (TDC) 1 18.
  • the correction signal 120 generated by the detector 1 17 is an analog signal including an up signal 122 and a down signal 124 in the analog mode.
  • a digital correction signal 126 is provided by the detector 1 12.
  • the analog up and down signals 122, 124 of the analog correction signal 120 is converted to a digital number by the TDC 118 to form the digital correction signal 126.
  • Other methods can be used by the detector 1 17 to provide a digital correction signal 126 in some circumstances.
  • the phase detector 104 generates the up signal 122 and the down signal 124 in accordance with the phase difference between a reference signal 128 and feedback signal 130 provided by the feedback 108.
  • a charge pump 132 generates an analog loop signal 134 based on the up and down signals 122, 124 when the PLL device 100 is in the analog mode.
  • the charge pump 132 and the analog loop filter 106 are illustrated with blocks having dashed lines to indicate that these blocks are not used in the digital mode. In the analog mode, the TDC 118, digital filter 1 14, and DAC 116 are not used.
  • the switching mechanism 102 is responsive to a control signal 136 to configure the PLL device 100 into either the partially digital loop (hybrid digital-analog loop) or the analog loop.
  • the switching mechanism 102 includes at least one switching element that enables a loop path through the analog loop filter 106 during the analog mode and enables a loop path including the digital loop filter 114 and DAC 116 during the digital mode.
  • the control signal 136 may be single signal that changes values or the cotnjrol signal may include multiple signals.
  • the switching mechanism 102 powers down, disconnects, and/or otherwise disables the TDC 118 and/or DAC 1 16 in the analog mode.
  • An example of a suitable technique for disabling the DAC 116 includes withdrawing or otherwise switching off the current reference signal (IREF discussed below in FIG. 13, FIG, 14 and FIG. 15) and set transistors and switches to an open or high impedance state. In some circumstances, other components may be disabled or disconnected from power during either the digital or analog mode.
  • IPF current reference signal
  • the phase detector 104 During the analog mode, the phase detector 104 generates the up and down signals 122, 124 which causes the charge pump 132 to generate the analog loop signal 134.
  • the analog loop filter 106 filters the analog loop signal 134 to provide a VCO control signal 138 to the VCO 108.
  • the VCO control signal 138 adjusts the frequency of a VCO output signal 140.
  • the VCO output signal 140 is fed back to the phase detector 116 through the feedback 1 10.
  • the feedback 1 10 may alter the VCO output signal 140 by dividing, scaling, or otherwise processing the VCO output signal 140 to generate the feedback signal 130.
  • the feedback may have a different configuration in the analog mode from the digital mode depending on the particular circumstances. For example, a divider ratio in the feedback may be changed between modes where the reference frequency changes and/or the VCO operating frequency changes when the PLL is switched from one mode to the other.
  • FIG. 2 is a block diagram of the PLL device 100 where the switching mechanism 102 includes a switching element 200 that connects filter elements 202, 204, 206 to form an integrator 208 during the digital mode.
  • the DAC 116 is a current DAC that includes a current source output stage 210.
  • suitable current DACs include current steering DACs and current pulse DACs. The discussion below with reference to FIG. 13, FIG. 14 and FIG. 15 describes examples of current DACs.
  • the current source output stage 210 provides an analog current signal 212.
  • the integrator 208 integrates the current signal 212 to provide a VCO control voltage signal 138 to the VCO 108.
  • the analog loop filter 106 includes at least one filter element 206 that is configured as the integrator 208 during the digital mode. During the analog mode, the filter element 206 is connected to the other filter elements 202, 204 to form the analog loop filter 106. As discussed below, for example, a capacitor forming part of the analog loop filter 106 can be connected to the output of the DAC 116 and to ground to form the integrator 208 during the digital mode.
  • the analog loop filter 106 has a frequency response selected in accordance with the particular requirements of the PLL device 100 when in the analog mode.
  • An example of a suitable response includes having a first pole at the origin, a zero at a first frequency and a second pole at a second frequency greater than the first frequency when represented by pole-zero plot in a complex plane.
  • the feedback 208 in the example of FIG. 2 includes a fractional N divider 214 that divides the VCO output signal by a number to generate the appropriately divided feedback signal 130 to the detector.
  • the feedback does not necessarily change between modes but there are circumstances where the divider ratio may be changed to accommodate a change in VCO frequency or reference signal frequency.
  • the switching mechanism 102 is responsive to the control signal 136 generated by a controller 216 in the example of FIG. 2.
  • the controller 216 is any combination of hardware, logic and/or code that determines when to configure the PLL into the digital mode and the analog mode and that can generate the control signal 136 having a first value in the digital mode and a second value in the analog mode.
  • the control signal 136 may include multiple signals in some circumstances. Accordingly, the terms "first control signal value" and "second control signal value” at least include two values of a single control signal and values of two different control signals.
  • the controller 216 may be a processor, microprocessor, or processor arrangement that performs the functions of managing the PLL device 100.
  • FIG. 3 is schematic illustration of a switching mechanism 102 connected to the charge pump 132 and the current DAC 116 where switching element 200 is a transistor 300.
  • the transistor 300 is connected to the filter elements 202, 204, 206 where the filter elements include a resistor 302, a first capacitor 304 and a second capacitor 306.
  • the transistor 300 is an N-Channel field effect transistor (FET).
  • FET N-Channel field effect transistor
  • Other types of transistors can be used in accordance with known techniques.
  • the control signal 136 provides a bias at the gate of the FET 300 where one control signal value causes the FET 300 to from a connection to ground 308 to bypass the resistor 302 and a second control signal value results in a high impedance (i.e. open circuit).
  • the high impedance results in a circuit that includes the first capacitor 304 connected through the resistor 302 to ground 308. Accordingly, one control signal value connects the filter elements to form the analog loop filter 106 and the other control signal value connects the filter elements to form an integrator 208.
  • the two formed circuits are discussed below with reference to FIG. 4 and FIG. 6.
  • the FET series resistance when the control signal provides a bias at the gate of the FET to form a connection to ground is relatively small compared to the resistor and is equal to or smaller than the series resistance inherent in the capacitor.
  • FIG. 4 is a schematic diagram of the analog loop filter 106 formed when the switching mechanism 102 configures the PLL device 100 in the analog loop. Any number of filter elements and configurations can be used for the analog loop filter 106.
  • the analog loop filter 106 includes the two capacitors 304, 306 and the resistor 302 to form a filter response that can be represented in a complex plane as having two poles and a zero.
  • FIG. 5 is a graphical representation 500 of the filter response of the exemplary loop filter in a complex plane.
  • the filter response includes a first pole 502 at the origin, a zero 504 at a first frequency, and a second pole 506 at a second frequency higher than the first frequency.
  • FIG. 6 is a schematic diagram of the integrator 208 formed when the switching mechanism 102 configures the PLL device 100 in the hybrid digital-analog loop.
  • the first capacitor 304 and the second capacitor 306 are connected in parallel to provide a parallel capacitance which forms the integrator 208.
  • the capacitors 304, 306 integrate the current signal 212 provided by the current DAC to form the VCO control signal 138.
  • FIG. 7 is a block diagram of a configurable PLL device 100 with two point modulation having a lower frequency port 702 in the reference path.
  • the PLL device 100 is switchable between the digital mode and analog mode as described above.
  • two point modulation can be used to modulate the VCO output signal 140.
  • a two point modulation port 700 includes a lower frequency port 702 and an upper frequency port 704 where the lower frequency port 702 provides modulation by data signal components having lower frequencies than the frequencies of data signal components used for modulation through the upper frequency port 704.
  • the lower frequency port 702 is within the reference signal path.
  • the data signal input data signal 706 is combined with the reference signal prior to the phase detector.
  • the data signal 706 may be combined with the reference signal 128 using any known technique.
  • An example of suitable technique for combining the signals includes using a mixer, or a modulator, to mix or modulate the reference signal with the data signal. Other techniques may be used to combine signals. In circumstances, the signal may be combined using a summer, for example.
  • the upper frequency port 704 combines the input data 706 with the digital filter output signal 708 provided by the digital loop filter 1 14. The two signals are combined by a summer 710 in the exemplary embodiment.
  • the data signal 706 may be processed before injection into the lower frequency port 702 and/or the upper frequency port 704.
  • FIG. 8 is block diagram of a dual mode PLL with two point modulation having a lower frequency port 802 in the feedback path.
  • the PLL device 100 is switchable between the digital mode and analog mode as described above.
  • two point modulation can be used to modulate the VCO output signal 140.
  • a two point modulation port includes an upper frequency port 704 and a lower frequency port 802 where the lower frequency port 802 provides modulation by data signal components having lower frequencies than the frequencies of data signal components used for modulation through the upper frequency port 704.
  • the lower frequency port 802 is within the feedback path.
  • the data signal 706 is used to alter the feedback signal 130.
  • An example of suitable technique for implementing the lower frequency port 802 includes using a sigma-delta modulator. An example of such an implementation is discussed in further detail with reference to FIG. 9.
  • the upper frequency port 704 combines the input data 706 with the digital filter output signal 708 provided by the digital loop filter 1 14.
  • the two signals are combined by a summer 710 in the exemplary embodiment.
  • the data signal 706 may be processed before injection into the lower frequency port 802 and/or the upper frequency port 704.
  • FIG. 9 is a block diagram of a PLL device 900 in accordance with the exemplary embodiment including two point modulation having a sigma delta modulation lower frequency port 902 in the feedback 110 path.
  • the input phase data 706 is applied to two points in the PLL creating an all pass transfer function from input phase data to modulation VCO output.
  • the lower frequency modulation port 902 is at the input of the feedback divider delta sigma modulator 904.
  • the feedback 110 includes a fractional N divider 214. By causing the feedback division ratio to vary with the input phase data, the input phase modulation within the bandwidth of the PLL is transferred to the VCO output 140.
  • the upper frequency modulation port 704 is applied to the gain adaptation and normalization device 906.
  • the gain adaptation and normalization device 906 measures the phase error input to the digital loop filter 114 to estimate the variation between actual and expected analog gains of the current mode DAC 116, analog integrator 208 and VCO voltage to frequency gain and applies a scaling factor to the input phase data 706.
  • the gain adjusted signal including the phase data combined with the output of the digital loop filter 1 14 in the combiner 908. This creates the high frequency modulation path which transfers input phase modulation outside the bandwidth of the PLL to the VCO output 140.
  • the input phase data applied to the gain adaptation and normalization device 906 is digitally differentiated before being summed with filter output.
  • digital differentiation can be included in the digital loop filter 1 14 to compensate for the analog integration performed by the integrator 208.
  • the input phase data applied to the gain adaptation and normalization device 906 is digitally differentiated before being summed with the digitally differentiated digital filter output.
  • the upper frequency port 704 combines the input data 706 with the digital filter output signal 708 provided by the digital loop filter 1 14.
  • the two signals are combined by adding in the exemplary embodiment.
  • the data signal may be processed before injection into the lower frequency port and/or the upper frequency port.
  • FIG. 10 is a flow chart of a method of managing a PLL device 100 in accordance with the exemplary embodiment of the invention. The method may be implemented using any combination of hardware, software, and/or firmware.
  • a controller 216 generates control signal(s) 136 to manage components of the PLL device 100.
  • a phase detector 104 an analog loop filter 106, and a voltage controller oscillator (VCO) 108 are connected to configure the PLL device 100 in an analog mode to form an analog loop.
  • the switching mechanism 102 connects components of the PLL device 100 to form an analog phase locked loop.
  • the switching mechanism 102 is responsive to a control signal 136 to connect and configure the device components into the analog loop.
  • a suitable switching mechanism 102 includes a switching element 200 such as FET 300.
  • step 1004 it is determined whether the PLL device 100 should be configured in the digital mode.
  • the digital mode is selected when using a digital filter is advantageous to using analog loop filtering.
  • the digital mode is selected when the PLL is used for the transmission of signals and two point modulation is applied or when cancellation signals are injected into the two point modulation ports to reduce spurs or noise. If it is determined that the PLL device 100 should be switched to the digital mode, the method continues at step 1006. Otherwise, the method returns to step 1004 to continue monitoring the system to determine if a switch should be made.
  • step 1006 at least the phase detector 104, a time to digital converter (TDC) 1 18, a digital loop filter 1 14, a digital to analog converter (DAC) 1 16 and the VCO 108 are connected to configure the PLL device 100 in the digital mode to form a hybrid digital- analog loop.
  • the switching mechanism 102 connects components of the PLL device 100 to form hybrid digital-analog phase locked loop where a portion of the loop operates using digital signals and a portion of the loop operates using analog signals.
  • the switching mechanism 102 is responsive to the control signal 136 to connect and configure the device components into the hybrid digital- analog loop.
  • step 1008 it is determined whether the PLL device 100 should be configured in the analog mode.
  • the analog mode is selected when there is no advantage to using digital filtering.
  • the method returns to step 1002. Otherwise, the method returns to step 1002 to continue monitoring the system to determine if a switch should be made.
  • FIG. 11 is a flow chart of method of configuring the PLL device in the analog mode. Accordingly, the method discussed with reference to FIG. 1 1 provides an exemplary method for performing step 1002 of FIG. 10.
  • the TDC 1 18 is disabled.
  • the TDC 1 19 is turned off or is otherwise controlled to decrease or eliminate power consumption.
  • the switching mechanism 102 may include transistors or other switching elements that connect and disconnect power to the TDC 1 18. Where the TDC includes switching circuitry for controlling power consumption, such circuitry can be considered to be part of the switching mechanism 102 for the discussion herein.
  • the controller 216 provides a signal to the switching mechanism to disable the TDC 1 18. In the exemplary embodiment, the TDC is disabled by blocking the up and down signals from entering the TDC.
  • An example of suitable technique includes directing the signals through a pair of AND gates or MUXes such that, in TDC enabled mode, the output of the AND or MUX is UP and DN and, in the charge pump enabled mode, the output of the AND or MUX is set to "0" such that there are no transitions on the UP and DN inputs to TDC even though the UP and DN outputs from PFD are toggling.
  • Such an arrangement can be accomplished by switching modes when UP and DN are both low coming out of the PFD and by having TDC ring oscillator VDD be collapsed when the TDC is disabled. This will avoid putting the TDC in a state where it is consuming power due to the ring oscillator running, even though TDC is not being used.
  • the plurality of filter elements 202, 204, 206 are connected to form the analog loop filter 106.
  • one or more switching elements 200 establish electrical connections between the filter elements 202, 204, 206 to form the analog loop filter 104 between the charge pump 132 and the VCO 108.
  • the FET 300 provides an open circuit across the resistor 302 to create a two pole, single zero filter.
  • the charge pump 132 is connected between the phase detector 104 and the analog loop filter 106.
  • the switching mechanism 102 connects the charge pump 132.
  • the switching mechanism activates circuitry to apply a bias current to the charge pump which allows the PFD up and down signals to control the charge pump output switches that conduct current from the charge pump to the loop filter.
  • the single switching element 200 may connect multiple components to perform multiple steps of configuring the PLL device 100 in the analog loop. For example, forming the analog loop filter 106 may also result in connecting the charge pump.
  • FIG. 12 is a flow chart of method of configuring the PLL device 100 in the digital mode. Steps 1202, 1204 and 1206 provide an example procedure for performing step 1006 of FIG. 10. Step 1208 is an additional step to the method discussed with reference to FIG. 10 that is performed when the PLL device 100 is configured in the hybrid digital analog loop
  • the TDC 118 is enabled.
  • the TDC is enabled by allowing the up and down signals from PFD to enter the TDC.
  • the charge pump 132 is disconnected. Power is turned off during digital mode by blocking bias current from charge pump and blocking the PFD up and down signals so that charge pump output switches are always forced to off, making the charge pump output appear as a high impedance in shunt with the integrating capacitor.
  • the plurality of filter elements 202, 204, 206 are connected to form an integrator between the DAC and the VCO.
  • the FET creates a short circuit across the resistor 302 to directly connect the capacitor to ground.
  • the two capacitors result in a parallel capacitance that forms the integrator.
  • the VCO output signal 140 is modulated through a two point modulation port.
  • the two point modulation port comprises an upper frequency port and a lower frequency port, wherein the lower frequency port is connected within the feedback path and uses sigma-delta modulation.
  • the upper frequency port is connected between the digital loop filter and the DAC.
  • Other two- point modulation techniques may be uses in some circumstances.
  • the lower frequency port may be connected with the reference signal path such that the data signal is combined with the reference signal.
  • FIG. 10 The method steps described above with reference to FIG. 10, FIG, 1 1 and FIG. 12 may be performed in a different order than described. Tasks described as performed in a single step may be partially performed by other steps. Accordingly, tasks described as performed in a single step may be performed by multiple steps in some situations. Further, some steps may include several tasks that may be performed by additional steps that are not shown.
  • FIG. 13 is a schematic representation of a current steering DAC 1300 with a current source output stage 1302.
  • the digital input word is DI ⁇ n:0>.
  • MY indicates the relative size between PMOS transistors and MX indicates the relative size between NMOS transistors.
  • Iref is an input current bias.
  • the exemplary current source output stage 1302 is implemented using active devices such as transistors.
  • the output stage discussed with reference to FIG. 13 includes a current mirror 1304 having a reference input NMOS transistor 1306 where the source of the reference input NMOS transistor 1306 is connected to ground 1308.
  • the drain and gate of the input reference NMOS transistor are connected to a reference current input 1310.
  • the reference input NMOS transistor 1306 generates a reference voltage at the drain and gate nodes.
  • the reference voltage is coupled to the gates of a plurality of NMOS transistors 1312-1316.
  • the plurality of NMOS transistors 1313-1316 have sources connected to ground, and drains each individually connected to the sources of NMOS differential pairs 1317-1320.
  • One drain output of each differential pair is connected to the DAC output 1322 and the other can be connected to a dump node, such as power supply 1324.
  • the DAC output 1322 is biased with a PMOS current source 1326 of a PMOS current mirror 1328.
  • the PMOS current mirror includes the current source 1326 and a reference device 1330, where the current source 1326 which provides half of the maximum current that can be provided by the NMOS current sources 1312-1316 when all current sources are switched to the output 1322.
  • FIG. 14 is a schematic representation of a current steering DAC 1400 with a current source output stage 1402 in accordance with another configuration.
  • one drain output of each differential pair 1317-1320 is connected directly to the DAC output 1322 and the other is connected to the reference device 1330 of the PMOS current mirror 1328.
  • the sources of the devices of the PMOS current mirror are connected to the positive power supply 1324.
  • the gate and drain of the reference device 1330 are both connected to the drains of the NMOS differential pair transistors which are not connected directly to the DAC output 1322.
  • the voltage generated on the gate of the PMOS current mirror reference device 1 130 is applied to the PMOS current source transistor 1326 that has a drain connected to the DAC output 1322.
  • FIG. 15 is a schematic representation of exemplary current pulse DAC 1500 with a current source output stage 1502.
  • the digital input word is DI ⁇ n:0> and a sign bit to indicate if the filtered phase error is positive or negative. All transistors have the same width/length ratio.
  • the current source output stage 1502 is implemented as a single NMOS transistor 1502 with drain connected to the DAC output 1504, the gate connected to a reference voltage created by applying a reference current 1506 to the drain and gate of a NMOS transistor 1508 with source connected to ground 1308, and the source connected to a switch 1510 which connects to ground 1308.
  • the DAC output value is programmed by pulsing the switch 1510 on and off a number of times equal to the DAC input word DI ⁇ n:0>.
  • a complementary current source output stage 1512 is implemented as a single PMOS transistor 1512 with drain connected to the DAC output 1504, the gate connected to a reference voltage 1514 created by applying a copy of the NMOS reference current to the drain and gate of a PMOS transistor 1516 with source connected to the positive power supply 1324, and the source connected to a switch 1518 which connects to the positive power supply 1324.
  • Either the NMOS 1502 or the PMOS current source 1504 is selected to be active by the sign bit of the DAC input word. If the input word is unsigned, the most significant bit of the DAC input can be used as the sign bit.
  • a ring oscillator 1520 drives a pulse counter 1522, the output of the counter 1522 drives a digital comparator 1524 which compares the count with the DAC digital input word, or digital input word minus the most significant bit for unsigned DAC digital input words.
  • logic circuitry 1526 applies couples the ring oscillator signal to the gate control of the switch 1502, 1510 in the source of the NMOS current source transistor 1502 or PMOS current source transistor 1512 and creates one equal pulse of current for each ring oscillator period.
  • the ring oscillator signal is blocked from the gate control of the NMOS or PMOS current source switch transistor.
  • the counter is reset to zero once at the start of each reference period, allowing the next DAC input word to be converted to an analog current output sample.
  • the DAC output for this example is a series of current pulses where the total number of pulses per sample is equal to the DAC input word.
  • An example of suitable technique for disabling the DAC during the analog mode includes disabling the bias current signal (IREF) and to seting all switches controlled by DI ⁇ n:0> as wells as the FETs 1510, 1518 to an open or high impedance state.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • a general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
  • a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
  • the steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two.
  • a software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium.
  • the storage medium may be integral to the processor.
  • the processor and the storage medium may reside in an ASIC.
  • the ASIC may reside in a user terminal.
  • the processor and the storage medium may reside as discrete components in a user terminal.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
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US8339165B2 (en) 2012-12-25
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CN102648581B (zh) 2015-11-25
EP2510621B1 (en) 2014-06-18
US20130181756A1 (en) 2013-07-18
KR20120101536A (ko) 2012-09-13
JP5661793B2 (ja) 2015-01-28
US20110133799A1 (en) 2011-06-09
CN102648581A (zh) 2012-08-22
JP2013513343A (ja) 2013-04-18
US8884672B2 (en) 2014-11-11
KR101470938B1 (ko) 2014-12-09

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