WO2011070981A1 - Dispositif à semi-conducteurs et procédé de production associé - Google Patents

Dispositif à semi-conducteurs et procédé de production associé Download PDF

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Publication number
WO2011070981A1
WO2011070981A1 PCT/JP2010/071728 JP2010071728W WO2011070981A1 WO 2011070981 A1 WO2011070981 A1 WO 2011070981A1 JP 2010071728 W JP2010071728 W JP 2010071728W WO 2011070981 A1 WO2011070981 A1 WO 2011070981A1
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Prior art keywords
film
insulating film
opening
oxide semiconductor
semiconductor device
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PCT/JP2010/071728
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English (en)
Japanese (ja)
Inventor
近間　義雅
錦　博彦
純史 太田
裕二 水野
猛 原
哲也 会田
鈴木　正彦
竹井　美智子
興史 中川
祥征 春本
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シャープ株式会社
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Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to RU2012128513/28A priority Critical patent/RU2503085C1/ru
Priority to JP2011545195A priority patent/JP5095864B2/ja
Priority to BR112012013851A priority patent/BR112012013851A2/pt
Priority to KR1020127017540A priority patent/KR101273831B1/ko
Priority to CN201080056072.8A priority patent/CN102652330B/zh
Priority to US13/514,081 priority patent/US8685803B2/en
Priority to EP10835902.7A priority patent/EP2511896B1/fr
Publication of WO2011070981A1 publication Critical patent/WO2011070981A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode

Definitions

  • the present invention relates to a semiconductor device including a thin film transistor and a manufacturing method thereof.
  • an active matrix liquid crystal display device or an organic EL display device is opposed to a substrate (hereinafter referred to as “TFT substrate”) in which a thin film transistor (hereinafter referred to as “TFT”) is formed as a switching element for each pixel.
  • TFT substrate a substrate
  • TFT thin film transistor
  • a counter substrate on which electrodes and color filters are formed and a light modulation layer such as a liquid crystal layer provided between the TFT substrate and the counter substrate are provided.
  • the TFT substrate includes a plurality of source wirings, a plurality of gate wirings, a plurality of TFTs disposed at intersections thereof, a pixel electrode for applying a voltage to a light modulation layer such as a liquid crystal layer, and an auxiliary Capacitance wiring, auxiliary capacitance electrodes, and the like are formed.
  • terminal portions for connecting the source wiring and the gate wiring to the input terminals of the driving circuit are provided at the ends of the TFT substrate.
  • the drive circuit may be formed on the TFT substrate or may be formed on a separate substrate (circuit substrate).
  • Patent Document 1 The configuration of the TFT substrate is disclosed in Patent Document 1, for example.
  • Patent Document 1 the configuration of the TFT substrate disclosed in Patent Document 1 will be described with reference to the drawings.
  • FIG. 12A is a schematic plan view showing an outline of the TFT substrate
  • FIG. 12B is an enlarged plan view showing one pixel on the TFT substrate
  • 13 is a cross-sectional view of the TFT and the terminal portion in the semiconductor device shown in FIG.
  • the TFT substrate has a plurality of gate wirings 2016 and a plurality of source wirings 2017.
  • Each region 2021 surrounded by the wirings 2016 and 2017 is a “pixel”.
  • a plurality of connection portions 2041 for connecting each of the plurality of gate wirings 2016 and the source wirings 2017 to the driving circuit are arranged in a region 2040 other than a region (display region) where a pixel is formed in the TFT substrate.
  • Each connection portion 2041 constitutes a terminal portion for connecting to external wiring.
  • a region 2040 of the TFT substrate where a plurality of terminal portions are arranged is referred to as a “terminal arrangement region”.
  • a pixel electrode 2020 is provided so as to cover each region 2021 serving as a pixel.
  • a TFT is formed.
  • the TFT includes a gate electrode G, gate insulating films 2025 and 2026 covering the gate electrode G, a semiconductor layer 2019 disposed on the gate insulating film 2026, a source electrode S connected to both ends of the semiconductor layer 2019, and And a drain electrode D.
  • the TFT is covered with a protective film 2028.
  • An interlayer insulating film 2029 is formed between the protective film 2028 and the pixel electrode 2020.
  • the source electrode S of the TFT is connected to the source wiring 2017 and the gate electrode G is connected to the gate wiring 2016. Further, the drain electrode D is connected to the pixel electrode 2020 in the contact hole 2030.
  • an auxiliary capacitance wiring 2018 is formed in parallel with the gate wiring 2016.
  • the auxiliary capacitance line 2018 is connected to the auxiliary capacitance.
  • the auxiliary capacitance includes an auxiliary capacitance electrode 2018b formed of the same conductive film as the drain electrode, an auxiliary capacitance electrode 2018a formed of the same conductive film as the gate wiring, and a gate insulating film 2026 positioned therebetween. It is composed of
  • the gate insulating films 2025 and 2026 and the protective film 2028 are not formed over the connection portion 2041 extending from each gate wiring 2016 or the source wiring 2017, and the connection wiring 2044 is formed so as to be in contact with the upper surface of the connection portion 2041. ing. Thereby, the electrical connection between the connection portion 2041 and the connection wiring 2044 is ensured.
  • the TFT substrate 2013 is disposed so as to face the substrate 2014 on which the counter electrode and the color filter are formed with the liquid crystal layer 2015 interposed therebetween.
  • a region 2021 (also referred to as a “pixel portion”) that serves as a pixel and a terminal portion are formed by a common process to suppress an increase in the number of masks and processes. preferable.
  • Patent Document 1 discloses that an interlayer insulating film 2029 is formed using an organic insulating film, and the insulating films 2025 and 2026 and the protective film 2028 are etched using the interlayer insulating film 2029 as a mask.
  • an active layer of a TFT using an oxide semiconductor film such as zinc oxide instead of a silicon semiconductor film.
  • an oxide semiconductor TFT is referred to as an “oxide semiconductor TFT”.
  • An oxide semiconductor has higher mobility than amorphous silicon. For this reason, the oxide semiconductor TFT can operate at a higher speed than the amorphous silicon TFT.
  • the oxide semiconductor film is formed by a simpler process than the polycrystalline silicon film, the oxide semiconductor film can be applied to a device that requires a large area.
  • oxide semiconductor TFT having a bottom gate structure
  • carrier electrons may be generated due to oxygen defects in the TFT manufacturing process, for example, in a heat treatment step, and the resistance may be lowered.
  • oxide semiconductor film under the source / drain electrode etching process and the interlayer insulating film forming process is easily damaged.
  • a structure in which a channel protective film is provided so as to cover a region where a channel is formed (channel forming region) in the semiconductor layer has been proposed.
  • the channel protective film functions as an etch stop when etching is performed to form the source / drain electrode. . For this reason, the damage which a channel formation area receives by an etching can be reduced.
  • Patent Document 2 describes a configuration of a pixel portion of a TFT substrate having a channel protection type TFT. However, the TFT of Patent Document 2 is formed using a silicon film.
  • FIG. 14 is a cross-sectional view showing a part of the TFT substrate described in Patent Document 2.
  • a thin film transistor 1141 and an auxiliary capacitor 1142 are provided in each pixel of the TFT substrate.
  • a gate wiring 1102, a gate insulating film 1104, a semiconductor layer 1113 having a channel formation region, a channel protective film 1108, a source region 1118, a drain region 1117, a drain electrode 1121, and a source wiring 1122 are formed.
  • the thin film transistor 1141 is covered with a protective film 1127, and a pixel electrode 1131 is provided over the protective film 1127.
  • the pixel electrode 1131 is connected to the drain electrode 1121 in a contact hole formed in the protective film 1127.
  • the auxiliary capacitor 1142 includes a capacitor wiring 1151 formed of the same conductive film as the gate wiring 1102 and a pixel electrode 1131 as an electrode, and a gate insulating film 1104 and a protective film 1127 sandwiched between the electrodes as a dielectric. .
  • the insulating film formed between the channel formation region of the semiconductor layer and the source / drain electrodes is referred to as “channel protective film” or “etch stopper”, and the insulating film covering the TFT and the bottom gate structure
  • the insulating film provided on the source / drain electrodes is simply referred to as “protective film” to distinguish the two.
  • the gate wiring 1102 and the external wiring provided on the protective film 1127 in the contact holes formed in the gate insulating film 1104 and the protective film 1127 on the gate wiring 1102. Can be electrically connected.
  • etching for forming the channel protective film 1108, etching for forming the source / drain electrodes 1121 and 1122, and etching for forming a contact hole in the protective film 1127 are performed. This is performed (FIGS. 7 to 9 of Patent Document 2). It is considered that the contact hole in the terminal portion is formed by collectively etching the protective film 1127 and the gate insulating film 1104 when the protective film 1127 is etched.
  • Patent Document 3 it is proposed to reduce the number of masks to be used by using a halftone mask in a method of manufacturing a TFT substrate having a channel protection type TFT.
  • the method of Patent Document 3 has a complicated manufacturing process and may reduce mass productivity.
  • an oxide film such as a SiO 2 film is often used as a gate insulating film or a protective film. This is because oxygen vacancies can be recovered by oxygen contained in the oxide film when oxygen vacancies are generated in the oxide semiconductor layer.
  • an interlayer insulating film 2029 is formed using an organic insulating film, and this is used as a mask to gate insulating films 2025 and 2026 and a protective film.
  • a contact hole in the terminal portion is formed.
  • SiO 2 is used as one of the gate insulating films 2025 and 2026 and the protective film 2028, the etching rate of SiO 2 is very low, so that the etching time becomes long.
  • the organic insulating film (interlayer insulating film) 2029 that is a mask may be damaged.
  • the contact hole in the terminal portion is formed by collectively etching the protective film 1127 and the gate insulating film 1104 using a resist mask.
  • the etching rate of SiO 2 is very low. Mask peeling failure may occur. If the etch rate is low, it is difficult to form a desired tapered shape on the wall surface of the contact hole in the terminal portion, and the wall surface may be substantially perpendicular to the substrate. In such a case, there is a problem that the wiring formed in the contact hole of the terminal portion is likely to be cut.
  • the etching mask may be damaged, or the contact hole taper shape may not be optimized and the wiring may be disconnected. There is a possibility that the reliability of the TFT substrate may be lowered.
  • the present invention has been made in order to solve the above-described circumstances, and its main object is to provide a terminal portion in a semiconductor device including an oxide semiconductor TFT and a terminal portion that connects an electrode of the TFT and an external wiring.
  • the damage to the mask is reduced and the taper shape of the wall surface of the contact hole is controlled with high accuracy.
  • the semiconductor device of the present invention is a semiconductor device including a substrate, a thin film transistor formed on the substrate, and a terminal portion that electrically connects the thin film transistor and an external wiring, and the thin film transistor includes the substrate A gate wiring provided on the gate wiring; a first insulating film formed on the gate wiring; a channel region formed on the first insulating film; and a source region and a drain located on both sides of the channel region, respectively
  • An island-shaped oxide semiconductor layer having a region, a second insulating film provided in contact with the oxide semiconductor layer, and provided on the second insulating film and electrically connected to the source region A source line, a drain electrode provided on the second insulating film and electrically connected to the drain region, provided on the source line and the drain electrode,
  • a protective film covering the thin film transistor wherein the terminal portion is formed on the first connection portion formed from the same conductive film as the gate wiring, and the source wiring and the drain electrode A second connection portion formed from the same conductive film and a third connection portion formed on the second connection
  • the first connection part is in contact with the first connection part in the first opening provided in the film
  • the third connection part is in contact with the second connection part in the second opening part provided in the protective film.
  • the second connection portion covers the end surfaces of the first insulating film and the second insulating film in the first opening, and does not cover the end surface of the protective film in the second opening.
  • the second opening is located inside the first opening when viewed from the normal direction of the surface of the substrate.
  • the pixel electrode may further include a pixel electrode electrically connected to the drain electrode, and the third connection portion may be formed of the same conductive film as the pixel electrode.
  • the storage capacitor further includes a storage capacitor formed on the substrate, wherein the storage capacitor is formed of the same conductive film as the gate wiring and the first insulation covering the storage capacitor wiring.
  • An auxiliary capacitance forming semiconductor layer formed from the same oxide semiconductor film as the oxide semiconductor layer, and an auxiliary capacitance electrode provided on the auxiliary capacitance forming semiconductor layer, The auxiliary capacitance electrode is in contact with the auxiliary capacitance forming semiconductor layer in the opening formed in the second insulating film.
  • the auxiliary capacitance electrode is a part of the drain electrode, and the pixel electrode is in contact with the auxiliary capacitance electrode in an opening formed in the protective film.
  • the auxiliary capacitance electrode is a part of the pixel electrode.
  • a gate-source connection portion for electrically connecting the gate wiring and the source wiring; wherein the source wiring is provided in the first insulating film and the second insulating film; The gate wiring may be in contact with the first opening.
  • An organic insulating film may be further provided between the protective film and the pixel electrode.
  • At least one of the first insulating film and the protective film contains SiO 2 .
  • the first insulating film has a stacked structure including a SiO 2 film and a SiNx film, and the SiO 2 film is an uppermost layer of the stacked structure and may be in contact with a lower surface of the oxide semiconductor layer. .
  • the protective film may have a laminated structure including a SiO 2 film and a SiNx film, and the SiO 2 film may be a lowermost layer of the laminated structure.
  • At least the first insulating film and the oxide are provided between the upper surface and sidewall of the gate wiring and the source wiring, and between the upper surface and sidewall of the gate wiring and the drain electrode.
  • a semiconductor layer is provided.
  • the second insulating film may be further provided between the upper surface and sidewall of the gate wiring and the source wiring, and between the upper surface and sidewall of the gate wiring and the drain electrode.
  • the second insulating film covers all the upper surfaces and sidewalls of the surface of the oxide semiconductor layer except the source region and the drain region, and the first insulating film in the vicinity of the sidewall of the oxide semiconductor layer. It may be in contact with the upper surface of the film.
  • the width of the oxide semiconductor layer along the channel length direction may be larger than the width of the gate wiring along the channel length direction.
  • a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device according to any one of the above, wherein (A) a gate wiring conductive film is formed on a substrate and patterned to form a gate wiring. Forming a first connecting portion; (B) forming a first insulating film on the gate wiring and the first connecting portion; and (C) activating a thin film transistor on the first insulating film. Forming an oxide semiconductor layer to be a layer; (D) forming a second insulating film covering the oxide semiconductor layer and the first insulating film; and (E) etching stop the oxide semiconductor layer.
  • first and second insulating films etching the first and second insulating films to form a source contact forming opening and a drain contact forming opening exposing the oxide semiconductor layer in the second insulating film. And forming a first opening in the second insulating film and the first insulating film to expose a surface of the first connection portion; and (F) forming a source / drain electrode on the second insulating film.
  • a source wiring in contact with the oxide semiconductor layer in the source contact formation opening, and a drain electrode in contact with the oxide semiconductor layer in the drain contact formation opening Forming a second connection portion in contact with the first connection portion in the first opening, and (G) forming a protective film on the source wiring, the drain electrode, and the second connection portion; (H) forming a second opening that exposes the second connection portion in the protective film; and (I) a third that contacts the second connection portion in the second opening on the protective film.
  • the step (H) includes a step of forming an opening exposing the drain electrode in the protective film, and the step (I) forms a transparent conductive film on the protective film and patterns the same.
  • the step of forming the third connection portion and the pixel electrode may be a step of contacting the drain electrode in the opening that exposes the drain electrode.
  • the etching time is shortened to form a mask.
  • the taper shape of the wall surface of the contact hole can be controlled with high accuracy.
  • the semiconductor device can be easily manufactured without complicating the manufacturing process.
  • FIGS. 4A to 4F are process cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • 1 is a plan view of a semiconductor device according to a first embodiment of the present invention
  • (a) is a plan view of a pixel unit 101 in the semiconductor device
  • (b) to (d) are a gate terminal and a source in the semiconductor device, respectively. It is a top view of a terminal and a gate-source connection part.
  • 2A is a cross-sectional view taken along line II ′ shown in FIG. 2A and line II-II ′ shown in FIG. 2B or line III-III ′ shown in FIG. It is.
  • FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention
  • (a) is a plan view of a pixel unit 101 in the semiconductor device
  • (b) to (d) are a gate terminal and a source in the semiconductor device, respectively. It is a
  • FIG. 7 is a plan view of a semiconductor device according to a second embodiment of the present invention, (a) is a plan view of a pixel unit 201 in the semiconductor device, and (b) to (d) are a gate terminal and a source in the semiconductor device, respectively. It is a top view of a terminal and a gate-source connection part.
  • 5A is a cross-sectional view taken along the line II ′ shown in FIG. 5A and the line II-II ′ shown in FIG.
  • FIG. 5B is a sectional view taken along line IV-IV ′ shown in FIG. (A)-(c) is process sectional drawing which shows an example of the manufacturing method of the semiconductor device of Embodiment 3 by this invention, respectively.
  • FIG. 5B is a sectional view taken along line IV-IV ′ shown in FIG. (A)-(c) is process sectional drawing which shows an example of the manufacturing method of the semiconductor device of Embodiment 3 by this invention, respectively.
  • an enlarged cross-sectional view illustrating a terminal portion when disconnection occurs in a connection portion 23c It is sectional drawing which illustrates the structure of the other semiconductor device of Embodiment 3 by this invention. It is sectional drawing which illustrates the structure of the further another semiconductor device of Embodiment 3 by this invention.
  • (A)-(c) is process sectional drawing which shows an example of the manufacturing method of the semiconductor device of Embodiment 4 by this invention, respectively.
  • (A) is a typical top view which shows the outline of the conventional TFT substrate
  • (b) is an enlarged plan view which shows one pixel in the TFT substrate of (a). It is sectional drawing of TFT and the terminal part in the conventional TFT substrate shown in FIG. It is sectional drawing which shows a part of conventional TFT substrate.
  • the semiconductor device of the present embodiment only needs to include a TFT substrate on which at least one oxide semiconductor TFT is formed, and widely includes various display devices, TFT substrates, electronic devices, and the like.
  • the TFT substrate has a display area including a plurality of pixel portions and a terminal arrangement area formed in an area other than the display area.
  • an oxide semiconductor TFT and an auxiliary capacitor are formed in each pixel portion of the display area, and a plurality of terminal portions are formed in the terminal arrangement area.
  • FIG. 1A to 1F are schematic process cross-sectional views for explaining a method for manufacturing a semiconductor device of this embodiment.
  • a gate wiring 3a is formed in a region (TFT formation region) A where a TFT is to be formed on the substrate 1, and a region (auxiliary capacitance formation region) B where a supplementary capacitor is to be formed.
  • a gate wiring connecting portion 3c is formed in a storage capacitor wiring 3b and a region (terminal portion forming region) C where a gate / source terminal portion is to be formed.
  • the TFT formation region A and the auxiliary capacitance formation region B are located in each pixel portion 101 in the display region, and the terminal portion formation region C is a terminal disposed in a region other than the display region, for example, the periphery of the substrate 1. Located in the placement area 102. Normally, a large number of source terminal portions and gate terminal portions are formed in the terminal arrangement region 102, but only a formation region C of one gate or source terminal portion is shown here.
  • the gate wiring 3a, the auxiliary capacitance wiring 3b, and the connection portion 3c are formed by forming a metal film (for example, a Ti / Al / Ti film) on the substrate 1 by sputtering or the like and then patterning the metal film.
  • the patterning of the metal film is performed by forming a resist mask by known photolithography and removing a portion not covered with the resist mask. Thereafter, the resist mask is peeled off from the substrate 1.
  • an insulating film 5 is formed so as to cover the gate wiring 3a, the auxiliary capacitance wiring 3b, and the connection portion 3c. Subsequently, an island-shaped oxide semiconductor layer 7a to be a TFT channel layer is formed in the TFT formation region A, and an island-shaped oxide semiconductor layer 7b is formed in the auxiliary capacitance formation region B.
  • the insulating film 5 for example, a SiO 2 film having a thickness of about 400 nm is formed by a CVD method.
  • the insulating film 5 may be a single layer made of, for example, a SiO 2 film, or may have a laminated structure in which the SiNx film is a lower layer and the SiO 2 film is an upper layer. Case of a single layer of SiO 2 film, it is preferable that the thickness of the SiO 2 film is 300nm or more 500nm or less.
  • the thickness of the SiNx film is 200nm or more 500nm or less, it is preferable that the thickness of the SiO 2 film is 20nm or more 150nm or less.
  • the oxide semiconductor layers 7a and 7b can be formed as follows. First, an In—Ga—Zn—O-based semiconductor (IGZO) film having a thickness of 30 nm to 300 nm, for example, is formed on the insulating film 5 by sputtering. Thereafter, a resist mask covering a predetermined region of the IGZO film is formed by photolithography. Next, the portion of the IGZO film that is not covered with the resist mask is removed by wet etching. Thereafter, the resist mask is peeled off. In this way, island-shaped oxide semiconductor layers 7a and 7b are obtained. Note that the oxide semiconductor layers 7a and 7b may be formed using another oxide semiconductor film instead of the IGZO film.
  • IGZO In—Ga—Zn—O-based semiconductor
  • the insulating film 9 is deposited on the entire surface of the substrate 1, the insulating film 9 is patterned.
  • a SiO 2 film (thickness: about 150 nm, for example) is formed as the insulating film 9 on the insulating film 5 and the oxide semiconductor layers 7a and 7b by the CVD method.
  • the insulating film 9 preferably includes an oxide film such as SiOy.
  • an oxide film such as SiOy.
  • the oxide film when oxygen vacancies are generated in the oxide semiconductor layers 7a and 7b, the oxygen vacancies can be recovered by oxygen contained in the oxide films, and thus the oxide semiconductor layers 7a and 7b. The oxidation deficiency can be reduced more effectively.
  • the use of a single layer of SiO 2 film as the insulating film 9, the insulating film 9, a SiO 2 film as a lower layer may have a laminated structure of the SiNx film as an upper layer.
  • the thickness of the insulating film 9 (the total thickness of each layer in the case of a laminated structure) is preferably 50 nm or more and 200 nm or less.
  • the surface of the oxide semiconductor layer 7a can be more reliably protected in the patterning process of the source / drain electrodes.
  • it exceeds 200 nm a larger step is generated in the source electrode and the drain electrode, which may cause disconnection.
  • a resist mask that covers a predetermined region of the insulating film 9 is formed by photolithography.
  • a portion of the insulating film 9 that is not covered with the resist mask is removed by wet etching.
  • not only the insulating film 9 but also the insulating film 5 therebelow is etched in the terminal portion forming region C, and the oxide semiconductor layer 7a under the insulating film 9 is etched in the TFT forming region A and the auxiliary capacitance forming region B. , 7b are selected so as not to be etched.
  • CF 4 / O 2 (flow rate: 475 sccm / 25 sccm) is used as an etching gas
  • the temperature of the substrate 1 is set to 60 ° C.
  • dry etching is performed in the chamber.
  • the degree of vacuum in the chamber is 15 mT.
  • the applied power is 1000 W and the etching time is 7 minutes.
  • the portions of the insulating film 9 where the source contact and the drain contact are formed are etched to form two openings 11as and 11ad that expose the oxide semiconductor layer 7a.
  • the insulating film 9 covers a region to be a channel in the oxide semiconductor layer 7a and functions as the channel protective film 9a.
  • a portion of the insulating film 9 located on the oxide semiconductor layer 7b is etched to form an opening 11b exposing the oxide semiconductor layer 7b.
  • the terminal portion formation region C a portion of the insulating film 9 located on the connecting portion 3c and the insulating film 5 therebelow are continuously etched to obtain an opening portion 11c exposing the surface of the connecting portion 3c. It is done.
  • the diameter of the opening 11c is, for example, 20 ⁇ m.
  • the etching conditions are selected according to the material of the insulating films 5 and 9 so that the insulating films 5 and 9 are etched using the oxide semiconductor layers 7a and 7b as an etch stop. It is preferable. As a result, the insulating film 9 and the insulating film 5 are collectively etched (GI / ES simultaneous etching) in the terminal portion forming region C, and only the insulating film 9 can be etched in the TFT forming region A and the auxiliary capacitance forming region B. .
  • the etching conditions here include the type of etching gas, the temperature of the substrate 1, the degree of vacuum in the chamber, and the like when dry etching is used. When wet etching is used, the type of etching solution, etching time, and the like are included.
  • a conductive film is formed on the entire surface of the substrate 1 as shown in FIG.
  • a metal film such as a Ti / Al / Ti film is formed by sputtering, for example. Thereafter, the metal film is patterned by, for example, photolithography.
  • the source wiring 13as is in contact with the regions located on both sides of the region serving as the channel region in the oxide semiconductor layer 7a inside the openings 11as and 11ad and on the insulating film 9. Then, the drain electrode 13ad is formed.
  • the drain electrode 13ad extends to the auxiliary capacitance line 3b in the auxiliary capacitance formation region B, and is in contact with the oxide semiconductor layer 7b through the opening 11b.
  • a portion of the drain electrode 13ad that is in contact with the oxide semiconductor layer 7b also functions as an auxiliary capacitance electrode.
  • a connection portion 13c electrically connected to the connection portion 3c is formed inside the opening portion 11c and on the insulating film 9.
  • a region of the oxide semiconductor layer 7a in contact with the source wiring 13as is referred to as a “source region”, and a region in contact with the drain electrode 13ad is referred to as a “drain region”.
  • a region of the oxide semiconductor layer 7a located on the gate wiring 3a and sandwiched between the source region and the drain region is referred to as a “channel region”.
  • the oxide semiconductor TFT is formed in the TFT formation region A, and the auxiliary capacitance Cs is formed in the auxiliary capacitance formation region B.
  • the auxiliary capacitance Cs is configured by using the auxiliary capacitance wiring 3b, the drain electrode 13ad and the oxide semiconductor layer 7b as electrodes, and the insulating film 5 as a dielectric.
  • a protective film 15 is deposited on the entire surface of the substrate 1 so as to cover the oxide semiconductor TFT and the auxiliary capacitor Cs.
  • an oxide film thickness: about 265 nm, for example
  • the protective film 15 may be a single layer made of, for example, a SiO 2 film, or may have a laminated structure in which the SiO 2 film is a lower layer and the SiNx film is an upper layer. Case of a single layer of SiO 2 film, it is preferable that the thickness of the SiO 2 film is 50nm or more 300nm or less.
  • the thickness of the SIO 2 film is preferably 50 nm to 150 nm and the thickness of the SiNx film is preferably 50 nm to 200 nm.
  • the protective film 15 is patterned by photolithography.
  • the opening 17b exposing the drain electrode 13ad is formed in the protective film 15.
  • the opening 17b is formed on the auxiliary capacitor Cs.
  • an opening 17 c that exposes the connection portion 13 c is formed in the protective film 15.
  • the widths of the opening 11c and the opening 17c may be substantially equal, but the opening 17c is slightly smaller than the opening 11c when viewed from the normal direction of the surface of the substrate 1, It is preferable to arrange in the part 11c. Accordingly, the openings 11c and 17c are arranged so as to overlap each other when viewed from the normal direction of the substrate, and thus the contact holes of the terminal portions can be configured by the openings 11c and 17c.
  • a transparent conductive film is formed on the protective film 15 and in the openings 17b and 17c, and the transparent conductive film is patterned. Thereby, the pixel electrode 19 in contact with the exposed surface of the drain electrode 13ad and the connection portion 19c in contact with the exposed surface of the connection portion 13c are formed.
  • the pixel electrode 19 is disposed separately for each pixel.
  • a transparent conductive film is deposited by sputtering, for example.
  • an ITO film thickness: 50 to 200 nm
  • the ITO film is patterned by known photolithography.
  • the pixel electrode 19, the auxiliary capacitor Cs, and the thin film transistor TFT are shown one by one.
  • the TFT substrate usually has a plurality of pixel portions 101, and the plurality of pixel portions.
  • a pixel electrode 19, an auxiliary capacitor Cs, and a thin film transistor TFT are arranged in each of the 101.
  • the terminal arrangement region 102 the same number of terminal portions as the source wiring 13as and the gate wiring 3a are formed.
  • a gate / source connection portion for connecting the source wiring and the gate wiring.
  • the insulating film 9 and the insulating film 5 on the gate wiring are simultaneously etched to form an opening that exposes the gate wiring (or its connecting portion). It is preferable.
  • a gate-source connection portion having a configuration in which the source wiring and the gate wiring are in direct contact with each other can be obtained.
  • FIG. 2A is a plan view of the pixel portion 101 in the semiconductor device
  • FIGS. 2B to 2D are gate terminals, source terminals, and gate / source connections of the terminal arrangement region 102 in the semiconductor device, respectively.
  • 3A is along the line II ′ shown in FIG. 2A and the line II-II ′ shown in FIG. 2B or the line III-III ′ shown in FIG. 2C. It is sectional drawing.
  • FIG. 3B is a cross-sectional view taken along line IV-IV ′ shown in FIG.
  • each pixel portion 101 a source wiring 13as extending along the pixel row direction, a gate wiring 3a and an auxiliary capacitance wiring 3b extending along the pixel column direction are formed.
  • a thin film transistor TFT is formed in the vicinity of a point where the source line 13as and the gate line 3a intersect, and an auxiliary capacity Cs is formed on the auxiliary capacity line 3b.
  • the oxide semiconductor layer 7a of the TFT is connected to the source wiring 13as and the drain electrode 13ad through the openings 11as and 11ad of the insulating film 9, respectively. Further, the drain electrode 13ad extends to the auxiliary capacitance line 3b and is connected to the pixel electrode 19 in the opening 17b of the protective film 15 on the auxiliary capacitance Cs.
  • the oxide semiconductor layer 7b of the auxiliary capacitor Cs is connected to the auxiliary capacitor electrode (here, the drain electrode 13ad) in the opening 11b of the insulating film 9, and is connected to the pixel electrode 19 in the opening 17b of the protective film 15. Yes.
  • the opening 17b is disposed in the opening 11b.
  • connection portion 3 c is connected to the connection portion 13 c in the opening portion 11 c obtained by etching the insulating film 5 and the insulating film 9 simultaneously, and in the opening portion 17 c of the protective film 15.
  • the connection part 19c is connected.
  • the connection portion 3c is an end face (opening portion) of the insulating films 5 and 9 in the opening portion 11c. 11c) and the end face of the protective film 15 in the opening 17c (the wall of the opening 17c) is not covered.
  • the opening 17c is disposed in the opening 11c.
  • the gate wiring connection portion 3d is directly connected to the source wiring 13as in the opening 11d obtained by etching the insulating film 5 and the insulating film 9 simultaneously.
  • the source wiring 13as is covered with a protective film 15.
  • the semiconductor device of the present embodiment is manufactured using the method described above with reference to FIG. 1, it has the following advantages over the prior art.
  • a protective film having a laminated structure in which an organic insulating film is an upper layer and an inorganic insulating film is a lower layer is formed, and the inorganic insulating film and the gate insulating film are etched using the organic insulating film as a mask.
  • the contact hole of the terminal part was formed (GI / Pass simultaneous etching).
  • the etching time becomes very long. For this reason, the surface of the organic insulating film used as a mask may be damaged during etching.
  • the contact hole in the terminal portion is formed in two stages. That is, the insulating film 5 to be the gate insulating film and the insulating film 9 for forming the channel protective film (etch stop) are simultaneously etched to form the opening 11c (GI / ES simultaneous etching). Subsequently, after the formation of the source / drain electrodes, the protective film 15 is etched separately from the GI / ES simultaneous etching to form an opening 17c in the protective film 15 (Pass etching). In general, the thickness of the protective film 15 is larger than the thickness of the insulating film 9 for forming the channel protective film.
  • the total thickness of the film to be etched is smaller than that in the conventional GI / Pass simultaneous etching in which the gate insulating film and the protective film are simultaneously etched. Can be small. Therefore, since the etching time can be greatly shortened, damage to the etching mask can be reduced.
  • the tapered shape of the contact hole in the terminal portion is controlled by the etching conditions in the GI / Pass simultaneous etching.
  • the etching conditions in the GI / Pass simultaneous etching On the other hand, in this embodiment, it is controlled mainly by the etching conditions in the etching (pass etching) of only the protective film 15.
  • the etching mask resist film
  • both the gate insulating film and the protective film have a laminated structure (for example, a two-layer structure)
  • the conventional method performs etching on the four-layer film, and the taper shape is very controlled. It becomes difficult.
  • the taper shape can be controlled by etching the two-layer film constituting the protective film, so that the controllability of the taper shape can be greatly improved.
  • the wall surface of the contact hole can be more reliably inclined at a predetermined angle (taper angle) with respect to the normal line of the substrate. It is possible to prevent cutting. Therefore, an electrical connection between the source wiring or the gate wiring in the terminal portion and the input portion of the driver circuit can be ensured.
  • the gate wiring and the source wiring are electrically connected through a transparent conductive film for forming the pixel electrode in the gate / source connection portion (for example, FIG. 4 of Patent Document 2). Therefore, if the wall surface of the contact hole in the gate / source connection portion is not sufficiently inclined with respect to the normal line of the substrate, the source wiring constituting the wall surface and the transparent conductive film formed on the wall surface are electrically connected. There is a problem that cannot be connected.
  • this embodiment has the following merits as compared with the configuration disclosed in Patent Document 3.
  • the gate electrode, the gate insulating film, and the oxide semiconductor layer are patterned using the same mask.
  • the side walls of these layers are covered with an insulating film that functions as an etch stop.
  • an insulating film functioning as an etch stop is provided between the side wall of the gate electrode and the source electrode, and there is a possibility that a short circuit occurs between these electrodes.
  • the insulating film 5 serving as the gate insulating film, the oxide semiconductor layer 7a, and the insulating film 9 functioning as an etch stop are longer than the gate wiring 3a in the channel length direction.
  • the side walls are covered with an insulating film 5, an oxide semiconductor layer 7 a and an insulating film 9.
  • insulating film 5 and insulating film 9 there are at least two layers of insulating films (insulating film 5 and insulating film 9) between the upper surface and side walls of gate wiring 3a and source wiring 13as and between the upper surface and side walls of gate wiring 3a and drain electrode 13ad. ) Exists. For this reason, the above-mentioned short circuit can be prevented. Further, even in the case where a hole is formed in the insulating film 5, particularly in a portion of the insulating film 5 located between the gate wiring 3 a and the source / drain electrodes 13 as and 13 ad, these can be covered with the insulating film 9. It is possible to suppress the occurrence of point defects between the two.
  • the insulating film 5, at least one of the insulating film 9 and the protective film 15 preferably contains SiO 2.
  • oxygen is supplied from these films to the oxide semiconductor layer 7a serving as the active layer of the TFT, so that oxygen vacancies generated in the oxide semiconductor layer 7a can be further reduced.
  • the oxide semiconductor layer 7a becomes low resistance resulting from an oxygen defect, a leakage current and a hysteresis can be reduced.
  • the surface on the oxide semiconductor layer 7a side among these insulating films that is, the upper surface of the insulating film 5, the lower surface of the insulating film 9, and the lower surface of the protective film 15
  • SiO 2 the surface on the oxide semiconductor layer 7a side among these insulating films
  • the insulating film 9 including the channel protective film 9a preferably covers the entire upper surface (except for the source / drain regions) and the entire sidewall of the island-shaped oxide semiconductor layer 7a.
  • oxygen defects are formed in the channel region of the oxide semiconductor layer 7a and its vicinity by an oxidation-reduction reaction. This can be suppressed. As a result, it is possible to suppress the resistance of the oxide semiconductor layer 7a from being lowered due to oxygen defects, and thus leakage current and hysteresis can be reduced.
  • the insulating film 9 is preferably longer than the oxide semiconductor layer 7a in the channel width direction and in contact with the upper surface of the insulating film 5 located in the vicinity of the sidewall of the oxide semiconductor layer 7a. Accordingly, the insulating film 9 can more reliably protect not only the upper surface of the oxide semiconductor layer 7a but also the side wall.
  • the oxide semiconductor layers 7a and 7b in this embodiment include, for example, a Zn—O based semiconductor (ZnO), an In—Ga—Zn—O based semiconductor (IGZO), an In—Zn—O based semiconductor (IZO), or a Zn— A layer made of a Ti—O based semiconductor (ZTO) is preferable.
  • ZnO Zn—O based semiconductor
  • IGZO In—Ga—Zn—O based semiconductor
  • IZO In—Zn—O based semiconductor
  • ZTO Ti—O based semiconductor
  • Embodiment 2 a method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to the drawings.
  • This embodiment is different from Embodiment 1 in that a pixel electrode is used instead of a drain electrode as an auxiliary capacitance electrode.
  • 4 (a) to 4 (f) are schematic process cross-sectional views for explaining the semiconductor device manufacturing method of the present embodiment.
  • the same components as those in FIG. 1 are schematic process cross-sectional views for explaining the semiconductor device manufacturing method of the present embodiment.
  • the gate wiring 3a is formed in the TFT formation region A where the TFT is to be formed on the substrate 1
  • the auxiliary capacitance wiring 3b is formed in the auxiliary capacitance forming region B where the auxiliary capacitance is to be formed
  • a gate wiring connection portion 3c is formed in a terminal portion formation region C where a gate / source terminal is to be formed.
  • the formation methods and materials of the wirings 3a and 3b and the connection portion 3c are the same as the methods and materials described above with reference to FIG.
  • an insulating film 5 is formed so as to cover the gate wiring 3a, the auxiliary capacitance wiring 3b, and the connection portion 3c.
  • an island-shaped oxide semiconductor layer 7a to be a TFT channel layer is formed in the TFT formation region A, and an island-shaped oxide semiconductor layer 7b is formed in the auxiliary capacitance formation region B.
  • the formation method and materials of the insulating film 5 and the oxide semiconductor layers 7a and 7b are the same as those described above with reference to FIG.
  • the insulating film 9 is patterned. As a result, in the TFT formation region A, portions of the insulating film 9 where the source contact and the drain contact are formed are etched to form two openings 11as and 11ad that expose the oxide semiconductor layer 7a.
  • the insulating film 9 covers a region to be a channel in the oxide semiconductor layer 7a and functions as a channel protective film 9a.
  • the auxiliary capacitance forming region B a portion of the insulating film 9 located on the oxide semiconductor layer 7b is etched to form an opening 11b exposing the oxide semiconductor layer 7b.
  • a portion of the insulating film 9 located on the connecting portion 3c and the insulating film 5 therebelow are continuously etched to obtain an opening portion 11c exposing the surface of the connecting portion 3c. It is done.
  • the formation method, material, and etching method of the insulating film 9 are the same as those described above with reference to FIG.
  • a conductive film is deposited on the entire surface of the substrate 1 and then patterned.
  • the source wiring 23as is in contact with the regions located on both sides of the region serving as the channel region in the oxide semiconductor layer 7a inside the openings 11as and 11ad and on the insulating film 9.
  • a drain electrode 23ad are formed.
  • the drain electrode 23ad in the present embodiment has an island pattern that covers a part of the oxide semiconductor layer 7a, and does not extend to the auxiliary capacitance formation region B as in the first embodiment.
  • connection portion 23c is formed in the opening 11c and on the insulating film 9 so as to be in contact with the connection portion 3c.
  • this etching process also removes a portion of the conductive film located on the surface of the oxide semiconductor layer 7b in the auxiliary capacitance formation region B (that is, inside the opening 11b). In this manner, an oxide semiconductor TFT is formed in the TFT formation region A.
  • the material and forming method of the conductive film are the same as those described above with reference to FIG.
  • a protective film 25 is deposited on the entire surface of the substrate 1.
  • the protective film 25 is patterned by photolithography, wet etching, and a resist peeling cleaning process.
  • an opening 27a that exposes the surface of the drain electrode 23ad is formed in the protective film 25.
  • an opening 27b that exposes the surface of the oxide semiconductor layer 7b is formed in the protective film 25.
  • an opening 27c that exposes the connection portion 23c is formed.
  • the material, formation method, and etching method of the protective film 25 are the same as those described above with reference to FIG.
  • a transparent conductive film (for example, an ITO film) is formed on the protective film 25 and in the openings 27a, 27b, and 27c, and the transparent conductive film is patterned.
  • the pixel electrode 29 in contact with the exposed surface of the drain electrode 23ad and the oxide semiconductor layer 7b and the connection portion 29c in contact with the exposed surface of the connection portion 23c are formed.
  • the auxiliary capacitor Cs is formed in the auxiliary capacitor forming region B by this process.
  • the auxiliary capacitance Cs is configured by using the auxiliary capacitance wiring 3b, the oxide semiconductor layer 7b and the pixel electrode 29 as electrodes, and the insulating film 5 as a dielectric.
  • FIG. 5A is a plan view of the pixel portion 201 in the semiconductor device.
  • FIGS. 5B to 5D are gate terminals, source terminals, and gate-source connections of the terminal arrangement region 202 in the semiconductor device, respectively. It is a top view of a part. 6A is along the line II ′ shown in FIG. 5A and the line II-II ′ shown in FIG. 5B or the line III-III ′ shown in FIG. 5C. It is sectional drawing.
  • FIG. 6B is a cross-sectional view taken along the line IV-IV ′ shown in FIG.
  • each pixel portion 201 a source wiring 23as extending along the pixel row direction, a gate wiring 3a and an auxiliary capacitance wiring 3b extending along the pixel column direction are formed.
  • a thin film transistor TFT is formed in the vicinity of a point where the source line 23as and the gate line 3a intersect.
  • the oxide semiconductor layer 7a of the TFT is connected to the source wiring 23as and the drain electrode 23ad in the openings 11as and 11ad of the insulating film 9, respectively.
  • the drain electrode 23ad is electrically connected to the pixel electrode 29 in the opening 27a of the protective film 25.
  • the auxiliary capacitance Cs is formed on the auxiliary capacitance wiring 3b.
  • the oxide semiconductor layer 7b of the auxiliary capacitor Cs is connected to the pixel electrode 29 in a contact hole formed by the opening 11b of the insulating film 9 and the opening 27b of the protective film 25. Accordingly, the pixel electrode 29 also functions as an auxiliary capacitance electrode.
  • the opening 27b is disposed inside the opening 11b.
  • connection portion 3c is connected to the connection portion 23c in the opening portion 11c obtained by etching the insulating film 5 and the insulating film 9 simultaneously.
  • the connection part 23 c is connected to the connection part 29 c in the opening part 27 c of the protective film 25.
  • the connection portion 23c is the insulating film 5 in the opening portion 11c. , 9 (the wall surface of the opening portion 11c), and the end surface of the protective film 25 in the opening portion 27c (the wall surface of the opening portion 27c) is not covered.
  • the opening 27 c is disposed in the opening 11 c when viewed from the normal direction of the surface of the substrate 1.
  • a gate / source connection portion may be formed in the terminal arrangement region 202 of the substrate 1 in some cases.
  • the gate wiring connection portion 3d is directly connected to the source wiring 23as in the opening 11c obtained by etching the insulating film 5 and the insulating film 9 simultaneously.
  • the source wiring 23as is covered with a protective film 25.
  • etching GI / ES simultaneous etching
  • etching on the insulating film 5 to be the gate insulating film and the insulating film 9 for forming the channel protective film (etch stop) and etching of the protective film 25 (Pass etching) are performed.
  • contact holes for the terminal portions are formed.
  • the etching time can be greatly reduced as compared with the conventional method of simultaneously etching the gate insulating film and the protective film. Therefore, similarly to the first embodiment, damage to the etching mask can be reduced.
  • the taper shape of the wall surface of the contact hole can be controlled with higher accuracy.
  • the gate wiring connection portion 3d and the source wiring 23as in the gate / source connection portion are independent of the taper shape of the wall surface of the contact hole of the gate / source connection portion.
  • the connecting portion 3d and the source wiring 23as can be more reliably electrically connected.
  • the island pattern of the drain electrode extends to the auxiliary capacitance Cs and is used as the auxiliary capacitance electrode.
  • the drain electrode is not formed in the auxiliary capacitor Cs.
  • the oxide semiconductor layer 7b in the auxiliary capacitance formation region B functions as an etch stop in the conductive film patterning step (FIG. 4D) for forming the source wiring 23as, the drain electrode 23ad, and the connection portion 23c. It can be realized by doing.
  • the drain electrode is used as the auxiliary capacitance electrode as in the first embodiment, it is necessary to provide a margin so that the drain electrode and the auxiliary capacitance wiring are surely overlapped. For this reason, it is designed so that one of the auxiliary capacitor wiring and the drain electrode has a large planar shape.
  • the width of the drain electrode on the auxiliary capacitor wiring is designed to be larger than the width of the auxiliary capacitance wiring.
  • Each of the drain electrode and the auxiliary capacitance electrode is formed of a metal film or the like, and when the planar shape thereof becomes large, it becomes a factor that the aperture ratio decreases.
  • the width of the oxide semiconductor layer 7b and the pixel electrode 29 is designed to be larger than the width of the auxiliary capacitance line 3b.
  • both the oxide semiconductor layer 7b and the pixel electrode 29 are transparent, and even if these patterns are enlarged, the aperture ratio is not reduced. Therefore, the aperture ratio can be increased as compared with the first embodiment.
  • FIG. 7A to 7C are schematic process cross-sectional views for explaining the method for manufacturing the semiconductor device of the present embodiment. For simplicity, the same components as those in FIG.
  • the gate wiring 3a, the auxiliary capacitance wiring 3b, the connection portion 3c, and the like are formed on the substrate 1 by the same method as in the second embodiment (FIGS. 4A to 4D).
  • the insulating film 5, the oxide semiconductor layers 7a and 7b, the insulating film 9, the source wiring 23as, the drain electrode 23ad, and the connection portion 23c are formed.
  • a protective film 25 and an organic insulating film 36 are formed in this order on the surface of the substrate 1.
  • the protective film 25 for example, an oxide film having a thickness of 50 nm to 300 nm is formed by a CVD method.
  • the organic insulating film 36 is formed, for example, by applying an acrylic resin film having a thickness of 1 ⁇ m or more and 4 ⁇ m or less.
  • the surface of the substrate 1 is preferably planarized by the organic insulating film 36.
  • the protective film 25 is patterned by dry etching using the organic insulating film 36 as a mask.
  • an opening 37a exposing the surface of the drain electrode 23ad is formed in the protective film 25 and the organic insulating film 36.
  • an opening 37b that exposes the surface of the oxide semiconductor layer 7b is formed in the terminal portion formation region C.
  • an opening 37c that exposes the connection portion 23c is formed in the terminal portion formation region C.
  • a transparent conductive film for example, an ITO film
  • the protective film 25 is formed on the protective film 25 and in the openings 37a, 37b, and 37c, and the transparent conductive film is patterned.
  • the pixel electrode 29 in contact with the exposed surface of the drain electrode 23ad and the oxide semiconductor layer 7b and the connection portion 29c in contact with the exposed surface of the connection portion 23c are formed.
  • the pixel electrode 29 also functions as an electrode for the auxiliary capacitor Cs. In this way, the semiconductor device of this embodiment is obtained.
  • the plan view of the semiconductor device of this embodiment is the same as the plan view of the semiconductor device of Embodiment 2 described above with reference to FIG.
  • the openings 27a, 27b, and 27c of the protective film 25 shown in FIG. 5 become the openings 37a, 37b, and 37c of the protective film 25 and the organic insulating film 36 in this embodiment.
  • the cross-sectional view of the source / drain connection portion in the present embodiment is the same as the cross-sectional view of the source / drain connection portion of Embodiment 2 shown in FIG.
  • etching GI / ES simultaneous etching
  • etching on the insulating film 5 for forming the gate insulating film and the insulating film 9 for forming the channel protective film (etch stop), etching of the organic insulating film 36 and the protective film 25 are performed.
  • a contact hole in the terminal portion is formed by etching (pass etching).
  • the etching time can be greatly reduced as compared with the conventional method of simultaneously etching the gate insulating film and the protective film. Therefore, similarly to the above-described embodiment, damage to the etching mask can be reduced.
  • the taper shape of the wall surface of the contact hole can be controlled with higher accuracy.
  • the gate wiring connection portion 3d and the source wiring 23as can be more reliably electrically connected.
  • an overlap margin between the auxiliary capacitance wiring 3b, the oxide semiconductor layer 7b, and the pixel electrode 29 can be provided without reducing the aperture ratio.
  • connection portion 23c even when the connection portion 23c is disconnected inside the contact hole of the terminal portion, it is possible to more reliably secure the electrical connection between the gate wiring 3c and the connection portion 29c. There is also.
  • FIG. 8 is an enlarged cross-sectional view illustrating a terminal portion when disconnection occurs in the connection portion 23c.
  • the wall surface of the opening 11c made of the insulating film 5 and the insulating film 9 does not have a desired taper shape (for example, the wall surface of the opening 11c is substantially perpendicular to the surface of the substrate 1). )
  • the connection 23c formed inside the opening 11c may be disconnected.
  • the protective film 25 is deposited only on the connection portion 23c where the disconnection occurs by a CVD method or the like.
  • connection part 29c deposited in the opening part 37c hardly breaks.
  • the connection 29c and the gate wiring 3c can be electrically connected via the connection 23c.
  • the configuration of the semiconductor device of the present embodiment is not limited to the configuration described above with reference to FIG. 9 and 10 are cross-sectional views showing other examples of the semiconductor device of this embodiment.
  • the organic insulating film 36 is formed on the protective film 25.
  • the organic insulating film 36 is formed on the protective film 15 in the semiconductor device of the first embodiment. It may be formed.
  • the plan view of the semiconductor device shown in FIG. 9 is the same as the plan view of the semiconductor device of the first embodiment shown in FIG.
  • the openings 17b and 17c of the protective film 15 shown in FIG. 2 are openings of the protective film 15 and the organic insulating film 36 in this embodiment.
  • the cross-sectional view of the source / drain connection portion is the same as the cross-sectional view of the source / drain connection portion of the first embodiment shown in FIG. According to the semiconductor device shown in FIG. 9, the same effect as in the first embodiment can be obtained.
  • the connection portion 13 c is disconnected, the electrical connection between the wirings in the terminal portion can be ensured.
  • the protective film 25 and the organic insulating film 36 are also formed in the terminal portion forming region C.
  • the protective film 25 and the organic insulating film are formed in the terminal portion forming region C.
  • the film 36 may not be formed.
  • the protective film 15 and the organic insulating film 36 may not be formed in the terminal portion formation region C.
  • FIGS. 11A to 11C are schematic process cross-sectional views for explaining the method for manufacturing a semiconductor device of this embodiment. For simplicity, the same components as those in FIG.
  • the gate wiring 3a, the auxiliary capacitance wiring 3b, and the connection portion 3c are formed on the substrate 1.
  • the formation method of the gate wiring 3a, the auxiliary capacitance wiring 3b, and the connection portion 3c is the same as the method described above with reference to FIG.
  • the SiNx film 5L and the SiO 2 film 5U are formed in this order so as to cover the gate wiring 3a, the auxiliary capacitance wiring 3b, and the connection portion 3c, whereby the insulating film 5 is formed. obtain. Thereafter, oxide semiconductor layers 7 a and 7 b are formed on the insulating film 5.
  • the SiNx film 5L having a thickness of, for example, 200 nm to 500 nm and the SiO 2 film 5U having a thickness of, for example, 20 nm to 150 nm are formed by CVD.
  • the oxide semiconductor layers 7a and 7b are obtained by forming an IGZO film having a thickness of, for example, 30 nm to 300 nm by sputtering and patterning the film.
  • the method for forming the oxide semiconductor layers 7a and 7b is the same as the method described above with reference to FIG.
  • an insulating film 9 is deposited on the surface of the substrate 1 by the method described above with reference to FIG. Thereafter, an opening for forming a source contact and an opening for forming a drain contact are formed in the insulating film 9 in the TFT formation region A, and the oxide semiconductor layer 7b is exposed in the insulating film 9 in the auxiliary capacitance forming region B. An opening to be formed is formed. At the same time, in the terminal portion formation region C, the insulating film 9 and the insulating film 5 are etched to form openings. Next, a metal film is formed on the insulating film 9 and in the opening of the insulating film 9 by the method described above with reference to FIG. 4 (d), and is patterned to form the source wiring 23as, the drain electrode 23ad, and the connection. A portion 23c is formed.
  • the protective film 25 is formed on the surface of the substrate 1 by forming the SiO 2 film 25L and the SiNx film 25U in this order.
  • the SiO 2 film 25L having a thickness of, for example, 50 nm or more and 150 nm or less and the SiNx film 25U having a thickness of, for example, 50 nm or more and 200 nm or less are formed by CVD.
  • the protective film 25 is patterned by photolithography, wet etching, and resist stripping and cleaning processes. Thereby, in the TFT formation region A, an opening 27a that exposes the surface of the drain electrode 23ad is formed in the protective film 25. In addition, in the auxiliary capacitance formation region B, an opening 27b that exposes the surface of the oxide semiconductor layer 7b is formed. Further, in the terminal portion formation region C, an opening 27c that exposes the connection portion 23c is formed.
  • a transparent conductive film (for example, ITO film) is formed on the protective film 25 and in the openings 27a, 27b, and 27c as described above with reference to FIG. Pattern the film.
  • ITO film transparent conductive film
  • the pixel electrode 29 in contact with the exposed surface of the drain electrode 23ad and the oxide semiconductor layer 7b and the connection portion 29c in contact with the exposed surface of the connection portion 23c are formed.
  • plan view of the semiconductor device of this embodiment is the same as the plan view of the semiconductor device of Embodiment 2 described above with reference to FIG. Further, the cross-sectional view of the source / drain connection portion in the present embodiment is the same as the cross-sectional view of the source / drain connection portion of Embodiment 2 shown in FIG.
  • the same effect as in the second embodiment can be obtained. Further, when a laminated film made of a SiO 2 film and a SiNx film is used as the insulating film (gate insulating film) 5 and the protective film 25, the following merits are obtained.
  • an oxide semiconductor TFT when a single layer of a SiNx film is used as a gate insulating film and a protective film, heat treatment is performed in a state where the oxide semiconductor layer is in contact with SiNx in the manufacturing process. Oxygen can be reduced. In addition, the oxide semiconductor layer is easily damaged by plasma when the SiNx film is formed. As a result, the characteristics of the oxide semiconductor TFT may be deteriorated.
  • the SiO 2 film is used as a single layer as the gate insulating film and the protective film, the above problems do not occur, but the dielectric constant of the SiO 2 film is lower than that of the SiNx film, so In order to ensure this, it is necessary to increase the thickness of the SiO 2 film. For this reason, it becomes a factor causing a decrease in the on-current of the TFT.
  • the gate insulating film and the protective film when a laminated film made of a SiO 2 film and a SiNx film is used as the gate insulating film and the protective film, a sufficient breakdown voltage can be ensured even if it is thinner than the gate insulating film and the protective film made of only the SiO 2 film. Accordingly, it is possible to suppress a decrease in the on-current of the TFT due to the gate insulating film and the protective film. Further, by disposing the SiO 2 film on the film in contact with the oxide semiconductor layer or the film closest to the oxide semiconductor layer in the stacked film, oxygen in the oxide semiconductor layer is reduced by SiNx, or the SiNx film is formed. When forming, the oxide semiconductor layer can be prevented from being damaged by plasma.
  • the insulating film 5 in this embodiment has a laminated structure including an SiO 2 film and an SiNx film, and the uppermost layer of the laminated structure, that is, the layer in contact with the lower surface of the oxide semiconductor layer may be an SiO 2 film.
  • the protective film 25 has a laminated structure including an SiO 2 film and an SiNx film, and the lowermost layer of the laminated structure, that is, the layer located closest to the oxide semiconductor layer may be an SiO 2 film.
  • the insulating film 5 and the protective film 25 both have a laminated structure, but if only one of them has the laminated structure as described above, the above effect can be obtained. . However, if these films 5 and 25 both have the above laminated structure, a more remarkable effect can be obtained.
  • an organic insulating film may be provided between the protective film 25 and the pixel electrode 29 in the semiconductor device of this embodiment.
  • the protective film (SINx / SiO 2 ) 25 may be etched using the organic insulating film as an etching mask (pass etching) separately from the simultaneous etching of the insulating films 5 and 9. Thereby, the taper shape of the opening of the protective film 25 can be controlled while suppressing the surface damage of the organic insulating film.
  • a laminated film made of a SiNx film and a SiO 2 film is used as the insulating film 5 and the protective film 25 in the semiconductor device of the second embodiment.
  • the insulating film in the semiconductor device of the first embodiment is used.
  • 5 and the protective film 15 may be a laminated film made of SiO 2 and SiNx.
  • an organic insulating film as described in Embodiment 3 may be provided between the protective film 15 and the pixel electrode 19.
  • the present invention relates to a circuit substrate such as an active matrix substrate, a liquid crystal display device, a display device such as an organic electroluminescence (EL) display device and an inorganic electroluminescence display device, an imaging device such as an image sensor device, an image input device, and a fingerprint.
  • a circuit substrate such as an active matrix substrate, a liquid crystal display device, a display device such as an organic electroluminescence (EL) display device and an inorganic electroluminescence display device, an imaging device such as an image sensor device, an image input device, and a fingerprint.
  • EL organic electroluminescence
  • the present invention can be widely applied to an apparatus including a thin film transistor such as an electronic apparatus such as a reading apparatus. In particular, it can be suitably applied to large liquid crystal display devices and the like.

Abstract

L'invention concerne un dispositif à semi-conducteurs comprenant : un transistor à couches minces contenant un câblage de grille (3a), un premier film isolant (5), une couche semi-conductrice à oxyde en forme d'îlot (7a), un second film isolant (9), un câblage source (13as), une électrode de drain (13ad) et un film protecteur ; et une section de terminal contenant un premier connecteur (3c) formé à partir du même film conducteur que le câblage de grille, un deuxième connecteur (13c) formé à partir du même film conducteur que le câblage source et l'électrode de drain, et un troisième connecteur (19c) formé sur le deuxième connecteur. Le deuxième connecteur entre en contact avec le premier connecteur au sein d'une première ouverture (11c) prévue pour le premier et le second film isolant. Le troisième connecteur (19c) entre en contact avec le deuxième connecteur au sein d'une seconde ouverture (17c) prévue pour le film protecteur. Le deuxième connecteur (13c) recouvre les surfaces d'extrémité du premier et du second film isolant au niveau de la première ouverture (11c), et ne recouvre pas la surface d'extrémité du film protecteur (15) au niveau de la seconde ouverture (17c). Par conséquent, la forme conique de l'orifice de contact de la section de terminal peut être contrôlée avec une grande précision.
PCT/JP2010/071728 2009-12-09 2010-12-03 Dispositif à semi-conducteurs et procédé de production associé WO2011070981A1 (fr)

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RU2012128513/28A RU2503085C1 (ru) 2009-12-09 2010-12-03 Полупроводниковое устройство и способ его изготовления
JP2011545195A JP5095864B2 (ja) 2009-12-09 2010-12-03 半導体装置およびその製造方法
BR112012013851A BR112012013851A2 (pt) 2009-12-09 2010-12-03 dispositivo semicondutor e método para produzir o mesmo
KR1020127017540A KR101273831B1 (ko) 2009-12-09 2010-12-03 반도체 장치 및 그 제조 방법
CN201080056072.8A CN102652330B (zh) 2009-12-09 2010-12-03 半导体装置及其制造方法
US13/514,081 US8685803B2 (en) 2009-12-09 2010-12-03 Semiconductor device and method for producing same
EP10835902.7A EP2511896B1 (fr) 2009-12-09 2010-12-03 Dispositif à semi-conducteurs et procédé de production associé

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CN (1) CN102652330B (fr)
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RU2503085C1 (ru) 2013-12-27
CN102652330B (zh) 2014-09-17
CN102652330A (zh) 2012-08-29
EP2511896B1 (fr) 2019-05-08
JP2013051421A (ja) 2013-03-14
KR101273831B1 (ko) 2013-06-11
JP5095864B2 (ja) 2012-12-12
EP2511896A1 (fr) 2012-10-17
EP2511896A4 (fr) 2016-08-31
KR20120089773A (ko) 2012-08-13
JP5518966B2 (ja) 2014-06-11
US8685803B2 (en) 2014-04-01
JPWO2011070981A1 (ja) 2013-04-22
BR112012013851A2 (pt) 2019-09-24

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