CN105655349B - 阵列基板及其制作方法、显示面板、显示装置 - Google Patents
阵列基板及其制作方法、显示面板、显示装置 Download PDFInfo
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Abstract
本发明涉及一种阵列基板及其制作方法、显示面板、显示装置,其中的阵列基板包括衬底和依次形成在衬底上的第一导电层、第一绝缘层、半导体层、第二导电层、第二绝缘层和第三导电层;所述第一导电层中的栅极图形、所述半导体层中的有源区图形、所述第二导电层中的源漏极图形形成至少一个薄膜晶体管;所述第二绝缘层中设有所述第三导电层与所述第二导电层之间的连接过孔;在所述连接过孔的设置区域内,所述半导体层还包括隔垫图形。基于此,本发明可以解决有源层的刻蚀工艺会导致源漏金属层的连接过孔形貌异常的问题,并通过对制作工艺的简单调整实现良率的显著提升。
Description
技术领域
本发明涉及显示技术,具体涉及一种阵列基板及其制作方法、显示面板、显示装置。
背景技术
现有的底栅型薄膜晶体管的制作工艺中,有源层的刻蚀工艺通常会对栅极保护层的表面造成一定程度的损伤,使得其表面粗糙而凹凸不平,由此导致沉积在栅极保护层上的源漏金属层存在晶粒粗大的问题。对于后续的制作工艺来说,源漏金属层存在的晶粒粗大问题会导致源漏金属层表面粗糙,从而导致源漏金属层的连接过孔形貌异常、沉积在连接过孔内的ITO断线,以及断线部分的源漏金属层容易被腐蚀等问题,对产品良率有着非常不利的影响。
发明内容
针对现有技术中的缺陷,本发明提供一种阵列基板及其制作方法、显示面板、显示装置,可以解决有源层的刻蚀工艺会导致源漏金属层的连接过孔形貌异常的问题。
第一方面,本发明提供了一种阵列基板,包括衬底和依次形成在衬底上的第一导电层、第一绝缘层、半导体层、第二导电层、第二绝缘层和第三导电层;所述第一导电层中的栅极图形、所述半导体层中的有源区图形、所述第二导电层中的源漏极图形形成至少一个薄膜晶体管;所述第二绝缘层中设有所述第三导电层与所述第二导电层之间的连接过孔;在所述连接过孔的设置区域内,所述半导体层还包括隔垫图形。
可选地,所述第三导电层的形成材料包括透明导电材料。
可选地,还包括设置在所述第一绝缘层与第二绝缘层之间的第四导电层;所述第四导电层的形成材料包括透明导电材料;
所述第三导电层包括像素电极图形而所述第四导电层包括公共电极图形,或者,所述第三导电层包括公共电极图形而所述第四导电层包括像素电极图形。
可选地,所述第一导电层还包括扫描线图形;所述第三导电层还包括数据线图形。
第二方面,本发明还提供了一种阵列基板的制作方法,包括:
在衬底上形成包括栅极图形的第一导电层;
在所述第一导电层和所述衬底上形成第一绝缘层;
在所述第一绝缘层上形成包括有源区图形和隔垫图形的半导体层;
在所述半导体层和所述第一绝缘层上形成包括源漏极图形的第二导电层;
在所述第二导电层、所述半导体层和所述第一绝缘层上形成第二绝缘层;
在所述第二绝缘层上形成第三导电层;
其中,所述第二绝缘层中设有所述第三导电层与所述第二导电层之间的连接过孔;所述隔垫图形位于所述连接过孔的设置区域内。
可选地,所述第三导电层的形成材料包括透明导电材料。
可选地,在形成所述半导体层与形成所述第二绝缘层之间,还包括:
在所述第一绝缘层上形成第四导电层;所述第四导电层的形成材料包括透明导电材料;
其中,所述第三导电层包括像素电极图形而所述第四导电层包括公共电极图形,或者,所述第三导电层包括公共电极图形而所述第四导电层包括像素电极图形。
可选地,所述第一导电层还包括扫描线图形;所述第三导电层还包括数据线图形。
第三方面,本发明还提供了一种显示面板,包括上述任意一种的阵列基板。
第四方面,一种显示装置,包括上述任意一种的显示面板。
由上述技术方案可知,本发明在薄膜晶体管的有源区图形所在的半导体层中设置了可以将第一绝缘层与第二导电层分隔开的隔垫图形,从而可以保障隔垫图形上的源漏金属层的平整度,因此可以解决有源层的刻蚀工艺会导致源漏金属层的连接过孔形貌异常的问题。而相当于现有技术而言,本发明可以通过对制作工艺的简单调整实现良率的显著提升。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作一简单的介绍,显而易见地,下面描述中的附图是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是本发明一个实施例中一种阵列基板的剖面结构示意图;
图2是图1所示的阵列基板的局部俯视结构示意图;
图3是有源层的刻蚀工艺会导致连接过孔断线的原因示意图;
图4是本发明一个实施例中一种阵列基板上的电路结构示意图
图5是本发明一个实施例中一种阵列基板的制作方法的步骤流程示意图;
图6至图13是本发明一个实施例中一种阵列基板的制作流程示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
图1是本发明一个实施例中一种阵列基板的剖面结构示意图。图2 是图1所示的阵列基板的局部俯视结构示意图。可以理解的是,图1 示出了该阵列基板在一个像素内的剖面结构,而图2示出了该阵列基板在一个像素内的隐藏了部分结构的俯视结构。参见图1和图2,该阵列基板包括衬底11和依次形成在衬底11上的第一导电层12、第一绝缘层13、半导体层14、第二导电层15、第二绝缘层16和第三导电层 17;第一导电层12中的栅极图形、半导体层14中的有源区图形AL、第二导电层15中的源漏极图形形成至少一个薄膜晶体管。举例来说,上述衬底11、第一绝缘层13和上述第二绝缘层16可以均由透明且绝缘的材料形成,并主要起到保持两侧结构电绝缘的作用。而在任意一个薄膜晶体管的栅极图形的设置区域内,其源漏极图形在至少两个位置处分别与其有源区图形AL欧姆接触,从而可以在有源区图形AL中形成位于源极与漏极之间的沟道区,实现该薄膜晶体管的功能。当然,根据所应用的具体显示应用的不同,阵列基板可以按照与上述方式相同的方式以第一导电层12中的栅极图形、半导体层14中的有源区图形AL、第二导电层15中的源漏极图形形成任意数量的薄膜晶体管,本发明对此不做限制。
此外,在图示的阵列基板用于组成IPS(In-Plane Switching,平面转换)或者ADS(Advanced Super Dimension Switch,高级超维场转换) 类型的显示装置时,图1中的第三导电层17与第四导电层18可以分别作为用于控制液晶偏转的像素电极与公共电极中的一个,即第三导电层17包括像素电极图形而第四导电层18包括公共电极图形,或者,第三导电层17包括公共电极图形而第四导电层18包括像素电极图形。其中,第四导电层18设置在第一绝缘层13与第二绝缘层16之间,并与第三导电层17一样均由透明导电材料形成。由此,第三导电层17 与第四导电层18的设置区域内可以形成透光的像素开口,并可以控制对应区域内的液晶的偏转。
然而,图1和图2所示的第三导电层17作为像素电极需要与每一像素内的源漏极图形相连,因此第二绝缘层16中设有第三导电层17 与第二导电层15之间的连接过孔H1,而第三导电层17可以在每一像素内通过该连接过孔H1与第二导电层15的源漏极图形相连。特别地,在连接过孔H1的设置区域内,半导体层14还包括隔垫图形PL。
可以理解的是,图1和图2所示的阵列基板的制作过程可以包括若干次在衬底11上进行的构图工艺,而为了说明上述隔垫图形PL的作用,下面以没有设置隔垫图形PL的阵列基板为参照,具体说明未设置隔垫图形PL时有源层的刻蚀工艺会导致连接过孔断线的原因。
图3是有源层的刻蚀工艺会导致连接过孔断线的原因示意图。参见图3,在衬底11上形成第一导电层12和第一绝缘层13之后,需要在图3中未示出的位置形成上述包括有源层图形AL的半导体层14,在此过程中需要对半导体层进行刻蚀,而这一过程可能会使得第一绝缘层13的上表面出现损伤而变得凹凸不平。此后,在第一绝缘层13 上形成第二导电层15的过程中,例如金属沉积的制作过程会在第一绝缘层13上表面的不平整的条件下造成如图所示的第二导电层15的局部晶粒粗大。虽然第二导电层15的局部晶体粗大可能并不会影响第二绝缘层16的上表面平整度以及连接过孔H1的内表面平整度,但是在例如沉积氧化铟锡(ITO)的第三导电层17的制作过程中上述局部晶体粗大的问题会导致如图所示的第三导电层17的局部折断。在折断情况严重的情况下,连接过孔H1内并不能形成第二导电层15与第三导电层17之间的有效连接,形成电路局部断路而导致不良。
而在本发明实施例中可以理解的是,半导体层14中隔垫图形PL 的设置会使得连接过孔H1的设置区域内,第二绝缘层16在隔垫图形 PL的保护下并不会因为半导体层14的刻蚀工艺而表面受到损伤。由此,在该区域内形成的第二导电层15不会出现局部晶粒粗大的情况,从而形成在连接过孔H1内的第三导电层17也不会出现如图3所示的折断的情况。
可以看出,本发明实施例在薄膜晶体管的有源区图形所在的半导体层中设置了可以将第一绝缘层与第二导电层分隔开的隔垫图形,从而可以保障隔垫图形上的源漏金属层的平整度,因此可以解决有源层的刻蚀工艺会导致源漏金属层的连接过孔形貌异常的问题。而相当于现有技术而言,本发明实施例可以通过对制作工艺的简单调整(如半导体层的掩膜图形的调整)实现良率的显著提升。
而可以理解的是,图1和图2仅以IPS或ADS显示模式为例说明了可以通过隔垫图形的设置来解决连接过孔形貌异常的问题,而在本发明的其他实施例中则可以不限制阵列基板所应用的显示装置类型,即阵列基板只需要具有上述至少一个薄膜晶体管、上述连接过孔和上述隔垫图形的结构就可以在各自的具体结构中解决连接过孔形貌异常的问题,本发明对此不做限制。
作为一种阵列基板上电路连接关系的具体示例,图4是本发明一个实施例中一种阵列基板上的电路结构示意图。参见图4,该阵列基板还包括连接多行扫描线(如G1、G2、G3和G4示出的四行扫描线) 的扫描驱动电路21,以及连接多列数据线(如D1、D2、D3、D4和 D5示出的五列数据线)的数据驱动电路22。由此,阵列基板上的像素区域由多行扫描线与多列数据线交叉限定出来,且每一像素内的薄膜晶体管TFT的源漏极图形分别连接第三导电层17在每一像素内的像素电极图形和一列数据线,每一像素内的薄膜晶体管TFT的栅极图形连接一行扫描线。基于此,在扫描驱动电路21依次向多行扫描线输出栅极开启信号的同时,数据驱动电路22可以通过多列数据线向每一像素内的像素电极写入对应的数据电压,以实现阵列基板的显示驱动。可以理解的是,上述多行扫描线可以作为扫描线图形包含在上述第一导电层12中,而上述多列数据线可以作为数据线图形包含在上述第三导电层15中。
基于同样的发明构思,并作为一种阵列基板的制作流程的具体示例,图5是本发明一个实施例中一种阵列基板的制作方法的步骤流程示意图。参见图5,该制作方法包括:
步骤501:在衬底上形成包括栅极图形的第一导电层;
步骤502:在第一导电层和衬底上形成第一绝缘层;
步骤503:在第一绝缘层上形成包括有源区图形和隔垫图形的半导体层;
步骤504:在半导体层和第一绝缘层上形成包括源漏极图形的第二导电层;
步骤505:在第二导电层、半导体层和第一绝缘层上形成第二绝缘层;
步骤506:在第二绝缘层上形成第三导电层;
其中,第二绝缘层中设有第三导电层与第二导电层之间的连接过孔;隔垫图形位于连接过孔的设置区域内。
可以理解的是,本发明实施例的制作方法可以用于上述任意一种阵列基板的制作。举例来说,图6至图13是本发明一个实施例中一种阵列基板的制作流程示意图,本发明实施例的制作方法可以按照下述流程进行:
参见图6,上述步骤501可以具体通过一次构图工艺(第一次)以导电材料在衬底11上形成包括栅极图形的第一导电层12。在第一导电层12包括上述扫描线图形时,扫描线图形也可以也包含在导体材料形成的图案当中。可以理解的是,步骤501可以具体包括金属材料的沉积、金属材料层上光刻胶掩膜层的形成、金属材料层的刻蚀以及光刻胶掩膜层的剥离的过程等等。
参见图7,上述步骤502可以具体通过化学气相沉积(CVD)或其同等方式在第一导电层12上以透明绝缘材料形成第一绝缘层13。
参见图8,上述步骤503可以具体通过一次构图工艺(第二次)以半导体材料形成在第一绝缘层13上形成包括有源区图AL形和隔垫图形PL的半导体层14。可以理解的是,步骤503可以具体包括半导体材料的沉积、半导体材料层上光刻胶掩膜层的形成、半导体材料层的刻蚀以及光刻胶掩膜层的剥离的过程等等。而可以理解的是,现有技术中半导体材料层的刻蚀通常会对第一绝缘层13的上表面造成损伤。
参见图9,上述步骤503与步骤504之间可以具体通过一次构图工艺(第三次)以透明导电材料在第一绝缘层13上形成第四导电层18 的步骤,其中第四导电层18包括公共电极图形。可以理解的是,该步骤可以具体包括透明导电材料的沉积、透明导电材料层上光刻胶掩膜层的形成、透明导电材料层的刻蚀以及光刻胶掩膜层的剥离的过程等等。当然,该步骤也可以在步骤502至步骤505之间的任意一个时刻进行,本发明对此不做限制。
参见图10,上述步骤504可以具体包括在半导体层14和第一绝缘层13上通过一次构图工艺(第四次)以导体材料形成包括源漏极图形的第二导电层15。其中,在第二导电层15包括上述数据线图形时,数据线图形也可以也包含在导体材料形成的图案当中。可以理解的是,步骤504可以具体包括金属材料的沉积、金属材料层上光刻胶掩膜层的形成、金属材料层的刻蚀以及光刻胶掩膜层的剥离的过程等等。
参见图11,上述步骤505可以具体通过化学气相沉积(CVD)或其同等方式以透明绝缘材料在第二导电层15、半导体层14、第一绝缘层13及第四导电层18上形成第二绝缘层16。
参见图12,由于第二绝缘层16中设有第三导电层17与第二导电层15之间的连接过孔H1,而且隔垫图形PL位于连接过孔H1的设置区域内,因此步骤505与步骤506之间还可以具体包括通过一次构图工艺(第五次)在连接过孔H1的设置区域内刻蚀掉部分第二绝缘层16以形成连接过孔H1的流程。可以理解的是,第三导电层17与第二导电层15之间的连接位置通常都是固定的,因此隔垫图形PL的设置位置也是根据连接过孔H1的设置位置进行设置的。
参见图13,上述步骤506可以具体通过一次构图工艺(第六次) 以透明导电材料在第二绝缘层16上形成第三导电层17的步骤,其中第三导电层17包括像素电极图形。可以理解的是,该步骤可以具体包括透明导电材料的沉积、透明导电材料层上光刻胶掩膜层的形成、透明导电材料层的刻蚀以及光刻胶掩膜层的剥离的过程等等。
由此,经过上述流程,本发明实施例的制作方法可以形成如图1 所示的阵列基板的结构。当然,在阵列基板具有其他结构的情况下,本发明实施例的制作方法可以做适应性调整,本发明对此不做限制。
基于同样的发明构思,本发明还提供了一种显示面板,包括上述任意一种的阵列基板。需要说明的是,本发明实施例的显示面板可以是如液晶显示面板或者OLED(OrganicLight-Emitting Diode,有机发光二极管)显示面板的任意一种显示面板。可以理解的是,该显示面板的阵列基板具有上述包括隔垫图形的半导体层的结构,因此可以解决有源层的刻蚀工艺会导致源漏金属层的连接过孔形貌异常的问题,并通过对制作工艺的简单调整实现良率的显著提升。
基于同样的发明构思,本发明实施例提供一种包括上述任意一种阵列基板的显示装置,该显示装置可以为:手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置由于包括上述任意一种阵列基板的阵列基板,因而可以解决同样的技术问题,并取得相同的技术效果。
需要说明的是,在本文中,诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来,而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且,术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下,由语句“包括一个……”限定的要素,并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应做广义理解,例如,可以是固定连接,也可以是可拆卸连接,或一体地连接;可以是机械连接,也可以是电连接;可以是直接相连,也可以通过中间媒介间接相连,可以是两个元件内部的连通。对于本领域的普通技术人员而言,可以根据具体情况理解上述术语在本发明中的具体含义。
本发明的说明书中,说明了大量具体细节。然而能够理解的是,本发明的实施例可以在没有这些具体细节的情况下实践。在一些实例中,并未详细示出公知的方法、结构和技术,以便不模糊对本说明书的理解。类似地,应当理解,为了精简本发明公开并帮助理解各个发明方面中的一个或多个,在上面对本发明的示例性实施例的描述中,本发明的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而,并不应将该公开的方法解释呈反映如下意图:即所要求保护的本发明要求比在每个权利要求中所明确记载的特征更多的特征。更确切地说,如权利要求书所反映的那样,发明方面在于少于前面公开的单个实施例的所有特征。因此,遵循具体实施方式的权利要求书由此明确地并入该具体实施方式,其中每个权利要求本身都作为本发明的单独实施例。
最后应说明的是:以上各实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围,其均应涵盖在本发明的权利要求和说明书的范围当中。
Claims (8)
1.一种阵列基板,其特征在于,包括衬底和依次形成在衬底上的第一导电层、第一绝缘层、半导体层、第二导电层、第二绝缘层和第三导电层;所述第一导电层中的栅极图形、所述半导体层中的有源区图形、所述第二导电层中的源漏极图形形成至少一个薄膜晶体管;所述第二绝缘层中设有所述第三导电层与所述第二导电层之间的连接过孔;在所述连接过孔的设置区域内,所述半导体层还包括隔垫图形,所述隔垫图形与所述有源区图形间隔设置,且所述隔垫图形不作为电容或电容的一部分工作;
还包括设置在所述第一绝缘层与第二绝缘层之间的第四导电层;所述第四导电层的形成材料包括透明导电材料;
所述第三导电层包括像素电极图形而所述第四导电层包括公共电极图形,或者,所述第三导电层包括公共电极图形而所述第四导电层包括像素电极图形。
2.根据权利要求1所述的阵列基板,其特征在于,所述第三导电层的形成材料包括透明导电材料。
3.根据权利要求1至2中任意一项所述的阵列基板,其特征在于,所述第一导电层还包括扫描线图形;所述第三导电层还包括数据线图形。
4.一种阵列基板的制作方法,其特征在于,包括:
在衬底上形成包括栅极图形的第一导电层;
在所述第一导电层和所述衬底上形成第一绝缘层;
在所述第一绝缘层上形成包括有源区图形和隔垫图形的半导体层;
在所述半导体层和所述第一绝缘层上形成包括源漏极图形的第二导电层;
在所述第二导电层、所述半导体层和所述第一绝缘层上形成第二绝缘层;
在所述第二绝缘层上形成第三导电层;
其中,所述第二绝缘层中设有所述第三导电层与所述第二导电层之间的连接过孔;所述隔垫图形位于所述连接过孔的设置区域内,所述隔垫图形与所述有源区图形间隔设置,且所述隔垫图形不作为电容或电容的一部分工作;
在形成所述半导体层与形成所述第二绝缘层之间,还包括:
在所述第一绝缘层上形成第四导电层;所述第四导电层的形成材料包括透明导电材料;
其中,所述第三导电层包括像素电极图形而所述第四导电层包括公共电极图形,或者,所述第三导电层包括公共电极图形而所述第四导电层包括像素电极图形。
5.根据权利要求4所述的阵列基板的制作方法,其特征在于,所述第三导电层的形成材料包括透明导电材料。
6.根据权利要求4至5中任意一项所述的阵列基板的制作方法,其特征在于,所述第一导电层还包括扫描线图形;所述第三导电层还包括数据线图形。
7.一种显示面板,其特征在于,包括如权利要求1至3中任一项所述的阵列基板。
8.一种显示装置,其特征在于,包括如权利要求7所述的显示面板。
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CN110992834A (zh) * | 2019-12-19 | 2020-04-10 | 京东方科技集团股份有限公司 | 一种显示面板和显示装置 |
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