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  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
  • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
  • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
  • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
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  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
  • H10D64/251—Source or drain electrodes for field-effect devices
  • H10D64/257—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/351—Substrate regions of field-effect devices
  • H10D62/357—Substrate regions of field-effect devices of FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
  • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
  • H10D64/251—Source or drain electrodes for field-effect devices
  • H10D64/254—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
  • H10D64/311—Gate electrodes for field-effect devices
  • H10D64/411—Gate electrodes for field-effect devices for FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/851—Dispositions of multiple connectors or interconnections
  • H10W72/874—On different surfaces
  • H10W72/877—Bump connectors and die-attach connectors

Definitions

• the invention relates generally to gallium nitride transistors and, more particularly, to performance improvement and yield enhancement methods associated with the same.
• Gallium nitride materials include gallium nitride and its alloys such as aluminum gallium nitride, indium gallium nitride and aluminum indium gallium nitride. These materials are semiconductor compounds that have a relatively wide, direct bandgap, which permits highly energetic electronic transitions to occur. Gallium nitride materials have a number of attractive properties including high electron mobility, the ability to efficiently emit blue light and the ability to transmit signals at high frequency, among others. Accordingly, gallium nitride materials are being investigated in many microelectronic applications such as transistors and optoelectronic devices.
• gallium nitride material-based devices Despite the attractive properties noted above, a number of challenges exist in connection with developing gallium nitride material-based devices. For example, it may be difficult to grow high quality gallium nitride materials on certain substrates, particularly silicon, due to property difference (e.g., lattice constant and thermal expansion coefficient) between the gallium nitride material and the substrate material. Also, it has been challenging to form gallium nitride material devices meeting the cost requirements for certain applications.
• property difference e.g., lattice constant and thermal expansion coefficient
• High power and medium power gallium nitride microwave transistors are now available and all types use a multifinger structure. Some of the power switching devices described in the research literature also use multifinger structures. Alternative new matrix island based structures are shown herein and these confer significant advantages in all switching applications. Following the practice of all power transistors, the structures are optimized for grounded source circuit applications where it is desirable to minimize the inductance and resistance of the source connection. To this end the transistors are commonly constructed with a series of via connections that subtend the entire vertical structure. These commonly used through- substrate via connections are difficult to manufacture and control. To reach the areas where smaller number of large vias can be made, air bridges may have to be constructed from each of the source connections. See, for example, US. Pat. No. 7,352,016 B2. However, air bridges are a source of manufacturing and handling problems.
• U.S. Patent No. 7,550,821 B2 discloses a nitride semiconductor device in which air bridges are eliminated altogether.
• a plurality of first electrodes and a plurality of second electrodes are formed (spaced apart from each other) on an active region in a nitride semiconductor layer (which is formed on a main surface of a substrate).
• An interlayer insulating film is formed on the nitride semiconductor layer.
• the interlayer insulating film has openings that respectively expose the first electrodes and has a planarized top surface.
• a first electrode pad is formed in a region over the active region in the interlayer insulating film and is electrically connected to the exposed first electrodes through the respective openings.
• the source- substrate contacts are placed adjacent to the active areas and are directly connected to the source electrodes, there is an area increase penalty in this multifinger structure.
• the nitride semiconductor device of Shibata et al. is also accordingly limited by the high on- resistance typical of power switching transistors using conventional multifinger structures.
• US Patent 7,250,641 B2 discloses a nitride semiconductor device that comprises: a silicon substrate; a first aluminum gallium nitride layer formed as a channel layer on the silicon substrate in an island shape; and a second aluminum gallium nitride layer formed as a barrier layer of a first conductive type or i-type on the first aluminum gallium nitride layer.
• the islands disclosed therein are completely isolated from each other with no common gate electrode between them; each island is thus a separate device.
• the embodiments disclosed by Saito et al (e.g. as in Fig. 1) require the juxtaposition of three source electrodes, island to island.
• the island concept disclosed by Saito et al serves only as a separation of isolated devices; i.e. there is no intrinsic mode of operation invoked between the islands.
• the new topology described herein eliminates source connection air bridges and allows the gate electrode to be tracked in up to two additional directions leading to an on-resistance reduction of 1.5 to 5 times compared with conventional multi-finger structures. In this way the large area requirements of ladder (or multifinger structures) are eliminated.
• a few examples of the present invention may be based upon relatively complex silicon based templates. However this, together with the new island based surface topologies, greatly simplify the costly gallium nitride device process steps.
• the present invention eliminates the air bridges that are well known to cause power transistor manufacturing and handling difficulties. Both the older gallium arsenide devices and the newer gallium nitride devices suffer yield losses.
• the present invention provides a topology that in one realization uses a multiplicity of small short vias that make air bridges or through substrate source electrode via connections mechanisms unnecessary. Sources and drains are made to consist only of islands that are reduced in size sufficiently only to allow the positioning of a ball grid or/and via grid within each source and drain. By this unique means bonds are eliminated as well as air bridges.
• a nitride semiconductor device comprising: a substrate; a nitride semiconductor layer formed on a main surface of the substrate; a plurality of first island electrodes and a plurality of second island electrodes spaced apart from each other so as to be alternatively arranged to produce two-dimensional active regions in all feasible areas of the nitride semiconductor layer; a plurality of strip electrodes that are formed in a region between each first island electrode and each second island electrode on the nitride semiconductor layer, and that serve as gate electrodes of a multi-island field effect transistor, where each of the island electrodes is either a drain electrode or a source electrode of the field effect transistor; and a plurality of ball connections, with a ball connection on a surface of each source electrode and each drain electrode.
• the ball connection on the surface of each source electrode may be replaced by a via.
• the ball connection is preferably formed of gold, while the nitride semiconductor layer is preferably a hetero layer consisting of a layer of undoped gallium nitride beneath a layer of undoped aluminum gallium nitride.
• the island electrodes are preferably each a four-sided figure, or preferably triangular shaped. Alternatively, the islands may be a combination of various variants of polygon shapes that allow drain/source juxtapositioning.
• Each gate electrode is preferably attached to a gate pad using a low-resistance means, such as (but not limited to) a metal strap.
• the nitride semiconductor device may further comprising one or more epitaxial layers in between the substrate and the nitride semiconductor layer. Each of the epitaxial layer is lightly doped. Field plates may be inserted within the epitaxial layers.
• source island electrodes are always juxtaposed with drain island electrodes, and a gate always exists between them.
• the via can be eliminated and replaced by a ball grid identical to that used for the drain islands.
• the islands if are each a four-sided figure possessing a two-fold or four-fold symmetry, this allows the gate to run in two directions; if the islands are triangular, then the gate can be run in three directions. As a result the gate track can be much larger for a given dice size.
• the multifinger structure can be abandoned and sources and drains made to consist only of islands.
• the island topology disclosed herein preferably triangular or rectangular island structures, provide numerous advantages over the common multi-finger or interdigitated structure. These island topologies result in the specific transistor resistance being less than 70% of those achieved by equivalent-area multi-finger layouts. More significantly, the effective overall device area ratios are 3 to 5 times superior because of the reduced surface interconnect and pad requirements.
• the present invention provides a device with a larger gate width (or "Wg") within a given active area.
• Wg gate width
• the topologies provide a great increase in the current handling capability per unit overall device area, rather than just within the active area.
• Another inventive aspect of this invention relates to the design of the field plates buried within various epitaxial layers. Because the silicon conductive substrate will produce unwanted increases in the capacitance of the active regions, a lightly doped singular, dual or a series of epitaxial layers of intrinsic silicon material (lightly doped) can be grown on the substrate. The thickness of this or these layers can be varied and a buried conductive layer or a series of layers can be inserted to act as buried field plates. Multiple field plates of various sizes and shapes can be introduced. These field plates reduce the peak electric field near the gate edge that is juxtaposed to the drain and therefore increases the maximum voltage that the transistor can withstand.
• these field plates can be arranged to provide a very even distribution of the electrical stress between the gate edge and the drain edge.
• a unique and exceptionally linear or very high voltage device can be constructed.
• the novel vertical epitaxial silicon based structure can in addition assist with problems related to the mechanical stresses that arise due the disparity between the thermal expansion of silicon and gallium nitride.
• FlG. 1 illustrates a plan view example of a prior art building block structure.
• FIG. 2 illustrates a plan view of an embodiment of the present invention.
• FIG. 3 illustrates a cross section taken along the line I-I' of Fig. 2
• FIG. 4 illustrates a plan view of the embodiment shown in Fig. 2.
• FIG. 5 illustrates a plan of a second embodiment of the present invention.
• FIG. 6 illustrates a plan view of a third embodiment of the present invention.
• FIG. 7 illustrates packaging of the embodiment shown in Fig. 4.
• wafer template and substrate used in the following description include any structure having an exposed surface with which to form the circuit structure of the invention.
• substrate or template are understood to include semiconductor wafers.
• substrate or template are also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon.
• Wafers, templates and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art.
• the term conductor is understood to include semiconductors
• the term insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors.
• the field of the invention pertains generally to high and medium power gallium nitride transistors. More specifically, the invention relates to the transistors that operate at high temperatures where large gallium nitride devices have thermal gradients that impair performance.
• the connection system for each source and/or drain includes a separate thermal sink.
• the small, short vias are able to provide a low resistance connection to the back of the wafer.
• the wafer doping level can be chosen to tailor the resistance to the particular needs of every type of transistor.
• Wafers that are heavily doped enable the formation of positive temperature coefficient resistors that operate reliably over temperature ranges extending to 600 0 K.
• Positive temperature coefficient can be chosen to be between 0.1 1% per 0 K and 1.1% per 0 K using wafer doping levels between lOEl ⁇ cm "3 and 10E18cm "3 .
• the small, short via can be varied in length, depth and/or width to provide appropriate compensation.
• the resistor temperature coefficients can be chosen so that they reach as low as 10% of their room temperature value. Operation in this alternative mode will counteract the natural tendency of gallium nitride devices to reduce their performance at higher temperatures. Transition temperatures from positive to negative temperature coefficients can be chosen between 600 0 K and 900 0 K. While this negative temperature coefficient of resistance is not generally valuable, it is possible to use gold or another suitable dopant to achieve a negative temperature coefficient.
• the new structure and layout may be used and a suitably employed to provide a series source resistance that has a negative temperature coefficient.
• gallium nitride transistor based on the schema proposed herein that exhibits very stable performance over a wide temperature range from below 300 0 K to over 600 0 K. Extremely simple bias methods and very stable, linear performance may be obtained. However the device design difficulty centers around the problem of balancing the positive effects of the source resistance reduction versus the declining performance of the typical of the intrinsic gallium nitride transistors as the temperature increases.
• the vertical arrangements described herein have aspects that notably contribute to the performance of the fabricated transistors. It is known that heavily doped substrates have disadvantages associated with the drain-source and channel-source capacitance. This higher capacitance arises from the fact that the substrate acts as one plate of a capacitor. To obviate the effects of this, a very lightly doped substrate has been used typically. Some of the designs described herein however require a heavily doped bulk substrate. To reduce the capacitance effect another aspect of the vertical structure proposed herein is the novel inclusion of a very lightly doped epitaxial layer or a series of epitaxial layers grown upon the substrate in such a way that an idealized interfacial structure is maintained.
• the present invention provides for a strained layer super lattice, which may assist with the further growth of GaN/ AlGaN heterolayers.
• High quality GaN/ AlGaN heterolayers can be grown over the epitaxial layer or layers by inserting a GaN AIN super lattice over an AIN buffer layer directly grown on the epitaxial layer or layers.
• the epitaxial layer or layers can be grown to extend, for example, over a thickness range of 3 to 20 microns.
• the smaller capacitance is preferred since it can be chosen to be part of the required matching network. However this will require the capacitance to be a minimum and the required epitaxial layer thickness will be at a maximum.
• the 20-micron dimension may be extended to further reduce the capacitance.
• Each or any of the epitaxial layers, where several are used, may contain a buried layer acting as a field plate below the gate.
• the combination of a buried field plate or plates and the conductive substrate obviates the absolute need for metal surface mounted field plates.
• the combination of surface field plates and the proposed buried field plates will provide very high breakdown voltage performance. It is possible, where the epitaxial layer is thin that a buried layer field plate is not required resulting in a simplified process. A choice can be made between reducing drain-source capacitance or alternatively reducing the field stress, resulting in an ideal epitaxial thickness of each transistor application.
• the reduced peak electric field for the transistor device of the present invention compared to a simple transistor device results from reduced field crowding at the drain side edge of the gate electrode. This reduction is attributed to the singular or combinational effects of the novel field plates that act to provide the same stress reduction or additional stress reduction that surface field plates provide.
• the stress reduction leads to improved electrical performance characteristics including increased operation voltage and/or reduced gate leakage current.
• Gallium nitride has a different crystal structure than silicon and when gallium nitride structure is formed on silicon substrates, dislocations may result. Defects and dislocations that are in the vicinity of an active region can greatly impair device performance. Because of the novel layout style of the proposed devices, it is possible to electrically isolate defective individual transistors and remove them from the main structure. Either the gate connection of the defective device can be disconnected or the drain connection or both. In the particular case of a normally-off transistor it may be sufficient to just disconnect the gate electrode. The disconnection mechanism could be based on a fuse or laser methodology. Owing to the leakage current or capacitive coupling involved, it may be additionally necessary to ground the gate electrode to the source electrode.
• a metal-to-metal short circuit can be achieved with a high- energy laser.
• the source electrodes 100 are connected by air bridges 125 to source pads 130, which are further, connected by a large via 135.
• the drain electrodes 120 are connected to a common drain pad 105; and the gate electrodes 110 are connected to a common gate pad 115.
• ten gate electrodes are connected to the gate pad and five drain electrodes are connected to the drain pad.
• the large via is required to make a connection to the back of the substrate (not shown).
• the area required for the nitride semiconductor device is about three times as large as the area of an active region 130 (the area in which source, drain and electrodes are located) . It is possible to reduce the size of an electrode pad, but such reduction in size of the electrode pad is limited in view of the yield.
• FIG. 2 illustrates a unique topology, where the adjacent positioning of the substrate contacts (short vias) does not impair the active area density.
• the gate width is greatly increased for a given active area because the gate runs in two dimensions. There are no limitations, except breakdown voltage and line width limits, upon the on-resistance that can be achieved by this topology.
• each source electrode (100) is accompanied by a via (1 1 1); each source electrode (100) is surrounded by an adjacent drain electrode (120).
• Each drain electrode (120) is accompanied by a drain bump (105), which is often a conventional ball made of gold.
• the gate electrode is shown as 110, which is connected to a gate strap (175) by a contact (106).
• the gate strap (175) also connects to a gate pad (115). In this manner, each island electrodes has its own pad, thereby reducing the size of the overall device.
• the islands, or tiles, shown in Fig. 2, are an embodiment of an overall feature wherein source and drain electrodes must alternate in a two-dimensional topology.
• the source electrode (100) and the drain electrode (120) are preferably formed from titanium and aluminum.
• the gate electrode (1 10) is preferably formed from palladium.
• FIG. 3 illustrates a cross-sectional view taken along I-F of Fig. 2.
• a substrate (155) preferably made of silicon, forms a base upon which successive insulating epitaxial layers 150, 145, and 140 are deposited.
• a buffer layer (135) is deposited upon the epitaxial layer (140), upon which an undoped gallium nitride layer (130) is deposited.
• a final undoped layer of aluminum gallium nitride (125) is deposited upon layer 120.
• Within the three epitaxial layers 150, 145, and 140 are two field plates 160 and 165, which are conductive in nature. These are preferably formed of a dopant of silicon.
• the source electrode is shown as 110, which has via (111) thereon, while a drain electrode is shown at 120.
• a gate electrode 110 sits in between the source electrode (100) and the drain electrode (120), upon which is a layer of oxide (170), preferably silicon nitride.
• a gate strap (175) is shown atop the layer 170.
• FIG. 2 The rectangular equivalent shown in Fig. 2 may be replaced by any four-sided figure without losing the advantages stated.
• the rectangle can be rotated and an alternative use of the rectangle, for example, is shown in FIG. 5.
• FIGS. 4 and 5 are extremely advantageous because they allow for increased gate width.
• the source electrodes and vias are shown as 1 10 and 11 1 respectively, while the drain electrodes and ball connections are shown as 120 and 105, respectively.
• the gate is run in both directions.
• the active useful gate width is not however doubled since some active area is lost in the transition between individual island devices.
• the island topologies of FIGS. 4 and 5 have been found to provide 1.5 to 1.7 times the gate width. The on-resistance of such devices is proportionately lowered.
• the fuse/antifuse (106) serves to join a gate electrode (110) with a gate strap (175); the gate strap (175) connects to a gate pad (175).
• the respective gate widths are: interdigitated, 0.7 meters, rectangular island, 1.1 meters, and triangular island, 1.1 meters.
• a GaN transistor with a 1.4 meter gate width can therefore be made using dice size of less than 3mm x 3mm. Such a device will have an on-resistance of 10- 15 milliohms and will be capable of switching 100 Amperes.
• the island topology allows for the spaces between active devices to be used as connection points.
• a low unit resistance metal strap 175 the problem of metal gate resistance can be eliminated.
• the strap can be placed to act as an auxiliary field plate by positioning it separate from the gate as it transits the active gate-drain channel area. This is shown in FIG. 2 and FIG. 3.
• FIGS. 2, 4, 5 and 6 No provisions for conventional bonds or packages are shown in FIGS. 2, 4, 5 and 6.
• An alternative advantageous packaging technique is shown in a cross-section view in FIG. 7.
• the absence of air bridges allows the dice (200) to be eutectically bonded (via a eutectic bond (205)) to the copper/source heatsink clip (210).
• This can be inverted to allow the gold bump gate (215) and drain (220) connections to be made directly to copper tracks (225) on a multichip assembly.
• This arrangement greatly reduces the overall area of the mounted device compared to packages that use wire bonds and reduces the inductance of the drain and source connections.
• all of the heat dissipation can be removed through the copper track on board, and the copper/source heatsink clip removed.
• the drain, the source and the gate connections all have gold bumps, no via connections, and an insulative high resistance substrate is used.

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• 2010
  • 2010-08-04 EP EP10805910.6A patent/EP2465141B1/en active Active
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  • 2010-08-04 US US13/388,694 patent/US9064947B2/en active Active
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