WO2009144839A1 - 試験装置および情報処理システム - Google Patents
試験装置および情報処理システム Download PDFInfo
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- WO2009144839A1 WO2009144839A1 PCT/JP2008/064349 JP2008064349W WO2009144839A1 WO 2009144839 A1 WO2009144839 A1 WO 2009144839A1 JP 2008064349 W JP2008064349 W JP 2008064349W WO 2009144839 A1 WO2009144839 A1 WO 2009144839A1
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- interrupt
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31907—Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31919—Storing and outputting test patterns
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/2733—Test interface between tester and unit under test
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/277—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault-free response
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Computer Networks & Wireless Communication (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Signal Processing (AREA)
- Tests Of Electronic Circuits (AREA)
- Information Transfer Systems (AREA)
Abstract
Description
1.米国特許出願第61/057206号 出願日 2008年5月30日
Claims (6)
- 被試験デバイスを試験する試験装置であって、
それぞれが前記被試験デバイスと信号を授受する複数の処理部と、
前記複数の処理部を制御する制御装置と、
前記複数の処理部が発生した割り込みの要求を前記制御装置に通知する割込制御部と、
を備え、
前記割込制御部は、
割込イネーブル状態においていずれかの前記処理部から割り込みの要求を受けた場合に、前記制御装置に割り込みを通知するとともに割込ディセーブル状態に遷移し、
前記割込ディセーブル状態において前記処理部から割り込みの要求を受けた場合に、前記制御装置に割り込みを通知せず、
前記割込ディセーブル状態において前記制御装置からの指示を受けた場合に、前記割込イネーブル状態に遷移する
試験装置。 - 前記制御装置は、
前記割込制御部から割り込み要求の通知を受けた場合に、当該割り込みを処理し、
後続の割り込みの要求を受け付け可能となったことに応じて、割り込みの要求の受け入れが可能となったことを前記割込制御部に通知する
請求項1に記載の試験装置。 - 前記割込制御部による割り込みの要求を通知するパケットを生成して、前記制御装置に送信するパケット処理部を更に備える
請求項1から2の何れかに記載の試験装置。 - 前記複数の処理部のそれぞれは、第1レベルから第2レベルに変化した場合に割り込みの要求が発生したことを示す割込信号を出力し、
前記割込制御部は、前記割込ディセーブル状態から前記割込イネーブル状態へ遷移したときに、前記複数の処理部のそれぞれから出力された前記割込信号の少なくとも1つが前記第2レベルの場合には、前記制御装置に割り込みを通知するとともに前記割込ディセーブル状態に遷移する
請求項1から3の何れかに記載の試験装置。 - それぞれが、複数の前記処理部と、前記割込制御部と、信号合成部とを有する1または複数の試験ユニットを備え、
前記信号合成部は、当該試験ユニット内の前記複数の処理部のそれぞれから出力された前記割込信号のうち少なくとも1つが前記第2レベルの場合に、前記第2レベルとなる信号を、当該試験ユニット内の前記割込制御部に供給する
請求項4に記載の試験装置。 - 複数の処理部と、
前記複数の処理部を制御する制御装置と、
前記複数の処理部が発生した割り込みの要求を前記制御装置に通知する割込制御部と、
を備え、
前記割込制御部は、
割込イネーブル状態においていずれかの前記処理部から割り込みの要求を受けた場合に、前記制御装置に割り込みを通知するとともに割込ディセーブル状態に遷移し、
前記割込ディセーブル状態において前記処理部から割り込みの要求を受けた場合に、前記制御装置に割り込みを通知せず、
前記割込ディセーブル状態において前記制御装置からの指示を受けた場合に、前記割込イネーブル状態に遷移する
情報処理システム。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010514326A JPWO2009144839A1 (ja) | 2008-05-30 | 2008-08-08 | 試験装置および情報処理システム |
US12/945,758 US20110208448A1 (en) | 2008-05-30 | 2010-11-12 | Test apparatus and information processing system |
Applications Claiming Priority (2)
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US5720608P | 2008-05-30 | 2008-05-30 | |
US61/057,206 | 2008-05-30 |
Related Child Applications (1)
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US12/945,758 Continuation US20110208448A1 (en) | 2008-05-30 | 2010-11-12 | Test apparatus and information processing system |
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WO2009144839A1 true WO2009144839A1 (ja) | 2009-12-03 |
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Family Applications (4)
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PCT/JP2008/064251 WO2009144837A1 (ja) | 2008-05-30 | 2008-08-07 | 試験装置および情報処理システム |
PCT/JP2008/064349 WO2009144839A1 (ja) | 2008-05-30 | 2008-08-08 | 試験装置および情報処理システム |
PCT/JP2008/064347 WO2009144838A1 (ja) | 2008-05-30 | 2008-08-08 | 試験装置、情報処理システムおよびデータ伝送方法 |
PCT/JP2008/065598 WO2009144844A1 (ja) | 2008-05-30 | 2008-08-29 | 試験装置および試験方法 |
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PCT/JP2008/064251 WO2009144837A1 (ja) | 2008-05-30 | 2008-08-07 | 試験装置および情報処理システム |
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PCT/JP2008/064347 WO2009144838A1 (ja) | 2008-05-30 | 2008-08-08 | 試験装置、情報処理システムおよびデータ伝送方法 |
PCT/JP2008/065598 WO2009144844A1 (ja) | 2008-05-30 | 2008-08-29 | 試験装置および試験方法 |
Country Status (4)
Country | Link |
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US (4) | US20110196638A1 (ja) |
JP (4) | JP4674273B2 (ja) |
KR (4) | KR101137537B1 (ja) |
WO (4) | WO2009144837A1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10288685B2 (en) * | 2014-04-30 | 2019-05-14 | Keysight Technologies, Inc. | Multi-bank digital stimulus response in a single field programmable gate array |
TWI615619B (zh) * | 2016-06-24 | 2018-02-21 | 致伸科技股份有限公司 | 與受測物通訊之方法以及應用該方法之系統 |
TWI653519B (zh) * | 2017-05-03 | 2019-03-11 | 和碩聯合科技股份有限公司 | 配置單元、檢測系統及檢測方法 |
CN114968365B (zh) * | 2022-07-27 | 2022-10-28 | 广州智慧城市发展研究院 | 适配器寄存器单元及包含其的主机适配器电路 |
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WO2008044421A1 (fr) * | 2006-10-12 | 2008-04-17 | Advantest Corporation | Testeur et procédé de commande |
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JPS63213018A (ja) | 1987-02-28 | 1988-09-05 | Ricoh Co Ltd | 外部記憶制御装置 |
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JPH0581165A (ja) * | 1991-09-19 | 1993-04-02 | Fujitsu Ltd | データ転送回路 |
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-
2008
- 2008-08-07 JP JP2010514324A patent/JP4674273B2/ja active Active
- 2008-08-07 KR KR1020107025746A patent/KR101137537B1/ko active IP Right Grant
- 2008-08-07 WO PCT/JP2008/064251 patent/WO2009144837A1/ja active Application Filing
- 2008-08-08 KR KR1020107025609A patent/KR101138198B1/ko active IP Right Grant
- 2008-08-08 JP JP2010514325A patent/JP4674274B2/ja not_active Expired - Fee Related
- 2008-08-08 JP JP2010514326A patent/JPWO2009144839A1/ja active Pending
- 2008-08-08 WO PCT/JP2008/064349 patent/WO2009144839A1/ja active Application Filing
- 2008-08-08 WO PCT/JP2008/064347 patent/WO2009144838A1/ja active Application Filing
- 2008-08-08 KR KR1020107025469A patent/KR101215387B1/ko not_active IP Right Cessation
- 2008-08-29 JP JP2010514329A patent/JP4674275B2/ja active Active
- 2008-08-29 KR KR1020107026131A patent/KR101137539B1/ko active IP Right Grant
- 2008-08-29 WO PCT/JP2008/065598 patent/WO2009144844A1/ja active Application Filing
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2010
- 2010-11-09 US US12/942,915 patent/US20110196638A1/en not_active Abandoned
- 2010-11-12 US US12/945,736 patent/US8942946B2/en active Active
- 2010-11-12 US US12/945,758 patent/US20110208448A1/en not_active Abandoned
- 2010-11-12 US US12/945,731 patent/US8805634B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS5460537A (en) * | 1977-10-24 | 1979-05-16 | Nec Corp | Interruption control unit |
JPS5556259A (en) * | 1978-10-19 | 1980-04-24 | Nec Corp | Interruption circuit |
WO2008044421A1 (fr) * | 2006-10-12 | 2008-04-17 | Advantest Corporation | Testeur et procédé de commande |
Also Published As
Publication number | Publication date |
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JP4674274B2 (ja) | 2011-04-20 |
KR20110005271A (ko) | 2011-01-17 |
JP4674275B2 (ja) | 2011-04-20 |
KR101215387B1 (ko) | 2012-12-26 |
US20110208448A1 (en) | 2011-08-25 |
KR20110005273A (ko) | 2011-01-17 |
JPWO2009144839A1 (ja) | 2011-09-29 |
JPWO2009144837A1 (ja) | 2011-09-29 |
KR101137539B1 (ko) | 2012-04-23 |
KR20110005265A (ko) | 2011-01-17 |
JP4674273B2 (ja) | 2011-04-20 |
WO2009144838A1 (ja) | 2009-12-03 |
US20110208465A1 (en) | 2011-08-25 |
KR20110005283A (ko) | 2011-01-17 |
US20110282616A1 (en) | 2011-11-17 |
JPWO2009144844A1 (ja) | 2011-09-29 |
US20110196638A1 (en) | 2011-08-11 |
KR101137537B1 (ko) | 2012-04-23 |
WO2009144837A1 (ja) | 2009-12-03 |
US8942946B2 (en) | 2015-01-27 |
KR101138198B1 (ko) | 2012-05-14 |
JPWO2009144838A1 (ja) | 2011-09-29 |
WO2009144844A1 (ja) | 2009-12-03 |
US8805634B2 (en) | 2014-08-12 |
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