US20110208448A1

US20110208448A1 - Test apparatus and information processing system

Info

Publication number: US20110208448A1
Application number: US12/945,758
Authority: US
Inventors: Kazumoto Tamura
Original assignee: Advantest Corp
Current assignee: Advantest Corp
Priority date: 2008-05-30
Filing date: 2010-11-12
Publication date: 2011-08-25
Also published as: US20110208465A1; JP4674275B2; KR20110005283A; WO2009144837A1; US8805634B2; WO2009144844A1; KR101138198B1; KR20110005271A; JPWO2009144844A1; KR20110005265A; JP4674274B2; JPWO2009144838A1; WO2009144838A1; KR101137537B1; US8942946B2; KR101215387B1; US20110282616A1; JPWO2009144839A1; JPWO2009144837A1; US20110196638A1

Abstract

Provided is a test apparatus that tests a device under test, comprising a plurality of processing sections that each send and receive signals to and from the device under test; a control apparatus that controls the processing sections; and an interrupt control section that notifies the control apparatus concerning interrupt requests generated by the processing sections, wherein, when an interrupt request is received from a processing section while the interrupt control section is in an interrupt enable state, the interrupt control section notifies the control apparatus concerning the interrupt and transitions to an interrupt disable state; when an interrupt request is received from the processing section while the interrupt control section is in the interrupt disable state, the interrupt control section does not notify the control apparatus concerning the interrupt; and when instructions are received from the control apparatus while the interrupt control section is in the interrupt disable state, the interrupt control section transitions to the interrupt enable state.

Description

BACKGROUND

1. Technical Field
The present invention relates to a test apparatus that tests a device under test and an information processing system.
2. Related Art
A test apparatus for testing a semiconductor device or the like includes one or more test units and a control apparatus. Each test unit supplies a test signal to the device under test.
The control apparatus can be realized as a computer connected to the test units via a serial communication cable or the like. The control apparatus issues an access request to each of the test units to control the test units.
Each test unit includes a processing section such as a pattern generator. Each processing section can request an interrupt for the control apparatus. For example, each processing section can request an interrupt by supplying an interrupt control section in the test unit with an interrupt signal that changes from logic L to logic H. Upon detecting a rising edge of the interrupt signal, the interrupt control section that receives the interrupt signal transmits a packet indicating the interrupt to the control apparatus.
Each test unit may include a plurality of processing sections that request interrupts for the control apparatus. In this case the interrupt control section receives the interrupt signals from the plurality of processing sections and generates a packet indicating an interrupt for each processing section.
However, when sequential interrupt requests are generated in a short time by two processing sections, e.g. a first processing section and a second processing section, the interrupt control section supplies the control apparatus with the interrupt request from the second processing section during or immediately before the execution of the interrupt from the first processing section by the control apparatus. In such a case, the control apparatus cannot properly perform the processes corresponding to the respective interrupt requests.
Furthermore, the interrupt control section may perform an OR operation on the interrupt signals output from the processing sections and generate the packet indicating the interrupt based on an edge of the signal resulting from the OR operation. As a result, even when two processing sections sequentially generate interrupt requests in a short time, the edge indicating the later interrupt request is eliminated, and so the interrupt control apparatus does not receive the interrupt request from the second processing section while executing the process corresponding to the interrupt request from the first processing section.
However, when generating a packet requesting an interrupt based on a signal obtained by performing the OR operation on the interrupt signals output from a plurality of processing sections, even when the process corresponding to the earlier interrupt request is completed, an edge corresponding to the later interrupt request is not generated. Accordingly, in this case, a process such as clearing the signal resulting from the OR operation must be performed after completion of the process corresponding to the earlier interrupt request.

SUMMARY

Therefore, it is an object of an aspect of the innovations herein to provide a test apparatus and an information processing system, which are capable of overcoming the above drawbacks accompanying the related art. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the innovations herein.
According to a first aspect related to the innovations herein, provided is a test apparatus that tests a device under test, comprising a plurality of processing sections that each send and receive signals to and from the device under test; a control apparatus that controls the processing sections; and an interrupt control section that notifies the control apparatus concerning interrupt requests generated by the processing sections. In the test apparatus, when an interrupt request is received from a processing section while the interrupt control section is in an interrupt enable state, the interrupt control section notifies the control apparatus concerning the interrupt and transitions to an interrupt disable state; when an interrupt request is received from the processing section while the interrupt control section is in the interrupt disable state, the interrupt control section does not notify the control apparatus concerning the interrupt; and when instructions are received from the control apparatus while the interrupt control section is in the interrupt disable state, the interrupt control section transitions to the interrupt enable state.
According to a second aspect related to the innovations herein, provided is an information processing system comprising a plurality of processing sections; a control apparatus that controls the processing sections; and an interrupt control section that notifies the control apparatus concerning interrupt requests generated by the processing sections. In the information processing system, when an interrupt request is received from a processing section while the interrupt control section is in an interrupt enable state, the interrupt control section notifies the control apparatus concerning the interrupt and transitions to an interrupt disable state; when an interrupt request is received from the processing section while the interrupt control section is in the interrupt disable state, the interrupt control section does not notify the control apparatus concerning the interrupt; and when instructions are received from the control apparatus while the interrupt control section is in the interrupt disable state, the interrupt control section transitions to the interrupt enable state.
The summary clause does not necessarily describe all necessary features of the embodiments of the present invention. The present invention may also be a sub-combination of the features described above. The above and other features and advantages of the present invention will become more apparent from the following description of the embodiments taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a configuration of a test apparatus 10 according to an embodiment of the present invention.

FIG. 2 shows a configuration of a test unit 12 according to the present embodiment.

FIG. 3 shows state transitions of the interrupt control section 46.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, some embodiments of the present invention will be described. The embodiments do not limit the invention according to the claims, and all the combinations of the features described in the embodiments are not necessarily essential to means provided by aspects of the invention.
FIG. 1 shows a configuration of a test apparatus 10 according to an embodiment of the present invention. The test apparatus 10 tests a device under test such as a semiconductor device. The test apparatus 10 includes one or more test units 12 and a control apparatus 14.
Each test unit 12 sends and receives signals to and from the device under test. For example, each test unit 12 may supply the device under test with a test signal having a waveform corresponding to a test pattern, and judge acceptability of the device under test by comparing a response signal from the device under test to a logic value corresponding to an expected value pattern.
The control apparatus 14 provides an access request to each of the one or more test units 12 to control the test units 12. The control apparatus 14 may be realized as a computer that functions as the control apparatus 14 by executing a program. One or more transmission lines 22, which each have a length of several meters, may be connected between the control apparatus 14 and the one or more test units 12 to transmit serial data.
FIG. 2 shows a configuration of a test unit 12 according to the present embodiment. Each of the one or more test units 12 includes a plurality of processing sections 42, a signal combining section 44, an interrupt control section 46, and a packet processing section 48.
The processing sections 42 send and receive signals to and from the device under test. In the present example, the test unit 12 includes a first processing section 42-1 and a second processing section 42-2. The first processing section 42-1 performs a functional test on the device under test. The second processing section 42-2 supplies DC power supply voltage to the device under test. The second processing section 42-2 also performs a DC test on the device under test.
Each processing section 42 operates according to commands received from the control apparatus 14. In other words, the processing sections 42 are controlled by the control apparatus 14.
Each processing section 42 makes an interrupt request to the control apparatus 14. In the present example, each processing section 42 issues an interrupt signal that is at a first level, e.g. logic level L, when not making an interrupt request to the control apparatus 14 and at a second level, e.g. logic level H, when making an interrupt request to the control apparatus 14. In other words, each processing section 42 generates an interrupt signal that indicates generation of an interrupt request when changing from the first level to the second level.
The signal combining section 44 supplies the interrupt control section 46 in the test unit 12 with a signal at the second level when at least one of the interrupt signals output by the processing sections 42 in the test unit 12 is the second level. When interrupt signals in which the first level is logic level L and the second level is logic level H are supplied from the processing sections 42, the signal combining section 44 supplies the interrupt control section 46 with a signal obtained as the logical sum of the received interrupt signals.
The interrupt control section 46 notifies the control apparatus 14 concerning the interrupt requests generated by the processing sections 42. A detailed explanation of the control of the interrupt control section 46 is provided in FIG. 3.
The packet processing section 48 receives, via the transmission line 22, a packet that includes a command or response transmitted from the control apparatus 14 to the test unit 12. The packet processing section 48 extracts the command or response included in the packet. The packet processing section 48 then sends the extracted command or response to a destination processing section 42 indicated by the command or response.
The packet processing section 48 receives the responses or commands to be sent from the signal combining sections 44 to the control apparatus 14. The packet processing section 48 generates a packet including the received commands or responses. The packet processing section 48 transmits the generated packet to the control apparatus 14 via the transmission line 22.
Furthermore, the packet processing section 48 generates a packet providing notification about the interrupt request by the interrupt control section 46, and sends this packet to the control apparatus 14. After transmitting the packet providing interrupt request notification to the control apparatus 14, the packet processing section 48 receives from the control apparatus 14 a packet indicating that subsequent interrupt requests can be received and processed. The packet processing section 48 then notifies the interrupt control section 46 that subsequent interrupt requests can be received and processed.
FIG. 3 shows state transitions of the interrupt control section 46. The interrupt control section 46 transitions between an interrupt enable state ST100 and an interrupt disable state ST200, and switches the control process depending on the state.
First, in an initial state, the interrupt control section 46 transitions to the interrupt enable state ST100. When the interrupt control section 46 receives an interrupt request from a processing section 42 while in the interrupt enable state ST100, the interrupt control section 46 notifies the control apparatus 14 concerning this interrupt request. In other words, when at least one of the interrupt signals changes from the first level to the second level, which in the present corresponds to the signal output by the signal combining section 44 changing from the first level to the second level, while the interrupt control section 46 is in the interrupt enable state ST100, the interrupt control section 46 causes the packet processing section 48 to send a packet providing notification of the interrupt request to the control apparatus 14. At the same time, when the interrupt control section 46 receives an interrupt request from one of the processing sections 42 while in the interrupt enable state ST100, the interrupt control section 46 transitions from the interrupt enable state ST100 to the interrupt disable state ST200.
Here, when notification of the interrupt request is received from the interrupt control section 46, the control apparatus 14 processes the interrupt. Upon completing processing of the interrupt and becoming able to receive and process a subsequent interrupt request, the control apparatus 14 notifies the interrupt control section 46 that an interrupt request can be received. For example, the control apparatus 14 may transmit to the test unit 12, via the transmission line 22, a packet notifying the interrupt control section 46 that a subsequent interrupt request can be received. Furthermore, the processing section 42 in the test unit 12 that requested the interrupt changes the interrupt signal output therefrom from the second level to the first level in response to the control apparatus 14 completing the processing of the interrupt.
When an interrupt request is received from a processing section 42 while in the interrupt disable state ST200, the interrupt control section 46 does not notify the control apparatus 14 concerning the interrupt request. In other words, even when at least one of the interrupt signals changes from the first level to the second level while the interrupt control section 46 is in the interrupt disable state ST200, the interrupt control section 46 does not transmit a packet providing notification of the interrupt request to the control apparatus 14.
When instructions are received from the control apparatus 14 while in the interrupt disable state ST200, the interrupt control section 46 transitions from the interrupt disable state ST200 to the interrupt enable state ST100. More specifically, upon receiving notification from the control apparatus 14 that an interrupt request can be received, the interrupt control section 46 transitions to the interrupt enable state ST100.
In this way, the interrupt control section 46 transitions to the interrupt disable state ST200 during a period from when notification concerning the interrupt request is provided to the control apparatus 14 to when the control apparatus 14 becomes able to receive an interrupt request. As a result, during this period, the interrupt control section 46 does not notify the control apparatus 14 about other interrupts. Accordingly, the control apparatus 14 can correctly process each interrupt.
Furthermore, when the interrupt control section 46 has transitioned from the interrupt disable state ST200 to the interrupt enable state ST100, if at least one of the interrupt signals output by the processing sections 42 is the second level, the interrupt control section 46 transitions back to the interrupt disable state ST200 and notifies the control apparatus 14 about the interrupt. In the present example, when the interrupt control section 46 has transitioned from the interrupt disable state ST200 to the interrupt enable state ST100, if the signal output by the signal combining section 44 is the second level, the interrupt control section 46 transitions back to the interrupt disable state ST200 and notifies the control apparatus 14 about the interrupt. As a result, the interrupt control section 46 can notify the control apparatus 14 about each interrupt request without performing a process such as clearing the interrupt signals output by the processing sections 42 after the control apparatus 14 completes the process corresponding to the interrupt request.
While the embodiments of the present invention have been described, the technical scope of the invention is not limited to the above described embodiments. It is apparent to persons skilled in the art that various alterations and improvements can be added to the above-described embodiments. It is also apparent from the scope of the claims that the embodiments added with such alterations or improvements can be included in the technical scope of the invention.
The technology described via the above embodiments is not limited to use in a test apparatus 10, and can be applied in a common information processing system. For example, the technology described via the above embodiments can be applied in an information processing system that includes one or more processing units that process information and a control apparatus that controls the processing units. In this case, the test units of the information processing system have the same function and configuration as the test units 12 according to the above embodiments and the control apparatus of the information processing system has the same function and configuration as the control apparatus 14 according to the above embodiments.

Claims

1. A test apparatus that tests a device under test, comprising:

a plurality of processing sections that each send and receive signals to and from the device under test;

a control apparatus that controls the processing sections; and

an interrupt control section that notifies the control apparatus concerning interrupt requests generated by the processing sections, wherein

when an interrupt request is received from a processing section while the interrupt control section is in an interrupt enable state, the interrupt control section notifies the control apparatus concerning the interrupt and transitions to an interrupt disable state,

when an interrupt request is received from the processing section while the interrupt control section is in the interrupt disable state, the interrupt control section does not notify the control apparatus concerning the interrupt, and

when instructions are received from the control apparatus while the interrupt control section is in the interrupt disable state, the interrupt control section transitions to the interrupt enable state.

2. The test apparatus according to claim 1, wherein

when an interrupt request notification is received from the interrupt control section, the control apparatus processes the interrupt, and

the control apparatus notifies the interrupt control section that an interrupt request can be received, in response to the control apparatus becoming able to receive and process a subsequent interrupt request.

3. The test apparatus according to claim 1, further comprising a packet processing section that generates a packet providing notification concerning interrupt requests by the interrupt control section and transmits the packet to the control apparatus.

4. The test apparatus according to claim 1, wherein

each processing section outputs an interrupt signal indicating that an interrupt request is generated when changing from a first level to a second level, and

when the interrupt control section has transitioned from the interrupt disable state to the interrupt enable state, if at least one of the interrupt signals output by the processing sections is the second level, the interrupt control section notifies the control apparatus concerning the interrupt and transitions to the interrupt disable state.

5. The test apparatus according to claim 4, comprising one or more test units that each include a plurality of the processing sections, the interrupt control section, and a signal combining section, wherein

in each of the one or more test units, when at least one of the interrupt signals output by the processing sections is the second level, the signal combining section supplies the interrupt control section with a signal at the second level.

6. An information processing system comprising:

a plurality of processing sections;

a control apparatus that controls the processing sections; and