WO2008044421A1

WO2008044421A1 - Tester and control method

Info

Publication number: WO2008044421A1
Application number: PCT/JP2007/067764
Authority: WO
Inventors: Norio Kumaki
Original assignee: Advantest Corporation
Priority date: 2006-10-12
Filing date: 2007-09-12
Publication date: 2008-04-17
Also published as: TW200817702A; JPWO2008044421A1; KR20090077822A; JP5008673B2

Abstract

A tester for testing a device under test comprises a control processor for executing a test program to test the device under test, a test unit connected to the device and adapted to test the device according to an instruction of the control processor, and relay modules connected to the control processor and test unit and adapted to relaying a control instruction from the control processor to the test unit. Each relay module has a buffer section for buffering a control instruction to be written at the address allocated to the unit under test by the control processor, a timing storage section storing the timing at which a control instruction received from the control processor is transmitted to the unit under test, and a buffer control section for transmitting a control instruction buffered in the buffer section to the unit under test at the timing stored in the timing storage section.

Description

Specification

Test apparatus and control method

Technical field

[0001] The present invention relates to a test apparatus and a control method. In particular, the present invention relates to a test apparatus and a control method for transmitting a control command from a control processor to a test unit in order to control a test unit for testing a device under test. This application is related to the following US patent applications: For designated countries where incorporation by reference of documents is permitted, the contents described in the following application are incorporated into this application by reference and made a part of this application.

1. Application No. 11/546, 926 Application 曰 October 2006 曰

2. Application No. 11/546, 929 Application 10 October 2006 曰

Background art

[0002] A control processor provided in a test apparatus operates based on an installed control program and transmits a command to a test unit. This allows the control of the test unit, eg the force S to start the test unit properly or change the settings of the active test unit.

[0003] However, the order of instructions to be processed is determined according to the specifications of the test unit. If the execution order of instructions violates the specifications, the test unit and the device under test may be damaged. There is a risk that. For this reason, the programmer creates a control program to execute instructions in an order that complies with this specification!

[0004] In addition, in the test unit, a timing at which an instruction is to be executed is determined according to the specification. For example, after a voltage change, the test unit may malfunction due to an unstable voltage, such as waiting for a predetermined period before executing the next command! /. For this reason, the programmer appropriately inserts an instruction that waits for a certain period of time without executing the instruction into the control program.

[0005] In addition, a certain instruction is determined to be executed at a timing when the test unit is in a predetermined state. As a method for detecting such a state change, a control process is used. Polling by the server or interrupt processing from the test unit to the control processor can be considered.

[0006] For reference technology relating to a semiconductor test apparatus, refer to Patent Document 1.

[0007] Patent Document 1: Japanese Patent Laid-Open No. 11 64450

Disclosure of the invention

Problems to be solved by the invention

[0008] The instruction to wait for a certain period of time can be realized, for example, by setting a waiting time in a timer outside the control processor and generating an interrupt from the timer to the control processor. In addition, it can be realized by causing an unnecessary process such as an idle loop in the control program or by performing a standby process by the function of the operating system that controls the control processor.

However, the time that the force control processor waits may be different from the time assumed by the programmer. This is because the instruction execution timing varies. For example, when the control processor receives various interrupts and performs other processes, or when multiple tasks are executed in a time-sharing manner, the instruction execution timing may be delayed. As a result, if the timing of instruction execution is advanced due to variations in execution timing, a sufficient waiting time cannot be secured and the next process may be performed, which may damage the test unit.

[0010] In order to avoid such a situation, the programmer creates a control program so as to ensure a standby time sufficiently longer than the actually required standby time. As a result, the time required to change the setting is significantly longer than originally required, which may reduce the overall efficiency of the test process.

[0011] Polling by the control processor refers to a process of periodically reading out a register in the test unit from the control processor and detecting a change in state based on a change in the value. However, the process of reading the value from the register may require an I / O wait time for the control processor, which takes a longer time compared to the instruction execution of the control processor, and the control processor's computing power may not be effectively utilized. there were.

On the other hand, if an attempt is made to implement interrupt processing, each test unit needs a mechanism for realizing an interrupt, which may complicate the design of the entire test apparatus. Furthermore, If an attempt is made to detect an error quickly, the presence or absence of an interrupt must be checked frequently, and the operating system that controls the interrupt may increase the processing load on the control processor.

[0013] As described above, in order to quickly and appropriately detect a change in the state of the test unit, the control processor is required to have a high computing capacity. For this reason, even in a test apparatus having a plurality of test units, a control processor is required for each test unit, and a large number of control processors are mounted in the test apparatus. An increase in the number of control processors can increase the size and cost of the test equipment and its cooling equipment, which in turn can increase the failure rate of the test equipment.

Means for solving the problem

[0014] Accordingly, an object of one aspect of the present invention is to provide a test apparatus and a control method that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

That is, according to the first aspect of the present invention, a test apparatus for testing a device under test, which is connected to a control processor that executes a test program for testing the device under test, and the device under test, A test unit that tests the device under test according to an instruction from the control processor, and a relay unit that is connected to the control processor and the test unit and relays a control command transmitted from the control processor to the test unit. The buffer unit for notifying the control instruction to be written to the address assigned to the test unit from the control processor, and the timing for transmitting the control instruction received from the control processor to the test unit are stored. In response to the arrival of the timing stored in the timing storage unit and the timing storage unit, A control command buffered in § portion, to provide a test device having a buffer control unit to be transmitted to the test unit.

[0016] According to the second aspect of the present invention, a control processor that executes a test program for testing a device under test, and a test that is connected to the device under test and tests the device under test according to an instruction from the control processor. A control method for controlling a test apparatus comprising a unit and written to an address assigned to the test unit by a control processor. The control instruction to be buffered, the timing received when the control instruction should be sent to the test unit is stored, and the buffered control instruction is sent to the test unit when the timing is reached A control method is provided.

[0017] In a third aspect of the present invention, there is provided a test apparatus for testing a device under test, a control processor for executing a test program for testing the device under test, and a control processor connected to the device under test. A test unit that tests the device under test according to the instructions of the device, and a relay unit that is connected to the control processor and the test unit and relays control commands transmitted from the control processor to the test unit. The relay unit is a polling unit that repeatedly reads the status register that indicates the status of the test unit specified by the control processor, and the value of the status register reaches the expected value specified by the control processor. And a processing control unit that transmits a control command to be processed by the test unit to the test unit after the value of the status register reaches the expected value. To provide.

[0018] In the fourth embodiment of the present invention, a control processor that executes a test program for testing the device under test and a device under test connected to the device under test and in response to an instruction of the control processor. A control method for controlling a test apparatus comprising a test unit for testing a test unit, wherein a status register indicating the status of the test unit designated by the control processor is repeatedly read, and the value of the status register is designated by the control processor. A control method is provided to send a control command to be processed by the test unit to the test unit after the status register value reaches the expected value in response to the expected value.

[0019] Note that the above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

Brief Description of Drawings

FIG. 1 shows the overall configuration of the test apparatus 10.

[FIG. 2] The functional configuration of the relay unit 20 is shown.

FIG. 3 shows a functional configuration of the buffer control unit 35.

FIG. 4 shows the flow of processing for relaying instructions from the control processor 15 to the test unit 40 by the relay unit 20.

FIG. 5 shows details of processing in S420 of FIG. FIG. 6 shows details of processing in S430 of FIG.

FIG. 7 shows a first example of an instruction group buffered in the buffer unit 200.

FIG. 8 shows a second example of an instruction group buffered in the buffer unit 200.

FIG. 9 shows an overall configuration of a test apparatus 10 in a modification of the present embodiment.

FIG. 10 shows an example of an instruction group buffered in the buffer unit 200 in a modification of the present embodiment.

Explanation of symbols

[0021] 10 ··· Test equipment, 15 · · · Control processor, 20 · · · Relay unit, 40 · · · Test unit, 50 · · Device under test, 100 · 'Test program, 400 · · · Status register 410 ··· Status register 30 ··· Processing control unit 200 · 'Buffer unit 210 · · · Timing storage unit 220 · · Condition storage unit 230 · Polling unit 35 'Buffer control section, 300 ... Extraction section, 310 ... Write section, 320 ... Detection section, 330 ... Transmission section

BEST MODE FOR CARRYING OUT THE INVENTION

[0022] Hereinafter, (1) aspect of the present invention will be described through embodiments of the present invention. However, the following embodiments are not limited to the invention according to the claims and are described in the embodiments. Not all combinations of features are essential for the solution of the invention.

FIG. 1 shows the overall configuration of the test apparatus 10. The test apparatus 10 includes a control processor 15, a plurality of relay units 20, and a plurality of test units 40. The control processor 15 executes a test program 100 for testing the device under test. The control processor 15 may execute a plurality of test programs 100, each controlling a different test unit 40! /. Each of the multiple test programs 100 is an operating system equipped with an execution mechanism called multitask, multiprocess, or multithread! /, And the computer resources of the control processor 15 are time-divided in parallel. May be executed.

Each of the plurality of test units 40 is provided corresponding to each of the plurality of devices under test 50. Each of the plurality of test units 40 is connected to the corresponding device under test 50 and tests the device under test 50 in accordance with an instruction from the control processor 15. Each of the plurality of test units 40 has a status register that indicates the status of the test unit 40. For example, each of the plurality of test units 40 has a first A status register 400 which is an example of the second status register, and a status register 410 which is an example of the second status register. In the figure, only one test unit 40 has a force S illustrating the status registers 400, 410, and each other test unit 40 may also have a status register. Each of the plurality of test units 40 stores the state of the test unit 40 in these state registers in accordance with the state change due to the progress of the test.

Each of the plurality of relay units 20 is provided corresponding to each of the plurality of test units 40. Each of the plurality of relay units 20 is connected to the control processor 15 and the corresponding test unit 40. Each of the plurality of relay units 20 relays a control command transmitted from the control processor 15 to the corresponding test unit 40. Specifically, the storage area in the relay unit 20 and the storage area in the test unit 40 are mapped to a virtual address space in which the test program 100 operates on the control processor 15. Then, the control processor 15 executes a write command in the test program 100 to write to the virtual address space, that is, the relay unit 20 or the test unit 40. The control command for the test unit 40 is, for example, a command for setting / changing the magnitude of the voltage applied from the test unit 40 to the device under test 50, and setting / changing the frequency of the test signal. Or an instruction to start the test sequence.

The relay unit 20 receives the write data for the address space allocated to the test unit 40 from the control processor 15 and transfers it to the test unit 40 as it is. On the other hand, the relay unit 20 performs write processing on the register or memory in the relay unit 20 according to the content of the write data for the address space allocated to the relay unit 20. The relay unit 20 controls the instruction transfer timing according to the written contents. For example, the relay unit 20 may transmit data such as a control command received following the write data to the test unit 40 after waiting for a time indicated by the write data.

As described above, the test apparatus 10 according to the present embodiment controls the timing of transmitting a command to the test unit 40 by the relay unit 20 provided separately from the control processor 15. As a result, the processing load on the control processor 15 is reduced and the control command transmission is reduced. The purpose is to control the timing accurately.

Next, a functional configuration of one relay unit 20 among the plurality of relay units 20 will be described.

FIG. 2 shows a functional configuration of the relay unit 20. The relay unit 20 includes a processing control unit 30, a buffer unit 200, a timing storage unit 210, a condition storage unit 220, and a polling unit 230. As an example of implementation, the buffer unit 200, the timing storage unit 210, and the condition storage unit 220 are implemented by a storage medium such as a register and a memory, and the polling unit 230 and the processing control unit 30 are implemented by a sequencer. . First, the processing function when the control processor 15 writes the timing at which the control command should be transmitted to the test unit 40 prior to writing the control command to the address assigned to the test unit 40 will be described. . The buffer unit 200 should be written from the control processor 15 to the timing value to be written from the control processor 15 for the address assigned to the relay unit 20 and the address assigned to the corresponding test unit 40. Buffer control instructions sequentially.

Specifically, the buffer unit 200 sequentially receives the timing write command for writing the timing value and the control command write command for writing the control command received from the control processor 15. The timing write command is, for example, a set of an address in the address space allocated to the relay unit 20 and a timing value to be written to the address. On the other hand, the control command write command is, for example, a set of an address in the address space allocated to the test unit 40 and a control command to be written to the address.

The timing storage unit 210 stores the timing at which the control command received from the control processor 15 should be transmitted to the test unit 40. This timing is stored as a timing value by the buffer control unit 35 in accordance with the timing write command. The processing control unit 30 has a buffer control unit 35. In addition to storing the above timing value, the buffer control unit 35 controls the transmission timing of the control command received after the timing write command. Specifically, the buffer control unit 35 responds to the test instruction buffered in the buffer unit 200 in response to the arrival of the timing stored in the timing storage unit 210. Sent to Test Unit 40. This timing value is, for example, a delay amount for delaying transmission of a control command received subsequently. That is, the buffer control unit 35 delays the processing of the control command write command received after the timing write command until the timing is reached in response to the output of the buffer unit 200 and the timing write command. Let

[0032] Next, after the control processor 15 writes the address and expected value of the status register in the address space allocated to the test unit 40 to the address allocated to the relay unit 20, the test unit The processing function for writing a control command to the address assigned to 40 is explained. The condition storage unit 220 stores the address of the status register indicating the status of the test unit 40 received from the control processor 15 and the expected value compared with the value of the status register. These addresses and expected values are stored by the buffer control unit 35. That is, when the buffer control unit 35 obtains a condition write command for writing the address and expected value of the status register from the buffer unit 200, the buffer control unit 35 stores the address and expected value in the condition storage unit 220.

It should be noted that the address of the status register may be a virtual address in the control processor 15 assigned to the status register, as well as the status register number and other identification information.

[0034] The polling unit 230 repeatedly reads out a status register (one or both of the status register 400 and the status register 410 depending on the designation of the control processor 15) designated by the control processor 15 and indicating the status of the test unit 40. . Specifically, polling unit 230 tests a read command with the address of the status register (that is, the address stored in condition storage unit 220) as the read address in response to obtaining the condition write command from nother unit 200. Issue repeatedly to unit 40. In response to the read status register value having reached the expected value specified by the control processor 15, the processing control unit 30 performs processing after the status register value has reached the expected value. Control command to be sent to test unit 40. The control instruction to be processed after the value of the status register reaches the expected value is, for example, an instruction written by a control instruction write command received after the conditional write command. That is, the buffer control unit 35 receives the control command write command received after the conditional write command in response to the value of the status register reaching the expected value. Send to 0.

Alternatively or in addition, the buffer control unit 35 should transmit a subsequent control instruction from the control processor 15 in response to the value of the status register becoming an expected value. An interrupt may be issued to the control processor. This process is effective when a series of test processes have been completed. That is, for example, the buffer controller 35 issues an interrupt to the control processor 15 and restarts the control processor 15, so that the next test can be started with the force S.

FIG. 3 shows a functional configuration of the buffer control unit 35. The buffer control unit 35 includes an extraction unit 300, a writing unit 310, a detection unit 320, and a transmission unit 330. The extraction unit 300 sequentially extracts the write commands buffered in the buffer unit 200. The extraction unit 300 may extract one write command from the top of the FIFO buffer unit 200 in response to a write completion notification from the writing unit 310 or a transmission completion notification from the transmission unit 330. In addition, the take-out unit 300 may immediately delete the write command from the buffer unit 200 after taking out the write command for the relay unit 20, or the write command after the completion of the processing corresponding to the write command. You can delete the command from the buffer part 200! /.

The writing unit 310 is an example of the timing writing unit according to the present invention, and stores the timing in the timing storage unit 210 in response to taking out the timing writing command. Further, the writing unit 310 stores the address of the state register and the expected value in the condition storage unit 220 in response to taking out the conditional writing command. The detection unit 320 detects the arrival of the timing stored in the timing storage unit 210. Further, the detection unit 320 detects the force at which the value of the status register read by the polling unit 230 becomes the expected value.

Transmitting section 330 transmits the control command write command received after the timing write command to test unit 40 on condition that the arrival of timing is detected. In addition, the transmission unit 330 transmits the control command write command received after the conditional write command to the test unit 40 on condition that the value of the status register becomes the expected value.

FIG. 4 shows a flow of processing for relaying an instruction from the control processor 15 to the test unit 40 by the relay unit 20. The buffer unit 200 is a control command to be written from the control processor 15 to the address assigned to the test unit 40 or the relay unit 20. Is buffered (S400). The extraction unit 300 sequentially extracts the write commands buffered in the buffer unit 200 (S410). If the extracted write command is a write command for the address space assigned to the relay unit 20, the relay unit 20 writes to the timing storage unit 210 or the condition storage unit 220 (S420). If the extracted write command is a write command for the address of the status registers 400 and 410 of the test unit 40, the relay unit 20 performs transmission processing of the control command (S430).

FIG. 5 shows details of the processing in S420 of FIG. The writing unit 310 determines whether or not the extracted command force is an S timing write command (S500). If it is a timing write command (S500: YES), the writing unit 310 stores the timing designated by the timing write command in the timing storage unit 210 (S510). If it is a conditional write command (S52 0: YES), the writing unit 310 causes the condition storage unit 220 to store the condition for transmitting the subsequent control instruction, that is, the address of the status register and the expected value (S530). .

FIG. 6 shows details of the processing in S430 of FIG. The detection unit 320 is a timing storage unit

The arrival of the timing stored in 210 is detected (S600). When the arrival of timing is detected or when the timing is not set in the first place (S600: YES), the detection unit 320 has the value of the status register set to the expected value specified by the control processor 15. Is determined (S610). In this determination, the value of the status register may be used for the determination after being masked with a predetermined mask value. Specifically:

Yes

First, the control processor 15 specifies whether or not to mask each bit of the value of the status register read by the polling unit 230 as the expected value when writing the address and expected value of the status register. The mask value and the expected value after mask indicating the value that should be satisfied by the masked status register value are written in the condition storage unit 220. Then, the polling unit 230 reads the value of the status register and determines whether or not the value obtained by masking the value of the status register with the mask value becomes the expected value after masking.

[0043] Then, when the arrival of the timing is detected and the value of the status register reaches the expected value (S600: YES, S610: YES), the detection unit 320 of the buffer control unit 35 performs the condition writing. Control command write command received after command or timing write command It is transmitted to the test unit 40 (S620). If a mask value is specified in the status register, the masked value must be the expected value after masking.

[0044] In the case where the arrival of timing is not detected or the value of the status register becomes the expected value! /, NA! /, The processing control unit 30 obtains the conditional write command from the buffer unit 200. Then, it is determined whether or not the force has passed the preset time-out time (S630). If! /? Has passed (S630: YES), the process control unit 30 issues a timeout interrupt to the control processor 15 (S640). As a result, even if a condition has been set but it does not hold due to a failure, etc., or even if the set condition has an error and the condition does not hold, error detection processing and the next test are performed. It can be started properly.

[0045] Upon receiving this interrupt, the control processor 15 erases the contents of the buffer unit 200 and allows the relay unit 20 to issue an instruction to erase the contents of the buffer unit 200 so that the next processing can be started correctly. May be issued. In this case, when receiving this command, the relay unit 20 erases the write command in the buffer unit 200 without buffering in the software unit 200. As another example, the control processor 15 may issue an instruction for reading the contents of the buffer unit 200 to the relay unit 20. In this case, when receiving this command, the relay unit 20 reads the write command from the buffer unit 200 and transmits it to the control processor 15 without buffering the command in the buffer unit 200. By implementing these mechanisms, it is possible to improve the efficiency of recovery and cause investigation after an error occurs.

[0046] Further, the processing control unit 30 determines whether or not a specific condition is satisfied, for example, a force at which a predetermined value of a specific state register becomes an expected value (S650). The state in which the state register has reached the expected value is, for example, a state indicating that a series of tests by the test apparatus 10 has been completed. In this case (S650: YES), the processing control unit 30 issues an interrupt to the control processor 15 that causes the control processor 15 to transmit a subsequent control command, that is, a control command for the next test (S640). .

FIG. 7 shows a first example of an instruction group buffered in the buffer unit 200. Using the first example, an example will be described in which a plurality of conditions to be satisfied in order to execute a control command are set. In this first example, in the FIFO buffer unit 200, in order from the top, the condition write command 1 which is the first condition write command for writing the condition to the status register 400, A condition write command 2, which is a second condition write command for writing a condition to the status register 410, and a control command for controlling the test unit 40 are stored. The conditional write command 1 is composed of a first address for specifying the status register 400 in the address space of the control processor 15 and a first expected value to be compared with the status register 400. The conditional write command 2 is composed of a second address for specifying the status register 410 in the address space of the control processor 15 and a second expected value to be compared with the status register 410.

That is, the control processor 15 sends a control command to the test unit 40 on the condition that the status register 400 becomes the first expected value and the status register 410 becomes the second expected value. If desired, the address and first expected value of the status register 400 and the address and second expected value of the status register 410 are sequentially written to the addresses assigned to the buffer unit 200. After that, the control processor 15 writes a control command at the address assigned to the test unit 40. As a result, as shown in FIG. 7, the conditional write command 1, the conditional write command 2, and the control instruction are sequentially stored in the buffer unit 200.

[0049] When the notifier unit 200 is in such a state, the polling unit 230 obtains the conditional write command 1 for writing the address of the state register 400 and the first expected value from the buffer unit 200. In response, the first read command having the address of the status register 400 as the read address is repeatedly issued to the test unit 40. Then, the buffer control unit 35 writes the address of the status register 410 and the second expected value received after the condition write command 1 in response to the value of the status register 400 becoming the first expected value. Takes condition write command 2 from buffer section 200.

[0050] Then, the polling unit 230 repeatedly issues a second read command to the test unit 40 with the address of the status register 410 as the read address in response to the acquisition of the conditional write command 2 from the buffer unit 200. To do. Then, the buffer control unit 35 transmits the control command write command received after the conditional write command 2 to the test unit 40 in response to the value of the status register 410 becoming the second expected value. . In this way, if multiple condition write commands are used, multiple conditions that must be satisfied in order to execute the control instruction can be specified. Can do.

FIG. 8 shows a second example of the instruction group buffered in the buffer unit 200. Using the second example, a process for setting a plurality of different conditions to be satisfied in order to execute a control command will be described. In this second example, the FIFO buffer unit 200 writes, in order from the top, a timing write command that determines the timing at which a control command should be transmitted to the test unit 40, and a condition in the status register 400. And a control command for controlling the test unit 40 are stored.

That is, the control processor 15 sequentially issues a timing write command, a condition write command, and a control command write command in this order. In such a state, the detection unit 320 detects the arrival of the timing written by the timing write command. When the arrival of the timing is detected, the extraction unit 300 extracts the next command, that is, the conditional write command, from the buffer unit 200. Then, in response to the acquisition of the condition write command for writing the address and expected value of the status register 400 from the buffer unit 200, the polling unit 230 issues a read command with the address of the status register 400 as the read address. Issue repeatedly. Then, the buffer control unit 35 transmits the control command write command received after the condition write command to the test unit 40 in response to the value of the status register 400 becoming the expected value. In this way, the condition to be satisfied in order to execute the control command may be a combination of a plurality of different types of conditions! /.

FIG. 9 shows an overall configuration of the test apparatus 10 in a modification of the present embodiment. This modification is intended to test a single device under test 50 in cooperation with a plurality of test units 40. As the performance of the device under test 50 increases, the number of input / output terminals of the device under test 50 also increases, and one device under test 50 may not be tested depending on one test unit 40. In such a case, a plurality of test units 40 are connected to part of the input / output terminals of the device under test 50 for testing.

[0054] Specifically, the test apparatus 10 according to the present modification tests the device under test 50-1 using the test unit 40-1 and the test unit 40-2. The test apparatus 10 tests the device under test 50-2 using the test unit 40-3 and the test unit 40-4. In addition, each of the relay units 20— ;! to 4 is associated with each of the test units 40— ;! to 4. This is provided. In such a form, the relay units 20 — ;! ˜2 may share the same address space in the control processor 15. Further, the relay units 20-3 to 4 may share the same address space in the control processor 15. An example of instruction relay processing in this case will be described with reference to FIG.

[0055] The configuration other than the configuration described with reference to FIG. 9 is substantially the same as the test apparatus 10 according to the embodiment described with reference to FIGS.

FIG. 10 shows an example of a group of instructions buffered in the buffer unit 200 in the modification example of the present embodiment. Since the relay unit 20-1 and the relay unit 20-2 share the same address space, the same instruction group is included in the buffer unit 200 of the relay unit 20-1 and the buffer unit 200 of the relay unit 20-2. Buffered. Specifically, each buffer unit 200 includes, in order from the top, control command 1 for test unit 40-1, control command 2 for test unit 40-2, and control command 1 for test unit 40-1. They are remembered in this order.

[0057] When the fetch unit 300 of the relay unit 20-1 fetches the control command 1 from the head of the buffer unit 200, the fetch unit 300 determines whether the write destination of the control command 1 is the test unit 40-1. Since the write destination is the test unit 40-1, the relay unit 20-1 transmits the control command 1 to the test unit 40-1. On the other hand, the fetch unit 300 of the relay unit 20-2 discards the control command 1 without executing the control command 1 because the write destination of the control command 1 at the head of the buffer unit 200 is not the test unit 40-2.

[0058] When the execution or discard of the first control instruction 1 is completed, the relay unit 20 — ;! ~ 2 moves to the processing of the next instruction. That is, when the buffer unit 200 of the relay unit 20-1 takes out the control command 2, the control command 2 is discarded because the write destination of the control command 2 is the test unit 40-2. On the other hand, the buffer unit 200 of the relay unit 20-2 transmits the control command to the test unit 40-2 because the write destination of the control command 2 is the test unit 40-2. The same applies to the subsequent control instructions.

As described above, according to this modification, even when one device under test 50 is tested using a plurality of test units 40, the address space viewed from the control processor 15 is determined for each device under test 50. Can be set to Even in this case, the relay unit 20 The instructions for each test unit 40 are distributed and processed appropriately. As described above, according to the present modification, in addition to the processing described in the embodiment shown in FIGS. 1 to 8, the instruction distribution processing is also concentrated on the relay unit 20, and the load on the control processor 15 is increased. Can reduce power S. Furthermore, it is possible to use the existing test program 100 and the test unit 40 easily.

[0060] As described above, the (1) aspect of the present invention has been described using the embodiments. The technical scope of the present invention is not limited to the scope described in the above embodiments. Various modifications or improvements can be added to the above embodiment. For example, the relay unit 20 shown in the present embodiment or its modification may be included in the corresponding test unit 40 and mounted. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

As is apparent from the above description, according to the embodiment (1) of the present invention, it is possible to realize a test apparatus and a control method for accurately and efficiently controlling the operation timing of the test unit. Monkey.

Claims

The scope of the claims

[1] A test apparatus for testing a device under test,

A control processor that executes a test program for testing the device under test; a test unit that is connected to the device under test and tests the device under test according to instructions from the control processor;

A relay unit connected to the control processor and the test unit and relaying a control command transmitted from the control processor to the test unit;

With

The relay unit is

A buffer unit for buffering the control instruction to be written to an address assigned to the test unit from the control processor;

A timing storage unit for storing a timing at which the control command received from the control processor is to be transmitted to the test unit;

A test apparatus comprising: a buffer control unit that transmits the control command buffered in the buffer unit to the test unit in response to the arrival of the timing stored in the timing storage unit.

[2] Prior to the writing of the control command, the control processor writes the timing at which the control command should be transmitted to the test unit to the address assigned to the relay unit,

The buffer unit sequentially buffers the timing write command for writing the timing and the control command write command for writing the control command received from the control processor,

The buffer control unit delays processing of the control command write command received after the timing write command until the timing is reached in response to taking out the timing write command from the buffer unit.

The test apparatus according to claim 1.

[3] The buffer control unit includes:

An extraction unit for sequentially retrieving the write commands buffered in the buffer unit; A timing writing unit for storing the timing in the timing storage unit in response to taking out the timing writing command;

The detection unit that detects the arrival of the timing stored in the timing storage unit, and the control command write command received after the timing write command on the condition that the arrival of the timing is detected, The test apparatus according to claim 2, further comprising: a transmission unit that transmits to the test unit.

[4] The test apparatus tests a plurality of devices under test.

Each of the plurality of test units is provided corresponding to each of the plurality of devices under test,

Each of the plurality of relay units is provided corresponding to each of the plurality of test units.

The test apparatus according to claim 3.

[5] A test apparatus comprising: a control processor that executes a test program for testing a device under test; and a test unit that is connected to the device under test and tests the device under test according to instructions from the control processor. A control method for controlling,

Buffer control instructions to be written from the control processor to the address assigned to the test unit;

Storing the timing at which the control command received from the control processor is to be transmitted to the test unit;

Send the buffered control instructions to the test unit in response to the timing being reached

Control method.

[6] A test apparatus for testing a device under test,

A relay unit connected to the control processor and the test unit and relaying a control command transmitted from the control processor to the test unit; With

The relay unit is

A polling unit that repeatedly reads a status register designated by the control processor and indicating the status of the test unit;

In response to the value of the status register becoming the expected value designated by the control processor, the control unit should process the control instruction to be processed after the value of the status register becomes the expected value. Processing control unit to send to

Test equipment with

[7] The control processor writes the address of the status register and the expected value in the address space assigned to the test unit to the address assigned to the relay unit, and then assigns the test unit to the test unit. Write the control command to the specified address,

The relay unit further includes a buffer unit for sequentially buffering a condition write command for writing the status register address and the expected value received from the control processor and a control command write command for writing the control command. And

In response to the acquisition of the conditional write command from the buffer unit, the polling unit repeatedly issues a read command having the address of the status register as a read address to the test unit,

The processing control unit includes a buffer control unit that transmits the control command write command received after the conditional write command to the test unit in response to the value of the status register becoming the expected value. Include

The test apparatus according to claim 6.

[8] The control processor specifies whether or not to mask each bit of the value of the status register read by the polling unit as the expected value when writing the address of the status register and the expected value. Write a value and an expected value after mask indicating the value to be satisfied by the masked status register value;

The buffer control unit receives a value after the condition write command is received in response to a value obtained by masking the value of the status register with the mask value being the expected value after masking. Send the control command write command to the test unit.

The test apparatus according to claim 7.

[9] The control processor outputs the control instruction on the condition that the first status register becomes the first expected value and the second status register becomes the second expected value. When transmitting to the test unit, the address of the first status register and the first expected value, the address of the second status register and the second expected value are assigned to the relay unit. After sequentially writing to the address, write the control command to the address assigned to the test unit,

The polling unit acquires the first condition write command for writing the address of the first state register and the first expected value from the buffer unit, and First issue a first read command with the address as the read address to the test unit,

The buffer control unit receives the second status register received after the first conditional write command in response to the value of the first status register becoming the first expected value. The second conditional write command for writing the address and the second expected value is taken out from the notfer unit,

In response to the acquisition of the second conditional write command from the buffer unit, the polling unit sends a second read command having the address of the second status register as a read address to the test unit. And repeatedly issue

The buffer control unit receives the control command write command received after the second conditional write command in response to the value of the second status register becoming the second expected value. Send to test unit

The test apparatus according to claim 7.

[10] The processing control unit issues a time-out interrupt to the control processor in response to elapse of a preset time-out period after the conditional write command is acquired from the buffer unit. The test apparatus according to Item 6.

[11] The processing control unit transmits a subsequent control command from the control processor in response to the value of the status register becoming an expected value specified by the control processor. 7. The test apparatus according to claim 6, wherein an interrupt is issued to the control processor as much as possible. A control method for controlling a test apparatus comprising: a control processor that executes a test program for testing a device under test; and a test unit that is connected to the device under test and tests the device under test according to instructions from the control processor And repeatedly reading a status register designated by the control processor and indicating the status of the test unit,

In response to the value of the state register becoming an expected value designated by the control processor, the control unit should process the control instruction to be processed after the value of the state register becomes the expected value. Send to

Control method.