JP5008673B2 - Test apparatus and control method - Google Patents

Description

The present invention relates to a test apparatus and a control method. In particular, the present invention relates to a test apparatus and a control method for transmitting a control command from a control processor to a test unit in order to control a test unit for testing a device under test. This application is related to the following US patent applications: For designated countries where incorporation by reference of documents is permitted, the contents described in the following application are incorporated into this application by reference and made a part of this application.
1. Application No. 11 / 546,926 Application Date October 12, 20062. Application number 11 / 546,929 Application date October 12, 2006

  A control processor provided in the test apparatus operates based on the installed control program, and transmits a command to the test unit. Thereby, the control of the test unit, for example, the test unit can be appropriately activated, or the setting of the test unit in operation can be changed.

  However, in the test unit, the order of instructions to be processed is determined according to its specifications. If the execution order of instructions violates the specifications, the test unit and the device under test may be damaged. . For this reason, the programmer creates a control program so that instructions are executed in an order conforming to this specification.

  Further, the timing for executing the instruction is determined in the test unit according to the specification. For example, after a voltage change or the like, if the next command is not executed after waiting for a predetermined period, the test unit may malfunction due to an unstable voltage. For this reason, the programmer appropriately inserts an instruction that waits for a certain period without executing the instruction into the control program.

  Further, a certain instruction is determined to be executed at a timing when the test unit is in a predetermined state. As a method for detecting such a state change, polling by the control processor or interrupt processing from the test unit to the control processor can be considered.

  As a reference technique related to the semiconductor test apparatus, refer to Patent Document 1.

JP-A-11-64450

  The instruction to wait for a certain period can be realized, for example, by setting a standby time in a timer outside the control processor and generating an interrupt from the timer to the control processor. In addition, it can be realized by performing an originally unnecessary process such as an idle loop in the control program or by performing a standby process by the function of the operating system that controls the control processor.

  However, the time that the control processor waits may be different from the time assumed by the programmer. This is because the instruction execution timing varies. For example, when the control processor receives various interrupt processes to perform other processes, or when a plurality of tasks are executed in a time-sharing manner, the instruction execution timing may be delayed. As a result, if the instruction execution timing is advanced due to a variation in execution timing, a sufficient waiting time cannot be ensured, and the next processing may be performed to damage the test unit or the like.

  In order to avoid such a situation, the programmer creates a control program so that a standby time sufficiently longer than the actually required standby time can be secured. As a result, the time required for the setting change or the like is significantly longer than the originally required time, which may reduce the efficiency of the entire test process.

  The polling by the control processor refers to a process of periodically reading out a register in the test unit from the control processor and detecting a state change based on a change in the value. However, the process of reading the value from the register takes a longer time than the instruction execution of the control processor, and the control processor has an input / output waiting time, and the calculation power of the control processor may not be effectively utilized.

  On the other hand, if an interrupt process is to be realized, a mechanism for realizing an interrupt is required for each test unit, which may complicate the design of the entire test apparatus. Furthermore, if an interrupt is to be detected quickly, the presence / absence of the interrupt must be checked frequently, and the operating system that controls the interrupt may increase the processing load on the control processor.

  As described above, in order to quickly and appropriately detect the change in the state of the test unit, the control processor is required to have a high computing capacity. For this reason, even in a test apparatus having a plurality of test units, a control processor is required for each test unit, and a large number of control processors are mounted in the test apparatus. An increase in the number of control processors can increase the size and cost of the test apparatus and its cooling apparatus, and thus increase the failure occurrence rate of the test apparatus.

  Accordingly, an object of one aspect of the present invention is to provide a test apparatus and a control method that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  That is, according to the first aspect of the present invention, there is provided a test apparatus for testing a device under test, a control processor for executing a test program for testing the device under test, and an instruction of the control processor connected to the device under test. A test unit that tests the device under test according to the control processor, and a relay unit that is connected to the control processor and the test unit and relays a control command transmitted from the control processor to the test unit. A buffer unit that buffers a control instruction to be written to an address assigned to the test unit, a timing storage unit that stores a timing received from the control processor and that should be transmitted to the test unit, and a timing storage In response to the arrival of the timing stored in the buffer. File has been the control command to provide a test apparatus and a buffer control unit to be transmitted to the test unit.

  According to a second aspect of the present invention, a control processor that executes a test program for testing a device under test, and a test unit that is connected to the device under test and tests the device under test according to an instruction of the control processor are provided. A control method for controlling a test apparatus, wherein a control instruction to be written to an address assigned to a test unit from a control processor is buffered, and a control instruction received from the control processor should be transmitted to the test unit A control method is provided for storing timing and transmitting a buffered control instruction to a test unit in response to timing arrival.

  According to a third aspect of the present invention, there is provided a test apparatus for testing a device under test, the control processor executing a test program for testing the device under test, and connected to the device under test according to an instruction from the control processor. A test unit for testing the device under test and a relay unit connected to the control processor and the test unit and relaying a control command transmitted from the control processor to the test unit. The relay unit is designated by the control processor. In addition, a polling unit that repeatedly reads out the status register indicating the status of the test unit, and a test after the status register value reaches the expected value in response to the status register value becoming the expected value specified by the control processor Provided is a test apparatus having a processing control unit for transmitting a control command to be processed by a unit to a test unit

  According to a fourth aspect of the present invention, a control processor that executes a test program for testing a device under test and a test unit that is connected to the device under test and tests the device under test according to instructions from the control processor are provided. A control method for controlling a test apparatus, in which a status register designated by a control processor indicating a status of a test unit is repeatedly read out, and the value of the status register becomes an expected value designated by the control processor. Provided is a control method for transmitting a control command to be processed by the test unit to the test unit after the value of the status register reaches the expected value.

  The above summary of the invention does not enumerate all necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

The whole structure of the test apparatus 10 is shown. The function structure of the relay part 20 is shown. A functional configuration of the buffer control unit 35 is shown. A flow of processing for relaying an instruction from the control processor 15 to the test unit 40 by the relay unit 20 is shown. Details of the processing in S420 of FIG. 4 are shown. Details of the processing in S430 of FIG. 4 are shown. A first example of an instruction group buffered in the buffer unit 200 is shown. The 2nd example of the instruction group buffered by the buffer part 200 is shown. The whole structure of the test apparatus 10 in the modification of this embodiment is shown. An example of an instruction group buffered in the buffer unit 200 in a modification of the present embodiment will be described.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Test apparatus, 15 ... Control processor, 20 ... Relay part, 40 ... Test unit, 50 ... Device under test, 100 ... Test program, 400 ... Status register, 410 ... Status register, 30 ... Processing control unit, 200 ... Buffer unit, 210 ... Timing storage unit, 220 ... Condition storage unit, 230 ... Polling unit, 35 ... Buffer Control unit, 300 ... extraction unit, 310 ... writing unit, 320 ... detection unit, 330 ... transmission unit

  Hereinafter, the (1) aspect of the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims, and the features described in the embodiments are described below. Not all combinations are essential for the solution of the invention.

  FIG. 1 shows the overall configuration of the test apparatus 10. The test apparatus 10 includes a control processor 15, a plurality of relay units 20, and a plurality of test units 40. The control processor 15 executes a test program 100 for testing the device under test. The control processor 15 may execute a plurality of test programs 100 that control different test units 40. Each of the plurality of test programs 100 may be executed in parallel by dividing the computer resources of the control processor 15 in an operating system having an execution mechanism called multitask, multiprocess, or multithread.

  Each of the plurality of test units 40 is provided corresponding to each of the plurality of devices under test 50. Each of the plurality of test units 40 is connected to the corresponding device under test 50 and tests the device under test 50 according to an instruction from the control processor 15. Each of the plurality of test units 40 includes a status register that indicates the status of the test unit 40. For example, each of the plurality of test units 40 includes a status register 400 that is an example of a first status register and a status register 410 that is an example of a second status register. In the figure, the status registers 400 and 410 are illustrated for only one test unit 40, but each of the other test units 40 may also have a status register. Each of the plurality of test units 40 stores the state of the test unit 40 in these state registers in accordance with the state change due to the progress of the test.

  Each of the plurality of relay units 20 is provided corresponding to each of the plurality of test units 40. Each of the plurality of relay units 20 is connected to the control processor 15 and the corresponding test unit 40. Each of the relay units 20 relays a control command transmitted from the control processor 15 to the corresponding test unit 40. Specifically, the storage area in the relay unit 20 and the storage area in the test unit 40 are mapped to a virtual address space in which the test program 100 operates on the control processor 15. Then, the control processor 15 executes a write command in the test program 100 to write to the virtual address space, that is, the relay unit 20 or the test unit 40. The control command for the test unit 40 is, for example, a command for setting / changing the magnitude of the voltage applied from the test unit 40 to the device under test 50, or setting / changing the frequency of a test signal. It may be a command or a command for instructing the start of the test sequence operation.

  The relay unit 20 receives the write data for the address space assigned to the test unit 40 from the control processor 15 and transfers it to the test unit 40 as it is. On the other hand, the relay unit 20 performs write processing on the register or memory in the relay unit 20 according to the content of the write data for the address space allocated to the relay unit 20. The relay unit 20 controls the instruction transfer timing according to the written contents. For example, the relay unit 20 may transmit data such as a control command received following the write data to the test unit 40 after waiting for a time indicated by the write data.

  As described above, the test apparatus 10 according to the present embodiment controls the timing of transmitting a command to the test unit 40 by the relay unit 20 provided separately from the control processor 15. This aims to reduce the processing load on the control processor 15 and accurately control the timing of control command transmission.

  Subsequently, a functional configuration of one relay unit 20 among the plurality of relay units 20 will be described.

  FIG. 2 shows a functional configuration of the relay unit 20. The relay unit 20 includes a processing control unit 30, a buffer unit 200, a timing storage unit 210, a condition storage unit 220, and a polling unit 230. As an example of the implementation, the buffer unit 200, the timing storage unit 210, and the condition storage unit 220 are implemented by a storage medium such as a register and a memory, and the polling unit 230 and the process control unit 30 are implemented by a sequencer. First, the processing function when the control processor 15 writes the timing at which the control command should be transmitted to the test unit 40 prior to the writing of the control command to the address assigned to the test unit 40 will be described. The buffer unit 200 controls the timing value to be written from the control processor 15 to the address assigned to the relay unit 20 and the control value to be written from the control processor 15 to the address assigned to the corresponding test unit 40. Buffer instructions sequentially.

  Specifically, the buffer unit 200 sequentially buffers a timing write command for writing a timing value and a control command write command for writing a control command received from the control processor 15. The timing write command is, for example, a set of an address in the address space allocated to the relay unit 20 and a timing value to be written to the address. On the other hand, the control command write command is, for example, a set of an address in an address space allocated to the test unit 40 and a control command to be written to the address.

  The timing storage unit 210 stores the timing at which the control command received from the control processor 15 should be transmitted to the test unit 40. This timing is stored as a timing value by the buffer control unit 35 in accordance with the timing write command. The processing control unit 30 includes a buffer control unit 35. In addition to storing the timing value, the buffer control unit 35 controls the transmission timing of the control command received following the timing write command. Specifically, the buffer control unit 35 transmits the control command buffered in the buffer unit 200 to the corresponding test unit 40 in response to the arrival of the timing stored in the timing storage unit 210. This timing value is, for example, a delay amount for delaying transmission of a control command received subsequently. That is, the buffer control unit 35 delays the processing of the control command write command received after the timing write command until the timing is reached in response to taking out the timing write command from the buffer unit 200.

  Next, the control processor 15 writes the address and expected value of the status register in the address space assigned to the test unit 40 to the address assigned to the relay unit 20 and then assigned to the test unit 40. A processing function when a control command is written to a specific address will be described. The condition storage unit 220 stores the address of the state register indicating the state of the test unit 40 received from the control processor 15 and the expected value to be compared with the value of the state register. These addresses and expected values are stored by the buffer control unit 35. That is, when the buffer control unit 35 obtains a condition write command for writing the address and expected value of the status register from the buffer unit 200, the buffer control unit 35 stores the address and expected value in the condition storage unit 220.

  The address of the status register may be a virtual address in the control processor 15 assigned to the status register, as well as the status register number and other identification information.

  The polling unit 230 repeatedly reads out a status register (one or both of the status register 400 and the status register 410 according to the designation of the control processor 15) designated by the control processor 15 and indicating the status of the test unit 40. Specifically, in response to the acquisition of the condition write command from the buffer unit 200, the polling unit 230 sends a read command having the address of the status register (that is, the address stored in the condition storage unit 220) as a read address to the test unit 40. Issue repeatedly. In response to the read state register value having reached the expected value designated by the control processor 15, the processing control unit 30 should be processed by the test unit 40 after the state register value has reached the expected value. A control command is transmitted to the test unit 40. The control instruction to be processed after the value of the status register reaches the expected value is, for example, an instruction written by a control instruction write command received after the conditional write command. That is, the buffer control unit 35 transmits the control command write command received after the conditional write command to the test unit 40 in response to the value of the status register reaching the expected value.

  Instead of this, or in addition to this, the buffer control unit 35 interrupts the control processor to cause the control processor 15 to transmit a subsequent control command in response to the value of the status register reaching the expected value. May be issued. This process is effective when a series of test processes are completed. That is, for example, the buffer control unit 35 can start the next test from the beginning by issuing an interrupt to the control processor 15 and restarting the control processor 15.

  FIG. 3 shows a functional configuration of the buffer control unit 35. The buffer control unit 35 includes an extraction unit 300, a writing unit 310, a detection unit 320, and a transmission unit 330. The extracting unit 300 sequentially extracts the write commands buffered in the buffer unit 200. The take-out unit 300 may take out one write command from the head of the FIFO buffer unit 200 in response to a write completion notification from the write unit 310 or a transmission completion notification from the transmission unit 330. In addition, the take-out unit 300 may immediately delete the write command from the buffer unit 200 after taking out the write command for the relay unit 20, or the write command after completion of the processing corresponding to the write command May be deleted from the buffer unit 200.

  The writing unit 310 is an example of a timing writing unit according to the present invention, and stores the timing in the timing storage unit 210 in response to taking out the timing writing command. Further, the writing unit 310 stores the address of the state register and the expected value in the condition storage unit 220 in response to taking out the conditional writing command. The detection unit 320 detects the arrival of the timing stored in the timing storage unit 210. The detection unit 320 detects whether the value of the status register read by the polling unit 230 has reached an expected value.

  The transmission unit 330 transmits the control command write command received after the timing write command to the test unit 40 on condition that the arrival of timing is detected. Further, the transmission unit 330 transmits the control command write command received after the conditional write command to the test unit 40 on the condition that the value of the status register becomes the expected value.

  FIG. 4 shows a flow of processing for relaying a command from the control processor 15 to the test unit 40 by the relay unit 20. The buffer unit 200 buffers a control command to be written from the control processor 15 to the address assigned to the test unit 40 or the relay unit 20 (S400). The extraction unit 300 sequentially extracts the write commands buffered in the buffer unit 200 (S410). If the extracted write command is a write command for the address space allocated to the relay unit 20, the relay unit 20 writes to the timing storage unit 210 or the condition storage unit 220 (S420). If the extracted write command is a write command for the address of the status registers 400 and 410 of the test unit 40, the relay unit 20 performs control command transmission processing (S430).

  FIG. 5 shows details of the processing in S420 of FIG. The writing unit 310 determines whether or not the extracted command is a timing write command (S500). If it is a timing write command (S500: YES), the writing unit 310 stores the timing designated by the timing write command in the timing storage unit 210 (S510). If it is a conditional write command (S520: YES), the writing unit 310 causes the condition storage unit 220 to store the condition for transmitting the subsequent control command, that is, the address of the state register and the expected value (S530).

  FIG. 6 shows details of the processing in S430 of FIG. The detection unit 320 detects the arrival of the timing stored in the timing storage unit 210 (S600). When the arrival of timing is detected, or when the timing is not set in the first place (S600: YES), the detection unit 320 determines whether the value of the status register has reached the expected value specified by the control processor 15. Judgment is made (S610). In this determination, the value of the status register may be used for the determination after being masked by a predetermined mask value. Specifically, it is as follows.

  First, the control processor 15 writes a mask value specifying whether or not to mask each bit of the value of the status register read by the polling unit 230 as the expected value when writing the address and expected value of the status register, The post-mask expected value indicating the value to be satisfied by the value of the state register thus written is written in the condition storage unit 220. Then, the polling unit 230 reads the value of the status register and determines whether or not the value obtained by masking the value of the status register with the mask value becomes the expected value after masking.

  Then, when the arrival of timing is detected and the value of the status register reaches the expected value (S600: YES, S610: YES), the detection unit 320 of the buffer control unit 35 performs the conditional write command or timing. The control command write command received after the write command is transmitted to the test unit 40 (S620). If a mask value is specified in the status register, the condition is that the masked value becomes the expected value after masking.

  When the arrival of timing is not detected or the value of the status register is not the expected value, the process control unit 30 sets a timeout time set in advance after the conditional write command is acquired from the buffer unit 200. It is determined whether or not elapses (S630). If it has elapsed (S630: YES), the process control unit 30 issues a timeout interrupt to the control processor 15 (S640). As a result, even if the condition is set but it does not hold due to a failure, etc., or even if the set condition has an error and the condition does not hold, error detection processing and the next test are performed. It can be started properly.

  The control processor 15 that has received this interrupt may issue an instruction to erase the contents of the buffer unit 200 to the relay unit 20 in order to erase the contents of the buffer unit 200 and start the next processing correctly. Good. In this case, when receiving this command, the relay unit 20 erases the write command in the buffer unit 200 without buffering in the buffer unit 200. As yet another example, the control processor 15 may issue a command for reading the contents of the buffer unit 200 to the relay unit 20. In this case, when receiving this command, the relay unit 20 reads the write command from the buffer unit 200 and transmits it to the control processor 15 without buffering the command in the buffer unit 200. By implementing these mechanisms, it is possible to improve the efficiency of recovery and cause investigation after an error occurs.

  In addition, the process control unit 30 determines whether a specific condition is satisfied, for example, whether a predetermined value in a specific state register is an expected value (S650). The state in which the state register has reached its expected value is a state indicating that a series of tests by the test apparatus 10 has been completed, for example. In this case (S650: YES), the process control unit 30 issues an interrupt to the control processor 15 in order to cause the control processor 15 to transmit a subsequent control command, that is, a control command for the next test (S640).

  FIG. 7 shows a first example of an instruction group buffered in the buffer unit 200. An example of setting a plurality of conditions to be satisfied in order to execute a control command will be described using the first example. In the first example, in the FIFO buffer unit 200, the condition write command 1 which is a first condition write command for writing a condition to the state register 400 and the condition in the state register 410 are sequentially set from the top. A conditional write command 2 that is a second conditional write command for writing and a control command for controlling the test unit 40 are stored. The conditional write command 1 is composed of a first address for specifying the status register 400 in the address space of the control processor 15 and a first expected value to be compared with the status register 400. The conditional write command 2 includes a second address for specifying the state register 410 in the address space of the control processor 15 and a second expected value to be compared with the state register 410.

  That is, if the control processor 15 wishes to send a control command to the test unit 40 on condition that the status register 400 becomes the first expected value and the status register 410 becomes the second expected value, The address and first expected value of the status register 400, and the address and second expected value of the status register 410 are sequentially written to the addresses assigned to the buffer unit 200. Thereafter, the control processor 15 writes a control command at the address assigned to the test unit 40. As a result, as shown in FIG. 7, the conditional write command 1, the conditional write command 2, and the control instruction are sequentially stored in the buffer unit 200.

  When the buffer unit 200 is in such a state, the polling unit 230 receives the conditional write command 1 for writing the address of the state register 400 and the first expected value from the buffer unit 200, and the state register A first read command having the address 400 as a read address is repeatedly issued to the test unit 40. Then, the buffer control unit 35 writes the address of the status register 410 and the second expected value received after the condition write command 1 in response to the value of the status register 400 becoming the first expected value. The write command 2 is taken out from the buffer unit 200.

  Then, in response to the acquisition of the conditional write command 2 from the buffer unit 200, the polling unit 230 repeatedly issues a second read command having the address of the status register 410 as a read address to the test unit 40. Then, the buffer control unit 35 transmits a control command write command received after the conditional write command 2 to the test unit 40 in response to the value of the status register 410 becoming the second expected value. As described above, when a plurality of condition write commands are used, a plurality of conditions to be satisfied in order to execute the control command can be designated.

  FIG. 8 shows a second example of the instruction group buffered in the buffer unit 200. A process for setting a plurality of different conditions to be satisfied in order to execute a control command will be described using a second example. In this second example, in the FIFO buffer unit 200, in order from the top, a timing write command for determining the timing at which a control command should be transmitted to the test unit 40, and a condition for writing a condition in the status register 400 A condition write command and a control command for controlling the test unit 40 are stored.

  That is, the control processor 15 sequentially issues a timing write command, a condition write command, and a control command write command in this order. In such a state, the detection unit 320 detects the arrival of the timing written by the timing write command. When the arrival of timing is detected, the extraction unit 300 extracts the next command, that is, the conditional write command, from the buffer unit 200. Then, in response to the acquisition of the condition write command for writing the address and expected value of the state register 400 from the buffer unit 200, the polling unit 230 sends a read command having the address of the state register 400 as a read address to the test unit 40. And repeatedly issue. Then, the buffer control unit 35 transmits the control command write command received after the condition write command to the test unit 40 in response to the value of the status register 400 becoming the expected value. As described above, the condition to be satisfied in order to execute the control command may be a combination of a plurality of different types of conditions.

  FIG. 9 shows the overall configuration of the test apparatus 10 in a modification of the present embodiment. This modification is intended to test a single device under test 50 in cooperation with a plurality of test units 40. As the performance of the device under test 50 increases, the number of input / output terminals of the device under test 50 also increases, and one device under test 50 may not be tested by one test unit 40. In such a case, a plurality of test units 40 are connected to some of the input / output terminals of the device under test 50 for testing.

  Specifically, the test apparatus 10 according to this modification tests the device under test 50-1 using the test unit 40-1 and the test unit 40-2. The test apparatus 10 tests the device under test 50-2 using the test unit 40-3 and the test unit 40-4. In addition, each of the relay units 20-1 to 20-4 is provided in association with each of the test units 40-1 to 40-4. In such a form, the relay units 20-1 and 20-2 may share the same address space in the control processor 15. Further, the relay units 20-3 to 4 may share the same address space in the control processor 15. An example of the instruction relay process in this case will be described with reference to FIG.

  The configuration other than the configuration described with reference to FIG. 9 is substantially the same as the test apparatus 10 according to the embodiment described with reference to FIGS.

  FIG. 10 shows an example of an instruction group buffered in the buffer unit 200 in the modification of the present embodiment. Since the relay unit 20-1 and the relay unit 20-2 share the same address space, the buffer group 200 of the relay unit 20-1 and the buffer unit 200 of the relay unit 20-2 have the same instruction group. Buffered. Specifically, in each buffer unit 200, in order from the top, a control command 1 for the test unit 40-1, a control command 2 for the test unit 40-2, and a control command 1 for the test unit 40-1 are provided. They are stored in this order.

  When the take-out unit 300 of the relay unit 20-1 takes out the control command 1 from the head of the buffer unit 200, it determines whether the write destination of the control command 1 is the test unit 40-1. Since the write destination is the test unit 40-1, the relay unit 20-1 transmits this control command 1 to the test unit 40-1. On the other hand, the take-out unit 300 of the relay unit 20-2 discards the control command 1 without executing the control command 1 because the write destination of the first control command 1 in the buffer unit 200 is not the test unit 40-2.

  When the execution or discard of the first control instruction 1 is completed, the relay units 20-1 and 20-2 both move to processing of the next instruction. That is, when the buffer unit 200 of the relay unit 20-1 takes out the control instruction 2, the control instruction 2 is discarded because the write destination of the control instruction 2 is the test unit 40-2. On the other hand, since the write destination of the control command 2 is the test unit 40-2, the buffer unit 200 of the relay unit 20-2 transmits the control command to the test unit 40-2. The same applies to the subsequent control commands.

  As described above, according to this modification, even when one device under test 50 is tested using a plurality of test units 40, the address space viewed from the control processor 15 is set for each device under test 50. Can do. Even in this case, the instructions to the respective test units 40 are appropriately distributed and processed by the relay unit 20. As described above, according to this modification, in addition to the processing described in the embodiment shown in FIGS. 1 to 8, instruction distribution processing is also concentrated on the relay unit 20, and the load on the control processor 15 is increased. Can be reduced. Furthermore, the existing test program 100 and the test unit 40 can be easily used.

  The (1) aspect of the present invention has been described above using the embodiment, but the technical scope of the present invention is not limited to the scope described in the above embodiment. Various changes or improvements can be added to the above embodiment. For example, the relay unit 20 shown in the present embodiment or a modification example thereof may be included in the test unit 40 corresponding thereto and mounted. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  As is clear from the above description, according to the (1) embodiment of the present invention, it is possible to realize a test apparatus and a control method for accurately and efficiently controlling the operation timing of the test unit.

Claims (12)

A test apparatus for testing a device under test,
A control processor for executing a test program for testing the device under test;
A test unit connected to the device under test and testing the device under test in accordance with instructions from the control processor;
A relay unit that is connected to the control processor and the test unit and relays a control command transmitted from the control processor to the test unit;
The relay unit is
A buffer unit for buffering the control instruction to be written to the address assigned to the test unit from the control processor;
A timing storage unit that stores a timing at which the control command received from the control processor is to be transmitted to the test unit;
A test apparatus comprising: a buffer control unit that transmits the control command buffered in the buffer unit to the test unit in response to the arrival of the timing stored in the timing storage unit. Prior to the writing of the control command, the control processor writes the timing at which the control command should be sent to the test unit to the address assigned to the relay unit,
The buffer unit sequentially buffers the timing write command for writing the timing and the control command write command for writing the control command received from the control processor,
The buffer control unit delays processing of the control command write command received after the timing write command until the timing is reached in response to taking out the timing write command from the buffer unit. Item 2. The test apparatus according to Item 1. The buffer control unit
An extraction unit for sequentially retrieving the write commands buffered in the buffer unit;
A timing writing unit for storing the timing in the timing storage unit in response to taking out the timing writing command;
A detection unit for detecting arrival of the timing stored in the timing storage unit;
The test apparatus according to claim 2, further comprising: a transmission unit that transmits the control command write command received after the timing write command to the test unit on condition that the arrival of the timing is detected. . The test apparatus is for testing a plurality of devices under test.
Corresponding to each of the plurality of devices under test, each of the plurality of test units is provided,
The test apparatus according to claim 3, wherein each of the plurality of relay units is provided corresponding to each of the plurality of test units. A control method for controlling a test apparatus comprising: a control processor that executes a test program for testing a device under test; and a test unit that is connected to the device under test and tests the device under test according to an instruction from the control processor Because
Buffer control instructions to be written to addresses assigned to the test unit from the control processor;
Storing the timing at which the control command received from the control processor is to be transmitted to the test unit;
A control method for transmitting the buffered control command to the test unit in response to the arrival of the timing. A test apparatus for testing a device under test,
A control processor for executing a test program for testing the device under test;
A test unit connected to the device under test and testing the device under test in accordance with instructions from the control processor;
A relay unit that is connected to the control processor and the test unit and relays a control command transmitted from the control processor to the test unit;
The relay unit is
A polling unit that repeatedly reads a status register designated by the control processor and indicating the status of the test unit;
In response to the value of the state register becoming an expected value designated by the control processor, the control unit is to process the control instruction to be processed by the test unit after the value of the state register becomes the expected value. And a processing control unit for transmitting to the test apparatus. The control processor writes the address of the status register in the address space assigned to the test unit and the expected value to the address assigned to the relay unit, and then assigns the address assigned to the test unit. Write the control command to
The relay unit further includes a buffer unit that sequentially buffers the condition write command for writing the status register address and the expected value received from the control processor and the control command write command for writing the control command. ,
In response to obtaining the conditional write command from the buffer unit, the polling unit repeatedly issues a read command with the address of the status register as a read address to the test unit,
The processing control unit includes a buffer control unit that transmits the control command write command received after the conditional write command to the test unit in response to the value of the status register becoming the expected value. The test apparatus according to claim 6. The control processor specifies whether or not to mask each bit of the value of the status register read by the polling unit as the expected value in writing the address of the status register and the expected value; Write a masked expected value indicating the value to be satisfied by the value of the masked status register,
The buffer control unit receives the control command write command received after the conditional write command in response to a value obtained by masking the value of the state register with the mask value being the expected value after masking. The test apparatus according to claim 7, which is transmitted to the test unit. The control processor sends the control instruction to the test unit on condition that the first status register becomes the first expected value and the second status register becomes the second expected value. When transmitting, the address of the first status register and the first expected value, and the address of the second status register and the second expected value are assigned to the address assigned to the relay unit. After sequentially writing, the control command is written to the address assigned to the test unit,
The polling unit receives the first condition write command for writing the address of the first state register and the first expected value from the buffer unit, and then the address of the first state register. Is repeatedly issued to the test unit with a read address as
The buffer control unit receives an address of the second state register received after the first conditional write command in response to the value of the first state register becoming the first expected value. And taking out the second conditional write command for writing the second expected value from the buffer unit,
In response to the acquisition of the second conditional write command from the buffer unit, the polling unit repeats a second read command having the address of the second status register as a read address to the test unit. Issue,
The buffer control unit receives the control command write command received after the second conditional write command in response to the value of the second status register becoming the second expected value. The test apparatus according to claim 7, which is transmitted to the unit.   The process control unit issues a time-out interrupt to the control processor in response to elapse of a preset time-out period after the conditional write command is acquired from the buffer unit. Testing equipment.   The processing control unit issues an interrupt to the control processor to cause the control processor to transmit a subsequent control command in response to the value of the status register having reached an expected value designated by the control processor. The test apparatus according to claim 6. A control processor for executing a test program for testing the device under test;
A control method for controlling a test apparatus connected to the device under test and comprising a test unit for testing the device under test in accordance with an instruction from the control processor,
Repeatedly reading a status register designated by the control processor and indicating the status of the test unit;
In response to the value of the state register becoming an expected value designated by the control processor, the control unit is to process the control instruction to be processed by the test unit after the value of the state register becomes the expected value. Control method to send to.

Images