CN101661455A

CN101661455A - Communication method and system

Info

Publication number: CN101661455A
Application number: CN200910020705A
Authority: CN
Inventors: 洪胜峰
Original assignee: Qingdao Hisense Electronics Co Ltd
Current assignee: Qingdao Hisense Electronics Co Ltd
Priority date: 2009-04-02
Filing date: 2009-04-02
Publication date: 2010-03-03

Abstract

The invention relates to a communication method comprising at least one first CPU and one second CPU. The communication priority between the first CPU and the second CPU is defined, the first CPU and/or the second CPU transmits a communication instruction, a bus system receives the communication instruction transmitted by the CPU and then transfers the communication instruction to a priority identifying unit, and the priority identifying unit identifies the content of the communication instruction according to the priority sequence and executes the corresponding communication instruction content for accessing a register unit and waiting for a next communication instruction. The invention further relates to a corresponding communication system for realizing the communication between the CPUand the register.

Description

The means of communication and communication system

Technical field

When the present invention relates to adopt in a kind of large scale integrated circuit a plurality of CPU to examine, method and a kind of corresponding communication system of data core instruction communication between each CPU.

Background technology

At present, using the embedded type CPU kernel to constitute the SOPC system at FPGA is the integrated great development direction of digital circuit, in some complication systems, often need to use a more than CPU to manage the Different Logic circuit respectively, in order to coordinate the work between each CPU, just need between each CPU, communications protocol be set, to guarantee normally effectively carrying out of communication.

Though each IP kernel provider also can provide similar communication IP kernel at present, as application side, use this charge mandate IP kernel will increase cost of products, restriction is received in the dirigibility of Shi Yonging simultaneously.

Chinese patent CN200610145941.X has disclosed a kind of method of hardware access register, after hardware sends instruction, according to the priority level arbitration, see that at the appointed time the priority of whether instructing meets the requirements, thereby whether arbitration can visit.If but arbitration can not be visited at the appointed time, then need to rejudge whether allow visit by improving being provided with of priority and waiting timer, can cause the The limited time system that responds like this, especially the low instruction of priority level, and having only under the situation of this instruction, access speed is more impaired.The instruction that priority level is low more, the access time of loss is just many more, and for large-scale SOC, response speed has determined the accuracy and the stability of system.

Summary of the invention

The present invention is intended to by simple VHDL program design, can solve the data core instruction communication problem between a plurality of CPU at the fpga chip of different manufacturers.

Defective and consumer demand based on the above-mentioned background technology the invention provides a kind of means of communication, make a plurality of CPU to have avoided adopting the charge communication mode by realizing mutual communication between bus and the register.

Technical scheme provided by the invention is: a kind of means of communication, comprise at least the one CPU and the 2nd CPU, define the communication priority rank between a CPU and the 2nd CPU, the one CPU and/or the 2nd CPU send communication instruction, the communication instruction that bus system reception CPU sends also passes to the priority recognition unit, the priority recognition unit is carried out corresponding communication instruction access to content register cell according to the content of priority orders identification communication instruction, waits for next communication instruction.

In embodiments of the present invention, described register cell is provided with at least one and interrupts application/removing position, is used for first and second CPU and applies for each other interrupting.

In embodiments of the present invention, described registers group comprises control/status register and data register, all addressable control/status register of a CPU and the 2nd CPU and data register.

In embodiments of the present invention, described bus system number is corresponding with the CPU number, all is two.

Preferably, bus system converts the sequential of a CPU and the 2nd CPU to be complementary with registers group sequential.

The present invention also provides a kind of communication system, to realize the mutual communication between a plurality of CPU, comprise at least the one CPU and the 2nd CPU, register cell and priority recognition unit, the one CPU links to each other with the priority recognition unit by bus system with the 2nd CPU, it is characterized in that the priority recognition unit is not discerned the communication instruction that CPU sends according to predefined each CPU communication priority rank, the communication instruction after identification is just realized visit to register cell according to priority level.

In embodiments of the present invention, described bus system comprises and the corresponding bus interface number of CPU number, all is 2.

Preferably, described register cell comprises control/status register group and data register bank.

In embodiments of the present invention, described priority level is just arranged by the order of a CPU write operation, a CPU read operation, the 2nd CPU write operation, the 2nd CPU read operation.

Further, in described register cell, be provided with at least one and interrupt application/removing position, in order to realize application interruption mutually between a CPU and the 2nd CPU.

The means of communication between CPU provided by the invention and the register, each access order that instructs of priority level decision according to predefined, the direct execution sequence of decision instruction from high in the end, do not need dynamically to adjust priority level, and, interrupt application/removing position by set-up register, very simply determined the interruption of each instruction access order and corresponding CPU.

Description of drawings

Fig. 1 is that the communication signal stream of the preferred embodiment of the present invention transmits synoptic diagram;

Fig. 2 is the communication process synoptic diagram between 2 CPU of the preferred embodiment of the present invention and the register cell;

Fig. 3 is 51 kernel accessing time sequence synoptic diagram of the preferred embodiment of the present invention;

Fig. 4 is the fixedly Avalong bus access sequential synoptic diagram of latent period of the embodiment of the invention;

Fig. 5 is the process flow diagram of the preferred embodiment of the present invention means of communication;

Fig. 6 is the CPU accessing time sequence synoptic diagram of the preferred embodiment of the present invention.

Embodiment

Below in conjunction with accompanying drawing specific embodiments of the invention are done detailed explanation.

The present invention is the data core instruction means of communication and a device between a kind of a plurality of CPU.Can solve the data core instruction communication problem between a plurality of CPU at the fpga chip of different producers by simple VHDL program design.

Referring to shown in Figure 1, in the preferred embodiments of the present invention, communication system can be divided into five class functional units: control/status register group, data register bank, priority judgement, a CPU and the 2nd CPU, at least 2 group bus interface (is example with first cpu bus interface and second cpu bus interface).Control/status register group and data register bank are used to store the Content of communciation buffer memory between each CPU.Two Bus Interface Units are to be used for being connected with the 2nd CPU with a CPU who needs communication respectively, realize the visit of CPU to two registers group.The priority recognition unit is used to realize the realization of access conflict arbitration between two CPU.When CPU sends communication instruction, by bus interface, the communication instruction of CPU is delivered to the priority recognition unit, other according to the communication priority rank that pre-defines, the content of identification communication instruction according to the content after the identification, goes to realize the visit to registers group.

Control herein/status register group and data register bank can be defined as 8,16 or 32 voluntarily, use the number of registers also can set as required, to guarantee to satisfy the needs of communication.These two registers group all are to allow the twoport visit, and promptly a CPU and the 2nd CPU can read and write the same space of two registers group, thereby improve the utilization ratio of registers group.Registers group herein can adopt conventional register, to save the cost of communication system.

Bus Interface Unit is the bridge that connects between CPU and the registers group, converts the bus timing that extends out of different CPU to read-write sequence that two registers group are supported, thereby guarantees the communication operate as normal between each CPU and the register.

The priority recognition unit is arbitrated the sequencing of two CPU access register unit, and according to predefined access privileges, control is when a CPU and the 2nd CPU initiate accessing time sequence simultaneously, and the highest operational order of execution priority takes the lead in.

Two registers group in the present embodiment can both be visited by two CPU, but the priority of visit is different.We can be set in advance, and the priority that a CPU writes register manipulation is the highest, next is successively: a CPU read register, the 2nd CPU write register, are the 2nd CPU read register at last, and this order also can optionally be adjusted certainly.After a CPU or the 2nd CPU finish the read-write operation of register cell, apply for interrupting to the other side by register cell, carry out corresponding operation with request the other side.

The course of work between two CPU and the register is referring to shown in Figure 2.In order to realize " the shaking hands " between two CPU, need in control/status register group, be provided with 1 and interrupt application/removing position, define as " reg3 " among Fig. 2.When CPU1 writes reg3=1, will send look-at-me to CPU2, expression CPU1 prepares in the written data registers group to the data that CPU2 transmits, and CPU2 can read.After CPU2 receives that this interrupts application, with the information in the read data register group, and write reg3=0, be used for falling clearly this look-at-me.In like manner, when CPU2 prepared to CPU1 transmission data, CPU2 write reg=1, will send to CPU1 this moment and interrupt application, after reading of data is interrupted in the CPU1 response, write reg=0, was used for falling clearly this and interrupted application.Hence one can see that, write to interrupt applying for that position reg3=1 will send the interruption application to the other side CPU, if write reg=0, then be to fall self interrupt identification clearly.If relate to interruption application and the removing of a plurality of CPU, then the multidigit of set-up register is interruption application/removing position as required, thereby defines the break sequence of each CPU.

Each action that realizes in fpga chip that is to say that all by rising edge of clock signal or negative edge triggering for generating when having only rising edge or negative edge to arrive, chip could be carried out single stepping.The present invention with rising edge clock signal as trigger condition, when running into rising edge clock, program can judge whether that arbitrary CPU conducts interviews to this module, if request of access is arranged, will judge according to the CPU numbering and the visit action (reading or writing) of sending visiting demand, the order of successively decreasing according to the second capable from left to right priority among Fig. 2 responds the CPU visiting demand again.After determining it to be conducted interviews, will require register is read and write according to sequential by that CPU

The priority recognition unit receives cpu instruction from bus interface, discerns the cpu instruction content according to the order that a CPU writes, a CPU reads, the 2nd CPU writes, the 2nd CPU reads.When recognizing when being a CPU write command, carry out the write command of a CPU earlier, data are write the appointment register, reg3 is set to 0 then, thereby interrupts to the 2nd CPU application, and waits for the instruction that receives next CPU; If it is the 2nd CPU write command that the priority recognition unit identifies, then carry out the write command of the 2nd CPU earlier, data are write the appointment register, reg3 is set to 1 then, thereby interrupts to CPU application, and waits for the instruction that receives next CPU; When the priority recognition unit identifies is CPU when reading instruction, and then directly reads the data of specifying register, data is delivered to the bus interface of corresponding CPU, and wait for the instruction of next CPU.

Because the CPU of different company examines and extends out bus and is not quite similar, therefore use bus interface to connect CPU and internal register group, thereby realize reliable data transmission.Extend out bus with the Avalon bus used in the FPGA and 51 kernels and be example, 51 kernel bus timings as shown in Figure 3, a read-write cycle needs 12 time clock.And can fill order's cycle read and write access based on the Avalon bus of FPGA, also fixedly latent period bus timing can be set as required, or in the unknown slow devices of visit or when being visited by slow devices, waiting signal is set, has the read-write sequence of slow devices to determine the access time of Avalong bus end flexibly.The Avalon sequential as shown in Figure 4.Therefore, in the present example,, the read-write cycle of registers group fixedly can be made as for 12 cycles, to cooperate CPU speed because 51 kernels are fixed access cycle.If adopt other bus type and CPU core, so corresponding sequential and cycle can pre-determine according to calculating, thereby satisfy the requirements for access of register and CPU core.

As shown in Figure 6, bus interface part input end is a cpu i/f, must satisfy the accessing time sequence requirement of CPU, could realize the communication with CPU.The output terminal of bus interface is fixed as the Avalon bus interface timing of the FPGA of altera corp.Therefore, bus interface partly is exactly the bridge of different CPU visit internal register.

Referring to shown in Figure 5, the means of communication of the present invention's design comprise first step S1, preestablish priority level, mainly be to set the access privileges of each CPU and the priority level of read/write operation, be defined under the prerequisite that a plurality of instruction access are arranged simultaneously, determine sequencing; The second step S2, CPU sends communication instruction, and promptly the access instruction that reads or writes register of CPU can be that a CPU sends instruction separately, also may be 2 instructions that CPU sends access register simultaneously; Third step S3 differentiates according to priority height order, mainly refers to the order that the priority recognition unit transmits according to bus herein, according to pre-determined priority orders, judges the execution sequence of each instruction; The 4th step S4 carries out the instruction that CPU sends, and promptly mainly is the access instruction that reads or writes register of carrying out CPU; The 5th step S5 waits for next communication instruction, promptly execute instruction after, wait for the arrival whether next instruction is arranged.If there are a plurality of instructions to need to carry out herein, then execute first instruction after, the order execution priority comes the second high-order instruction, after executing whole instructions, waits for the arrival of next instruction again.

Simple structure of the present invention, adaptability is strong, adopts identical programming language and design philosophy, has saved design time and cost to the full extent, when also effectively having guaranteed simultaneously a plurality of CPU access register, the reaction efficiency of register.

The above; it only is the specific embodiment of the present invention; but protection scope of the present invention is not limited thereto; any those of ordinary skill in the art are in the disclosed technical scope of the present invention; variation or the replacement that can expect without creative work all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain that claims were limited.

Claims

1, a kind of means of communication, comprise at least the one CPU and the 2nd CPU, define the communication priority rank between a CPU and the 2nd CPU, the one CPU and/or the 2nd CPU send communication instruction, the communication instruction that bus system reception CPU sends also passes to the priority recognition unit, the priority recognition unit is carried out corresponding communication instruction access to content register cell according to the content of priority orders identification communication instruction, waits for next communication instruction.

2, the means of communication according to claim 1 is characterized in that, described register cell is provided with at least one and interrupts application/removing position.

3, the means of communication according to claim 1 is characterized in that, described registers group comprises control/status register and data register, all addressable control/status register of a CPU and the 2nd CPU and data register.

4, the means of communication according to claim 1 is characterized in that, described bus system number is corresponding with the CPU number.

5, the means of communication according to claim 1 is characterized in that, bus system converts the sequential of a CPU and the 2nd CPU to be complementary with registers group sequential.

6, a kind of communication system, comprise at least the one CPU and the 2nd CPU, register cell and priority recognition unit, the one CPU links to each other with the priority recognition unit by bus system with the 2nd CPU, it is characterized in that, the priority recognition unit is not discerned the communication instruction that CPU sends according to predefined each CPU communication priority rank, and the communication instruction after identification is just realized visit to register cell according to priority level.

7, communication system according to claim 6 is characterized in that, described bus system comprises and the corresponding bus interface number of CPU number.

8, communication system according to claim 6 is characterized in that, described register cell comprises control/status register group and data register bank.

9, communication system according to claim 6 is characterized in that, described priority level is just arranged by the order of a CPU write operation, a CPU read operation, the 2nd CPU write operation, the 2nd CPU read operation.

10, communication system according to claim 6 is characterized in that, in described register cell, is provided with at least one and interrupts application/removing position.