WO2006027981A1 - 立体的電子回路装置とそれを用いた電子機器およびその製造方法 - Google Patents
立体的電子回路装置とそれを用いた電子機器およびその製造方法 Download PDFInfo
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- WO2006027981A1 WO2006027981A1 PCT/JP2005/015892 JP2005015892W WO2006027981A1 WO 2006027981 A1 WO2006027981 A1 WO 2006027981A1 JP 2005015892 W JP2005015892 W JP 2005015892W WO 2006027981 A1 WO2006027981 A1 WO 2006027981A1
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- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
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- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
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Definitions
- Three-dimensional electronic circuit device electronic device using the same, and manufacturing method thereof
- the present invention relates to a compact solid electronic circuit device in which a board module on which electronic components are mounted is built in a housing, an electronic device using the same, and a method for manufacturing the same.
- FIG. 16 In Japanese Patent Laid-Open No. 2002-207986 (hereinafter referred to as “patent document”), as shown in FIG. 16, two memory module substrates 420 each having a memory chip 410 mounted on one side of a mother substrate 400 are provided. There is disclosed a memory force having a structure in which a circuit control element 430 for controlling the memory chip 410 is mounted on the other surface of the mother substrate 400 and laminated in a housing 480 while being laminated in layers.
- the memory module substrates 420 are connected by an elastic body covered with a Cu ball 440 having a diameter of about 300 ⁇ m or a conductive film.
- the lower surface of the lower memory module substrate 420 and the mother substrate 400 are similarly connected by an elastic body coated with a Cu ball 450 or a conductive film.
- a bypass chip capacitor 460 is mounted on the upper surface of the mother substrate 400, and a connection terminal 470 for connecting to an external circuit is provided on the lower surface.
- a Cu ball or a conductive layer is provided between the memory module substrate and between the memory module substrate and the mother substrate.
- the wiring is connected by an elastic body covered with a conductive film.
- the size of the Cu ball cannot be reduced because it is necessary to secure the distance between the substrates by the size of the Cu ball and prevent the memory chip from contacting.
- the wiring connection can be formed only in one direction from the memory module substrate to the mother substrate.
- memory module boards that contain different ICs such as logic ICs and ASICs require fine wiring connections because the number of electrodes to be connected increases as the number of stacked layers increases. For this reason, force that is difficult to miniaturize for wiring connection with Cu balls, for example, it is possible to arrange them in a staggered manner so that Cu balls do not contact each other.
- the area for the connection electrode is increased, there is a problem that the mounting area of the semiconductor element or the like is decreased.
- the module substrate uses Cu balls as fulcrums, and the module substrate itself crawls. There is also a problem.
- a three-dimensional electronic circuit device of the present invention includes a control circuit, a housing including a connection terminal and a first wiring pattern, and an electronic component at its electrode end.
- a plurality of substrate modules having a second wiring pattern connected to electrode terminals on the surface of the first resin sheet are embedded in the first resin sheet so that the child is exposed.
- a board module unit in which the second wiring patterns between different board modules are connected by a through conductor portion, and the board module unit is fitted into the housing. 1 has a configuration in which the wiring pattern and the through conductor are connected.
- a connecting module or the like is used to connect a board module unit in which a necessary number of board modules having electronic components embedded therein are stacked and integrated together to the first wiring pattern formed on the inner surface of the housing.
- a three-dimensional electronic circuit device can be obtained that is thin and can be mounted at a high density without limiting the mounting density.
- the integrated board module unit can realize a three-dimensional electronic circuit device with improved mechanical strength and excellent reliability.
- a control circuit a housing including a connection terminal and a first wiring pattern, and electrode terminals are formed in the vicinity of two opposite sides of one surface.
- the bonded electronic component in which the other surfaces of the two electronic components are bonded together by shifting the positions of the electrode terminals, is embedded in the first resin sheet so that the surface of the electrode terminals is exposed.
- a plurality of substrate modules having a second wiring pattern connected to the electrode terminals are stacked on the surface of the first resin sheet and integrated together, and the second wiring patterns between different substrate modules are penetrated.
- a board module unit connected by a conductor portion, the board module unit is fitted in the housing, and the first wiring pattern of the housing and the through conductor portion are connected.
- the manufacturing method of the three-dimensional electronic circuit device of the present invention includes a step of forming a connection terminal, a control circuit, and a first wiring pattern on a housing, and an electrode having an electrode terminal formed on one surface.
- the manufacturing method of the three-dimensional electronic circuit device of the present invention includes a step of forming a connection terminal, a control circuit, and a first wiring pattern on a housing, and in the vicinity of two opposite sides of one surface. Bonded electronic components are embedded so that the other surfaces of the two electronic components having electrode terminals are bonded together by shifting the positions of the electrode terminals and the electrode terminals are exposed. A plurality of substrate modules having a second wiring pattern connected to the resin sheet and the electrode terminals exposed on the surface of the first resin sheet are stacked and integrated to form a second between different substrate modules. Forming a board module unit in which the wiring patterns are connected by a through conductor, and connecting the through conductor of the board module unit to the first wiring pattern of the housing.
- a three-dimensional electronic circuit device having a large capacity and high functionality in a limited mounting space can be obtained by stacking and integrating thin, thin board modules on which electronic components are mounted at high density. Can be produced with high productivity.
- FIG. 1A is a cross-sectional view of a three-dimensional electronic circuit device according to a first embodiment of the present invention.
- FIG. 1B is a cross-sectional view of the board module unit of the three-dimensional electronic circuit device according to the first embodiment of the present invention.
- FIG. 1C is a cross-sectional view of the substrate module of the three-dimensional electronic circuit device according to the first embodiment of the present invention.
- FIG. 2 is a cross-sectional view of a three-dimensional electronic circuit device according to another example of the first embodiment of the present invention.
- FIG. 3 is a flowchart illustrating a method for manufacturing a board module unit according to the first embodiment of the present invention.
- FIG. 4A is a fragmentary cross-sectional view for explaining the method of manufacturing the board module unit according to the first embodiment of the present invention.
- FIG. 4B is a cross-sectional view of the relevant part for explaining the method of manufacturing the board module unit according to the first embodiment of the present invention.
- FIG. 4C is a fragmentary cross-sectional view for explaining the method of manufacturing the board module unit according to the first embodiment of the present invention.
- FIG. 5A is a cross-sectional view of the three-dimensional electronic circuit device according to the second embodiment of the present invention.
- FIG. 5B is a cross-sectional view of the board module unit of the three-dimensional electronic circuit device according to the second embodiment of the present invention.
- FIG. 5C is a cross-sectional view of the substrate module of the three-dimensional electronic circuit device according to the second embodiment of the present invention.
- FIG. 6 is a sectional view of a three-dimensional electronic circuit device according to another example of the second embodiment of the present invention.
- FIG. 7 is a flowchart for explaining a method of manufacturing a board module unit according to the second embodiment of the present invention.
- FIG. 8A is a cross-sectional view of the relevant part for explaining the method of manufacturing the board module unit according to the second embodiment of the present invention.
- FIG. 8B is a cross-sectional view of the relevant part for explaining the method of manufacturing the board module unit according to the second embodiment of the present invention.
- FIG. 8C is a cross-sectional view of an essential part for explaining the method of manufacturing the board module unit according to the second embodiment of the present invention.
- FIG. 8D is a cross-sectional view of the relevant part for explaining the method of manufacturing the board module unit according to the second embodiment of the present invention.
- FIG. 9 is an exploded perspective view for explaining a second wiring pattern formed on the surface of the substrate module according to the second embodiment of the present invention and a method for stacking these substrate modules.
- FIG. 10A is a cross-sectional view of a three-dimensional electronic circuit device according to a third embodiment of the present invention.
- FIG. 10B shows a substrate module of the three-dimensional electronic circuit device according to the third embodiment of the present invention. It is sectional drawing of a joule unit.
- FIG. 10C is a cross-sectional view of the substrate module of the three-dimensional electronic circuit device according to the third embodiment of the present invention.
- FIG. 11A is a schematic diagram illustrating a second wiring pattern formed on the substrate module according to the third embodiment of the present invention.
- FIG. 11B is a cross-sectional view illustrating the correspondence between the second wiring pattern of FIG. 11A and the electrode terminals of the bonded electronic component.
- FIG. 12 is a flowchart for explaining a method of manufacturing a board module unit according to the third embodiment of the present invention.
- FIG. 13A is a sectional view of a key part for explaining the method for manufacturing a board module unit according to the third embodiment of the present invention.
- FIG. 13B is a sectional view of a key part for explaining the method for manufacturing the substrate module unit according to the third embodiment of the present invention.
- FIG. 13C is a cross-sectional view of the relevant part for explaining the method for manufacturing the substrate module unit according to the third embodiment of the present invention.
- FIG. 13D is a sectional view of a key part for explaining the method for manufacturing the substrate module unit according to the third embodiment of the present invention.
- FIG. 14 is a cross-sectional view of a three-dimensional electronic circuit device according to another example of the third embodiment of the present invention.
- FIG. 15 is a diagram illustrating an example of an electronic apparatus using a three-dimensional electronic circuit device.
- FIG. 16 is a cross-sectional view showing a schematic structure of a conventional memory card.
- FIG. 1A is a cross-sectional view of a three-dimensional electronic circuit device according to a first embodiment of the present invention
- FIG. 1B is a cross-sectional view of a board module unit
- FIG. 1C is a cross-sectional view of a board module.
- the board module unit 110 has a connection terminal 120, a control circuit 130 including a semiconductor element, etc. It is fitted into a casing 150 having a wiring pattern 140. Then, the first wiring pattern 140 formed on the inner surface of the housing 150 and the second wiring pattern 180 of the board module unit 110 are made of conductive paste, solder, anisotropic conductive resin, or the like through the through conductor portion 170.
- a three-dimensional electronic circuit device 100 is configured by electrical and mechanical connection.
- the control circuit 130 is an LSI having a semiconductor element force, and is mounted on an electrode pad (not shown) of the first wiring pattern 140 formed on the inner surface of the housing 150 by, for example, a flip chip method. Has been.
- the housing 150 is provided with a connection terminal 120 integrally with the housing 150 for connection to an external circuit or an electronic device.
- the casing 150 is made of, for example, polyetherimide (PEI), polyethersulfone (PES), polysulfone (PSF), syndiotactic polystyrene (SPS), polyamide resin (PA), polyphenylene-oxide. (PPO), polyphenylene ether (PPE), polyphthalamide (PPA) and liquid crystal polymer (LCP).
- PEI polyetherimide
- PES polyethersulfone
- PSF polysulfone
- SPS syndiotactic polystyrene
- PA polyamide resin
- PPO polyphenylene-oxide.
- PPE polyphenylene ether
- PPA polyphthalamide
- LCP liquid crystal polymer
- the electrodes of the first wiring pattern 140 and the connection terminal 120 are formed by, for example, Cu plating, Cu foil, conductive paste, or the like.
- the board module unit 110 is integrated by, for example, stacking six board modules 160 shown in FIG. 1C and fusing them together by heating and pressing. .
- the second wiring patterns 180 formed on the different substrate modules 160 are electrically and mechanically connected by the through conductor portions 170.
- the connection boundary surface of the first resin sheet 210 of each board module 160 disappears, and each electronic component 190 is embedded in the integrated first resin sheet.
- the mechanical strength of the board module unit 110 can be improved, and the reliability of the casing 150 against deformation such as bending stress can be improved.
- the board module 160 embeds the electronic component 190 in the first resin sheet 210 so that the electrode terminal 200 is exposed
- This structure has a second wiring pattern 180 and a through conductor 170 on the surface.
- the through conductor portion 170 is formed by filling a conductive resin in a through hole opened at a predetermined position of the first resin sheet 210 by a laser beam method or a drill method.
- the electronic component 190 is a chip-shaped bare chip thinned by polishing the back surface.
- a semiconductor memory such as DRAM, SRAM, flash memory, or FRAM is used as the electronic component 190.
- the first resin sheet 210 for example, polyester resin, vinyl chloride, polycarbonate, polyether ether ketone, polyether ketone, polyaryl ketone, polyether imide, polyphenylene sulfide, syndiotactic polystyrene, Thermoplastics Thermoplastic resins such as polyimide or acrylonitrile butadiene styrene, and epoxy / acrylic thermosetting resins are used.
- a three-dimensional electronic circuit device has a control circuit 130 mounted on a substrate module unit 110.
- the first wiring pattern 140 on the inner surface of the casing 150 needs to be three-dimensionally formed. Compared to the case where the first wiring pattern 140 is formed on a plane, the fine electrode pads necessary for connecting the control circuit 130 are formed. It is difficult to form the first wiring pattern 140 having a gate. However, in the three-dimensional electronic circuit device shown in FIG. 2, only the first wiring pattern 140 is formed on the inner surface of the housing 150, and fine electrode pads and the like for mounting and connecting the control circuit 130 are formed. There is no need to do it. Therefore, by forming fine electrode pads to be connected to the control circuit 130 on the flat substrate module unit 110 side that can be easily miniaturized, it is possible to easily mount the control circuit 130 that requires fine, pitch electrode pads. Can do.
- FIG. 3 is a flowchart for explaining the manufacturing method of the substrate module unit 110 according to the first embodiment of the present invention.
- FIGS. 4A to 4C are diagrams showing the main processing steps in FIG. FIG.
- step S1 an electrode component 200 is formed on one surface, and an electronic component 190 that has been thinned by polishing the other surface is prepared. In the following description, it is assumed that the thickness of the electronic component 190 is about 50 ⁇ m.
- step S2 one or a plurality of electronic components 190 having electrode terminals 200 are placed on a first resin sheet 210 having a thickness of about 75 m and having a thermoplastic resin isotropic force. Place in position.
- step S3 the first resin sheet 210 on which the electronic component 190 is placed is sandwiched between, for example, hot press plates and heated and pressed.
- the pressure is 30 kgZcm 2
- the heating temperature is 160 ° C
- the press time is 1 minute.
- polyester resin polyethylene terephthalate (PETG), butyl chloride, polycarbonate, acrylonitrile butadiene styrene, or the like can be used.
- step S4 the residue of the first resin sheet 210 on the surface of the electrode terminal 200 of the electronic component 190 is removed by a photolithography method and an etching method, a laser beam method, or the like.
- the electrode terminal 200 is reliably exposed on the surface.
- the electrode terminal 200 may be exposed by pressing a jig heated to a temperature higher than the melting temperature of the first resin sheet 210.
- step S4 may be omitted if the electrode terminal 200 is exposed when an electronic component is embedded in the first resin sheet 210 in step S3.
- Step S5 the surface (back surface) opposite to the electrode terminal 200 surface of the electronic component 190 is laminated with a second resin sheet (not shown) having a thickness of about 25 m, for example.
- step S6 the second wiring pattern 180 for connecting the electrode terminals 200 is formed by, for example, screen printing, ink jet printing, dispense printing or transfer printing of conductive paste, metal foil transfer, plating, thin film It is formed by a method such as formation or photolithography.
- step S5 may be laminated with a second resin sheet after step S6 of forming the second wiring pattern 180 on the surface of the electrode terminal 200 of the electronic component 190.
- the electronic component 190 is embedded as shown in FIG.
- the composite resin sheet 220 with the turn 180 formed is completed.
- step S7 the composite resin sheet 220 produced by the above method is cut into 160 units of the substrate module.
- step S8 as shown in FIG. 4B, for example, six substrate modules 160 are stacked.
- step S9 the laminated substrate module 160 is sandwiched between, for example, a heat press plate and heated and pressed to thereby provide six first resin sheets 210 and second resin sheets. Melts together.
- the first resin sheet 210 and the second resin sheet are polyethylene terephthalate
- the applied pressure is 35 kgZcm 2
- the heating temperature is 150 ° C.
- the pressing time is 1 minute.
- step S10 through-holes are formed at predetermined positions of the integrated substrate module, and a conductive paste is filled and cured, thereby providing a through-conductor portion 170 as shown in FIG. 4C.
- the completed board module unit 110 is completed.
- the control circuit 130 is mounted on the casing 150 in which the first wiring pattern 140 and the connection terminal 120 are formed.
- the first wiring pattern is formed by, for example, metal fitting or conductive-based ink jet, dispenser, transfer, or the like.
- the board module unit 110 shown in FIG. 4C is fitted into the housing 150, and the first land 230 of the board module unit 110 and the second land 240 on the inner surface of the housing 150 are connected by a conductive paste or the like. To do.
- the board module unit 110 may be embedded in the casing 150 after being inserted into the casing 150 and filled with an insulating grease or the like.
- the three-dimensional electronic circuit device 100 as shown in FIG. 1A is completed by the above method.
- a through hole is formed for each board module 160 in the composite resin sheet 220, and when the board module 160 is laminated after cutting, the through hole is positioned as a through conductor portion 170 between different board modules 160.
- the second wiring pattern 180 may be connected. The same applies to the following embodiments.
- FIG. 5A is a sectional view of the three-dimensional electronic circuit device according to the second embodiment of the present invention
- FIG. I is a cross-sectional view of the board module unit
- FIG. 5C is a cross-sectional view of the board module. 5A to 5C, the same components as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.
- the board module unit 250 includes the connection terminal 120, the control circuit 130, and the first wiring pattern 140. It is fitted in the case 150 provided. Then, the first wiring pattern 140 formed on the inner surface of the casing 150 and the second wiring pattern 180 of the board module unit 250 are electrically and mechanically electrically conductive and the like via the through conductor 170. It has a connected structure.
- the board module unit 250 has a configuration in which the board modules 260 shown in FIG.
- the second wiring patterns 180 formed on each board module 260 are connected by a through conductor portion 170 provided in a region where the bonded electronic component 270 does not exist.
- the bonded electronic component 270 is formed by bonding the other surfaces of the two electronic components 190 having the electrode terminals 200 formed on one surface and bonding them together.
- the board module 260 has a structure in which the bonded electronic component 270 is embedded in the first resin sheet 210 and the second wiring pattern 180 is provided on the front surface 210A and the back surface 210B.
- the substrate module 160 of the first embodiment is different.
- the substrate of the first embodiment on which the same number of electronic components 190 are mounted Compared with the module 160, the board module 260 can be made thinner. In the standardized mounting space, the mounting density of the electronic components 190 can be improved. Furthermore, by laminating and laminating the thinned electronic parts 190, there is an effect that the strength against deformation and the like is increased and the reliability is improved.
- a three-dimensional electronic circuit device 100 is one in which a control circuit 130 is mounted on a board module unit 250.
- a control circuit 130 is mounted on a board module unit 250.
- FIG. 7 is a flowchart illustrating a method for manufacturing substrate module unit 250 according to the second embodiment of the present invention.
- 8A to 8D are cross-sectional views of main parts in the main processing steps of FIG.
- step S1 the other surfaces of the two electronic components 190 having the electrode terminals 200 formed on one surface are bonded to each other with, for example, a resin adhesive to produce the bonded electronic component 270.
- a resin adhesive to produce the bonded electronic component 270.
- the thickness of each electronic component 190 is about 50 m
- the thickness of the bonded electronic component 270 is about 100 m.
- step S2 one or a plurality of bonded electronic components 270 are placed at predetermined positions on the first resin sheet 210 made of thermoplastic resin having a thickness of about 125 m.
- step S3 for example, it is sandwiched between hot press plates and heated and pressurized.
- the bonded electronic component 270 is embedded in the first resin sheet 210 with at least the electrode terminal 200 surface exposed. At this time, if necessary, bonded electronic components 27
- the electrode terminal 200 is removed from the first resin sheet 21.
- step S4 the second wiring pattern 180 that connects the electrode terminals 200 on the front surface 210A and the back surface 210B side is formed on the first resin sheet 210 by a screen printing method or a photolithography method. Form.
- the junction electronics as shown in Figure 8A
- step S5 as shown in FIG. 8B, the composite resin sheet 360 produced by the above method is folded for each substrate module 260, and the second resin sheet 280 is disposed between the substrate modules. And laminate.
- the second resin sheet 280 ensures insulation between the substrate modules 260.
- FIG. 8B the layers are shown separated from each other for easy understanding of the stacked state.
- step S6 the folded composite resin sheet 360 is sandwiched between, for example, a heat press plate and heated and pressed to thereby apply the first resin sheet 210 and the second resin sheet 280.
- the applied pressure is 35 kgZcm 2
- the heating temperature is 120 ° C.
- the pressing time is 1 minute.
- the material of the first resin sheet and the second resin sheet need not be the same, but it is preferable that the melting temperatures are the same.
- the first and second resin sheets are made of different materials, the lower the melting temperature of the second resin sheet than that of the first resin sheet, the more misaligned the electronic components, etc. It is preferable in preventing. The same applies to the other embodiments.
- step S7 when the folded end portion 290 of the composite resin sheet 360 is cut, a plurality of substrate modules 260 stacked as shown in FIG. 8C are completed.
- step S8 when through holes are formed in a region where the junction electronic component 270 of the integrated substrate module 260 does not exist, and the through holes are filled with a conductive paste or the like and cured, FIG. 8D
- the board module unit 250 having the through conductor 170 as shown in FIG.
- step S7 and step S8 may be omitted, and the folded and stacked state of FIG. 8B may be stored in the mounting space. In this case, it is necessary to bend the second wiring pattern so that it does not break at the folded portion.
- the arrangement order force of the electrode terminals 200 of the bonded electronic component 270 is arranged.
- the electronic component 190 on the front surface 210A side and the back surface 210B side of the first resin sheet 210 are arranged. It differs from electronic component 190. Therefore, an example of the second wiring pattern 180 connected to the electrode terminal 200 of the bonded electronic component 270 of the board module unit 250 will be described with reference to FIG.
- FIG. 9 shows the second wiring pattern 180 formed on the surface 210 A of the first resin sheet of the board module 260, and these board modules 260 are laminated via the second resin sheet 280. Shows the state.
- the second wiring pattern formed on the back surface 210B of the first resin sheet of the substrate module 260 is not shown in the drawing notation, as in the case of the second wiring pattern 180 on the front surface 210A,
- the same electrode terminals 200 of the component 190 are connected to each other and to the left and right lands 300.
- the land 210 on the front surface 210A of the first resin sheet of the board module 260 and the land 300 on the back surface 210B immediately below it correspond to the same electrode terminal 200 and are electrically connected by the through conductor 170. Yes.
- these substrate modules 260 are stacked to form a substrate module unit.
- the through conductor portion is not shown in the second resin sheet.
- the example has been described in which individual electronic components are bonded together, but the present invention is not limited to this.
- the bonded electronic component is composed of an electronic component having the same shape such as a semiconductor memory, the bonded electronic component can be obtained with high productivity by the following method.
- the other surfaces of two wafers such as a silicon substrate on which a plurality of semiconductor memories having electrode terminals are formed on one surface are aligned and bonded together.
- the bonded wafer is separated into individual bonded electronic parts by cutting each semiconductor memory by dicing or the like.
- the substrate module unit may be formed by cutting each substrate module individually and stacking them. Thereby, since the part used as an edge part is unnecessary, the yield of the board module in a composite resin sheet can be improved.
- FIG. 10A is a sectional view of a three-dimensional electronic circuit device according to a third embodiment of the present invention
- FIG. 10B is a sectional view of a board module unit
- FIG. 10C is a sectional view of the board module. 10A to 10C, the same components as those in FIG. 5 are denoted by the same reference numerals and description thereof is omitted.
- the board module unit 310 includes the connection terminal 120, the control circuit 130, and the first wiring.
- the case 150 is fitted with a pattern 140.
- the first wiring pattern 140 formed on the inner surface of the housing 150 and the second wiring pattern 180 of the board module unit 310 are electrically and mechanically connected by a conductive paste or the like through the through conductor 170. Has a structured.
- the substrate module unit 310 has a configuration in which the substrate modules 320 shown in FIG. Then, the second wiring patterns 180 formed in each board module 320 are connected by a through conductor portion 170 provided in a region where the bonded electronic component 330 does not exist.
- the bonded electronic component 330 is embedded in the first resin sheet 210, and the second wiring pattern 180 is provided on at least one of the front surface 210A and the back surface 210B. It has a provided structure.
- two electronic components 340, 350 having electrode terminals in the vicinity of two sides facing each other are arranged so as not to overlap in the thickness direction, and the other surfaces are Are integrally formed by bonding. In this respect, it is different from the substrate module 260 of the second embodiment.
- FIG. 11A and FIG. 11B are diagrams for explaining an example of the second wiring pattern 180 connected to the electrode terminal 200 of the bonded electronic component 330 facing each other between the board modules 320.
- FIG. 11A shows the second wiring formed on the substrate module 320 arranged on the lower side of FIG. 11B.
- 3 is a schematic diagram illustrating a pattern 180.
- FIG. The black circles in the figure indicate the arrangement of the electrode terminals 200 of the electronic component 340 of the board module 320 arranged on the upper side of FIG. 11B, and the numbers indicate the arrangement order of the electrode terminals 200.
- white circles in the figure indicate the arrangement of the electrode terminals 200 of the electronic components 350 of the board module 320 arranged on the lower side of FIG. 11B, and the numbers indicate the arrangement order of the electrode terminals 200.
- the bonded electronic components 330 facing each other between the stacked substrate modules 320 are connected to the electrode terminals 200 having the same number.
- the second wiring pattern 180 can connect the same arrangement order of the electrode terminals 200 as long as it is formed on one of the substrate modules 320 to be stacked.
- the second resin sheet 280 of the three-dimensional electronic circuit device 100 of the second embodiment is not necessary.
- the board module 320 can be made thinner and the mounting density of electronic components can be improved in a limited mounting space.
- FIG. 12 is a flowchart illustrating a method for manufacturing substrate module unit 310 according to the third embodiment of the present invention.
- 13A to 13D are cross-sectional views of the main part in the main processing step of FIG.
- step S1 the other surfaces of the two electronic components 340 and 350 in which the electrode terminal 200 is formed in the vicinity of two sides facing each other are shifted from each other with respect to the direction of the electrode terminal 200.
- the bonded electronic component 330 is manufactured by bonding with a resin adhesive or the like.
- the thickness of the electronic components 340 and 350 is about 50 m, the thickness of the bonded electronic component 330 is about 100 ⁇ m.
- step S2 one or a plurality of bonded electronic components 330 are placed at predetermined positions on the first resin sheet 210 made of thermoplastic resin having a thickness of about 125 m.
- step S3 for example, it is sandwiched between hot press plates and heated and pressurized.
- the bonded electronic component 330 is embedded in the first resin sheet 210 with at least the electrode terminal 200 surface exposed. At this time, if necessary, the residue of the first resin sheet 210 on the electrode terminal 200 of the bonded electronic component 330 is removed by a photolithography method, a laser beam method, or the like. May be exposed on the front surface 210A and the back surface 210B of the first resin sheet 210!
- step S4 the second terminal as shown in FIG. 11A is connected between at least one of the front surface 210A and the back surface 210B of the first resin sheet 210 between the electrode terminals 200 of the bonded electronic component 330.
- the wiring pattern 180 is formed by a screen printing method or a photolithography method.
- the second wiring pattern 180 is a force that needs to be formed on both surfaces of any one of the substrate modules that are the outermost layers of the substrate module unit. It is sufficient to form only on the surface.
- step S5 as shown in FIG. 13B, the composite resin sheet 370 produced by the above method is folded for each substrate module 320 and laminated.
- the layers are shown separated from each other for easy understanding of the stacked state!
- step S6 the folded composite resin sheet 370 is sandwiched between, for example, a heat press plate and heated and pressed.
- the first resin sheet 210 of each board module 320 is melted and integrated.
- the pressing force is 35 kgZcm 2
- the heating temperature is 120 ° C.
- the pressing time is 1 minute.
- step S7 the end portion 290 of the folded composite resin sheet 370 is cut to complete a plurality of substrate modules 320 stacked as shown in FIG. 13C.
- step S8 when a through hole is formed in a region where the bonded electronic component 330 of the integrated substrate module 320 does not exist, and the through hole is filled with a conductive paste or the like and cured, FIG. 13D
- a three-dimensional electronic circuit device 100 has a control circuit 130 mounted on a board module unit 310.
- the electrode pads connected to the control circuit 130 are formed on the flat substrate module unit 310 side that can be easily miniaturized, so that the control circuit 130 with a fine electrode pad pitch can be easily mounted. be able to.
- the substrate module unit is formed by folding the composite resin sheet.
- the present invention is not limited to this.
- the substrate module unit may be formed by cutting each substrate module individually and stacking them. Thereby, since the part used as an edge part is unnecessary, the yield of the board module in a composite resin sheet can be improved.
- the three-dimensional electronic circuit device eliminates the need for a mother board, and can increase the mounting density of electronic components in a limited mounting space, so that a large capacity can be obtained. It is useful for information storage devices that achieve higher functionality and for electronic devices that incorporate them.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US11/660,515 US7768795B2 (en) | 2004-09-08 | 2005-08-31 | Electronic circuit device, electronic device using the same, and method for manufacturing the same |
JP2006535695A JP4424351B2 (ja) | 2004-09-08 | 2005-08-31 | 立体的電子回路装置の製造方法 |
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JP2004-261091 | 2004-09-08 | ||
JP2004261091 | 2004-09-08 |
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WO2006027981A1 true WO2006027981A1 (ja) | 2006-03-16 |
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PCT/JP2005/015892 WO2006027981A1 (ja) | 2004-09-08 | 2005-08-31 | 立体的電子回路装置とそれを用いた電子機器およびその製造方法 |
Country Status (4)
Country | Link |
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US (1) | US7768795B2 (ja) |
JP (1) | JP4424351B2 (ja) |
CN (1) | CN100539135C (ja) |
WO (1) | WO2006027981A1 (ja) |
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US10741498B2 (en) * | 2018-07-12 | 2020-08-11 | Samsung Electronics Co., Ltd. | Semiconductor package |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11220262A (ja) * | 1997-11-25 | 1999-08-10 | Matsushita Electric Ind Co Ltd | 回路部品内蔵モジュールおよびその製造方法 |
JP2000269411A (ja) * | 1999-03-17 | 2000-09-29 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2001077294A (ja) * | 1999-09-02 | 2001-03-23 | Nec Corp | 半導体装置 |
JP2001217388A (ja) * | 2000-02-01 | 2001-08-10 | Sony Corp | 電子装置およびその製造方法 |
JP2002207986A (ja) * | 2000-10-02 | 2002-07-26 | Matsushita Electric Ind Co Ltd | カード型記録媒体及びその製造方法 |
JP2003218319A (ja) * | 2002-01-18 | 2003-07-31 | Ibiden Co Ltd | マルチチップ半導体装置 |
JP2003289128A (ja) * | 2002-01-23 | 2003-10-10 | Matsushita Electric Ind Co Ltd | 回路部品内蔵モジュールおよびその製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0134648B1 (ko) * | 1994-06-09 | 1998-04-20 | 김광호 | 노이즈가 적은 적층 멀티칩 패키지 |
KR100447313B1 (ko) * | 1996-11-21 | 2004-09-07 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 장치 및 그 제조방법 |
US6038133A (en) | 1997-11-25 | 2000-03-14 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module and method for producing the same |
JP2001175834A (ja) | 1999-12-17 | 2001-06-29 | Toshiba Corp | カード型電子機器およびその製造方法 |
CN1259200C (zh) | 2000-10-02 | 2006-06-14 | 松下电器产业株式会社 | 卡型记录媒体及其制造方法 |
DE10164800B4 (de) * | 2001-11-02 | 2005-03-31 | Infineon Technologies Ag | Verfahren zur Herstellung eines elektronischen Bauelements mit mehreren übereinander gestapelten und miteinander kontaktierten Chips |
TW200302685A (en) | 2002-01-23 | 2003-08-01 | Matsushita Electric Ind Co Ltd | Circuit component built-in module and method of manufacturing the same |
JP2006165175A (ja) * | 2004-12-06 | 2006-06-22 | Alps Electric Co Ltd | 回路部品モジュールおよび電子回路装置並びに回路部品モジュールの製造方法 |
-
2005
- 2005-08-31 CN CNB2005800296137A patent/CN100539135C/zh not_active Expired - Fee Related
- 2005-08-31 JP JP2006535695A patent/JP4424351B2/ja not_active Expired - Fee Related
- 2005-08-31 WO PCT/JP2005/015892 patent/WO2006027981A1/ja active Application Filing
- 2005-08-31 US US11/660,515 patent/US7768795B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11220262A (ja) * | 1997-11-25 | 1999-08-10 | Matsushita Electric Ind Co Ltd | 回路部品内蔵モジュールおよびその製造方法 |
JP2000269411A (ja) * | 1999-03-17 | 2000-09-29 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2001077294A (ja) * | 1999-09-02 | 2001-03-23 | Nec Corp | 半導体装置 |
JP2001217388A (ja) * | 2000-02-01 | 2001-08-10 | Sony Corp | 電子装置およびその製造方法 |
JP2002207986A (ja) * | 2000-10-02 | 2002-07-26 | Matsushita Electric Ind Co Ltd | カード型記録媒体及びその製造方法 |
JP2003218319A (ja) * | 2002-01-18 | 2003-07-31 | Ibiden Co Ltd | マルチチップ半導体装置 |
JP2003289128A (ja) * | 2002-01-23 | 2003-10-10 | Matsushita Electric Ind Co Ltd | 回路部品内蔵モジュールおよびその製造方法 |
Cited By (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8476774B2 (en) | 2006-10-10 | 2013-07-02 | Tessera, Inc. | Off-chip VIAS in stacked chips |
US9899353B2 (en) | 2006-10-10 | 2018-02-20 | Tessera, Inc. | Off-chip vias in stacked chips |
US9378967B2 (en) | 2006-10-10 | 2016-06-28 | Tessera, Inc. | Method of making a stacked microelectronic package |
US9048234B2 (en) | 2006-10-10 | 2015-06-02 | Tessera, Inc. | Off-chip vias in stacked chips |
US8999810B2 (en) | 2006-10-10 | 2015-04-07 | Tessera, Inc. | Method of making a stacked microelectronic package |
US8883562B2 (en) | 2007-07-27 | 2014-11-11 | Tessera, Inc. | Reconstituted wafer stack packaging with after-applied pad extensions |
JP2010534951A (ja) * | 2007-07-27 | 2010-11-11 | テッセラ,インコーポレイテッド | 適用後パッド延在部を伴う再構成ウエハ積層パッケージング |
US8461672B2 (en) | 2007-07-27 | 2013-06-11 | Tessera, Inc. | Reconstituted wafer stack packaging with after-applied pad extensions |
JP2010536171A (ja) * | 2007-08-03 | 2010-11-25 | テセラ・テクノロジーズ・ハンガリー・ケイエフティー | 再生ウェーハを使用する積層型パッケージ |
US8551815B2 (en) | 2007-08-03 | 2013-10-08 | Tessera, Inc. | Stack packages using reconstituted wafers |
KR101533663B1 (ko) * | 2007-08-03 | 2015-07-03 | 테세라, 인코포레이티드 | 재구성된 웨이퍼를 이용한 스택 패키지 |
US8513794B2 (en) | 2007-08-09 | 2013-08-20 | Tessera, Inc. | Stacked assembly including plurality of stacked microelectronic elements |
US8680662B2 (en) | 2008-06-16 | 2014-03-25 | Tessera, Inc. | Wafer level edge stacking |
US8647923B2 (en) | 2009-04-06 | 2014-02-11 | Canon Kabushiki Kaisha | Method of manufacturing semiconductor device |
JP2010245288A (ja) * | 2009-04-06 | 2010-10-28 | Canon Inc | 半導体装置の製造方法 |
JP2010245286A (ja) * | 2009-04-06 | 2010-10-28 | Canon Inc | 半導体装置の製造方法 |
JP2013520786A (ja) * | 2010-02-22 | 2013-06-06 | ジャコブ,アンドレアス | 半導体モジュールを製造するための方法およびシステム |
US9165907B2 (en) | 2010-02-22 | 2015-10-20 | Interposers Gmbh | Method and a system for producing a semi-conductor module |
US9978703B2 (en) | 2010-02-22 | 2018-05-22 | Regibus Max Microelectronics Llc | Method and a system for producing a semi-conductor module |
JP2014029958A (ja) * | 2012-07-31 | 2014-02-13 | Ajinomoto Co Inc | 半導体装置の製造方法 |
JP2016530720A (ja) * | 2013-09-27 | 2016-09-29 | インテル・コーポレーション | 複数の積層半導体デバイスを相互接続する方法 |
US10643975B2 (en) | 2013-09-27 | 2020-05-05 | Intel Corporation | Method for interconnecting stacked semiconductor devices |
US11024607B2 (en) | 2013-09-27 | 2021-06-01 | Intel Corporation | Method for interconnecting stacked semiconductor devices |
US11676944B2 (en) | 2013-09-27 | 2023-06-13 | Intel Corporation | Method for interconnecting stacked semiconductor devices |
US12033983B2 (en) | 2013-09-27 | 2024-07-09 | Intel Corporation | Method for interconnecting stacked semiconductor devices |
Also Published As
Publication number | Publication date |
---|---|
JPWO2006027981A1 (ja) | 2008-05-08 |
US20080094793A1 (en) | 2008-04-24 |
JP4424351B2 (ja) | 2010-03-03 |
US7768795B2 (en) | 2010-08-03 |
CN101015057A (zh) | 2007-08-08 |
CN100539135C (zh) | 2009-09-09 |
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