US20110308721A1 - Apparatus for manufacturing semiconductor devices - Google Patents

Apparatus for manufacturing semiconductor devices Download PDF

Info

Publication number
US20110308721A1
US20110308721A1 US12/888,251 US88825110A US2011308721A1 US 20110308721 A1 US20110308721 A1 US 20110308721A1 US 88825110 A US88825110 A US 88825110A US 2011308721 A1 US2011308721 A1 US 2011308721A1
Authority
US
United States
Prior art keywords
bonding
module
wafer
wafers
loadlock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/888,251
Other languages
English (en)
Inventor
Marcel Broekaart
Ionut Radu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Assigned to S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES reassignment S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BROEKAART, MARCEL, RADU, IONUT
Priority to US13/306,719 priority Critical patent/US20120067524A1/en
Publication of US20110308721A1 publication Critical patent/US20110308721A1/en
Assigned to SOITEC reassignment SOITEC CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
Priority to US13/624,470 priority patent/US9138980B2/en
Priority to US14/722,794 priority patent/US20150279830A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B38/00—Ancillary operations in connection with laminating processes
    • B32B38/18—Handling of layers or the laminate
    • B32B38/1858—Handling of layers or the laminate using vacuum
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16K—VALVES; TAPS; COCKS; ACTUATING-FLOATS; DEVICES FOR VENTING OR AERATING
    • F16K51/00—Other details not peculiar to particular types of valves or cut-off apparatus
    • F16K51/02—Other details not peculiar to particular types of valves or cut-off apparatus specially adapted for high-vacuum installations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67126—Apparatus for sealing, encapsulating, glassing, decapsulating or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67201—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the load-lock chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2309/00—Parameters for the laminating or treatment process; Apparatus details
    • B32B2309/60—In a particular environment
    • B32B2309/64—Sterile
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2309/00—Parameters for the laminating or treatment process; Apparatus details
    • B32B2309/60—In a particular environment
    • B32B2309/65—Dust free, e.g. clean room
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2309/00—Parameters for the laminating or treatment process; Apparatus details
    • B32B2309/60—In a particular environment
    • B32B2309/68—Vacuum
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor

Definitions

  • the present invention relates to an apparatus for the manufacture of semiconductor devices wherein the apparatus comprises a bonding module for the molecular bonding of wafers.
  • Three-dimensional (3-D) integrated circuit technology where circuit structures formed on several silicon-on-insulator (SOI) substrates are bonded together and integrated into a 3-D circuit with dense-vertical connections becomes of increasing importance in modern semiconductor technology (see, for example, paper by Burns et al., entitled A Wafer-Scale 3-D Circuit Integration Technology, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 10, OCTOBER 2006, pages 2507-2516).
  • the building blocks of the 3-D circuit integration technology are fully depleted SOI (FDSOI) circuit fabrication, precision wafer-wafer alignment, low-temperature wafer-wafer oxide bonding (molecular bonding, oxide fusion bonding), and electrical connection of the circuit structures with dense vertical interconnections.
  • FDSOI fully depleted SOI
  • the wafer-scale 3-D technology offers higher density vertical interconnections and reduced system power.
  • Molecular bonding of wafers requires that the surfaces of the same are sufficiently smooth, free of particles or contamination, and that they are sufficiently close to each other to allow contact to be initiated, typically at a distance of less than a few nanometres at a point of initiation. The contact will be initiated at a local point where the two wafer surfaces have the closest approach to each other. In this case, the forces of attraction between the two surfaces are sufficiently high to cause propagation from this location of a “bonding wave” and molecular adhesion (bonding induced by all of the forces of attraction—Van Der Waals forces—of the electronic interaction between the atoms or the molecules of the two surfaces of the wafers that are to be bonded).
  • bonding wave it is referred to the front of the bond or the molecular adhesion spreading from the point of initiation and corresponding to the dissemination of the forces of attraction (Van Der Waals forces) from the point of initiation over the entire surface of close contact between the two wafers (bonding interface).
  • molecular bonding faces the severe problems of bonding interface defects, wafer misalignment and wafer overlay defects due to heterogeneous distortions which appear in the transfer layer during its assembly with the receiving substrate. Such distortions are not the result of elementary transformations (translation, rotation or combinations thereof) that could originate in inaccurate assembly of the substrates (misalignment).
  • the present invention relates to an apparatus for the manufacture of semiconductor devices comprising a bonding module comprising a vacuum chamber to provide bonding of wafers under a pressure below atmospheric pressure; and a loadlock module connected to the bonding module and configured and dimensioned for wafer transfer to the bonding module and connected to a first vacuum pumping device configured to reduce the pressure in the loadlock module to below atmospheric pressure.
  • the apparatus may further comprising a second vacuum pumping device connected via a control valve to the vacuum chamber of the bonding module and configured to reduce the pressure in the vacuum chamber of the bonding module below atmospheric pressure.
  • the apparatus provides external access to the loadlock module and has the loadlock module connected to the bonding module by gates, wherein the loadlock module comprises a first gate that can be opened and closed for receipt of a wafer from an external environment and a second gate that can be opened and closed for transfer of a wafer from the loadlock module to the bonding module.
  • the apparatus may also have a larger loadlock module, wherein the loadlock module comprises a multi wafer storage system for storing multiple wafers to be transferred to the bonding module.
  • the apparatus may further comprise at least one additional loadlock module connected to the bonding module and configured and dimensioned to receive one or more bonded wafers from the bonding module.
  • the apparatus also has chucks that can hold and move the first and second wafers
  • the bonding module comprises at least a first moveable bonding chuck configured and dimensioned to hold a first wafer and a second moveable bonding chuck different from the first bonding chuck and configured and dimensioned to hold a second wafer different from the first wafer.
  • the first and second bonding chucks are configured to hold the first and the second wafer, respectively, in a vertical position within less than 10° with respect to a horizontal plane, and the first bonding chuck and/or the second bonding chuck is made of metal or ceramics that resists bending and bowing.
  • the first bonding chuck and second bonding chuck can be configured and dimensioned to hold first and second wafers that are at least 300 mm in diameter.
  • the apparatus can further comprise a control unit configured to control the first and the second bonding chucks to move towards each other, and to locate the first and the second wafers at a predetermined distance to each other, release the first and the second wafers at the predetermined distance, and to initiate local application of a force to at least one of the first and the second wafers such that they locally become that close to each other that bonding is initiated.
  • a control unit configured to control the first and the second bonding chucks to move towards each other, and to locate the first and the second wafers at a predetermined distance to each other, release the first and the second wafers at the predetermined distance, and to initiate local application of a force to at least one of the first and the second wafers such that they locally become that close to each other that bonding is initiated.
  • the apparatus can also further comprise a control unit configured to control the first and the second bonding chucks to move towards each other to locate the first and the second wafers at a predetermined distance to each other and, subsequently, locally decreasing the clamping force applied by the first and/or second bonding chucks in order to hold the first and second wafer, respectively, such that the first and the second wafers locally become that close to each other that bonding is initiated.
  • a control unit configured to control the first and the second bonding chucks to move towards each other to locate the first and the second wafers at a predetermined distance to each other and, subsequently, locally decreasing the clamping force applied by the first and/or second bonding chucks in order to hold the first and second wafer, respectively, such that the first and the second wafers locally become that close to each other that bonding is initiated.
  • the apparatus can have a control unit, wherein the control unit is configured to control gradual or non-gradual release of the first and/or second wafer, wherein the first and the second wafer become sufficiently close to each other at an initial location that bonding is initiated.
  • the invention also relates to a manufacturing system comprising the apparatus as described above, and further comprising a load port module configured and dimensioned to introduce a wafer into the manufacturing system; a plasma module configured to perform a plasma treatment of a surface of the wafer introduced in the manufacturing system; a cleaning module configured to clean the surface of the wafer; and a moveable robot device configured and dimensioned to transport the wafer from one of either the load port module, plasma module, cleaning module, and loadlock module to any other one of these modules.
  • the present invention also relates to a method for bonding semiconductor wafers, comprising the steps of evacuating a vacuum chamber of a bonding module; transferring at least a first wafer and a second wafer from an external environment to a loadlock module that is connected to the bonding module; evacuating the loadlock module after transfer of at least the first and second wafers to the loadlock module; transferring at least the first and second wafers from the evacuated loadlock module to the evacuated vacuum chamber of the bonding module; positioning the first wafer and a second wafer on a first and a second bonding chuck, respectively; and moving the first and the second wafer towards each other by movement of the first and/or second bonding chuck such that a main surface of the first wafer and a main surface of the second wafer locally come sufficiently close to each other to allow bonding to be initiated.
  • the method may also further comprise controlling the first and second bonding chucks with a control unit to either unclamp the first and second wafers in a gradual or non-gradual manner.
  • the method also involves positioning a first wafer and a second wafer, wherein the first and the second wafers are positioned in a vertical position within less than 10° with respect to a horizontal plane on the first and the second bonding chuck, respectively, and moved into a vertical position sufficiently close to each another to allow bonding to be initiated.
  • the method may further comprise adjusting the vacuum of the vacuum chamber after transfer of at least the first wafer.
  • FIG. 1 illustrates an example of the inventive apparatus for the manufacture of a semiconductor device comprising a bonding module and a load lock module connected to the bonding module.
  • FIG. 2 illustrates an example of a bonding module according to the present invention.
  • FIG. 3 illustrates an example of a manufacturing system comprising the apparatus illustrated in FIG. 1 .
  • FIG. 4 illustrates a preferred embodiment in which a second loadlock module is connected to the bonding module to improve wafer throughput.
  • the present invention addresses the above-mentioned need and, accordingly, relates to an apparatus for the manufacture of semiconductor devices comprising a bonding module comprising a vacuum chamber to provide bonding of wafers under a pressure below atmospheric pressure, and a loadlock module connected to the bonding module and configured for wafer transfer to the bonding module and connected to a first vacuum pumping device configured to reduce the pressure in the loadlock module below atmospheric pressure.
  • molecular bonding of wafers is performed in an evacuated vacuum chamber of a bonding module. Since the bonding is performed under (partial) vacuum, bonding interface defects, such as edge voids, can be significantly suppressed without affecting the bonding strength. In addition, wafers are transferred from the evacuated loadlock module to the vacuum chamber of the bonding module thereby significantly increasing the throughput as compared to the prior art. Since the loadlock module provides the wafers to the bonding module at vacuum pressure close to the low-pressure of the evacuated vacuum chamber of the bonding module, switching of the bonding module from vacuum pressure to atmospheric pressure and vice versa between two bonding steps (bonding step and step of transfer of at least one wafer from the loadlock module to the bonding module) is avoided. The bonding module and loadlock module are air tight, so as to be seal against the external atmospheric pressure, in order to maintain a vacuum pressure below one atmosphere during evacuation, transfer and bonding.
  • the loadlock module is evacuated by a first pumping device, for example, to a pressure between about 5 mbars to below atmospheric pressure (below 1 bar), or more preferably, to a pressure in the range of 1 mbars to 10 mbars.
  • the vacuum chamber of the bonding module is, for example, evacuated by a second pumping device to a pressure in the range of 0.01 mbars to 10 mbars, or more preferably, 0.1 mbars to 5 mbars. It is also noted that the temperature in the vacuum chamber is kept at room temperature in order to avoid deformation of the wafers due to thermal expansion of the wafer semiconductor material.
  • the first and/or the second pumping devices can be connected to the loadlock module and the vacuum chamber of the bonding module, respectively, by respective separate control valves provided to control the desired degree of vacuum.
  • a multi-stage rotary vane pump can be provided, for example.
  • the bonding module encloses all means and devices necessary for the aligned wafer bonding process under vacuum, and is, thus, hermetically closed from the environment.
  • the loadlock module may be configured to receive and transfer to the bonding module one wafer at a time or it may be configured to receive multiple wafers at the same time, that can be stored in a multi wafer storing system provided in the loadlock module.
  • the size of the loadloack module can be minimized such that the vacuum of the vacuum chamber of the bonding module is not heavily affected by opening a gate separating the bonding module from the loadlock module during wafer transfer. In the latter case, the throughput can be increased.
  • the loadlock module may comprise a first gate that can be opened and closed for receipt of a wafer and a second gate that can be opened and closed for transfer of a wafer from the loadlock module to the bonding module. After the wafer is received in the loadlock module via the opened first gate and the first gate is closed again the first pumping device can start evacuating the loadlock module.
  • At least one additional loadlock module connected to the bonding module and configured to receive one or more wafers or wafer stacks that were already bonded in the bonding module is provided in order to even further increase the throughput by allowing a first loadlock module to act as a source of unbonded wafers and the second loadlock module to act as a receiver of bonded wafers.
  • the bonding module may comprise at least a first moveable bonding chuck configured to hold a first wafer and a second moveable bonding chuck different from the first bonding chuck and configured to hold a second wafer different from the first wafer.
  • a robot means or devices can be provided inside the bonding module that is configured to grip the wafers from the loadlock system and position them on the bonding chuck. Gripping can be achieved by mechanical means, electrostatic means or vacuum (if the clamping vacuum is well below the operating vacuum level of the vacuum chamber of the bonding module).
  • the robotic device can also include any arms, joints, translational or rotational motion devices, positioning sensors and actuators known to those in the art.
  • Two movable bonding chucks positioned face to face, to support and clamp the wafers may be provided inside the vacuum chamber of the boning module.
  • the chucks are movable in translation and rotation in order to be able to position and align the two wafers in front to each other.
  • Each bonding chuck shall be provided with a planarity as good as possible, because it has been determined that chuck bow is one of the main reasons for overlay defects.
  • the chucks are made of metal or ceramics, which resist bending and bowing, and cannot be easily deformed and maintain the planarity of the wafer.
  • Bow of the chucks should preferably be below 1 micron or even below 0.1 micron.
  • the first and second bonding chucks can be configured, dimensioned and orientated to hold the first and the second wafer, respectively, in a vertical position within less than 10° with respect to a horizontal plane.
  • Each wafer has two main surfaces and four side surfaces.
  • the main surfaces of the wafers are orientated almost vertically with respect to a horizontal plane whereupon the bonding module is located.
  • the main surfaces of the wafers are orientated inclined to the horizontal plane with an angle of less than about 10°, more particularly, with an angle of less than about 5°, and even more preferably, with an angle of at most about 1°.
  • the apparatus may also include a control unit for controlling operation of different modules of the apparatus as well as the transfer of wafers from one module to another by means of the robotic devices.
  • an optical positioning system can be provided in the bonding module that is operated to identify the exact position of alignment marks on the wafers, and the two chucks are then moved in translation and rotation to align the wafers in accordance with the identified alignment marks.
  • the actual molecular (oxide fusion) bonding process can be controlled by the above-mentioned control unit according to different alternatives.
  • the clamping is released to free the two wafers from their chuck, and an additional force is applied locally to cause intimate contact (in terms of the acting molecular forces) of the wafers and initiate the bonding wave propagation.
  • This additional force should be minimized, for instance below 5 N or even below 1 N, so that no deformation of the wafer results.
  • the inventive apparatus may further comprise a control unit configured to control the first and the second bonding chucks to move to each other to locate the first and the second wafers at a predetermined distance to each other, release the first and the second wafers at the predetermined distance and to initiate local application of a force by an appropriate local force application means or device to at least one of the first and the second wafers such that they locally become that close to each other that bonding is initiated.
  • a control unit configured to control the first and the second bonding chucks to move to each other to locate the first and the second wafers at a predetermined distance to each other, release the first and the second wafers at the predetermined distance and to initiate local application of a force by an appropriate local force application means or device to at least one of the first and the second wafers such that they locally become that close to each other that bonding is initiated.
  • bonding is initiated by molecular forces acting between the main surfaces of the wafers that have approached or been positioned closely to each other and are to be bonded.
  • the intimate contact is first created, and then the un-clamping of the wafer is performed gradually.
  • Intimate contact in terms of the acting molecular forces, can be created by slightly deforming locally at least one of the wafers while bringing the two wafers in contact to each other. Deformation can be realized by locally decreasing the clamping force that retains the wafer to the chuck.
  • the un-clamping is performed gradually to control the propagation speed of the bonding wave.
  • un-clamping is performed non-gradually rather than gradually without any control of the bonding wave propagation. The latter approach is easier to implement.
  • the apparatus according to the present invention may further comprise a control unit configured to control the first and the second bonding chucks to move to each other to locate the first and the second wafers at a predetermined distance to each other, and subsequently, locally decreasing the clamping force applied by the first and/or second bonding chucks in order to hold the first and second wafer, respectively, such that the first and the second wafers locally become close enough to each other that bonding is initiated.
  • a control unit configured to control the first and the second bonding chucks to move to each other to locate the first and the second wafers at a predetermined distance to each other, and subsequently, locally decreasing the clamping force applied by the first and/or second bonding chucks in order to hold the first and second wafer, respectively, such that the first and the second wafers locally become close enough to each other that bonding is initiated.
  • the control unit may be configured to control gradual or non-gradual release of the first and/or second wafer, wherein the first and the second wafer become sufficiently close to each other at an initial location that bonding is initiated, where the wafers are sufficiently close when the surfaces of the wafers are less than a few nanometres from each other, or the forces of attraction between the two surfaces are sufficiently high to cause propagation from this location of a “bonding wave” and molecular adhesion.
  • the present invention provides a manufacturing system (see also detailed discussion below) comprising the apparatus of one of the above-described examples and further comprising a load port module configured to introduce a wafer from an external environment in the manufacturing system; a plasma module configured to perform a plasma treatment of a surface of the wafer introduced in the manufacturing system; a cleaning module configured to clean the surface of the wafer; and a moveable robot means or device configured and dimensioned to transport the wafer from one of the load port module, plasma module, cleaning module, and loadlock module to another one of these modules.
  • One or more plasma modules can be provided for activating one or both of the main surfaces of wafers.
  • the cleaning module cleans and/or brushes the surfaces of the wafers that are to be bonded to each other in the bonding module.
  • the robot means is a device suitably configured and dimensioned to manipulate and transfer the wafers from the load port to any individual module, and also from any one module to any other.
  • the robot in a preferred embodiment moves along a robot moving area, to enable the transfer of the wafer from one place to another.
  • the system may also include a control unit controlling operation of the individual modules and transfer of the wafers by the robotic devices.
  • the present invention also relates to a method for the bonding of semiconductor wafers, comprising the steps of evacuating a vacuum chamber of a bonding module; transferring at least a first wafer to a loadlock module that is connected to the bonding module; evacuating the loadlock module after transfer of at least the first wafer to the loadlock module; transferring at least the first wafer from the evacuated loadlock module to the evacuated vacuum chamber of the bonding module; optionally adjusting the vacuum of the vacuum chamber after transfer of the at least the first wafer if this is desired due to quality reasons of the bonded wafers; positioning the first wafer and a second wafer on a first and a second bonding chuck, respectively; and moving the first and the second wafer to each other by movement of the first and/or second bonding chuck such that a main surface of the first wafer and a main surface of the second wafer locally come that close to each other that bonding is initiated.
  • first and the second wafers can be positioned in a vertical position within less than 10° with respect to a horizontal plane on the first and the second bonding chuck, respectively, and moved in that vertical position that close to each other that bonding is initiated.
  • the apparatus of the present invention comprises a bonding module 1 and a loadlock module 2 .
  • Bonding is performed in a vacuum chamber of the bonding module 1 .
  • the vacuum in the vacuum chamber of the bonding module 1 is established by a vacuum pump 3 that is connected to the vacuum chamber of the bonding module 1 via a conduit or vacuum manifold having a control valve 4 .
  • a vacuum can be provided in the loadlock module 2 by another vacuum pump 5 that is connect by conduit or vacuum manifold having another control valve 6 to the loadlock module 2 .
  • the loadlock module 2 comprises a first gate 7 that is opened when a wafer is transferred from the loadlock module 2 to the bonding module 1 and a second gate 8 that is opened when a wafer is transferred by a robot to the loadlock module 2 from outside the bonding and loadlock modules.
  • the loadlock module 2 may be configured as a one-wafer transfer module providing one single wafer at the same time to the bonding module 1 or may include a multi wafer storing systems for receiving multiple wafers via the second gate 8 from an external environment and storing the same and, then, providing these multiple wafers to the bonding module 1 at the same time.
  • the loadlock module 2 is evacuated to some predetermined pressure. Evacuation may be provided by the pumping device 5 at a rate of between 2.5 and 1,000 m 3 /h, in particular, more than 500 m 3 /h.
  • the vacuum chamber of the bonding module 1 is, for example, evacuated to a pressure in the range of 0.01 mbars to 10 mbars, or more preferably, 0.1 mbars to 5 mbars.
  • the one or more wafers are transferred upon opening of the first gate 7 to the vacuum chamber of the bonding module 1 that was already evacuated by the first pumping device 3 , such as a multi-stage rotary vane pump. Since during this transfer of the one or more wafers from the loadlock module 2 to the bonding module 1 the bonding module is not exposed to atmospheric pressure, only a relatively slight adjustment of the pressure of the vacuum chamber of the bonding module 1 is necessary if at all after completion of the wafer transfer and closing of the first gate 7 . Thus, the throughput can significantly be increased, since the bonding module 1 does not cycle completely between atmospheric pressure and the operating vacuum pressure.
  • the throughput can be even further increased when another loadlock module 2 ′ is provided, for example, on the left-hand-side of the bonding module 1 of FIG. 1 and connected to the bonding module 1 by another gate 7 ′ to receive the already bonded wafers. (see FIG. 4 .)
  • the loadlock module 2 ′ can be used to output the bonded wafers from the bonding module 1 to the loadlock module 2 ′, where the bonded wafers can then be passed to the external environment through another gate 8 ′, while the bonding module 1 and loadlock module 2 remain under vacuum.
  • the other loadlock module 2 ′ is evacuated before transfer of the bonded wafers from the bonding module 1 .
  • the bonding module comprises a vacuum chamber 1 and is connected to a pumping device (not shown) as described with reference to FIG. 1 .
  • the bonding module comprises an optical system 9 that allows determining the exact position of alignment marks on the surfaces of the wafers to be bonded in the bonding module 1 .
  • the optical system 9 is only necessary if the two wafers need to be perfectly aligned. This is the case when the two wafers present micro-components.
  • micro-components is meant to mean elements that result from technical steps carried out on or in the layers that must be positioned with precision.
  • the micro-components may be active or passive components, a mere contact point, or interconnections, like copper contact and interconnects.
  • the alignment step may be skipped, and thus provision of the optical system 9 are not necessary.
  • the bonding module 1 is provided with a first bonding chunk 10 and a second bonding chunk 11 that clamp a first wafer 12 and a second wafer 13 , respectively.
  • the bonding chunks 10 and 11 may be made of metal or ceramics to maintain planarity of the wafers 12 and 13 .
  • the bonding chunks 11 and 12 are shown to hold the wafers 12 and 13 with their horizontally orientated main surfaces face-to-face
  • the bonding chunks 11 and 12 may advantageously be arranged to hold the wafers 12 and 13 with their vertically orientated main surfaces face-to-face. In this case, deformation of the wafers due to their own weight can be avoided.
  • the optical system 9 is electrically coupled to a control unit 14 that is computing the displacement of the bonding chucks 11 and 12 in the plane of alignment and in rotation in order to perfectly align the two wafers 12 and 13 .
  • the control unit 14 controls movement of the bonding chucks 11 and 12 towards each other until the wafers 12 and 13 come into contact for molecular bonding.
  • FIG. 3 illustrates an example of a manufacturing system 20 comprising the apparatus illustrated in FIG. 1 .
  • the manufacturing system 20 comprises a bonding module 1 , such as for example, the bonding module 1 shown in FIG. 2 , and two loadlock modules 2 and 2 ′.
  • the manufacturing system 20 includes a load port 21 for introducing wafers into the manufacturing system 20 .
  • a robot device 22 is configured and dimensioned to manipulate and transfer the wafers from the load port 21 to any individual module of the manufacturing system 20 , and also from one module to the other.
  • the robot is moving along a robot moving area that may be predetermined (indicated by dashed lines), to enable the transfer of the wafer from one place or module to another.
  • the manufacturing system 20 comprises at least one plasma station 23 for activating one or two main surfaces of the wafers introduced into the manufacturing system 20 .
  • a second plasma station could be added, if the wafer processing requires that both main surfaces of the wafers need to be activated.
  • the same plasma station 23 can be used to treat both main surfaces.
  • a first cleaning station 24 is provided to clean a bonding main surface of a first wafer and a second cleaning station 25 is provided to clean a bonding main surface of a second wafer.
  • the manufacturing system 20 further comprises a control unit (not shown in FIG. 3 ) for controlling the robot device 22 for transporting wafers in the manufacturing system 20 .
  • the control unit may control the robot means or device 22 to pick a first wafer from load port 21 and transport it to plasma station 23 ; pick a second wafer from load port 21 and transport it to cleaning station 25 ; pick the first wafer from plasma station 23 and transport it to cleaning station 24 ; pick the second wafer from cleaning station 25 and transport it to loadlock module 2 ′; pick the first wafer from cleaning station 24 and transport it to loadlock module 2 ; and pick bonded first and second wafers after they have been processed in the bonding module 1 from the loadlock module 2 or 2 ′ and transport it to the load port 21 .
US12/888,251 2010-06-22 2010-09-22 Apparatus for manufacturing semiconductor devices Abandoned US20110308721A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US13/306,719 US20120067524A1 (en) 2010-06-22 2011-11-29 Apparatus for manufacturing semiconductor devices
US13/624,470 US9138980B2 (en) 2010-06-22 2012-09-21 Apparatus for manufacturing semiconductor devices
US14/722,794 US20150279830A1 (en) 2010-06-22 2015-05-27 Method for bonding semiconductor wafers using a molecular bonding apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FRFR1002618 2010-06-22
FR1002618A FR2961630B1 (fr) 2010-06-22 2010-06-22 Appareil de fabrication de dispositifs semi-conducteurs

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US13/306,719 Division US20120067524A1 (en) 2010-06-22 2011-11-29 Apparatus for manufacturing semiconductor devices
US13/624,470 Continuation US9138980B2 (en) 2010-06-22 2012-09-21 Apparatus for manufacturing semiconductor devices

Publications (1)

Publication Number Publication Date
US20110308721A1 true US20110308721A1 (en) 2011-12-22

Family

ID=42699871

Family Applications (4)

Application Number Title Priority Date Filing Date
US12/888,251 Abandoned US20110308721A1 (en) 2010-06-22 2010-09-22 Apparatus for manufacturing semiconductor devices
US13/306,719 Abandoned US20120067524A1 (en) 2010-06-22 2011-11-29 Apparatus for manufacturing semiconductor devices
US13/624,470 Active US9138980B2 (en) 2010-06-22 2012-09-21 Apparatus for manufacturing semiconductor devices
US14/722,794 Abandoned US20150279830A1 (en) 2010-06-22 2015-05-27 Method for bonding semiconductor wafers using a molecular bonding apparatus

Family Applications After (3)

Application Number Title Priority Date Filing Date
US13/306,719 Abandoned US20120067524A1 (en) 2010-06-22 2011-11-29 Apparatus for manufacturing semiconductor devices
US13/624,470 Active US9138980B2 (en) 2010-06-22 2012-09-21 Apparatus for manufacturing semiconductor devices
US14/722,794 Abandoned US20150279830A1 (en) 2010-06-22 2015-05-27 Method for bonding semiconductor wafers using a molecular bonding apparatus

Country Status (8)

Country Link
US (4) US20110308721A1 (ja)
EP (2) EP2432007A3 (ja)
JP (2) JP5943408B2 (ja)
KR (2) KR101234001B1 (ja)
CN (3) CN105428285A (ja)
FR (1) FR2961630B1 (ja)
SG (1) SG177106A1 (ja)
TW (2) TWI443769B (ja)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110097874A1 (en) * 2008-09-02 2011-04-28 S.O.I.Tec Silicon On Insulator Technologies Progressive trimming method
US8338266B2 (en) 2010-08-11 2012-12-25 Soitec Method for molecular adhesion bonding at low pressure
US8429960B2 (en) 2010-08-24 2013-04-30 Soitec Process for measuring an adhesion energy, and associated substrates
US20150076216A1 (en) * 2010-11-05 2015-03-19 Raytheon Company Reducing formation of oxide on solder
US9138980B2 (en) 2010-06-22 2015-09-22 Soitec Apparatus for manufacturing semiconductor devices
US9548232B2 (en) 2012-06-20 2017-01-17 Tokyo Ohka Kogyo Co., Ltd. Attaching apparatus
US20170207191A1 (en) * 2016-01-15 2017-07-20 Taiwan Semiconductor Manufacturing Company Ltd. Bonding system and associated apparatus and method
US10504730B2 (en) * 2016-02-16 2019-12-10 Ev Group E. Thallner Gmbh Device and method for bonding of substates

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102010048043A1 (de) * 2010-10-15 2012-04-19 Ev Group Gmbh Vorrichtung und Verfahren zur Prozessierung von Wafern
JP6011034B2 (ja) * 2012-06-04 2016-10-19 株式会社村田製作所 ウエハ接合装置
CN103489805A (zh) * 2012-06-12 2014-01-01 苏州美图半导体技术有限公司 晶圆键合系统
CN103626122B (zh) * 2013-04-28 2016-05-11 苏州迪纳精密设备有限公司 一种阳极键合批量化生产设备
CN105904824B (zh) * 2016-04-22 2017-09-29 哈尔滨工业大学 一种利用水蒸气辅助及紫外光活化的被键合物键合装置及方法
CN110120181A (zh) * 2019-04-16 2019-08-13 武汉华星光电技术有限公司 加压脱泡装置及加压脱泡方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5223001A (en) * 1991-11-21 1993-06-29 Tokyo Electron Kabushiki Kaisha Vacuum processing apparatus
US20030079828A1 (en) * 2000-09-27 2003-05-01 Kassir Salman M. Tool for applying an insert or tape to chucks or wafer carriers used for grinding, polishing, or planarizing wafers
US20030168145A1 (en) * 2000-08-18 2003-09-11 Tadatomo Suga Method and apparatus for mounting
US20050152089A1 (en) * 2003-12-26 2005-07-14 Ngk Insulators, Ltd. Electrostatic chuck and manufacturing method for the same, and alumina sintered member and manufacturing method for the same
US20080053619A1 (en) * 2005-09-02 2008-03-06 Yukinori Nakayama Substrate assembly apparatus and method

Family Cites Families (78)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10012A (en) * 1853-09-13 Safety-valve foe
IT1230026B (it) 1988-10-28 1991-09-24 Sgs Thomson Microelectronics Processo di saldatura di fette di silicio fra loro, per la fabbricazione di dispositivi a semiconduttore
JPH0389519A (ja) 1989-08-31 1991-04-15 Sony Corp 半導体基板の製法
JPH0719737B2 (ja) 1990-02-28 1995-03-06 信越半導体株式会社 Ｓ０１基板の製造方法
JPH0636413B2 (ja) 1990-03-29 1994-05-11 信越半導体株式会社 半導体素子形成用基板の製造方法
JPH04263425A (ja) 1991-02-18 1992-09-18 Toshiba Corp 半導体基板の研削装置及び研削方法
JP3132029B2 (ja) * 1991-03-18 2001-02-05 ソニー株式会社 ウエハ貼り合わせ装置
KR0126455B1 (ko) 1992-05-18 1997-12-24 가나이 쯔또무 수지재료의 접착강도 측정방법
JP2701709B2 (ja) * 1993-02-16 1998-01-21 株式会社デンソー ２つの材料の直接接合方法及び材料直接接合装置
JP3321882B2 (ja) 1993-02-28 2002-09-09 ソニー株式会社 基板はり合わせ方法
JPH0799295A (ja) 1993-06-07 1995-04-11 Canon Inc 半導体基体の作成方法及び半導体基体
JP2662495B2 (ja) 1993-06-28 1997-10-15 住友シチックス株式会社 接着半導体基板の製造方法
US5696327A (en) 1994-11-23 1997-12-09 Regents Of The University Of Minnesota Method and apparatus for separating a thin film from a substrate
US5668045A (en) 1994-11-30 1997-09-16 Sibond, L.L.C. Process for stripping outer edge of BESOI wafers
US6113721A (en) 1995-01-03 2000-09-05 Motorola, Inc. Method of bonding a semiconductor wafer
US5937312A (en) 1995-03-23 1999-08-10 Sibond L.L.C. Single-etch stop process for the manufacture of silicon-on-insulator wafers
JPH0917984A (ja) 1995-06-29 1997-01-17 Sumitomo Sitix Corp 貼り合わせｓｏｉ基板の製造方法
JP3352896B2 (ja) 1997-01-17 2002-12-03 信越半導体株式会社 貼り合わせ基板の作製方法
JP3352902B2 (ja) 1997-02-21 2002-12-03 信越半導体株式会社 貼り合わせ基板の作製方法
JP3720515B2 (ja) 1997-03-13 2005-11-30 キヤノン株式会社 基板処理装置及びその方法並びに基板の製造方法
JP3132425B2 (ja) 1997-06-20 2001-02-05 日本電気株式会社 衛星イントラネットサービスにおける通信時間短縮方式
US6153524A (en) 1997-07-29 2000-11-28 Silicon Genesis Corporation Cluster tool method using plasma immersion ion implantation
JP3216583B2 (ja) 1997-08-22 2001-10-09 住友金属工業株式会社 貼り合わせｓｏｉ基板の製造方法
AU9296098A (en) 1997-08-29 1999-03-16 Sharon N. Farrens In situ plasma wafer bonding method
SG78332A1 (en) 1998-02-04 2001-02-20 Canon Kk Semiconductor substrate and method of manufacturing the same
US6221774B1 (en) 1998-04-10 2001-04-24 Silicon Genesis Corporation Method for surface treatment of substrates
US6117695A (en) 1998-05-08 2000-09-12 Lsi Logic Corporation Apparatus and method for testing a flip chip integrated circuit package adhesive layer
US6008113A (en) * 1998-05-19 1999-12-28 Kavlico Corporation Process for wafer bonding in a vacuum
JP3635200B2 (ja) 1998-06-04 2005-04-06 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JPH11354761A (ja) 1998-06-09 1999-12-24 Sumitomo Metal Ind Ltd Ｓｏｉ基板及びその製造方法
JP3321455B2 (ja) 1999-04-02 2002-09-03 株式会社アークテック 電極引張試験方法、その装置及び電極引張試験用の基板／プローブ支持装置並びに電極プローブ接合装置
US20020187595A1 (en) 1999-08-04 2002-12-12 Silicon Evolution, Inc. Methods for silicon-on-insulator (SOI) manufacturing with improved control and site thickness variations and improved bonding interface quality
JP3632531B2 (ja) 1999-11-17 2005-03-23 株式会社デンソー 半導体基板の製造方法
US6616332B1 (en) 1999-11-18 2003-09-09 Sensarray Corporation Optical techniques for measuring parameters such as temperature across a surface
KR100789205B1 (ko) 2000-03-29 2007-12-31 신에쯔 한도타이 가부시키가이샤 실리콘 웨이퍼 및 에스오아이 웨이퍼의 제조방법, 그리고그 에스오아이 웨이퍼
WO2003008938A2 (de) 2001-07-16 2003-01-30 Siemens Aktiengesellschaft Verfahren zum bestimmen der haftfestigkeit einer beschichtung auf einem bauteil
US6736017B2 (en) 2001-08-24 2004-05-18 Symyx Technologies, Inc. High throughput mechanical rapid serial property testing of materials libraries
JP2003115519A (ja) * 2001-10-04 2003-04-18 Mitsubishi Electric Corp 半導体装置の製造方法、半導体製造装置、ロードロック室、基板収納ケース、ストッカ
JP4093793B2 (ja) 2002-04-30 2008-06-04 信越半導体株式会社 半導体ウエーハの製造方法及びウエーハ
FR2874455B1 (fr) 2004-08-19 2008-02-08 Soitec Silicon On Insulator Traitement thermique avant collage de deux plaquettes
US6846380B2 (en) * 2002-06-13 2005-01-25 The Boc Group, Inc. Substrate processing apparatus and related systems and methods
US6958255B2 (en) 2002-08-08 2005-10-25 The Board Of Trustees Of The Leland Stanford Junior University Micromachined ultrasonic transducers and method of fabrication
JP4556158B2 (ja) 2002-10-22 2010-10-06 株式会社Ｓｕｍｃｏ 貼り合わせｓｏｉ基板の製造方法および半導体装置
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US7399681B2 (en) 2003-02-18 2008-07-15 Corning Incorporated Glass-based SOI structures
US7176528B2 (en) 2003-02-18 2007-02-13 Corning Incorporated Glass-based SOI structures
JP4066889B2 (ja) 2003-06-09 2008-03-26 株式会社Ｓｕｍｃｏ 貼り合わせ基板およびその製造方法
WO2005022610A1 (ja) 2003-09-01 2005-03-10 Sumco Corporation 貼り合わせウェーハの製造方法
CN1864255A (zh) * 2003-10-09 2006-11-15 Snt株式会社 具有非烧结aln的静电吸盘及其制备方法
FR2860842B1 (fr) 2003-10-14 2007-11-02 Tracit Technologies Procede de preparation et d'assemblage de substrats
JP4700680B2 (ja) 2004-03-05 2011-06-15 ザ リージェンツ オブ ザ ユニヴァーシティ オブ カリフォルニア 超薄膜を分離するガラスによって調節された応力波及びナノエレクトロニクス素子の作製
JP4821091B2 (ja) * 2004-04-08 2011-11-24 株式会社ニコン ウェハの接合装置
US7442992B2 (en) 2004-05-19 2008-10-28 Sumco Corporation Bonded SOI substrate, and method for manufacturing the same
WO2006038030A2 (en) * 2004-10-09 2006-04-13 Applied Microengineering Limited Equipment for wafer bonding
JP2006303087A (ja) 2005-04-19 2006-11-02 Sumco Corp シリコンウェーハの貼り合わせ方法および貼り合わせ装置
JP4918229B2 (ja) 2005-05-31 2012-04-18 信越半導体株式会社 貼り合わせウエーハの製造方法
JP5122731B2 (ja) 2005-06-01 2013-01-16 信越半導体株式会社 貼り合わせウェーハの製造方法
US7705342B2 (en) 2005-09-16 2010-04-27 University Of Cincinnati Porous semiconductor-based evaporator having porous and non-porous regions, the porous regions having through-holes
KR100755368B1 (ko) 2006-01-10 2007-09-04 삼성전자주식회사 3차원 구조를 갖는 반도체 소자의 제조 방법들 및 그에의해 제조된 반도체 소자들
JP4721435B2 (ja) 2006-04-06 2011-07-13 本田技研工業株式会社 接着部の剥離検査方法
TWI363212B (en) * 2006-05-26 2012-05-01 Advanced Display Proc Eng Co Adhesive chuck, and apparatus and method for assembling substrates using the same
CN101090082A (zh) * 2006-06-15 2007-12-19 中国科学院半导体研究所 多功能半导体晶片键合装置
US20080044984A1 (en) 2006-08-16 2008-02-21 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of avoiding wafer breakage during manufacture of backside illuminated image sensors
US7473909B2 (en) 2006-12-04 2009-01-06 Axcelis Technologies, Inc. Use of ion induced luminescence (IIL) as feedback control for ion implantation
WO2008069259A1 (en) * 2006-12-05 2008-06-12 Semiconductor Energy Laboratory Co., Ltd. Film formation apparatus, film formation method, manufacturing apparatus, and method for manufacturing light-emitting device
FR2912839B1 (fr) 2007-02-16 2009-05-15 Soitec Silicon On Insulator Amelioration de la qualite de l'interface de collage par nettoyage froid et collage a chaud
JP5143477B2 (ja) 2007-05-31 2013-02-13 信越化学工業株式会社 Ｓｏｉウエーハの製造方法
US8245751B2 (en) * 2007-11-07 2012-08-21 Advanced Display Process Engineering Co., Ltd. Substrate bonding apparatus
JP5320736B2 (ja) * 2007-12-28 2013-10-23 株式会社ニコン 半導体ウエハ貼り合わせ装置
JP4209457B1 (ja) * 2008-02-29 2009-01-14 三菱重工業株式会社 常温接合装置
FR2935537B1 (fr) 2008-08-28 2010-10-22 Soitec Silicon On Insulator Procede d'initiation d'adhesion moleculaire
FR2935535B1 (fr) 2008-09-02 2010-12-10 S O I Tec Silicon On Insulator Tech Procede de detourage mixte.
FR2935536B1 (fr) 2008-09-02 2010-09-24 Soitec Silicon On Insulator Procede de detourage progressif
KR101650971B1 (ko) 2008-11-16 2016-08-24 수스 마이크로텍 리소그라피 게엠바하 웨이퍼 메이팅이 개선된 웨이퍼 본딩 방법 및 그 장치
EP2200077B1 (en) 2008-12-22 2012-12-05 Soitec Method for bonding two substrates
FR2961630B1 (fr) 2010-06-22 2013-03-29 Soitec Silicon On Insulator Technologies Appareil de fabrication de dispositifs semi-conducteurs
US8338266B2 (en) 2010-08-11 2012-12-25 Soitec Method for molecular adhesion bonding at low pressure
FR2964193A1 (fr) 2010-08-24 2012-03-02 Soitec Silicon On Insulator Procede de mesure d'une energie d'adhesion, et substrats associes

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5223001A (en) * 1991-11-21 1993-06-29 Tokyo Electron Kabushiki Kaisha Vacuum processing apparatus
US20030168145A1 (en) * 2000-08-18 2003-09-11 Tadatomo Suga Method and apparatus for mounting
US20030079828A1 (en) * 2000-09-27 2003-05-01 Kassir Salman M. Tool for applying an insert or tape to chucks or wafer carriers used for grinding, polishing, or planarizing wafers
US20050152089A1 (en) * 2003-12-26 2005-07-14 Ngk Insulators, Ltd. Electrostatic chuck and manufacturing method for the same, and alumina sintered member and manufacturing method for the same
US20080053619A1 (en) * 2005-09-02 2008-03-06 Yukinori Nakayama Substrate assembly apparatus and method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Takagi et al. Room Temperature Silicon Wafer Direct Bonding in Vacuum by Ar Beam Irradiation. Micro Electro Mechanical Systems, 1997. MEMS '97, Proceedings, IEEE., Tenth Annual International Workshop on. 26 Jan 1997 - 30 Jan 1997. Nagoya, Japan. pages 191-196. Online search. URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=581801 *

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110097874A1 (en) * 2008-09-02 2011-04-28 S.O.I.Tec Silicon On Insulator Technologies Progressive trimming method
US8679944B2 (en) 2008-09-02 2014-03-25 Soitec Progressive trimming method
US9138980B2 (en) 2010-06-22 2015-09-22 Soitec Apparatus for manufacturing semiconductor devices
US8338266B2 (en) 2010-08-11 2012-12-25 Soitec Method for molecular adhesion bonding at low pressure
US8871611B2 (en) 2010-08-11 2014-10-28 Soitec Method for molecular adhesion bonding at low pressure
US8429960B2 (en) 2010-08-24 2013-04-30 Soitec Process for measuring an adhesion energy, and associated substrates
US20150076216A1 (en) * 2010-11-05 2015-03-19 Raytheon Company Reducing formation of oxide on solder
US9132496B2 (en) * 2010-11-05 2015-09-15 Raytheon Company Reducing formation of oxide on solder
US9548232B2 (en) 2012-06-20 2017-01-17 Tokyo Ohka Kogyo Co., Ltd. Attaching apparatus
US20170207191A1 (en) * 2016-01-15 2017-07-20 Taiwan Semiconductor Manufacturing Company Ltd. Bonding system and associated apparatus and method
US10504730B2 (en) * 2016-02-16 2019-12-10 Ev Group E. Thallner Gmbh Device and method for bonding of substates
US10636662B2 (en) 2016-02-16 2020-04-28 Ev Group E. Thallner Gmbh Device and method for bonding of substrates
US10748770B2 (en) 2016-02-16 2020-08-18 Ev Group E. Thallner Gmbh Device and method for bonding of substrates
US10861699B2 (en) 2016-02-16 2020-12-08 Ev Group E. Thallner Gmbh Device and method for bonding of substrates
US11251045B2 (en) 2016-02-16 2022-02-15 Ev Group E. Thallner Gmbh Device and method for bonding of substrates
US11527410B2 (en) 2016-02-16 2022-12-13 Ev Group E. Thallner Gmbh Device and method for bonding of substrates

Also Published As

Publication number Publication date
KR101234001B1 (ko) 2013-02-18
EP2432007A3 (en) 2017-03-22
SG177106A1 (en) 2012-01-30
US20150279830A1 (en) 2015-10-01
EP2432007A2 (en) 2012-03-21
CN105428285A (zh) 2016-03-23
CN102299048A (zh) 2011-12-28
TWI443769B (zh) 2014-07-01
CN102437073B (zh) 2015-07-22
TW201203438A (en) 2012-01-16
US20130032272A1 (en) 2013-02-07
CN102437073A (zh) 2012-05-02
US20120067524A1 (en) 2012-03-22
US9138980B2 (en) 2015-09-22
KR101363351B1 (ko) 2014-02-14
JP5943408B2 (ja) 2016-07-05
TWI449118B (zh) 2014-08-11
KR20120016299A (ko) 2012-02-23
EP2400526A3 (en) 2013-01-16
FR2961630B1 (fr) 2013-03-29
TW201225203A (en) 2012-06-16
EP2400526A2 (en) 2011-12-28
FR2961630A1 (fr) 2011-12-23
JP2012039089A (ja) 2012-02-23
JP5776538B2 (ja) 2015-09-09
KR20110139149A (ko) 2011-12-28
JP2012099839A (ja) 2012-05-24

Similar Documents

Publication Publication Date Title
US9138980B2 (en) Apparatus for manufacturing semiconductor devices
KR102338773B1 (ko) 온-더-플라이 기판 센터링을 갖는 처리 장치
US8819923B2 (en) Joint apparatus
JP2007266058A (ja) 常温接合装置
JP2006248895A (ja) 接合方法及びこの方法により作成されるデバイス並びに接合装置
KR20210028660A (ko) 공유 본딩 반도체 인터페이스들
JP2015018920A (ja) 接合装置、接合システム、接合方法、プログラム及びコンピュータ記憶媒体
JP2015015269A (ja) 接合装置、接合システム、接合方法、プログラム及びコンピュータ記憶媒体
JP2017034107A (ja) 接合装置、接合システム、接合方法、プログラム及びコンピュータ記憶媒体
JP2005187321A (ja) 接合方法及びこの方法により作成されるデバイス並びに接合装置
JP4859895B2 (ja) 常温接合装置
JP4875678B2 (ja) 常温接合装置
Suga et al. A new wafer-bonder of ultra-high precision using surface activated bonding (SAB) concept
JP6244188B2 (ja) 接合装置、接合方法および接合システム
CN219873412U (zh) 一种晶圆键合设备
JP4875676B2 (ja) 常温接合装置
WO2023182255A1 (ja) 接合システムおよび接合方法
WO2022181655A1 (ja) 接合方法、基板接合装置および基板接合システム
JP2011129777A (ja) 基板重ね合わせ装置及びデバイスの製造方法
JPH0556953U (ja) 基板処理装置

Legal Events

Date Code Title Description
AS Assignment

Owner name: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, FRANC

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BROEKAART, MARCEL;RADU, IONUT;SIGNING DATES FROM 20100921 TO 20100927;REEL/FRAME:025325/0117

AS Assignment

Owner name: SOITEC, FRANCE

Free format text: CHANGE OF NAME;ASSIGNOR:S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES;REEL/FRAME:027800/0911

Effective date: 20110906

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION