US20110297912A1 - Non-Volatile Memory Having 3d Array of Read/Write Elements with Vertical Bit Lines and Laterally Aligned Active Elements and Methods Thereof - Google Patents

Non-Volatile Memory Having 3d Array of Read/Write Elements with Vertical Bit Lines and Laterally Aligned Active Elements and Methods Thereof Download PDF

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Publication number
US20110297912A1
US20110297912A1 US13/151,217 US201113151217A US2011297912A1 US 20110297912 A1 US20110297912 A1 US 20110297912A1 US 201113151217 A US201113151217 A US 201113151217A US 2011297912 A1 US2011297912 A1 US 2011297912A1
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Prior art keywords
memory
lines
bit lines
word
memory elements
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George Samachisa
Johann Alsmeier
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SanDisk Technologies LLC
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SanDisk 3D LLC
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Priority to US13/151,217 priority Critical patent/US20110297912A1/en
Priority to CN2011800286855A priority patent/CN102971799A/zh
Priority to PCT/US2011/039416 priority patent/WO2011156351A1/en
Priority to JP2013514293A priority patent/JP2013535101A/ja
Priority to KR1020137000288A priority patent/KR20130132373A/ko
Priority to EP11725298.1A priority patent/EP2580758A1/en
Priority to TW100120027A priority patent/TW201209827A/zh
Assigned to SANDISK 3D LLC reassignment SANDISK 3D LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ALSMEIER, JOHANN, SAMACHISA, GEORGE
Publication of US20110297912A1 publication Critical patent/US20110297912A1/en
Priority to US14/057,971 priority patent/US9245629B2/en
Assigned to SANDISK TECHNOLOGIES INC. reassignment SANDISK TECHNOLOGIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SANDISK 3D LLC.
Assigned to SANDISK TECHNOLOGIES INC. reassignment SANDISK TECHNOLOGIES INC. CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT LISTED PATENT NUMBER 8853569 TO THE CORRECT PATENT NUMBER 8883569 PREVIOUSLY RECORDED ON REEL 038300 FRAME 0665. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Assignors: SANDISK 3D LLC
Assigned to SANDISK TECHNOLOGIES LLC reassignment SANDISK TECHNOLOGIES LLC CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: SANDISK TECHNOLOGIES INC
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H10N70/235—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect between different crystalline phases, e.g. cubic and hexagonal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/823—Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/884—Switching materials based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors
    • H10N70/8845—Carbon or carbides

Definitions

  • the subject matter of this application is the structure, use and making of re-programmable non-volatile memory cell arrays, and, more specifically, to three-dimensional arrays of memory storage elements formed on semiconductor substrates.
  • flash memory A popular form of flash memory is a card that is removably connected to the host through a connector.
  • flash memory cards that are commercially available, examples being those sold under trademarks CompactFlash (CF), the MultiMediaCard (MMC), Secure Digital (SD), miniSD, microSD, Memory Stick, Memory Stick Micro, xD-Picture Card, SmartMedia and TransFlash.
  • CF CompactFlash
  • MMC MultiMediaCard
  • SD Secure Digital
  • miniSD microSD
  • Memory Stick Memory Stick Micro
  • xD-Picture Card SmartMedia
  • TransFlash Flash memory cards
  • flash memory systems in widespread use is the flash drive, which is a hand held memory system in a small elongated package that has a Universal Serial Bus (USB) plug for connecting with a host by plugging it into the host's USB receptacle.
  • USB Universal Serial Bus
  • SanDisk Corporation assignee hereof, sells flash drives under its Cruzer, Ultra and Extreme Contour trademarks.
  • flash memory systems a large amount of memory is permanently installed within host systems, such as within a notebook computer in place of the usual disk drive mass data storage system.
  • host systems such as within a notebook computer in place of the usual disk drive mass data storage system.
  • Each of these three forms of mass data storage systems generally includes the same type of flash memory arrays.
  • the flash memory is typically formed on one or more integrated circuit chips and the controller on another circuit chip. But in some memory systems that include the controller, especially those embedded within a host, the memory, controller and drivers are often formed on a single integrated circuit chip.
  • addresses of data files generated or received by the system are mapped into distinct ranges of a continuous logical address space established for the system.
  • the extent of the address space is typically sufficient to cover the full range of addresses that the system is capable of handling.
  • magnetic disk storage drives communicate with computers or other host systems through such a logical address space.
  • the host system keeps track of the logical addresses assigned to its files by a file allocation table (FAT) and the memory system maintains a map of those logical addresses into physical memory addresses where the data are stored.
  • FAT file allocation table
  • Most memory cards and flash drives that are commercially available utilize this type of interface since it emulates that of magnetic disk drives with which hosts have commonly interfaced.
  • Flash memory systems typically utilize integrated circuits with arrays of memory cells that individually store an electrical charge that controls the threshold level of the memory cells according to the data being stored in them. Electrically conductive floating gates are most commonly provided as part of the memory cells to store the charge but dielectric charge trapping material is alternatively used.
  • a NAND architecture is generally preferred for the memory cell arrays used for large capacity mass storage systems. Other architectures, such as NOR, are typically used instead for small capacity memories. Examples of NAND flash arrays and their operation as part of flash memory systems may be had by reference to U.S. Pat. Nos. 5,570,315, 5,774,397, 6,046,935, 6,373,746, 6,456,528, 6,522,580, 6,643,188, 6,771,536, 6,781,877 and 7,342,279.
  • the amount of integrated circuit area necessary for each bit of data stored in the memory cell array has been reduced significantly over the years, and the goal remains to reduce this further.
  • the cost and size of the flash memory systems are therefore being reduced as a result.
  • the use of the NAND array architecture contributes to this but other approaches have also been employed to reducing the size of memory cell arrays.
  • One of these other approaches is to form, on a semiconductor substrate, multiple two-dimensional memory cell arrays, one on top of another in different planes, instead of the more typical single array. Examples of integrated circuits having multiple stacked NAND flash memory cell array planes are given in U.S. Pat. Nos. 7,023,739 and 7,177,191.
  • variable resistance memory elements that may be set to either conductive or non-conductive states (or, alternately, low or high resistance states, respectively), and some additionally to partially conductive states and remain in that state until subsequently re-set to the initial condition.
  • the variable resistance elements are individually connected between two orthogonally extending conductors (typically bit and word lines) where they cross each other in a two-dimensional array. The state of such an element is typically changed by proper voltages being placed on the intersecting conductors.
  • variable resistive memory elements Since these voltages are necessarily also applied to a large number of other unselected resistive elements because they are connected along the same conductors as the states of selected elements being programmed or read, diodes are commonly connected in series with the variable resistive elements in order to reduce leakage currents that can flow through them.
  • the desire to perform data reading and programming operations with a large number of memory cells in parallel results in reading or programming voltages being applied to a very large number of other memory cells.
  • An example of an array of variable resistive memory elements and associated diodes is given in patent application publication no. US 2009/0001344 A1.
  • a 3D memory includes memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction.
  • the memory elements in each plane are accessed by a plurality of word lines and relatively short local bit lines in tandem with a plurality of global bit lines.
  • the plurality of local bit lines are in the z-direction through the plurality of planes and arranged in a two dimensional rectangular array of rows in the x-direction and columns in the y-directions.
  • the plurality of word lines in each plane are elongated in the x-direction and spaced apart in the y-direction between and separated from the plurality of local bit lines in the individual planes.
  • a non-volatile, reprogramming memory element is located near a crossing between a word line and local bit line and accessible by the word line and local bit line and wherein a group of memory elements are accessible in parallel by a common word line and a row of local bit lines.
  • the memory has the structure of a 3D resistive mesh.
  • the memory elements used in the three-dimensional array are preferably variable resistive memory elements. That is, the resistance (and thus inversely the conductance) of the individual memory elements is typically changed as a result of a voltage placed across the orthogonally intersecting conductors to which the element is connected.
  • the state may change in response to a voltage across it, a level of current though it, an amount of electric field across it, a level of heat applied to it, and the like.
  • it is the amount of time that the voltage, current, electric field, heat and the like is applied to the element that determines when its conductive state changes and the direction in which the change takes place. In between such state changing operations, the resistance of the memory element remains unchanged, so is non-volatile.
  • the three-dimensional array architecture summarized above may be implemented with a memory element material selected from a wide variety of such materials having different properties and operating characteristics.
  • the 3D memory preferably has a single-sided word line architecture with each word line exclusively connected to one row of memory elements. This is accomplished by providing one word line for each row of memory elements instead of sharing one word line between two rows of memory elements and linking the memory element across the array across the word lines.
  • a single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line. This helps to reduce the leakage across the resistive mesh.
  • the 3D array is formed by a process in which the R/W elements, and optionally diodes, are formed, not layer by layer vertically as in prior art, but laterally on all layers simultaneously. This is accomplished by creating a simple multi-layer structure, exposing a cross section of the stratified layers by opening a portal and forming fine structures in each of the exposed layers in a lateral direction. This process is advantageous whether diodes are included or not since it does not require as many numbers of processing steps as processing layer by layer.
  • diodes are commonly connected in series with the R/W elements of a 3D memory array in order to reduce leakage currents in the resistive mesh.
  • a R/W element also referred to earlier as NVM
  • the diode is typically much larger in size compared to the NVM.
  • the diodes form a layer above the NVM and substantially increase the thickness of the memory.
  • the various techniques disclosed in the description offer reduction in leakage enables a viable 3D array that can do away with a diode in series with every R/W element. At least, the reduction in leakage brought by the short bit lines and single-side word lines enables a viable 3D array to employ a less than ideal diode (or what might be considered as a “lousy diode”) in series with each R/W element.
  • each R/W element with a diode in series are formed in a lateral direction between a word line and a bit line at a crossing.
  • Forming the active devices such as diodes is a high-temperature process. If metallization takes place before the forming of the active devices, the metal will have to be able to withstand the high-temperature processes that follow. This may exclude the use of aluminum or copper for their better conductivity and economy. The increased resistance in the word lines can exacerbate leakage problems.
  • the present process allows the high-temperature process for all the layers to be clustered together and processed simultaneously, rather than layer by layer.
  • the metallization for the word lines can be performed after the high-temperature process. Therefore, it is amenable to using relatively low-temperature metallization.
  • FIG. 1 is an equivalent circuit of a portion of a three-dimensional array of variable resistance memory elements, wherein the array has vertical bit lines;
  • FIG. 2 is a schematic block diagram of a re-programmable non-volatile memory system which utilizes the memory cell array of FIG. 1 , and which indicates connection of the memory system with a host system;
  • FIG. 3 provides plan views of the two planes and substrate of the three-dimensional array of FIG. 1 , with some structure added;
  • FIG. 4 is an expanded view of a portion of one of the planes of FIG. 3 , annotated to show effects of programming data therein;
  • FIG. 5 is an expanded view of a portion of one of the planes of FIG. 3 , annotated to show effects of reading data therefrom;
  • FIG. 6 illustrates an example memory storage element
  • FIG. 7 is an isometric view of a portion of the three-dimensional array shown in FIG. 1 according to a first specific example of an implementation thereof;
  • FIG. 8 is cross-section of a portion of the three-dimensional array shown in FIG. 1 according to a second specific example of an implementation thereof;
  • FIGS. 9-14 illustrate a process of forming the three-dimensional array example of FIG. 8 .
  • FIG. 15 is a cross-section of a portion of the three-dimensional array shown in FIG. 1 according to a third specific example of an implementation thereof
  • FIG. 16 illustrates the read bias voltages and current leakage across multiple planes of the 3D memory shown in FIG. 1 and FIG. 3 .
  • FIG. 17 illustrates a three-dimensional memory with a double-global-bit-line architecture for improved access to a set of local bit lines.
  • FIG. 18 illustrates the elimination of leakage currents in the double-global-line architecture 3D array of FIG. 17 .
  • FIG. 19 illustrates schematically a single-sided word line architecture.
  • FIG. 20 illustrates one plane and substrate of the 3D array with the single-sided word line architecture.
  • FIG. 21 illustrates the elimination of leakage currents in the single-sided word-line architecture 3-D array of FIGS. 19 and 20 .
  • FIG. 22 is an isometric view of a portion of the 3D array with the single-sided word line architecture shown in FIG. 19 .
  • FIG. 23 illustrates a preferred 3D memory structure with vertical local bit lines and horizontally formed active memory elements and diodes.
  • FIG. 24A illustrates in more detail the R/W element and diode formed between a pair of word line and bit line at a crossing.
  • FIG. 24B illustrates schematically the equivalent circuit of the R/W memory element 346 and diode 336 in series between each crossing of a word line 340 and a local bit line 330 .
  • FIG. 25A illustrates the formation of the BEOL portion as a multi-layer structure being formed on top of the FEOL base layer.
  • FIG. 25B illustrates the formation of trenches where the plurality of local bit lines 330 are to be formed in the 3D structure of FIG. 25A .
  • FIG. 25C illustrates the formation of the local bit lines in the trenches of FIG. 25B .
  • FIG. 25D illustrates the formation of a portal to access the stratified 3D structure laterally.
  • FIG. 25E illustrates the formation of recessed spaces for forming the structures in each layer.
  • FIG. 25F illustrates the formation of the R/W layer followed by the word line for each of all the recessed spaces.
  • FIG. 25G illustrates the formation of the individual local bit line columns by first removing portions of the local bit line slab along the x-direction.
  • FIG. 26A illustrates the 3D structure is terraced to provide an offset at different layers.
  • FIG. 26B illustrates the formation of the surface metal lines connecting to the respective word lines by riser columns.
  • FIG. 27 illustrates another embodiment in where the word lines are accessed by metal wires at the base portion of the 3D structure, such as appropriating some of the global bit lines shown in FIG. 22 to act as global word lines.
  • FIG. 28 illustrates an efficient decoding of vertical bit lines and horizontal word lines in a 3D memory array via a set of global lines and select devices.
  • FIG. 29 illustrates a BEOL (top portion of the 3D memory) layout for the word lines and the R/W elements according to a first architecture for the 3D array shown in FIG. 28 .
  • FIG. 30A illustrates a first embodiment of the FEOL layout of a unit block when the BEOL has the first architecture of FIG. 29 .
  • FIG. 30B illustrates a second embodiment of the FEOL layout of a unit block when the BEOL has the first architecture of FIG. 29 .
  • FIG. 30C illustrates a third embodiment of the FEOL layout of a unit block when the BEOL has the first architecture of FIG. 29 .
  • FIG. 31 illustrates a BEOL (top portion of the 3D memory) layout for the word lines and the R/W elements according to a second architecture for the 3D array shown in FIG. 28 .
  • FIG. 32 illustrates a cross section of the BEOL layout of FIG. 31 in the y-z plane.
  • FIG. 33 illustrates a first embodiment of the FEOL layout of a unit block when the BEOL has the second architecture of FIG. 31 .
  • FIG. 34 illustrates a schematic top view of the entire 3D array including peripheral circuits.
  • FIG. 1 an architecture of a three-dimensional memory 10 is schematically and generally illustrated in the form of an equivalent circuit of a portion of such a memory.
  • This is a specific example of the three-dimensional array summarized above.
  • a standard three-dimensional rectangular coordinate system 11 is used for reference, the directions of each of vectors x, y and z being orthogonal with the other two.
  • a circuit for selectively connecting internal memory elements with external data circuits is preferably formed in a semiconductor substrate 13 .
  • a two-dimensional array of select or switching devices Q xy are utilized, where x gives a relative position of the device in the x-direction and y its relative position in the y-direction.
  • the individual devices Q xy may be a select gate or select transistor, as examples.
  • Global bit lines (GBL x ) are elongated in the y-direction and have relative positions in the x-direction that are indicated by the subscript.
  • the global bit lines (GBL x ) are individually connectable with the source or drain of the select devices Q having the same position in the x-direction, although during reading and also typically programming only one select device connected with a specific global bit line is turned on at time.
  • the other of the source or drain of the individual select devices Q is connected with one of the local bit lines (LBL xy ).
  • the local bit lines are elongated vertically, in the z-direction, and form a regular two-dimensional array in the x (row) and y (column) directions.
  • control gate lines SG y are elongated in the x-direction and connect with control terminals (gates) of a single row of select devices Q xy having a common position in the y-direction.
  • the select devices Q xy therefore connect one row of local bit lines (LBL xy ) across the x-direction (having the same position in the y-direction) at a time to corresponding ones of the global bit-lines (GBL x ), depending upon which of the control gate lines SG y receives a voltage that turns on the select devices to which it is connected.
  • the remaining control gate lines receive voltages that keep their connected select devices off.
  • Memory storage elements M zxy are formed in a plurality of planes positioned at different distances in the z-direction above the substrate 13 . Two planes 1 and 2 are illustrated in FIG. 1 but there will typically be more, such as 4 , 6 or even more.
  • word lines WL zy are elongated in the x-direction and spaced apart in the y-direction between the local bit-lines (LBL xy ).
  • the word lines WL zy of each plane individually cross adjacent two of the local bit-lines LBL xy on either side of the word lines.
  • the individual memory storage elements M zxy are connected between one local bit line LBL xy and one word line WL zy adjacent these individual crossings.
  • An individual memory element M zxy is therefore addressable by placing proper voltages on the local bit line LBL xy and word line WL zy between which the memory element is connected.
  • the voltages are chosen to provide the electrical stimulus necessary to cause the state of the memory element to change from an existing state to the desired new state. The levels, duration and other characteristics of these voltages depend upon the material that is used for the memory elements.
  • Each “plane” of the three-dimensional memory cell structure is typically formed of at least two layers, one in which the conductive word lines WL zy are positioned and another of a dielectric material that electrically isolates the planes from each other. Additional layers may also be present in each plane, depending for example on the structure of the memory elements M zxy .
  • the planes are stacked on top of each other on a semiconductor substrate with the local bit lines LBL xy being connected with storage elements M zxy of each plane through which the local bit lines extend.
  • FIG. 2 is a block diagram of an illustrative memory system that can use the three-dimensional memory 10 of FIG. 1 .
  • Data input-output circuits 21 are connected to provide (during programming) and receive (during reading) analog electrical quantities in parallel over the global bit-lines GBL x of FIG. 1 that are representative of data stored in addressed storage elements M zxy .
  • the circuits 21 typically contain sense amplifiers for converting these electrical quantities into digital data values during reading, which digital values are then conveyed over lines 23 to a memory system controller 25 .
  • data to be programmed into the array 10 are sent by the controller 25 to the input-output circuits 21 , which then programs that data into addressed memory element by placing proper voltages on the global bit lines GBL x .
  • one voltage level is typically placed on a global bit line to represent a binary “1” and another voltage level to represent a binary “0”.
  • the memory elements are addressed for reading or programming by voltages placed on the word lines WL zy and select gate control lines SG y by respective word line select circuits 27 and local bit line circuits 29 .
  • the memory elements lying between a selected word line and any of the local bit lines LBL xy connected at one instance through the select devices Q xy to the global bit lines GBL x may be addressed for programming or reading by appropriate voltages being applied through the select circuits 27 and 29 .
  • the memory system controller 25 typically receives data from and sends data to a host system 31 .
  • the controller 25 usually contains an amount of random-access-memory (RAM) 34 for temporarily storing such data and operating information. Commands, status signals and addresses of data being read or programmed are also exchanged between the controller 25 and host 31 .
  • RAM random-access-memory
  • the memory system operates with a wide variety of host systems. They include personal computers (PCs), laptop and other portable computers, cellular telephones, personal digital assistants (PDAs), digital still cameras, digital movie cameras and portable audio players.
  • the host typically includes a built-in receptacle 33 for one or more types of memory cards or flash drives that accepts a mating memory system plug 35 of the memory system but some hosts require the use of adapters into which a memory card is plugged, and others require the use of cables therebetween.
  • the memory system may be built into the host system as an integral part thereof.
  • the memory system controller 25 conveys to decoder/driver circuits 37 commands received from the host. Similarly, status signals generated by the memory system are communicated to the controller 25 from the circuits 37 .
  • the circuits 37 can be simple logic circuits in the case where the controller controls nearly all of the memory operations, or can include a state machine to control at least some of the repetitive memory operations necessary to carry out given commands. Control signals resulting from decoding commands are applied from the circuits 37 to the word line select circuits 27 , local bit line select circuits 29 and data input-output circuits 21 . Also connected to the circuits 27 and 29 are address lines 39 from the controller that carry physical addresses of memory elements to be accessed within the array 10 in order to carry out a command from the host.
  • the physical addresses correspond to logical addresses received from the host system 31 , the conversion being made by the controller 25 and/or the decoder/driver 37 .
  • the circuits 29 partially address the designated storage elements within the array 10 by placing proper voltages on the control elements of the select devices Q xy to connect selected local bit lines (LBL xy ) with the global bit lines (GBL x ).
  • the addressing is completed by the circuits 27 applying proper voltages to the word lines WL zy of the array.
  • the memory system of FIG. 2 utilizes the three-dimensional memory element array 10 of FIG. 1 , the system is not limited to use of only that array architecture.
  • a given memory system may alternatively combine this type of memory with other another type including flash memory, such as flash having a NAND memory cell array architecture, a magnetic disk drive or some other type of memory.
  • the other type of memory may have its own controller or may in some cases share the controller 25 with the three-dimensional memory cell array 10 , particularly if there is some compatibility between the two types of memory at an operational level.
  • each of the memory elements M zxy in the array of FIG. 1 may be individually addressed for changing its state according to incoming data or for reading its existing storage state, it is certainly preferable to program and read the array in units of multiple memory elements in parallel.
  • one row of memory elements on one plane may be programmed and read in parallel.
  • the number of memory elements operated in parallel depends on the number of memory elements connected to the selected word line.
  • the word lines may be segmented (not shown in FIG. 1 ) so that only a portion of the total number of memory elements connected along their length may be addressed for parallel operation, namely the memory elements connected to a selected one of the segments.
  • Previously programmed memory elements whose data have become obsolete may be addressed and re-programmed from the states in which they were previously programmed.
  • the states of the memory elements being re-programmed in parallel will therefore most often have different starting states among them. This is acceptable for many memory element materials but it is usually preferred to re-set a group of memory elements to a common state before they are re-programmed.
  • the memory elements may be grouped into blocks, where the memory elements of each block are simultaneously reset to a common state, preferably one of the programmed states, in preparation for subsequently programming them.
  • the reset operation is preferably chosen to cause the transition taking the longer time to be made.
  • the programming is then done faster than resetting.
  • the longer reset time is usually not a problem since resetting blocks of memory elements containing nothing but obsolete data is typically accomplished in a high percentage of the cases in the background, therefore not adversely impacting the programming performance of the memory system.
  • a three-dimensional array of variable resistive memory elements may be operated in a manner similar to current flash memory cell arrays.
  • Resetting a block of memory elements to a common state corresponds to erasing a block of flash memory cells to an erased state.
  • the individual blocks of memory elements herein may be further divided into a plurality of pages of storage elements, wherein the memory elements of a page are programmed and read together. This is like the use of pages in flash memories.
  • the memory elements of an individual page are programmed and read together. Of course, when programming, those memory elements that are to store data that are represented by the reset state are not changed from the reset state. Those of the memory elements of a page that need to be changed to another state in order to represent the data being stored in them have their states changed by the programming operation.
  • FIG. 3 provides plan schematic views of planes 1 and 2 of the array of FIG. 1 .
  • the different word lines WL zy that extend across each of the planes and the local bit lines LBL xy that extend through the planes are shown in two-dimensions.
  • Individual blocks are made up of memory elements connected to both sides of one word line, or one segment of a word line if the word lines are segmented, in a single one of the planes. There are therefore a very large number of such blocks in each plane of the array. In the block illustrated in FIG.
  • each of the memory elements M 114 , M 124 , M 134 , M 115 , M 125 and M 135 connected to both sides of one word line WL 12 form the block.
  • the memory elements of each block are connected between the single word line and different ones of the local bit lines, namely, for the block illustrated in FIG. 3 , between the word line WL 12 and respective local bit lines LBL 12 , LBL 22 , LBL 32 , LBL 13 , LBL 23 and LBL 33 .
  • a page is also illustrated in FIG. 3 .
  • One page is formed by the memory elements along one side of the word line of the block and the other page by the memory elements along the opposite side of the word line.
  • the example page marked in FIG. 3 is formed by memory elements M 114 , M 124 and M 134 .
  • a page will typically have a very large number of memory elements in order to be able to program and read a large amount of data at one time. Only a few of the storage elements of the page of FIG. 3 are included, for simplicity in explanation.
  • each of the memory elements M zxy is taken to include a non-volatile memory material that can be switched between two stable states of different resistance levels by impressing voltages (or currents) of different polarity across the memory element, or voltages of the same polarity but different magnitudes and/or duration.
  • one class of material may be placed into a high resistance state by passing current in one direction through the element, and into a low resistance state by passing current in the other direction through the element.
  • one element may need a higher voltage and a shorter time to switch to a high resistance state and a lower voltage and a longer time to switch to a lower resistance state.
  • a block includes all the memory elements that are electrically connected to one word line WL or segment thereof.
  • a block is the smallest unit of memory elements in the array that are reset together. It can include thousands of memory elements. If a row of memory elements on one side of a word line includes 1000 of them, for example, a block will have 2000 memory elements from the two rows on either side of the word line.
  • H volts are placed across each of the memory elements of the block.
  • this includes the memory elements M 114 , M 124 , M 134 , M 115 , M 125 and M 135 .
  • the resulting currents through these memory elements places any of them not already in a high resistance state, into that re-set state.
  • multiple blocks may be concurrently reset by setting any combination of word lines and the adjacent select gates to H or H′ respectively.
  • the only penalty for doing so is an increase in the amount of current that is required to simultaneously reset an increased number of memory elements. This affects the size of the power supply that is required.
  • the memory elements of a page are preferably programmed concurrently, in order to increase the parallelism of the memory system operation.
  • An expanded version of the page indicated in FIG. 3 is provided in FIG. 4 , with annotations added to illustrate a programming operation.
  • the individual memory elements of the page are initially in their reset state because all the memory elements of its block have previously been reset.
  • the reset state is taken herein to represent a logical data “1”.
  • An example of the relative timing of applying the above-listed programming voltages is to initially set all the global bit lines (GBLs), the selected select gate line (SG), the selected word line and two adjacent word lines on either side of the selected word line on the one page all to the voltage level M. After this, selected ones of the GBLs are raised to the voltage level H according to the data being programmed while simultaneously dropping the voltage of the selected word line to 0 volts for the duration of the programming cycle.
  • the word lines in plane 1 other than the selected word line WL 12 and all word lines in the unselected other planes can be weakly driven to M, some lower voltage or allowed to float in order to reduce power that must be delivered by word line drivers that are part of the circuits 27 of FIG. 2 .
  • voltages can be loosely coupled to outer word lines of the selected plane 1 and word lines of other planes that are allowed to float through memory elements in their low resistance state (programmed) that are connected between the floating local bit lines and adjacent word lines.
  • These outer word lines of the selected plane and word lines in unselected planes, although allowed to float, may eventually be driven up to voltage level M through a combination of programmed memory elements.
  • parasitic currents present during the programming operation that can increase the currents that must be supplied through the selected word line and global bit lines.
  • the memory element M 123 is connected between that voltage and the voltage level M on its word line WL 11 . This voltage difference can cause the parasitic current ⁇ I PI to flow.
  • parasitic currents can similarly flow from the same local bit line LBL 22 to an adjacent word line in other planes.
  • the presence of these currents may limit the number of planes that can be included in the memory system since the total current may increase with the number of planes.
  • the limitation for programming is in the current capacity of the memory power supply, so the maximum number of planes is a tradeoff between the size of the power supply and the number of planes. A number of 4-8 planes may generally be used in most cases.
  • the other source of parasitic currents during programming is to an adjacent page in the same block.
  • the local bit lines that are left floating will tend to be driven to the voltage level M of unselected word lines through any programmed memory element on any plane.
  • This in turn can cause parasitic currents to flow in the selected plane from these local bit lines at the M voltage level to the selected word line that is at zero volts.
  • An example of this is given by the currents I P2 , I P3 and I P4 shown in FIG. 4 .
  • these currents will be much less than the other parasitic current I P1 discussed above, since these currents flow only through those memory elements in their conductive state that are adjacent to the selected word line in the selected plane.
  • the above-described programming techniques ensure that the selected page is programmed (local bit lines at H, selected word line at 0) and that adjacent unselected word lines are at M.
  • other unselected word lines can be weakly driven to M or initially driven to M and then left floating.
  • word lines in any plane distant from the selected word line can also be left uncharged (at ground) or floating because the parasitic currents flowing to them are so low as to be negligible compared to the identified parasitic currents since they must flow through a series combination of five or more ON devices (devices in their low resistance state). This can reduce the power dissipation caused by charging a large number of word lines.
  • parasitic currents during such a read operation have two undesirable effects. As with programming, parasitic currents place increased demands on the memory system power supply. In addition, it is possible for parasitic currents to exist that are erroneously included in the currents though the addressed memory elements that are being read. This can therefore lead to erroneous read results if such parasitic currents are large enough.
  • all of the local bit lines except the selected row are floating. But the potential of the floating local bit lines may be driven to V R by any memory element that is in its programmed (low resistance) state and connected between a floating local bit line and a word line at V R , in any plane.
  • a parasitic current comparable to I P1 in the programming case ( FIG. 4 ) is not present during data read because both the selected local bit lines and the adjacent non-selected word lines are both at V R . Parasitic currents may flow, however, through low resistance memory elements connected between floating local bit lines and the selected word line.
  • each of these currents can be equal in magnitude to the maximum read current through an addressed memory element.
  • these parasitic currents are flowing from the word lines at the voltage V R to the selected word line at a voltage V R ⁇ Vsense without flowing through the sense amplifiers.
  • These parasitic currents will not flow through the selected local bit lines (LBL 12 , LBL 22 and LBL 32 in FIG. 5 ) to which the sense amplifiers are connected. Although they contribute to power dissipation, these parasitic currents do not therefore introduce a sensing error.
  • the neighboring word lines should be at V R to minimize parasitic currents, as in the programming case it may be desirable to weakly drive these word lines or even allow them to float.
  • the selected word line and the neighboring word lines can be pre-charged to V R and then allowed to float.
  • the sense amplifier When the sense amplifier is energized, it may charge them to V R so that the potential on these lines is accurately set by the reference voltage from the sense amplifier (as opposed to the reference voltage from the word line driver). This can occur before the selected word line is changed to V R ⁇ Vsense but the sense amplifier current is not measured until this charging transient is completed.
  • Reference cells may also be included within the memory array 10 to facilitate any or all of the common data operations (erase, program, or read).
  • a reference cell is a cell that is structurally as nearly identical to a data cell as possible in which the resistance is set to a particular value. They are useful to cancel or track resistance drift of data cells associated with temperature, process non-uniformities, repeated programming, time or other cell properties that may vary during operation of the memory. Typically they are set to have a resistance above the highest acceptable low resistance value of a memory element in one data state (such as the ON resistance) and below the lowest acceptable high resistance value of a memory element in another data state (such as the OFF resistance). Reference cells may be “global” to a plane or the entire array, or may be contained within each block or page.
  • multiple reference cells may be contained within each page.
  • the number of such cells may be only a few (less than 10), or may be up to a several percent of the total number of cells within each page.
  • the reference cells are typically reset and written in a separate operation independent of the data within the page. For example, they may be set one time in the factory, or they may be set once or multiple times during operation of the memory array. During a reset operation described above, all of the global bit lines are set low, but this can be modified to only set the global bit lines associated with the memory elements being reset to a low value while the global bit lines associated with the reference cells are set to an intermediate value, thus inhibiting them from being reset.
  • the global bit lines associated with the reference cells are set to a low value while the global bit lines associated with the data cells are set to an intermediate value.
  • this process is reversed and the global bit lines associated with the reference cells are raised to a high value to set the reference cells to a desired ON resistance while the memory elements remain in the reset state.
  • the programming voltages or times will be changed to program reference cells to a higher ON resistance than when programming memory elements.
  • the number of reference cells in each page is chosen to be 1% of the number of data storage memory elements, then they may be physically arranged along each word line such that each reference cell is separated from its neighbor by 100 data cells, and the sense amplifier associated with reading the reference cell can share its reference information with the intervening sense amplifiers reading data.
  • Reference cells can be used during programming to ensure the data is programmed with sufficient margin. Further information regarding the use of reference cells within a page can be found in U.S. Pat. Nos. 6,222,762, 6,538,922, 6,678,192 and 7,237,074.
  • reference cells may be used to approximately cancel parasitic currents in the array.
  • the value of the resistance of the reference cell(s) is set to that of the reset state rather than a value between the reset state and a data state as described earlier.
  • the current in each reference cell can be measured by its associated sense amplifier and this current subtracted from neighboring data cells.
  • the reference cell is approximating the parasitic currents flowing in a region of the memory array that tracks and is similar to the parasitic currents flowing in that region of the array during a data operation.
  • This correction can be applied in a two step operation (measure the parasitic current in the reference cells and subsequently subtract its value from that obtained during a data operation) or simultaneously with the data operation.
  • One way in which simultaneous operation is possible is to use the reference cell to adjust the timing or reference levels of the adjacent data sense amplifiers. An example of this is shown in U.S. Pat. No. 7,324,393.
  • a diode In conventional two-dimensional arrays of variable resistance memory elements, a diode is usually included in series with the memory element between the crossing bit and word lines.
  • the primary purpose of the diodes is to reduce the number and magnitudes of parasitic currents during resetting (erasing), programming and reading the memory elements.
  • a significant advantage of the three-dimensional array herein is that resulting parasitic currents are fewer and therefore have a reduced negative effect on operation of the array than in other types of arrays.
  • Diodes may also be connected in series with the individual memory elements of the three-dimensional array, as currently done in other arrays of variable resistive memory elements, in order to reduce further the number of parasitic currents but there are disadvantages in doing so. Primarily, the manufacturing process becomes more complicated. Added masks and added manufacturing steps are then necessary. Also, since formation of the silicon p-n diodes often requires at least one high temperature step, the word lines and local bit lines cannot then be made of metal having a low melting point, such as aluminum that is commonly used in integrated circuit manufacturing, because it may melt during the subsequent high temperature step.
  • the total magnitude of parasitic currents can be managed without the use of such diodes.
  • the absence of the diodes allows bi-polar operation; that is, an operation in which the voltage polarity to switch the memory element from its first state to its second memory state is opposite of the voltage polarity to switch the memory element from its second to its first memory state.
  • the advantage of the bi-polar operation over a unipolar operation is the reduction of power to switch the memory element and an improvement in the reliability of the memory element.
  • the level of parasitic currents increases with the number of planes and with the number of memory elements connected along the individual word lines within each plane. But since the number of word lines on each plane does not significantly affect the amount of parasitic current, the planes may individually include a large number of word lines.
  • the parasitic currents resulting from a large number of memory elements connected along the length of individual word lines can further be managed by segmenting the word lines into sections of fewer numbers of memory elements. Erasing, programming and reading operations are then performed on the memory elements connected along one segment of each word line instead of the total number of memory elements connected along the entire length of the word line.
  • the re-programmable non-volatile memory array being described herein has many advantages.
  • the quantity of digital data that may be stored per unit of semiconductor substrate area is high. It may be manufactured with a lower cost per stored bit of data. Only a few masks are necessary for the entire stack of planes, rather than requiring a separate set of masks for each plane.
  • the number of local bit line connections with the substrate is significantly reduced over other multi-plane structures that do not use the vertical local bit lines.
  • the architecture eliminates the need for each memory cell to have a diode in series with the resistive memory element, thereby further simplifying the manufacturing process and enabling the use of metal conductive lines. Also, the voltages necessary to operate the array are much lower than those used in current commercial flash memories.
  • each current path Since at least one-half of each current path is vertical, the voltage drops present in large cross-point arrays are significantly reduced.
  • the reduced length of the current path due to the shorter vertical component means that there are approximately one-half the number memory cells on each current path and thus the leakage currents are reduced as is the number of unselected cells disturbed during a data programming or read operation. For example, if there are N cells associated with a word line and N cells associated with a bit line of equal length in a conventional array, there are 2N cells associated or “touched” with every data operation.
  • N is the number of planes and is typically a small number such as 4 to 8
  • N+n cells are associated with a data operation. For a large N this means that the number of cells affected by a data operation is approximately one-half as many as in a conventional three-dimensional array.
  • the material used for the non-volatile memory storage elements M zxy in the array of FIG. 1 can be a chalcogenide, a metal oxide, or any one of a number of materials that exhibit a stable, reversible shift in resistance in response to an external voltage applied to or current passed through the material.
  • Metal oxides are characterized by being insulating when initially deposited.
  • One suitable metal oxide is a titanium oxide (TiO x ).
  • TiO x titanium oxide
  • FIG. 6 A previously reported memory element using this material is illustrated in FIG. 6 .
  • near-stoichiometric TiO 2 bulk material is altered in an annealing process to create an oxygen deficient layer (or a layer with oxygen vacancies) in proximity of the bottom electrode.
  • the top platinum electrode with its high work function, creates a high potential Pt/TiO 2 barrier for electrons. As a result, at moderate voltages (below one volt), a very low current will flow through the structure.
  • the bottom Pt/TiO 2-x barrier is lowered by the presence of the oxygen vacancies (O + 2 ) and behaves as a low resistance contact (ohmic contact).
  • the oxygen vacancies in TiO 2 are known to act as n-type dopant, transforming the insulating oxide in an electrically conductive doped semiconductor.
  • the resulting composite structure is in a non-conductive (high resistance) state.
  • the conductive path is broken by applying a large positive voltage across the structure of FIG. 6 . Under this positive bias, the oxygen vacancies move away from the proximity of the top Pt/TiO 2 barrier, and “break” the filament. The device returns to its high resistance state. Both of the conductive and non-conductive states are non-volatile. Sensing the conduction of the memory storage element by applying a voltage around 0.5 volts can easily determine the state of the memory element.
  • Suitable top electrodes include metals with a high work function (typically >4.5 eV) capable to getter oxygen in contact with the metal oxide to create oxygen vacancies at the contact.
  • Some examples are TaCN, TiCN, Ru, RuO, Pt, Ti rich TiOx, TiAlN, TaAlN, TiSiN, TaSiN, IrO 2 .
  • Suitable materials for the bottom electrode are any conducting oxygen rich material such as Ti(O)N, Ta(O)N, TiN and TaN.
  • the thicknesses of the electrodes are typically 1 nm or greater. Thicknesses of the metal oxide are generally in the range of 5 nm to 50 nm.
  • Solid electrolytes are somewhat similar to the metal oxides, and the conduction mechanism is assumed to be the formation of a metallic filament between the top and bottom electrode. In this structure the filament is formed by dissolving ions from one electrode (the oxidizable electrode) into the body of the cell (the solid electrolyte).
  • the solid electrolyte contains silver ions or copper ions
  • the oxidizable electrode is preferably a metal intercalated in a transition metal sulfide or selenide material such as A x (MB2) 1-x , where A is Ag or Cu, B is S or Se, and M is a transition metal such as Ta, V, or Ti, and x ranges from about 0.1 to about 0.7.
  • a x (MB2) 1-x a transition metal sulfide or selenide material
  • a x (MB2) 1-x where A is Ag or Cu, B is S or Se, and M is a transition metal such as Ta, V, or Ti
  • x ranges from about 0.1 to about 0.7.
  • Such a composition minimizes oxidizing unwanted material into the solid electrolyte.
  • One example of such a composition is Ag x (TaS2) 1-x .
  • Alternate composition materials include ⁇ -AgI.
  • the other electrode should be a good electrical conductor while remaining insoluble
  • solid electrolytes materials are: TaO, GeSe or GeS.
  • Other systems suitable for use as solid electrolyte cells are: Cu/TaO/W, Ag/GeSe/W, Cu/GeSe/W, Cu/GeS/W, and Ag/GeS/W, where the first material is the oxidizable electrode, the middle material is the solid electrolyte, and the third material is the indifferent (neutral) electrode.
  • Typical thicknesses of the solid electrolyte are between 30 nm and 100 nm.
  • carbon has been extensively studied as a non-volatile memory material.
  • a non-volatile memory element carbon is usually used in two forms, conductive (or grapheme like-carbon) and insulating (or amorphous carbon).
  • the difference in the two types of carbon material is the content of the carbon chemical bonds, so called sp 2 and sp 3 hybridizations.
  • sp 3 configuration the carbon valence electrons are kept in strong covalent bonds and as a result the sp 3 hybridization is non-conductive.
  • Carbon films in which the sp 3 configuration dominates, are commonly referred to as tetrahedral-amorphous carbon, or diamond like.
  • the carbon resistive switching nonvolatile memories is based on the fact that it is possible to transform the sp 3 configuration to the sp 2 configuration by applying appropriate current (or voltage) pulses to the carbon structure. For example, when a very short (1-5 ns) high amplitude voltage pulse is applied across the material, the conductance is greatly reduced as the material sp 2 changes into an sp 3 form (“reset” state).
  • the carbon resistance switching non-volatile memory elements have a capacitor like configuration where the top and bottom electrodes are made of high temperature melting point metals like W, Pd, Pt and TaN.
  • CNTs carbon nanotubes
  • a (single walled) carbon nanotube is a hollow cylinder of carbon, typically a rolled and self-closing sheet one carbon atom thick, with a typical diameter of about 1-2 nm and a length hundreds of times greater.
  • Such nanotubes can demonstrate very high conductivity, and various proposals have been made regarding compatibility with integrated circuit fabrication. It has been proposed to encapsulate “short” CNT's within an inert binder matrix to form a fabric of CNT's. These can be deposited on a silicon wafer using a spin-on or spray coating, and as applied the CNT's have a random orientation with respect to each other.
  • the CNT based memories When an electric field is applied across this fabric, the CNT's tend to flex or align themselves such that the conductivity of the fabric is changed. The switching mechanism from low-to-high resistance and the opposite is not well understood.
  • the CNT based memories have capacitor-like configurations with top and bottom electrodes made of high melting point metals such as those mentioned above.
  • the generally accepted explanation for the switching mechanism is that when a high energy pulse is applied for a very short time to cause a region of the material to melt, the material “quenches” in an amorphous state, which is a low conductive state. When a lower energy pulse is applied for a longer time such that the temperature remains above the crystallization temperature but below the melting temperature, the material crystallizes to form poly-crystal phases of high conductivity.
  • These devices are often fabricated using sub-lithographic pillars, integrated with heater electrodes. Often the localized region undergoing the phase change may be designed to correspond to a transition over a step edge, or a region where the material crosses over a slot etched in a low thermal conductivity material.
  • the contacting electrodes may be any high melting metal such as TiN, W, WN and TaN in thicknesses from 1 nm to 500 nm.
  • the memory materials in most of the foregoing examples utilize electrodes on either side thereof whose compositions are specifically selected.
  • those lines are preferably made of the conductive materials described above.
  • those segments are therefore made of the materials described above for the memory element electrodes.
  • Steering elements are commonly incorporated into controllable resistance types of memory storage elements.
  • Steering elements can be a transistor or a diode.
  • the diode can be a p-n junction (not necessarily of silicon), a metal/insulator/insulator/metal (MIIM), or a Schottky type metal/semiconductor contact but can alternately be a solid electrolyte element.
  • MIIM metal/insulator/insulator/metal
  • a characteristic of this type of diode is that for correct operation in a memory array, it is necessary to be switched “on” and “off” during each address operation.
  • the diode is in the high resistance state (“off” state) and “shields” the resistive memory element from disturb voltages.
  • three different operations are needed: a) convert the diode from high resistance to low resistance, b) program, read, or reset (erase) the memory element by application of appropriate voltages across or currents through the diode, and c) reset (erase) the diode.
  • one or more of these operations can be combined into the same step.
  • Resetting the diode may be accomplished by applying a reverse voltage to the memory element including a diode, which causes the diode filament to collapse and the diode to return to the high resistance state.
  • each cell is either reset or set and holds one bit of data.
  • the techniques of the present application are not limited to this simple case.
  • MLC multiple-level cell
  • Examples of MLC technology applied to three dimensional arrays of memory elements include an article entitled “Multi-bit Memory Using Programmable Metallization Cell Technology” by Kozicki et al., Proceedings of the International Conference on Electronic Devices and Memory, Grenoble, France, Jun. 12-17, 2005, pp. 48-53 and “Time Discrete Voltage Sensing and Iterative Programming Control for a 4F2 Multilevel CBRAM” by Schrogmeier et al. (2007 Symposium on VLSI Circuits).
  • a first example, illustrated in FIG. 7 is configured for use of memory element (NVM) material that is non-conductive when first deposited.
  • NVM memory element
  • a metal oxide of the type discussed above has this characteristic.
  • conductive filaments are formed between electrodes on opposite sides of the material in response to appropriate voltages placed on those electrodes. These electrodes are a bit line and a word line in the array. Since the material is otherwise non-conductive, there is no necessity to isolate the memory elements at the cross-points of the word and bit lines from each other.
  • Several memory elements may be implemented by a single continuous layer of material, which in the case of FIG.
  • FIG. 7 are strips of NVM material oriented vertically along opposite sides of the vertical bit lines in the y-direction and extending upwards through all the planes.
  • a significant advantage of the structure of FIG. 7 is that all word lines and strips of insulation under them in a group of planes may be defined simultaneously by use of a single mask, thus greatly simplifying the manufacturing process.
  • FIG. 7 a small part of four planes 101 , 103 , 105 and 107 of the three-dimensional array are shown. Elements of the FIG. 7 array that correspond to those of the equivalent circuit of FIG. 1 are identified by the same reference numbers. It will be noted that FIG. 7 shows the two planes 1 and 2 of FIG. 1 plus two additional planes on top of them. All of the planes have the same horizontal pattern of gate, dielectric and memory storage element (NVM) material. In each plane, metal word lines (WL) are elongated in the x-direction and spaced apart in the y-direction.
  • NVM gate, dielectric and memory storage element
  • Each plane includes a layer of insulating dielectric that isolates its word lines from the word lines of the plane below it or, in the case of plane 101 , of the substrate circuit components below it. Extending through each plane is a collection of metal local bit line (LBL) “pillars” elongated in the vertical z-direction and forming a regular array in the x-y direction.
  • LBL metal local bit line
  • Each bit line pillar is connected to one of a set of global bit lines (GBL) in the silicon substrate running in the y-direction at the same pitch as the pillar spacing through the select devices (Q xy ) formed in the substrate whose gates are driven by the select gate lines (SG) elongated in the x-direction, which are also formed in the substrate.
  • the switching devices Q xy may be conventional CMOS transistors (or vertical npn transistors) and fabricated using the same process as used to form the other conventional circuitry.
  • the select gate (SG) lines are replaced with the base contact electrode lines elongated in the x-direction. Also fabricated in the substrate but not shown in FIG.
  • I/O circuitry 7 are sense amplifiers, input-output (I/O) circuitry, control circuitry, and any other necessary peripheral circuitry.
  • NVM non-volatile memory element
  • LBL vertical local bit lines
  • WL word lines
  • M memory storage element
  • a small region of the NVM material between an intersecting local bit line (LBL) and word line (WL) is controllably alternated between conductive (set) and non-conductive (reset) states by appropriate voltages applied to the intersecting lines.
  • the non-conducting NVM material may be left in place between adjacent local bit lines if the operating voltages between the adjacent LBLs remain below the programming threshold.
  • a significant advantage of the configuration of FIG. 7 is that only one etching operation through a single mask is required to form the trenches through all the layers of material of the planes at one time.
  • process limitations may limit the number of planes that can be etched together in this manner. If the total thickness of all the layers is too great, the trench may need to be formed in sequential steps.
  • a first number of layers are etched and, after a second number of layers have been formed on top of the first number of trenched layers, the top layers are subjected to a second etching step to form trenches in them that are aligned with the trenches in the bottom layers. This sequence may be repeated even more times for an implementation having a very large number of layers.
  • FIG. 8 A second example of implementing the three-dimensional memory cell array of FIG. 1 is illustrated by FIG. 8 , and a process of forming this structure is outlined with respect to FIGS. 9-14 .
  • This structure is configured to use any type of material for the non-volatile memory storage elements, electrically conductive or non-conductive when deposited on the structure, such as those described above.
  • the NVM element is isolated from the LBL and is sandwiched between the bottom metal electrode and the word line.
  • the bottom electrode makes electrical contact with the LBL while the word line is electrically isolated from the LBL through an insulator.
  • the NVM elements at the intersections of the local bit lines (LBL) and word lines (WL) are electrically isolated from one another in the x and z-directions.
  • FIG. 8 shows a portion of each of three planes 111 , 113 and 115 of this second structural example on only one side of a local bit line (LBL).
  • the word lines (WL) and memory storage elements (M xy ) are defined in each plane as the plane is formed, using two masking steps.
  • the local bit lines crossing each plane of the group in the z-direction are defined globally after the last plane in the group is defined.
  • a significant feature of the structure of FIG. 8 is that the storage elements M xy are below their respective word lines, rather than serving as an insulator between the word lines (WL) and the vertical local bit lines (LBL) as done in the example of FIG. 7 .
  • a bottom electrode contacts the lower surface of each storage element M xy and extends laterally in the y-direction to the local bit line (LBL). Conduction through one of the memory cells is through the bit line, laterally along the bottom electrode, vertically in the z-direction through the switching material of the storage elements M xy (and optional layer of barrier metal, if present) and to the selected word line (WL).
  • LBL local bit line
  • WL selected word line
  • the word lines (WL) stop short in the y-direction of the local bit lines (LBL) and do not have the non-volatile memory (NVM) material sandwiched between the word and local bit lines at the same z-location as is the case in the example of FIG. 7 .
  • the storage elements M xy are similarly spaced from the local bit lines (LBL), being electrically connected thereto by the bottom electrode.
  • An outline of a process for forming one plane of the three-dimensional structure of FIG. 8 with storage elements M zxy in a regular array in the x-y direction is as follows:
  • FIG. 15 shows a small portion of three planes 121 , 123 and 125 .
  • the memory storage elements M zxy are also formed from a conductive switching material.
  • the bottom electrodes of the example of FIG. 8 are missing from the layers shown in FIG. 15 .
  • FIG. 15 The structure shown in FIG. 15 is made by essentially the same process as that described above for the second example.
  • the main difference is that in the second example, reference to the bottom electrode is replaced in this third example by the switching material, and reference to the switching material of the second embodiment is not used in this third embodiment.
  • the second example structure of FIG. 8 is particularly suited to any switching material that as deposited as an insulator or electrical conductor.
  • the third example structure shown in FIG. 15 is suited primarily for switching materials that are deposited as an electrical conductor (phase change materials, carbon materials, carbon nanotubes and like materials). By isolating the switching material such that it does not span the region between two stacks, the possibility of a conductive short between switching elements is eliminated.
  • diodes are commonly connected in series with the variable resistive elements of a memory array in order to reduce leakage currents that can flow through them.
  • the highly compact 3D reprogrammable memory described in the present invention has an architecture that does not require a diode in series with each memory element while able to keep the leakage currents reduced. This is possible with short local vertical bit lines which are selectively coupled to a set of global bit lines. In this manner, the structures of the 3D memory are necessarily segmented and couplings between the individual paths in the mesh are reduced.
  • parasitic currents may exist during a read operation and these currents have two undesirable effects. First, they result in higher power consumption. Secondly, and more seriously, they may occur in the sensing path of the memory element being sensed, cause erroneous reading of the sensed current.
  • FIG. 16 illustrates the read bias voltages and current leakage across multiple planes of the 3D memory shown in FIG. 1 and FIG. 3 .
  • FIG. 16 is a cross-sectional view across 4 planes along the x-direction of a portion of the perspective 3D view of the memory shown in FIG. 1 . It should be clear that while FIG. 1 shows the substrate and 2 planes, FIG. 16 shows the substrate and 4 planes to better illustrate the effect of current leakage from one plane to another.
  • a bias voltage is applied across the memory element and its element current I ELEMENT sensed.
  • the memory element 200 resides on Plane 4 and is accessible by selecting the word line 210 (Sel-WLi) and the local bit line 220 (Sel-LBLj).
  • the selected word line 210 (Sel-WLi) is set to 0v and the corresponding selected local bit line 220 (Sel-LBLj) is set to a reference such as 0.5V via a turned on select gate 222 by a sense amplifier 240 .
  • the current sensed by the sense amplifier 240 will just be the I ELEMENT of the memory element 200 .
  • the architecture shown in FIG. 1 and FIG. 16 has the unselected local bit lines (LBLj+1, LBLj+2, . . . ) and the selected local bit line (Sel-LBLj) all sharing the same global bit line 250 (GBLi) to the sense amplifier 240 .
  • the unselected local bit lines can only be isolated from the sense amplifier 240 by having their respective select gate such as gate 232 turned off. In this way, the unselected local bit lines are left floating and will couple to the reference 0.5V by virtue of adjacent nodes which are at 0.5V. However, the adjacent nodes are not exactly at the reference 0.5V. This is due to a finite resistance in each word line (perpendicular to the plane in FIG.
  • a 3D memory includes memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction.
  • the memory elements in each plane are accessed by a plurality of word lines and local bit lines in tandem with a plurality of global bit lines.
  • the plurality of local bit lines are in the z-direction through the plurality of planes and arranged in a two dimensional rectangular array of rows in the x-direction and columns in the y-directions.
  • the plurality of word lines in each plane are elongated in the x-direction and spaced apart in the y-direction between and separated from the plurality of local bit lines in the individual planes.
  • a non-volatile, reprogramming memory element is located near a crossing between a word line and local bit line and accessible by the word line and bit line and wherein a group of memory elements are accessible in parallel by a common word line and a row of local bit lines.
  • the 3D memory further includes a double-global-bit line architecture with two global bit lines respectively serving even and odd local bit lines in a column thereof in the y-direction.
  • This architecture allows one global bit line to be used by a sense amplifier to access a selected local bit line and the other global bit line to be used to access an unselected local bit lines adjacent the selected local bit line in the y-direction.
  • the adjacent, unselected local lines can be set to exactly a reference voltage same as that of the selected local bit line in order to eliminate leakage currents between adjacent bit lines.
  • FIG. 17 illustrates a three-dimensional memory with a double-global-bit-line architecture for improved access to a set of local bit lines.
  • An architecture of a three-dimensional memory 10 ′ is schematically and generally illustrated in the form of an equivalent circuit of a portion of such a memory. This is a specific example of the three-dimensional array summarized above.
  • a standard three-dimensional rectangular coordinate system 11 is used for reference, the directions of each of vectors x, y and z being preferably orthogonal with the other two and having a plurality of parallel planes stacked in the z-direction.
  • the local bit lines are elongated vertically, in the z-direction, and form a regular two-dimensional array in the x (row) and y (column) directions.
  • Memory storage elements M zxy are formed in a plurality of planes positioned at different distances in the z-direction above the substrate 13 .
  • Two planes 1 and 2 are illustrated in FIG. 17 but there will typically be more, such as 4, 6 or even more.
  • word lines WL zy are elongated in the x-direction and spaced apart in the y-direction between the local bit-lines (LBL xy ).
  • Each row of local bit lines LBL xy of each plane is sandwiched by a pair of word lines WL zy and WL zy+1 . Individually crossing between a local bit line a word line occurs at each plane where the local bit line intersects the plane.
  • the individual memory storage elements M zy are connected between one local bit line LBL xy and one word line WL zy adjacent these individual crossings.
  • An individual memory element M zxy is therefore addressable by placing proper voltages on the local bit line LBL xy and word line WL zy between which the memory element is connected.
  • the voltages are chosen to provide the electrical stimulus necessary to cause the state of the memory element to change from an existing state to the desired new state. The levels, duration and other characteristics of these voltages depend upon the material that is used for the memory elements.
  • Each “plane” of the three-dimensional memory cell structure is typically formed of at least two layers, one in which the conductive word lines WL zy are positioned and another of a dielectric material that electrically isolates the planes from each other. Additional layers may also be present in each plane, depending for example on the structure of the memory elements M zxy .
  • the planes are stacked on top of each other on a semiconductor substrate with the local bit lines LBL xy being connected with storage elements M zxy of each plane through which the local bit lines extend.
  • the three-dimensional memory 10 ′ shown in FIG. 17 is similar to the 3D memory 10 shown in FIG. 1 except for the structure of the global bit lines which has a doubling of the global bit lines.
  • a circuit for selectively connecting internal memory elements with external data circuits is preferably formed in a semiconductor substrate 13 .
  • a two-dimensional array of select or switching devices Q xy are utilized, where x gives a relative position of the device in the x-direction and y its relative position in the y-direction.
  • the individual devices Q xy may be a select gate or select transistor, as examples.
  • a pair of global bit lines (GBL xA , GBL xB ) is elongated in the y-direction and have relative positions in the x-direction that are indicated by the subscript.
  • the individual devices Qxy each couples a local bit line to one global bit line.
  • each local bit line in a row is coupleable to one of a corresponding pair of global bit lines.
  • even local bit lines are coupleable to a first one of a corresponding pair of global bit line while odd local bit lines are coupleable to a second one of the corresponding pair of global bit line.
  • a pair of global bit lines (GBL x′A , GBL x′B ) at about the x′-position are individually connectable with the source or drain of the select devices Q in such a manner that local bits (LBLx′y) at the x′-position and along the y-direction are coupleable alternately to the pair of global bit lines (GBL x′A , GBL x′B ).
  • each global bit line is typically coupled to one local bit line by accessing through a corresponding select device that has been turned on. In this way a sense amplifier can access the local bit line via the coupled global bit line.
  • control gate lines SG y are elongated in the x-direction and connect with control terminals (gates) of a single row of select devices Q xy having a common position in the y-direction.
  • the select devices Q xy therefore connect one row of local bit lines (LBL xy ) across the x-direction (having the same position in the y-direction) at a time to corresponding ones of the global bit-lines, depending upon which of the control gate lines SG y receives a voltage that turns on the select devices to which it is connected.
  • the double-global-bit line architecture there is a pair of global bit lines at about each x-position. If a row of local bit lines along the x-directions are coupleable to the first one of each pair of corresponding global bit lines, then along the y-direction, an adjacent row of local bit lines will be coupleable to the second one of each pair of corresponding global bit lines.
  • the row of local bit lines (LBL 11 , LBL 21 , LBL 31 , . . . ) along the x-direction are coupled to the first of each pair of corresponding global bit lines (GBL 1A , GBL 2A , GBL 3A , . . .
  • an adjacent row of local bit lines (LBL 12 , LBL 22 , LBL 32 , . . . ) along the x-direction are coupled to the second of each pair of corresponding global bit lines (GBL 1B , GBL 2B , GBL 3B , . . . ) by turning on select devices (Q 12 , Q 22 , Q 32 , . . . ) via the control gate line SG 2 .
  • a next adjacent row of local bit lines (LBL 13 , LBL 23 , LBL 33 , . . . ) are coupled to the first of each pair of corresponding global bit lines (GBL 1A , GBL 2A , GBL 3A , . . . ) in an alternating manner between the first and second one of each pair.
  • the row and adjacent row of local bit lines can be accessed independently at the same time. This is in contrast to the case of the single-global-bit-line architecture shown in FIG. 1 , where both a row and its adjacent row of local bit lines share the same corresponding global bit lines.
  • the leakage currents due to adjacent rows are not well controlled when the adjacent bit lines can not be set independently to the reference voltage in order to eliminate current leakage.
  • FIG. 18 illustrates the elimination of leakage currents in the double-global-line architecture 3D array of FIG. 17 .
  • the analysis of leakage current is similar to that described with respect to FIG. 16 .
  • the selected local bit line 220 (Sel-LBLj) allows the memory element 200 to be sensed by the sense amplifier 240 via the first one of the pair of global bit line GBL iA , which is maintained at a reference voltage (e.g., 0.5V).
  • the adjacent local bit line 230 can be accessed independently by the second one of the pair of global bit line GBL iB . This allows the adjacent local bit line 230 to be set to the same reference voltage. Since both the selected local bit line 220 and its adjacent local bit line (along the y-direction) are at the same reference voltage, there will be no leakage currents between the two local bit lines adjacent to each other.
  • the double-global-bit-line architecture doubles the number of global bit lines in the memory array compared to the architecture shown in FIG. 1 .
  • this disadvantage is offset by providing a memory array with less leakage currents among the memory elements.
  • a 3D memory includes memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction.
  • the memory elements in each plane are accessed by a plurality of word lines and local bit lines in tandem with a plurality of global bit lines.
  • the plurality of local bit lines are in the z-direction through the plurality of planes and arranged in a two dimensional rectangular array of rows in the x-direction and columns in the y-directions.
  • the plurality of word lines in each plane are elongated in the x-direction and spaced apart in the y-direction between and separated from the plurality of local bit lines in the individual planes.
  • a non-volatile, reprogramming memory element is located near a crossing between a word line and local bit line and accessible by the word line and bit line and wherein a group of memory elements are accessible in parallel by a common word line and a row of local bit lines.
  • the 3D memory has a single-sided word line architecture with each word line exclusively connected to one row of memory elements. This is accomplished by providing one word line for each row of memory elements instead of sharing one word line between two rows of memory elements and linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling for the row of local bit lines beyond the word line.
  • each word line is connected to two adjacent rows of memory elements associated with two corresponding rows of local bit lines, one adjacent row along one side of the word line and another adjacent row along the other side.
  • the word line WL 12 is connected on one side to a first row (or page) of memory elements (M 114 , M 124 , M 134 , . . . ) associated respectively with local bit lines (LBL 12 , LBL 22 , LBL 32 , . . . ) and also connected on another side to a second row (or page) of memory elements (M 115 , M 125 , M 135 , . . . ) associated respectively with local bit lines (LBL 13 , LBL 23 , LBL 33 , . . . )
  • FIG. 19 illustrates schematically a single-sided word line architecture. Each word line is connected to an adjacent row of memory elements associate with one row of local bit lines on only one side.
  • the 3D memory array with the double-sided word line architecture illustrated in FIG. 1 can be modified to the single-sided word line architecture where each word line except ones at an edge of the array will be replaced by a pair of word lines. In this way, each word line is connecting exclusively to one row of memory elements.
  • the word line WL 12 shown in FIG. 1 is now replaced in FIG. 19 by the pair of word lines WL 13 and WL 14 .
  • WL 13 is connected to one row of memory elements (M 114 , M 124 , M 134 , . . . )
  • WL 14 is connected to one row of memory elements (M 115 , M 125 , M 135 , . . . )
  • a row of memory elements constitutes a page which is read or written to in parallel.
  • FIG. 20 illustrates one plane and substrate of the 3D array with the single-sided word line architecture. Going from the double-sided word line architecture of FIG. 3 , similarly, WL 12 in FIG. 3 would be replaced by the pair WL 13 , WL 14 in FIG. 20 , etc.
  • a typical double-sided word line e.g., WL 12
  • WL 13 each single-sided word line is connected to only one row of memory elements.
  • FIG. 20 also illustrates a minimum block of memory elements that is erasable as a unit to be defined by two row of memory elements (M 113 , M 123 , M 133 , . . . ) and (M 114 , M 124 , M 134 , . . . ) sharing the same row of local bit lines (e.g., LBL 12 , LBL 22 , LBL 32 , . . . )
  • local bit lines e.g., LBL 12 , LBL 22 , LBL 32 , . . .
  • FIG. 21 illustrates the elimination of leakage currents in the single-sided word-line architecture 3-D array of FIGS. 19 and 20 .
  • the analysis of leakage current is similar to that described with respect to FIG. 16 .
  • the selected local bit line 220 (Sel-LBLj) is not coupled to an adjacent bit line 230 across the separated word lines 210 and 212 .
  • there is no leakage current between adjacent local bit lines and the sense current in the sense amplifier 240 via the global bit line 250 and the local bit line 220 will be just that from the current of the memory element I ELEMENT .
  • the single-sided word-line architecture doubles the number of word lines in the memory array compared to the architecture shown in FIG. 1 .
  • this disadvantage is offset by providing a memory array with less leakage currents among the memory elements.
  • FIG. 22 is an isometric view of a portion of the 3D array with the single-sided word line architecture shown in FIG. 19 .
  • FIG. 22 is one specific example of implementation for the single-sided word-line architecture.
  • the main difference compared to FIG. 7 is that each word line is connected to one side to a row of memory elements.
  • this architecture has the advantage of decoupling bit-line to bit line coupling across the plurality of word lines in the y-direction.
  • the 3D array is configured for use of memory element (NVM) material that is non-conductive when first deposited.
  • NVM memory element
  • a metal oxide of the type discussed earlier has this characteristic.
  • conductive filaments are formed between electrodes on opposite sides of the material in response to appropriate voltages placed on those electrodes. These electrodes are a bit line and a word line in the array. Since the material is otherwise non-conductive, there is no necessity to isolate the memory elements at the cross-points of the word and bit lines from each other.
  • Several memory elements may be implemented by a single continuous layer of material, which in the case of FIG. 22 are strips of NVM material oriented vertically along opposite sides of the vertical bit lines in the y-direction and extending upwards through all the planes.
  • a significant advantage of the structure of FIG. 22 is that all word lines and strips of insulation under them in a group of planes may be defined simultaneously by use of a single mask, thus greatly simplifying the manufacturing process.
  • FIG. 22 a small part of four planes 101 , 103 , 105 and 107 of the three-dimensional array are shown. Elements of the FIG. 22 array that correspond to those of the equivalent circuit of FIG. 19 are identified by the same reference numbers. It will be noted that FIG. 22 shows the two planes 1 and 2 of FIG. 19 plus two additional planes on top of them. All of the planes have the same horizontal pattern of word lines, dielectric and memory storage element (NVM) material. In each plane, metal word lines (WL) are elongated in the x-direction and spaced apart in the y-direction.
  • NVM dielectric and memory storage element
  • Each plane includes a layer of insulating dielectric that isolates its word lines from the word lines of the plane below it or, in the case of plane 101 , of the substrate circuit components below it. Extending through each plane is a collection of metal local bit line (LBL) “pillars” elongated in the vertical z-direction and forming a regular array in the x-y direction.
  • LBL metal local bit line
  • Each bit line pillar is connected to one of a set of global bit lines (GBL) in the silicon substrate running in the y-direction at the same pitch as the pillar spacing through the select devices (Q xy ) formed in the substrate whose gates are driven by the select gate lines (SG) elongated in the x-direction, which are also formed in the substrate.
  • the switching devices Q xy may be conventional CMOS transistors (or vertical npn transistors) and fabricated using the same process as used to form the other conventional circuitry.
  • the select gate (SG) lines are replaced with the base contact electrode lines elongated in the x-direction. Also fabricated in the substrate but not shown in FIG.
  • I/O 22 sense amplifiers, input-output (I/O) circuitry, control circuitry, and any other necessary peripheral circuitry.
  • select gate line (SG) for each row of local bit line pillars in the x-direction and one select device (Q) for each individual local bit line (LBL).
  • NVM non-volatile memory element
  • LBL vertical local bit lines
  • WL word lines
  • M memory storage element
  • a small region of the NVM material between an intersecting local bit line (LBL) and word line (WL) is controllably alternated between conductive (set) and non-conductive (reset) states by appropriate voltages applied to the intersecting lines.
  • the non-conducting NVM material may be left in place between adjacent local bit lines if the operating voltages between the adjacent LBLs remain below the programming threshold.
  • the single-sided word line architecture almost double the number of word line in the memory array compared to the double-sided one. This disadvantage is offset by providing a more partitioned memory array with less leakage currents among the memory elements.
  • variable resistive memory element described earlier can be written to any one of its states without starting from a given state. As such it is referred to as read/write (R/W) memory as compared to read/erase/program memory of the charge storage type.
  • R/W read/write
  • the resistive memory elements referred to earlier is also known as R/W memory elements or R/W elements.
  • the 3D array of such R/W elements can be considered as a 3D interconnected resistive mesh.
  • diodes are commonly connected in series with the R/W elements of a 3D memory array in order to reduce leakage currents in the resistive mesh.
  • a R/W element also referred to earlier as NVM
  • the diode is typically much larger in size compared to the NVM.
  • the diodes form a layer above the NVM and substantially increase the thickness of the memory.
  • the 3D array with relative short vertical bit lines described earlier in connection with FIG. 1 and FIG. 7 helps to limit the interconnectivity of the resistive mesh and therefore the leakage.
  • single-side word line architecture for the 3D array described earlier in connection with FIG. 19 also helps to segment the resistive mesh and further reduce the interconnectivity and leakage.
  • the reduction in leakage enables a viable 3D array that can do away with a diode in series with every R/W element. At least, the reduction in leakage brought by the short bit lines and single-side word lines enables a viable 3D array to employ a less than ideal diode (or what might be considered as a “lousy diode”) in series with each R/W element.
  • each R/W element with a diode in series are form in a lateral direction between a word line and a bit line at a crossing.
  • the 3D array is formed by a process in which the R/W elements and diodes are formed, not layer by layer vertically as in prior art, but laterally on all layers in parallel. This is accomplished by creating a simple multi-layer structure, exposing a cross section of the stratified layers by opening a portal and forming fine structures in each of the exposed layers in a lateral direction. This process is advantageous whether diodes are included or not.
  • Forming the active devices such as diodes is a high-temperature process. If metallization takes place before, the metal will have to be able to withstand the high-temperature processes that follow. This may exclude the use of aluminum or copper for their better conductivity and economy. The increased resistance in the word lines can exacerbate leakage problems.
  • the present process allows the high-temperature process for all the layers to be clustered together, and the metallization for the word lines to be performed after the high-temperature process.
  • FIG. 23 illustrates a preferred 3D memory structure with vertical local bit lines and horizontally formed active memory elements and diodes.
  • the 3D memory structure is defined with respect to an x-y-z coordinate system.
  • the local bit lines are in the z-direction
  • the word lines are in the x-direction
  • the global lines are in the y-direction.
  • the 3D structure can be regarded as comprising two portions.
  • a base portion commonly referred to as FEOL (“Front End Of (Manufacturing) Lines”), is supported by a semiconductor substrate on which active elements such as the select or switching devices Qxy are formed (see also FIG. 1 and FIG. 7 ).
  • a series of metal lines serving as global lines and various metal contact pads are formed on top of the active elements.
  • Each select device Qxy has a source connected to a metal line and drain connected to a drain terminal. In this way, the select device functions as a switch between the metal line and the drain terminal.
  • the Qxy for a given y along the x-direction have a common gate in the form of a poly line running along the x-direction.
  • the drain terminals are connected to respective local bit lines or word lines via contact pads 310 .
  • BEOL Back End Of (Manufacturing) Lines
  • BEOL is where the multiple layers of R/W material, word lines and vertical local bit lines are formed.
  • the local bit lines and connected to respective contact pads in the FEOL portion.
  • a plurality of local bit lines 330 in the z-direction are connected to a set of the contact points 310 .
  • a stack of memory element layers is formed.
  • word lines 340 surrounds from opposite sides a set of local bit line 330 .
  • the set of local bit lines (LBL 11 , LBL 21 , LBL, 31 , . . . ) is surrounded by word lines (WL 10 , WL 11 ) in layer 1 and (WL 20 , WL 21 ) in layer 2 , . . .
  • the bit line 330 is preferably formed from P+ polysilicon. In a region of a bit line where it is adjacent a word line, the region 332 is doped with N+ doping. In this way a diode 336 is formed in each region of the bit line 330 when it is adjacent a word line 340 . In between each word line 340 and the diode 336 is formed a R/W memory element 346 . In a preferred embodiment, the resistive memory element 346 is formed by a Ti layer 344 next to the word line 340 followed by a HfOx layer 342 . The top layer of the 3D structure is capped by a nitride layer 350 .
  • each vertical local bit line 330 along the x-direction e.g., LBL 11 , LBL 21 , LBL 31 , . . .
  • respective word lines WL 340 e.g., WL 10 , WL 20 , WL 30 , . . .
  • Similar R/W elements and diodes are formed on another side of the same set of bit lines 330 (LBL 11 , LBL 21 , LBL 31 , . . . ) along the x-direction and also connected to respective word lines (WL 11 , WL 21 , WL 31 , . . . ).
  • a dielectric such as an oxide 320 .
  • a 3D R/W array is formed similar to that illustrated schematically in FIG. 19 except for the diode in series between each R/W element and its respective bit line.
  • FIG. 24A illustrates in more detail the R/W element and diode formed between a pair of word line and bit line at a crossing.
  • the R/W memory element 346 is formed with the Ti layer 344 and the HfOx layer 342 .
  • the Ti layer is in electrical contact with the word line 340 while the HfOx layer 342 is in electrical contact with the diode 336 .
  • the bit line 330 is generally doped as a P+ polysilicon. However, it is countered doped as N+ in the region 332 where there is a crossing with a word line such as the word line 340 .
  • the resulting PN junction effectively forms the diode 336 which is disposed in series with the R/W element 346 between the word line 340 and the local bit line 330 .
  • FIG. 24B illustrates schematically the equivalent circuit of the R/W memory element 346 and diode 336 in series between each crossing of a word line 340 and a local bit line 330 .
  • the 3D memory structure shown in FIG. 23 and also in FIG. 24A and FIG. 24B has the advantage of realizing a 3D memory where each memory element has a diode isolation to reduce current linkage to adjacent local bit lines.
  • the horizontal (x-direction) orientation of the memory element 346 allows each diode to be formed as a region of a local bit line, thereby not taking up additional space.
  • FIGS. 25A-25F illustrate the formation of the BEOL (top) portion of 3D memory shown in FIG. 23 at various processing stages.
  • FIG. 25A illustrates the formation of the BEOL portion as a multi-layer structure being formed on top of the FEOL base layer.
  • a gross structure is formed as a sandwich of multiple alternate layers of oxide 320 and layer of sacrificial material 322 .
  • Undoped polysilicon is preferably used to form the sacrificial layer 322 as it can easily be etched away and replaced by other structures.
  • the FEOL base layer is formed with the switching devices Qxy which switch between respective global line and drain terminals as described earlier.
  • a metal pad of preferably W or TiN is formed on each drain terminal to make the connection. This is followed by a layer of oxide 320 .
  • the layer of oxide is then planarized to be flushed with that of the metal pads.
  • a sandwich of alternate layers of undoped polysilicon 322 and oxide 320 are laid down.
  • the sandwich is capped by a protective nitride layer 350 .
  • another sacrificial layer of oxide is also deposited on top of the nitride layer.
  • FIG. 25B illustrates the formation of trenches where the plurality of local bit lines 330 are to be formed in the 3D structure of FIG. 25A .
  • a hard mask (“HM”) deposition and lithography is set up so that vertical trenches running along the x-direction in the 3D structure can then be etched away to form the trenches where the local bit lines are to be formed.
  • the trenches are lined up with contact pads in the x-direction so that local bit lines will be formed to make contacts with the contact pads.
  • FIG. 25C illustrates the formation of the local bit lines in the trenches of FIG. 25B .
  • a BOE buffered oxide etch
  • the local bit lines 330 are then formed (in the form of a slab along the x-direction) by filling the trenches with P+ poly.
  • the P+ poly is then planarized.
  • FIG. 25D illustrates the formation of a portal to access the stratified 3D structure laterally. This allows the structures in each layer, such as R/W elements, diodes and word lines, to be formed for all layers in parallel. This is accomplished by HM deposition followed by litho and etch.
  • FIG. 25E illustrates the formation of recessed spaces for forming the structures in each layer.
  • the recessed spaces for all layers are created in parallel. This is accomplished by a KOH wet etch followed by a second, isotropic recess etch which selectively removes the undoped poly right up to the columns of the local bit lines.
  • the exposed bands of the slabs of local bit lines are then counter-doped with N+ by a gas-phase doping process. This will create a PN junction just below the exposed surface of the local bit lines.
  • the local bit lines are formed with N+ polysilicon.
  • the diode will then be made by P+ diffusion.
  • the N+ doping will be skipped.
  • the local bit lines can be formed with metal.
  • FIG. 25F illustrates the formation of the R/W layer followed by the word line for each of all the recessed spaces.
  • the recessed space is first BOE (Buffered Oxide Etched) etched.
  • the R/W material is formed by Atomic Layer Deposition of a first layer 342 (e.g., HFOx.) This is followed by depositing a second layer 344 (e.g., Ti (titanium)) by Chemical Vapor Deposition.
  • a first layer 342 e.g., HFOx.
  • a second layer 344 e.g., Ti (titanium)
  • the word lines 340 can be formed.
  • the metallization can be optimized for its conductivity without regard to subsequent high-temperature degradation.
  • aluminum or copper could be deposited.
  • high-temperature metals can also be contemplated such as a thin layer of TiN followed by a bulk layer of W (titanium) by Chemical Vapor Deposition. The excess from various depositions can be etched back.
  • FIG. 25G illustrates the formation of the individual local bit line columns by first removing portions of the local bit line slab along the x-direction. The resulting voids are then filled with oxide 320 as shown in FIG. 23 . The top surface is planarized by chemical and mechanical polishing.
  • FIG. 26A-26B illustrate the formation of metal lines and contacts for accessing the word lines 340 of the 3D memory shown in FIG. 23 .
  • the word lines are accessed by contacts from either top or bottom of the 3D memory structure.
  • Each word line is connected to a metal line at a surface of the 3D memory structure by a vertical riser column 314 .
  • FIG. 26A illustrates the 3D structure is terraced to provide an offset at different layers.
  • the word lines at each layer will have an unobstructed path for its riser column from the top.
  • the access is at the ends of the word lines.
  • terracing is formed at both ends of the 3D structure along the x-direction so that the metal lines at the surface is at half density compared to accessing all the word lines from one end. After terracing and creating an unobstructed view for each layer of word lines, the volume removed during terracing is refilled with oxide and planarized.
  • FIG. 26B illustrates the formation of the surface metal lines connecting to the respective word lines by riser columns.
  • the spaces for the riser columns are etched away from the top of each of the terrace layers to make way for the riser column.
  • the resulting void is then filled with a riser column 314 that connects a word line to the top surface of the 3D structure.
  • the riser column 314 can then be connected by a metal line 312 formed at the top surface.
  • the word lines are accessed via some of the global bit lines, such as those shown in FIG. 22 .
  • FIG. 27 illustrates another embodiment in where the word lines are accessed by metal wires at the base portion of the 3D structure, such as appropriating some of the global bit lines shown in FIG. 22 to act as global word lines.
  • the connection to a word line is brought to a metal line at the top of the 3D structure as in FIG. 26A and FIG. 26B .
  • a second column riser 316 drills down to make contact with an appropriate global word line via one of the contact pads 310 .
  • columns are evacuated from the top of the 3D structure and then filled with conductive material such as metal. Then the metal lines 312 at the top serving as connection bridges are formed.
  • a 3D memory having multiple layers of 2D array of R/W elements in the x-y plane are accessible by word lines among each layer and an array of vertical local lines in the z-direction common to all layers.
  • a plurality of metal lines along the y-direction is provided either at a base portion or a top surface of a 3D memory.
  • a first set of the metal lines is switchably connected to allow access to a first set of vertical local lines acting as a selected group vertical local bit lines.
  • a second set of the metal lines is switchably connected to allow access to a second set of vertical local lines connected to selected word lines in respective layers.
  • the set of metal lines serves as global access lines for selected sets of local bit lines and word lines.
  • the switching of the set of metal lines to the selected sets of local bit lines and word lines is accomplished by a set of switching transistors at the base portion of the 3D memory.
  • a set of riser columns provides the connections from the switching transistors to the metal lines.
  • the 3D memory array has a base layer (FEOL) portion and another portion (BEOL) having multiple layers memory element planes.
  • FEOL base layer
  • BEOL another portion
  • a set of metal lines acting as global bit lines are formed at the base portion (FEOL) of the 3D structure.
  • not all the metal lines in the set are used for decoding the local bit lines.
  • not all the local vertical lines in the array are used as local bit lines. Instead some of the metal lines and some of the local vertical lines are reserved for decoding a set of selected word lines, two from each layer.
  • This scheme provides a highly scalable decoding architecture. It allows decoding of any combination of word lines and local bit lines. It allows further segmentation of the word lines into local word lines, thereby helping to reduce the word line resistance and the interactivity of the 3D resistive mesh.
  • FIG. 28 illustrates an efficient decoding of vertical bit lines and horizontal word lines in a 3D memory array via a set of global lines and select devices.
  • An example 3D array with 4 layers stacked along the z-direction is shown. Similar to the 3D array shown in FIG. 17 and FIG. 23 , the 4 layers are accessible by a 2D array of local vertical lines 331 and 332 in the z-direction.
  • the 2D array of local vertical lines are partitioned into two sets.
  • a first set of local vertical lines 331 individually act as local bit lines and is switchably connected to a first set of global lines such as global bit lines 251 .
  • a second set of local vertical lines 332 individually act as interconnects that are switchably connected between the word lines 340 and a second set of the global lines such as global word lines 252 .
  • Each of the first set of local vertical lines 332 makes contact with a word line at each layer via a connector or contact 348 .
  • At each layer there will be a set of word lines 340 spaced apart along the y-direction and with each word line running along the x-direction.
  • FIG. 28 only shows one block of memory elements constituted from a selected pair of word lines 340 on each layer, wrapping on both sides of a selected page of vertical local lines 331 acting as local bit lines (LBL 11 , LBL 21 , LBL 31 , . . . , LBL (P-1)1 , LBL P1 ).
  • WL 10 and WL 11 are the selected pair of word lines at layer 1
  • WL 20 and WL 21 are the selected pair of word lines at layer 2
  • WL 30 and WL 31 are the selected pair of word lines at layer 3
  • WL 40 and WL 41 are the selected pair of word lines at layer 4 .
  • the decoding of a selected page of local bit lines is similar to before where there is a first set P metal lines (GBL 1 , GBL 2 , GBL 3 , . . . , GBL P ) acting as the first set of global lines (global bit lines) 251 to access the selected page of local bit lines among the first set of vertical local lines 331 . Since the memory has a page architecture with two word lines (even and odd) on each layer around the same page of local bit lines, there is a second set of 2 ⁇ 4 metal lines acting as a second set of global lines (global word lines) 252 .
  • GBL 1 , GBL 2 , GBL 3 , . . . , GBL P acting as the first set of global lines (global bit lines) 251 to access the selected page of local bit lines among the first set of vertical local lines 331 . Since the memory has a page architecture with two word lines (even and odd) on each layer around the same page of local bit lines, there is a second set of 2
  • the metal lines are distributed on both side of the first set, with a left flank of 4 metal lines (GWL 11 , GWL 21 , GWL 31 and GWL 41 ) respectively for the odd word lines (WL 11 , WL 21 , WL 31 and WL 41 ) at each of the 4 layers. Similar, there is a right flank of 4 meal lines (GWL 10 , GWL 20 , GWL 30 and GWL 40 ) respectively for the even word lines (WL 10 , WL 20 , WL 30 and WL 40 ) at each of the 4 layers.
  • the connections of the metal lines (global lines) to selected word lines and local bit lines are via the select devices Qxy 222 controlled by the select line 221 such as SG 1 acting as a block select line.
  • a selected page/block is decoded by asserting the block select line SG 1 .
  • the R/W elements 346 in the block are accessible by the global lines with the bit lines accessed via the global lines 251 and the word lines via the global lines 252 .
  • Sensing circuits are then connectable to the bit lines for sensing the memory state of the R/W elements.
  • FIG. 29 illustrates a plan view of a BEOL (top portion of the 3D memory) layout for the word lines and the R/W elements according to a first architecture for the 3D array shown in FIG. 28 .
  • the global lines 250 include global word lines 252 and global bit 251 lines
  • the global lines 250 are offset ( ⁇ 1 F; F is the feature length) from each of the pillars of vertical local lines 330 (include vertical local bit lines 331 and vertical local lines 332 ).
  • the array of vertical local lines are divided into a first set and a second set.
  • the first set acts as vertical local bit lines, where each local bit line 331 is used to access a R/W element 346 in combination with a word line 340 .
  • a local bit line is shared between a pair of word lines for accessing two R/W elements.
  • Each local bit line 331 is coupled to a metal line forming a global bit line 251 .
  • Each of the second set of vertical local lines 332 acts as an interconnect between a word line 340 and a metal line forming a global word lines 252 .
  • the vertical local line 332 is connected to the word line 340 via the connector 348 . If there are four layers, there will be four vertical local line per row of word lines.
  • the first vertical local line is connected to the word line on the first layer, the second vertical local line is connected to the word line on the second layer, etc.
  • a unit cell has dimension XF*YF.
  • XF is limited by bit line pillar to bit line spacing ( ⁇ 4 F).
  • YF is limited by local WL to local WL to R/W material to BL pillar ( ⁇ 2.5 F). These give a cell size of ⁇ 10 F2 for each layer.
  • the cell size is XF*XY/L layer.
  • the block can be selected by enabling a bank of select devices via a common gate select line (e.g., SG 1 , see FIG. 28 ).
  • a common gate select line e.g., SG 1 , see FIG. 28 .
  • the layout of the FEOL base portion of the 3D memory
  • P+2 L metal lines plus a number of select devices equal to (P+2 L)*(number of pair of word lines in each layer).
  • Each select device is an active region on the base portion (or FEOL plane) of the 3D memory.
  • a select device is formed on the substrate with a poly gate over a pair of source and drain diffusion spots.
  • a common poly line enables control over the bank of select devices in parallel.
  • FIG. 30A illustrates a first embodiment of the FEOL layout in a plan view of a unit block when the BEOL has the first architecture of FIG. 29 .
  • a plurality of select transistors 222 exists (not shown explicitly), each with its source and drain coinciding with either a vertical local line pillar 331 or 332 , or a contact 253 .
  • the select transistors are the select devices Qxy 222 shown in FIG. 28 .
  • the select devices for switching the bit lines 331 and word lines 340 to the global lines 251 and 252 respectively are size-limited by the spacing between pillars 331 or 332 along the y-direction.
  • FIG. 30B illustrates a second embodiment of the FEOL layout in a plan view of a unit block when the BEOL has the first architecture of FIG. 29 .
  • the active elements select transistors 222 not shown explicitly but each with its source and drain coinciding with either a vertical local line pillar 331 or 332 , or a contact 253 ) in a diagonal manner relative to the global lines, the length of the select devices can be increased by a factor of SQRT( 2 ).
  • FIG. 30C illustrates a third embodiment of the FEOL layout in a plan view of a unit block when the BEOL has the first architecture of FIG. 29 .
  • M again equals 2.
  • FIG. 31 illustrates a BEOL (top portion of the 3D memory) layout in a plan view for the word lines and the R/W elements according to a second architecture for the 3D array shown in FIG. 28 .
  • the global lines include global word lines 252 and global bit lines 251 ) are formed on the top part of the 3D memory.
  • the global lines are aligned with the pillars of vertical local lines 331 and 332 .
  • a unit cell has dimension XF*YF. XF is limited by vertical local line pillar 331 , 332 to pillar spacing ( ⁇ 2 F).
  • YF is limited by local WL 340 to local WL to R/W material 346 to vertical local line pillar 331 , 332 and also additional space for a contact 253 ( ⁇ 3.5 F). These give a cell size of ⁇ 7 F2 for each layer. Each bit line pillar make contact with a global line 251 or 252 .
  • FIG. 32 illustrates a cross section of the BEOL layout of FIG. 31 in the y-z plane.
  • a local bit line 331 associated with a word line 340 sits on one terminal (either source 224 or drain 226 ) of a select transistor 222 and makes a connection via the select transistor and a riser column 314 with one of the global lines 251 on the top of the 3D memory.
  • FIG. 33 illustrates a first embodiment of the FEOL layout in a plan view of a unit block when the BEOL has the second architecture of FIG. 31 .
  • M again equals 2.
  • the first embodiment of the second architecture shown in FIG. 33 is similar to the first embodiment of the first architecture shown in FIG. 30A .
  • the second and third embodiments of the first architecture shown respectively in FIG. 30B and FIG. 30C can readily be adapted to the second architecture.
  • FIG. 34 illustrates a schematic top view of the entire 3D array including peripheral circuits. It will be seen that the present architecture of using global lines to decode both the local bit lines and word lines is highly scalable.
  • the global word line drivers, sense amplifiers and block select drivers can be on the same side or on alternate side of the array.
  • each word line can be halved to reduce the resistance and capacitance across its length.
  • the length of the word line is halved, the number of world lines to decode is doubled, and more vertical local lines and global lines will need to be expropriated for word-line decoding.

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EP11725298.1A EP2580758A1 (en) 2010-06-08 2011-06-07 Non-volatile memory having 3d array of read/write elements with vertical bit lines and laterally aligned active elements and methods thereof
PCT/US2011/039416 WO2011156351A1 (en) 2010-06-08 2011-06-07 Non-volatile memory having 3d array of read/write elements with vertical bit lines and laterally aligned active elements and methods thereof
JP2013514293A JP2013535101A (ja) 2010-06-08 2011-06-07 垂直ビット線および横方向に整列したアクティブな素子を有する読み出し／書き込み素子の３次元アレイを有する不揮発性メモリおよびその方法
KR1020137000288A KR20130132373A (ko) 2010-06-08 2011-06-07 수직 비트 라인들을 갖는 판독/기입 엘리먼트들과 횡으로 정렬된 액티브 엘리먼트들의 3d 어레이를 갖는 비휘발성 메모리 및 그 방법
CN2011800286855A CN102971799A (zh) 2010-06-08 2011-06-07 具有含垂直位线和横向对准的有源元件的读/写元件的3d 阵列的非易失性存储器及其方法
TW100120027A TW201209827A (en) 2010-06-08 2011-06-08 Non-volatile memory having 3D array of read/write elements with vertical bit lines and laterally aligned active elements and methods thereof
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Cited By (106)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080299773A1 (en) * 2007-06-01 2008-12-04 Shinya Watanabe Semiconductor device manufacturing method
US20100148151A1 (en) * 2000-09-12 2010-06-17 Philips Lumileds Lighting Company, Llc Light emitting devices with improved light extraction efficiency
US20120044758A1 (en) * 2010-08-20 2012-02-23 Chung Shine C Circuit and system of using at least one junction diode as program selector for memories
US8199576B2 (en) 2009-04-08 2012-06-12 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a double-global-bit-line architecture
US20120147644A1 (en) * 2010-12-14 2012-06-14 Scheuerlein Roy E Continuous mesh three dimensional non-volatile storage with vertical select devices
US20120314468A1 (en) * 2011-06-10 2012-12-13 Unity Semiconductor Corporation Memory array with local bitlines and local-to-global bitline pass gates and gain stages
US8351236B2 (en) 2009-04-08 2013-01-08 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture
US8488359B2 (en) 2010-08-20 2013-07-16 Shine C. Chung Circuit and system of using junction diode as program selector for one-time programmable devices
JP2013153127A (ja) * 2012-01-24 2013-08-08 Toshiba Corp 記憶装置
US8526237B2 (en) 2010-06-08 2013-09-03 Sandisk 3D Llc Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereof
US8547720B2 (en) 2010-06-08 2013-10-01 Sandisk 3D Llc Non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines
US8607019B2 (en) 2011-02-15 2013-12-10 Shine C. Chung Circuit and method of a memory compiler based on subtractive approach
CN103474570A (zh) * 2012-06-06 2013-12-25 复旦大学 集成于集成电路的后端结构的电阻型存储器及其制备方法
JP2014049745A (ja) * 2012-08-31 2014-03-17 Toshiba Corp 半導体記憶装置、及びその製造方法
CN103681727A (zh) * 2012-09-17 2014-03-26 复旦大学 双层结构电阻型存储器及其制备方法
CN103682088A (zh) * 2012-09-10 2014-03-26 中国科学院微电子研究所 一种制造交叉点器件的方法
US20140085961A1 (en) * 2012-09-26 2014-03-27 Kohji Kanamori Semiconductor memory device
CN103904080A (zh) * 2012-12-28 2014-07-02 旺宏电子股份有限公司 三维存储器结构及其操作方法
US8804398B2 (en) 2010-08-20 2014-08-12 Shine C. Chung Reversible resistive memory using diodes formed in CMOS processes as program selectors
US8830720B2 (en) 2010-08-20 2014-09-09 Shine C. Chung Circuit and system of using junction diode as program selector and MOS as read selector for one-time programmable devices
US8848423B2 (en) 2011-02-14 2014-09-30 Shine C. Chung Circuit and system of using FinFET for building programmable resistive devices
US8861249B2 (en) 2012-02-06 2014-10-14 Shine C. Chung Circuit and system of a low density one-time programmable memory
US20140313813A1 (en) * 2013-04-23 2014-10-23 Kabushiki Kaisha Toshiba Semiconductor memory device and operation method thereof
US8912576B2 (en) 2011-11-15 2014-12-16 Shine C. Chung Structures and techniques for using semiconductor body to construct bipolar junction transistors
US8913449B2 (en) 2012-03-11 2014-12-16 Shine C. Chung System and method of in-system repairs or configurations for memories
US8917533B2 (en) 2012-02-06 2014-12-23 Shine C. Chung Circuit and system for testing a one-time programmable (OTP) memory
US8923085B2 (en) 2010-11-03 2014-12-30 Shine C. Chung Low-pin-count non-volatile memory embedded in a integrated circuit without any additional pins for access
US8988965B2 (en) 2010-11-03 2015-03-24 Shine C. Chung Low-pin-count non-volatile memory interface
US9007804B2 (en) 2012-02-06 2015-04-14 Shine C. Chung Circuit and system of protective mechanisms for programmable resistive memories
US9019791B2 (en) 2010-11-03 2015-04-28 Shine C. Chung Low-pin-count non-volatile memory interface for 3D IC
US9019742B2 (en) 2010-08-20 2015-04-28 Shine C. Chung Multiple-state one-time programmable (OTP) memory to function as multi-time programmable (MTP) memory
US9025357B2 (en) 2010-08-20 2015-05-05 Shine C. Chung Programmable resistive memory unit with data and reference cells
US9042153B2 (en) 2010-08-20 2015-05-26 Shine C. Chung Programmable resistive memory unit with multiple cells to improve yield and reliability
US20150145139A1 (en) * 2013-11-22 2015-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Word line coupling prevention using 3d integrated circuit
US9070437B2 (en) 2010-08-20 2015-06-30 Shine C. Chung Circuit and system of using junction diode as program selector for one-time programmable devices with heat sink
US9076526B2 (en) 2012-09-10 2015-07-07 Shine C. Chung OTP memories functioning as an MTP memory
US9136261B2 (en) 2011-11-15 2015-09-15 Shine C. Chung Structures and techniques for using mesh-structure diodes for electro-static discharge (ESD) protection
US20150262662A1 (en) * 2014-03-11 2015-09-17 Everspin Technologies, Inc. Nonvolatile logic and security circuits
US9165933B2 (en) 2013-03-07 2015-10-20 Sandisk 3D Llc Vertical bit line TFT decoder for high voltage operation
US9165647B1 (en) * 2014-06-04 2015-10-20 Intel Corporation Multistage memory cell read
US9183897B2 (en) 2012-09-30 2015-11-10 Shine C. Chung Circuits and methods of a self-timed high speed SRAM
US9202694B2 (en) 2013-03-04 2015-12-01 Sandisk 3D Llc Vertical bit line non-volatile memory systems and methods of fabrication
US9224496B2 (en) 2010-08-11 2015-12-29 Shine C. Chung Circuit and system of aggregated area anti-fuse in CMOS processes
US9236141B2 (en) 2010-08-20 2016-01-12 Shine C. Chung Circuit and system of using junction diode of MOS as program selector for programmable resistive devices
US20160020255A1 (en) * 2014-05-20 2016-01-21 Sandisk 3D Llc Memory hole bit line structures
US9251893B2 (en) 2010-08-20 2016-02-02 Shine C. Chung Multiple-bit programmable resistive memory using diode as program selector
US9269425B2 (en) 2011-12-30 2016-02-23 Sandisk 3D Llc Low forming voltage non-volatile storage device
US9324849B2 (en) 2011-11-15 2016-04-26 Shine C. Chung Structures and techniques for using semiconductor body to construct SCR, DIAC, or TRIAC
US9324447B2 (en) 2012-11-20 2016-04-26 Shine C. Chung Circuit and system for concurrently programming multiple bits of OTP memory devices
US9362338B2 (en) 2014-03-03 2016-06-07 Sandisk Technologies Inc. Vertical thin film transistors in non-volatile storage systems
US9379246B2 (en) 2014-03-05 2016-06-28 Sandisk Technologies Inc. Vertical thin film transistor selection devices and methods of fabrication
US9390796B2 (en) 2011-06-10 2016-07-12 Unity Semiconductor Corporation Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
US9412473B2 (en) 2014-06-16 2016-08-09 Shine C. Chung System and method of a novel redundancy scheme for OTP
US9431127B2 (en) 2010-08-20 2016-08-30 Shine C. Chung Circuit and system of using junction diode as program selector for metal fuses for one-time programmable devices
US9450023B1 (en) 2015-04-08 2016-09-20 Sandisk Technologies Llc Vertical bit line non-volatile memory with recessed word lines
US20160276018A1 (en) * 2015-03-19 2016-09-22 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
US9460807B2 (en) 2010-08-20 2016-10-04 Shine C. Chung One-time programmable memory devices using FinFET technology
US9496265B2 (en) 2010-12-08 2016-11-15 Attopsemi Technology Co., Ltd Circuit and system of a high density anti-fuse
US9496033B2 (en) 2010-08-20 2016-11-15 Attopsemi Technology Co., Ltd Method and system of programmable resistive devices with read capability using a low supply voltage
US20170047339A1 (en) * 2014-09-24 2017-02-16 Sandisk Technologies Llc Process for Word Line Connections in 3D Memory
US20170133101A9 (en) * 2010-08-20 2017-05-11 Shine C. Chung Method and structure for reliable electrical fuse programming
US20170148982A1 (en) * 2014-06-26 2017-05-25 Intel Corporation Oxide-based three-terminal resistive switching logic devices
US9818478B2 (en) 2012-12-07 2017-11-14 Attopsemi Technology Co., Ltd Programmable resistive device and memory using diode as selector
US9824768B2 (en) 2015-03-22 2017-11-21 Attopsemi Technology Co., Ltd Integrated OTP memory for providing MTP memory
CN108538879A (zh) * 2018-03-09 2018-09-14 上海新储集成电路有限公司 一种三维存储器的存储单元结构
US20180366190A1 (en) * 2016-02-15 2018-12-20 SK Hynix Inc. Electronic device
US10192615B2 (en) 2011-02-14 2019-01-29 Attopsemi Technology Co., Ltd One-time programmable devices having a semiconductor fin structure with a divided active region
US20190035731A1 (en) * 2017-07-31 2019-01-31 Globalfoundries Inc. Interconnect structure
US10229746B2 (en) 2010-08-20 2019-03-12 Attopsemi Technology Co., Ltd OTP memory with high data security
US10249379B2 (en) 2010-08-20 2019-04-02 Attopsemi Technology Co., Ltd One-time programmable devices having program selector for electrical fuses with extended area
WO2019069048A1 (en) * 2017-10-06 2019-04-11 Arm Ltd RECONFIGURABLE CIRCUIT ARCHITECTURE
US20190148393A1 (en) * 2017-11-10 2019-05-16 Macronix International Co., Ltd. 3d array arranged for memory and in-memory sum-of-products operations
EP3506360A1 (en) * 2017-12-29 2019-07-03 IMEC vzw Three-dimensional semiconductor memory device and method for manufacturing thereof
WO2019209441A1 (en) 2018-04-24 2019-10-31 Micron Technology, Inc. Cross-point memory array and related fabrication techniques
US10535413B2 (en) 2017-04-14 2020-01-14 Attopsemi Technology Co., Ltd Low power read operation for programmable resistive memories
US10566056B2 (en) 2011-06-10 2020-02-18 Unity Semiconductor Corporation Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
US10586832B2 (en) 2011-02-14 2020-03-10 Attopsemi Technology Co., Ltd One-time programmable devices using gate-all-around structures
CN111052376A (zh) * 2017-08-29 2020-04-21 美光科技公司 三维存储器阵列
US10719296B2 (en) 2018-01-17 2020-07-21 Macronix International Co., Ltd. Sum-of-products accelerator array
US10726914B2 (en) 2017-04-14 2020-07-28 Attopsemi Technology Co. Ltd Programmable resistive memories with low power read operation and novel sensing scheme
US20200258940A1 (en) * 2011-08-15 2020-08-13 Unity Semiconductor Corporation Vertical cross-point memory arrays
US10770160B2 (en) 2017-11-30 2020-09-08 Attopsemi Technology Co., Ltd Programmable resistive memory formed by bit slices from a standard cell library
US10783963B1 (en) 2019-03-08 2020-09-22 Macronix International Co., Ltd. In-memory computation device with inter-page and intra-page data circuits
US10910393B2 (en) 2019-04-25 2021-02-02 Macronix International Co., Ltd. 3D NOR memory having vertical source and drain structures
US10916317B2 (en) 2010-08-20 2021-02-09 Attopsemi Technology Co., Ltd Programmable resistance memory on thin film transistor technology
US10923204B2 (en) 2010-08-20 2021-02-16 Attopsemi Technology Co., Ltd Fully testible OTP memory
US10957392B2 (en) 2018-01-17 2021-03-23 Macronix International Co., Ltd. 2D and 3D sum-of-products array for neuromorphic computing system
US11062786B2 (en) 2017-04-14 2021-07-13 Attopsemi Technology Co., Ltd One-time programmable memories with low power read operation and novel sensing scheme
US11119674B2 (en) 2019-02-19 2021-09-14 Macronix International Co., Ltd. Memory devices and methods for operating the same
US11132176B2 (en) 2019-03-20 2021-09-28 Macronix International Co., Ltd. Non-volatile computing method in flash memory
US11139306B2 (en) 2019-05-28 2021-10-05 Winbond Electronics Corp. Memory device and method for fabricating the same
US11138497B2 (en) 2018-07-17 2021-10-05 Macronix International Co., Ltd In-memory computing devices for neural networks
WO2021236166A1 (en) * 2020-05-18 2021-11-25 Sandisk Technologies Llc Three-dimensional memory device including ferroelectric-metal-insulator memory cells and methods of making the same
US11282848B2 (en) 2020-05-18 2022-03-22 Sandisk Technologies Llc Three-dimensional memory device including ferroelectric-metal-insulator memory cells and methods of making the same
US11302716B2 (en) 2020-05-18 2022-04-12 Sandisk Technologies Llc Three-dimensional memory device including ferroelectric-metal-insulator memory cells and methods of making the same
US11393525B2 (en) 2020-09-17 2022-07-19 Kioxia Corporation Semiconductor memory device
US11562229B2 (en) 2018-11-30 2023-01-24 Macronix International Co., Ltd. Convolution accelerator using in-memory computation
US11615859B2 (en) 2017-04-14 2023-03-28 Attopsemi Technology Co., Ltd One-time programmable memories with ultra-low power read operation and novel sensing scheme
US11636325B2 (en) 2018-10-24 2023-04-25 Macronix International Co., Ltd. In-memory data pooling for machine learning
US11706934B2 (en) 2018-04-24 2023-07-18 Micron Technology, Inc. Cross-point memory array and related fabrication techniques
US11710519B2 (en) 2021-07-06 2023-07-25 Macronix International Co., Ltd. High density memory with reference memory using grouped cells and corresponding operations
US11737274B2 (en) 2021-02-08 2023-08-22 Macronix International Co., Ltd. Curved channel 3D memory device
US11916011B2 (en) 2021-04-14 2024-02-27 Macronix International Co., Ltd. 3D virtual ground memory and manufacturing methods for same
TWI834125B (zh) * 2021-07-09 2024-03-01 台灣積體電路製造股份有限公司 記憶體裝置以及其形成方法
US11934480B2 (en) 2018-12-18 2024-03-19 Macronix International Co., Ltd. NAND block architecture for in-memory multiply-and-accumulate operations
US12087758B2 (en) 2018-04-24 2024-09-10 Micron Technology, Inc. Buried lines and related fabrication techniques

Families Citing this family (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8270193B2 (en) 2010-01-29 2012-09-18 Unity Semiconductor Corporation Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
EP2731110B1 (en) * 2010-12-14 2016-09-07 SanDisk Technologies LLC Architecture for three dimensional non-volatile storage with vertical bit lines
US8797806B2 (en) 2011-08-15 2014-08-05 Micron Technology, Inc. Apparatus and methods including source gates
KR20130070153A (ko) * 2011-12-19 2013-06-27 에스케이하이닉스 주식회사 반도체 장치의 캐패시터, 레지스터, 메모리 시스템 및 이들의 제조 방법
KR101965686B1 (ko) * 2012-02-27 2019-04-04 삼성전자주식회사 수직형 저항 메모리 장치의 읽기 방법
KR20130098002A (ko) * 2012-02-27 2013-09-04 삼성전자주식회사 수직형 저항 메모리 장치의 프로그램 방법
US9171584B2 (en) * 2012-05-15 2015-10-27 Sandisk 3D Llc Three dimensional non-volatile storage with interleaved vertical select devices above and below vertical bit lines
US10541029B2 (en) 2012-08-01 2020-01-21 Micron Technology, Inc. Partial block memory operations
US9224945B2 (en) 2012-08-30 2015-12-29 Micron Technology, Inc. Resistive memory devices
US8729523B2 (en) * 2012-08-31 2014-05-20 Micron Technology, Inc. Three dimensional memory array architecture
US8841649B2 (en) * 2012-08-31 2014-09-23 Micron Technology, Inc. Three dimensional memory array architecture
US9318199B2 (en) * 2012-10-26 2016-04-19 Micron Technology, Inc. Partial page memory operations
US9093152B2 (en) 2012-10-26 2015-07-28 Micron Technology, Inc. Multiple data line memory and methods
US9064578B2 (en) 2012-12-18 2015-06-23 Micron Technology, Inc. Enable/disable of memory chunks during memory access
US20140175371A1 (en) * 2012-12-21 2014-06-26 Elijah V. Karpov Vertical cross-point embedded memory architecture for metal-conductive oxide-metal (mcom) memory elements
US10546998B2 (en) * 2013-02-05 2020-01-28 Micron Technology, Inc. Methods of forming memory and methods of forming vertically-stacked structures
JP2014179571A (ja) * 2013-03-15 2014-09-25 Toshiba Corp 抵抗変化型記憶装置
US9047933B2 (en) 2013-04-22 2015-06-02 Sandisk Technologies Inc. High speed signaling techniques to improve performance of integrated circuits
US9147493B2 (en) 2013-06-17 2015-09-29 Micron Technology, Inc. Shielded vertically stacked data line architecture for memory
US9281345B2 (en) 2013-07-09 2016-03-08 Kabushiki Kaisha Toshiba Resistance change type memory device with three-dimensional structure
US9437296B2 (en) * 2014-02-03 2016-09-06 Kabushiki Kaisha Toshiba Three-dimensional resistive memory device with adjustable voltage biasing
US9123392B1 (en) * 2014-03-28 2015-09-01 Sandisk 3D Llc Non-volatile 3D memory with cell-selectable word line decoding
US9437658B2 (en) * 2014-08-05 2016-09-06 Sandisk Technologies Llc Fully isolated selector for memory device
TWI565032B (zh) * 2014-08-29 2017-01-01 旺宏電子股份有限公司 記憶元件及其製造方法
KR102150251B1 (ko) 2014-09-05 2020-09-02 삼성전자주식회사 반도체 장치
US9299767B1 (en) * 2014-09-26 2016-03-29 Intel Corporation Source-channel interaction in 3D circuit
KR102288869B1 (ko) * 2014-10-01 2021-08-10 삼성전자주식회사 시스템 온 칩
KR20170085126A (ko) * 2014-11-18 2017-07-21 휴렛 팩커드 엔터프라이즈 디벨롭먼트 엘피 널링 증폭기를 구비한 멤리스티브 내적 엔진
TWI559508B (zh) * 2014-12-15 2016-11-21 旺宏電子股份有限公司 三維堆疊半導體結構及其製造方法
US9613975B2 (en) * 2015-03-31 2017-04-04 Sandisk Technologies Llc Bridge line structure for bit line connection in a three-dimensional semiconductor device
US9444036B1 (en) 2015-08-25 2016-09-13 HGST Netherlands B.V. Implementing segregated media based magnetic memory
US9443905B1 (en) 2015-08-25 2016-09-13 HGST Netherlands B.V. Implementing 3D scalable magnetic memory with interlayer dielectric stack and pillar holes having programmable area
US9431457B1 (en) 2015-08-25 2016-08-30 HGST Netherlands B.V. Implementing deposition growth method for magnetic memory
US9780143B2 (en) 2015-08-25 2017-10-03 Western Digital Technologies, Inc. Implementing magnetic memory integration with CMOS driving circuits
US10157656B2 (en) 2015-08-25 2018-12-18 Western Digital Technologies, Inc. Implementing enhanced magnetic memory cell
US9520444B1 (en) 2015-08-25 2016-12-13 Western Digital Technologies, Inc. Implementing magnetic memory pillar design
US9601193B1 (en) * 2015-09-14 2017-03-21 Intel Corporation Cross point memory control
US9978810B2 (en) * 2015-11-04 2018-05-22 Micron Technology, Inc. Three-dimensional memory apparatuses and methods of use
US10134470B2 (en) 2015-11-04 2018-11-20 Micron Technology, Inc. Apparatuses and methods including memory and operation of same
US10840300B2 (en) 2015-11-24 2020-11-17 Fu-Chang Hsu 3D vertical memory array cell structures with individual selectors and processes
US10483324B2 (en) 2015-11-24 2019-11-19 Fu-Chang Hsu 3D vertical memory array cell structures and processes
JP6515046B2 (ja) 2016-03-10 2019-05-15 東芝メモリ株式会社 半導体記憶装置
JP2017168598A (ja) * 2016-03-15 2017-09-21 東芝メモリ株式会社 半導体記憶装置及びその製造方法
US11017838B2 (en) * 2016-08-04 2021-05-25 Samsung Electronics Co., Ltd. Nonvolatile memory devices
US10446226B2 (en) 2016-08-08 2019-10-15 Micron Technology, Inc. Apparatuses including multi-level memory cells and methods of operation of same
US10096652B2 (en) 2016-09-12 2018-10-09 Toshiba Memory Corporation Semiconductor memory device
US10276555B2 (en) * 2016-10-01 2019-04-30 Samsung Electronics Co., Ltd. Method and system for providing a magnetic cell usable in spin transfer torque applications and including a switchable shunting layer
US10157670B2 (en) 2016-10-28 2018-12-18 Micron Technology, Inc. Apparatuses including memory cells and methods of operation of same
CN108257639B (zh) * 2016-12-29 2020-08-07 北京兆易创新科技股份有限公司 一种改善编程性能的方法和装置
TWI614755B (zh) * 2017-02-07 2018-02-11 群聯電子股份有限公司 解碼方法、記憶體儲存裝置及記憶體控制電路單元
US10510957B2 (en) 2017-07-26 2019-12-17 Micron Technology, Inc. Self-aligned memory decks in cross-point memory arrays
US10573362B2 (en) 2017-08-29 2020-02-25 Micron Technology, Inc. Decode circuitry coupled to a memory array
US11088206B2 (en) * 2017-10-16 2021-08-10 Sandisk Tehnologies Llc Methods of forming a phase change memory with vertical cross-point structure
CN109841628B (zh) * 2017-11-24 2021-05-28 旺宏电子股份有限公司 半导体结构及其形成方法
KR102524614B1 (ko) 2017-11-24 2023-04-24 삼성전자주식회사 반도체 메모리 소자
KR102577999B1 (ko) * 2018-05-31 2023-09-14 에스케이하이닉스 주식회사 집적 회로
KR102547947B1 (ko) * 2018-08-21 2023-06-26 삼성전자주식회사 비휘발성 메모리 장치
CN109524039B (zh) * 2018-11-21 2020-10-09 复旦大学 一种忆阻器阻态数目扩展的结构及相关方法
KR102649489B1 (ko) 2019-01-11 2024-03-21 삼성전자주식회사 가변 저항 메모리 소자
KR102634622B1 (ko) 2019-02-28 2024-02-08 에스케이하이닉스 주식회사 수직형 메모리 장치
US10910438B2 (en) * 2019-05-01 2021-02-02 Micron Technology, Inc. Memory array with graded memory stack resistances
TWI743784B (zh) * 2019-05-17 2021-10-21 美商森恩萊斯記憶體公司 形成三維水平ｎｏｒ記憶陣列之製程
US11335599B2 (en) * 2019-05-24 2022-05-17 Tokyo Electron Limited Self-aligned contacts for 3D logic and memory
JP2021044436A (ja) 2019-09-12 2021-03-18 キオクシア株式会社 半導体メモリ装置
US11508746B2 (en) 2019-10-25 2022-11-22 Micron Technology, Inc. Semiconductor device having a stack of data lines with conductive structures on both sides thereof
US11099784B2 (en) * 2019-12-17 2021-08-24 Sandisk Technologies Llc Crosspoint memory architecture for high bandwidth operation with small page buffer
US11605588B2 (en) 2019-12-20 2023-03-14 Micron Technology, Inc. Memory device including data lines on multiple device levels
JP6908738B1 (ja) 2020-01-06 2021-07-28 ウィンボンド エレクトロニクス コーポレーション 抵抗変化型記憶装置
US11145337B1 (en) 2020-04-13 2021-10-12 Nantero, Inc. Sense amplifiers
WO2021212446A1 (en) * 2020-04-24 2021-10-28 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices with drain-select-gate cut structures and methods for forming the same
KR20220005866A (ko) * 2020-07-07 2022-01-14 에스케이하이닉스 주식회사 반도체 장치
JP2022035525A (ja) * 2020-08-21 2022-03-04 キオクシア株式会社 半導体記憶装置の動作条件の調整方法
CN114171083A (zh) 2020-11-03 2022-03-11 台湾积体电路制造股份有限公司 存储器器件
CN112420720B (zh) * 2020-11-13 2024-02-09 武汉新芯集成电路制造有限公司 半导体器件
KR20220085622A (ko) * 2020-12-15 2022-06-22 삼성전자주식회사 반도체 메모리 소자
US11588105B2 (en) 2021-03-11 2023-02-21 International Business Machines Corporation Phase-change memory device with reduced programming voltage
KR20220168884A (ko) 2021-06-17 2022-12-26 삼성전자주식회사 반도체 메모리 소자
CN113689893A (zh) * 2021-08-26 2021-11-23 北京磐芯微电子科技有限公司 闪存阵列
CN118044350A (zh) * 2021-12-10 2024-05-14 铠侠股份有限公司 存储器件
US20230260581A1 (en) * 2022-02-15 2023-08-17 Micron Technology, Inc. Techniques for operating a vertical memory architecture

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5640343A (en) * 1996-03-18 1997-06-17 International Business Machines Corporation Magnetic memory array using magnetic tunnel junction devices in the memory cells
US6133126A (en) * 1997-09-18 2000-10-17 Siemens Aktiengesellschaft Method for fabricating a dopant region
US20040108528A1 (en) * 2001-06-28 2004-06-10 Sharp Laboratories Of America, Inc. Cross-point resistor memory array and method of fabrication
US20050045919A1 (en) * 2003-08-27 2005-03-03 Nec Corporation Semiconductor device
US6921932B1 (en) * 2002-05-20 2005-07-26 Lovoltech, Inc. JFET and MESFET structures for low voltage, high current and high frequency applications
US20070170543A1 (en) * 2006-01-26 2007-07-26 International Business Machines Corporation Methods and semiconductor structures for latch-up suppression using a conductive region
US20090261386A1 (en) * 2008-04-21 2009-10-22 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device and method of arranging wirings in the semiconductor integrated circuit device
US20100226195A1 (en) * 2009-03-03 2010-09-09 Macronix International Co., Ltd. Integrated circuit self aligned 3d memory array and manufacturing method

Family Cites Families (77)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3448302A (en) 1966-06-16 1969-06-03 Itt Operating circuit for phase change memory devices
US3638204A (en) * 1969-12-19 1972-01-25 Ibm Semiconductive cell for a storage having a plurality of simultaneously accessible locations
US4583201A (en) 1983-09-08 1986-04-15 International Business Machines Corporation Resistor personalized memory device using a resistive gate fet
US4805142A (en) 1986-07-01 1989-02-14 International Business Machines Corporation Multiple ROM data state, read/write memory cell
US5172338B1 (en) 1989-04-13 1997-07-08 Sandisk Corp Multi-state eeprom read and write circuits and techniques
JP3210355B2 (ja) * 1991-03-04 2001-09-17 株式会社東芝 不揮発性半導体記憶装置
US6222762B1 (en) 1992-01-14 2001-04-24 Sandisk Corporation Multi-state memory
US5555204A (en) 1993-06-29 1996-09-10 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device
KR0169267B1 (ko) 1993-09-21 1999-02-01 사토 후미오 불휘발성 반도체 기억장치
US5903495A (en) 1996-03-18 1999-05-11 Kabushiki Kaisha Toshiba Semiconductor device and memory system
US5737260A (en) 1996-03-27 1998-04-07 Sharp Kabushiki Kaisha Dual mode ferroelectric memory reference scheme
US5835396A (en) 1996-10-17 1998-11-10 Zhang; Guobiao Three-dimensional read-only memory
US5894437A (en) 1998-01-23 1999-04-13 Hyundai Elecronics America, Inc. Concurrent read/write architecture for a flash memory
KR100303056B1 (ko) 1998-11-07 2001-11-22 윤종용 온-칩테스트회로를구비한강유전체메모리장치
US6483736B2 (en) 1998-11-16 2002-11-19 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
JP3863330B2 (ja) 1999-09-28 2006-12-27 株式会社東芝 不揮発性半導体メモリ
US6314014B1 (en) 1999-12-16 2001-11-06 Ovonyx, Inc. Programmable resistance memory arrays with reference cells
US7372065B2 (en) 2000-02-11 2008-05-13 Axon Technologies Corporation Programmable metallization cell structures including an oxide electrolyte, devices including the structure and method of forming same
JP3800925B2 (ja) 2000-05-15 2006-07-26 日本電気株式会社 磁気ランダムアクセスメモリ回路
US6538922B1 (en) 2000-09-27 2003-03-25 Sandisk Corporation Writable tracking cells
US6664639B2 (en) 2000-12-22 2003-12-16 Matrix Semiconductor, Inc. Contact and via structure and method of fabrication
JP3631463B2 (ja) 2001-12-27 2005-03-23 株式会社東芝 不揮発性半導体記憶装置
US6522580B2 (en) 2001-06-27 2003-02-18 Sandisk Corporation Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states
US6825058B2 (en) 2001-06-28 2004-11-30 Sharp Laboratories Of America, Inc. Methods of fabricating trench isolated cross-point memory array
US6456528B1 (en) 2001-09-17 2002-09-24 Sandisk Corporation Selective operation of a multi-state non-volatile memory system in a binary mode
US6925007B2 (en) 2001-10-31 2005-08-02 Sandisk Corporation Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
US6678192B2 (en) 2001-11-02 2004-01-13 Sandisk Corporation Error management for writable tracking storage units
US6807086B2 (en) 2001-11-30 2004-10-19 Kabushiki Kaisha Toshiba Magnetic random access memory
US6771536B2 (en) 2002-02-27 2004-08-03 Sandisk Corporation Operating techniques for reducing program and read disturbs of a non-volatile memory
US7042749B2 (en) * 2002-05-16 2006-05-09 Micron Technology, Inc. Stacked 1T-nmemory cell structure
WO2003098636A2 (en) 2002-05-16 2003-11-27 Micron Technology, Inc. STACKED 1T-nMEMORY CELL STRUCTURE
US7067862B2 (en) 2002-08-02 2006-06-27 Unity Semiconductor Corporation Conductive memory device with conductive oxide electrodes
US6870755B2 (en) 2002-08-02 2005-03-22 Unity Semiconductor Corporation Re-writable memory with non-linear memory element
US6882553B2 (en) 2002-08-08 2005-04-19 Micron Technology Inc. Stacked columnar resistive memory structure and its method of formation and operation
US6781877B2 (en) 2002-09-06 2004-08-24 Sandisk Corporation Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells
US7324393B2 (en) 2002-09-24 2008-01-29 Sandisk Corporation Method for compensated sensing in non-volatile memory
US6839263B2 (en) 2003-02-05 2005-01-04 Hewlett-Packard Development Company, L.P. Memory array with continuous current path through multiple lines
US7233024B2 (en) 2003-03-31 2007-06-19 Sandisk 3D Llc Three-dimensional memory device incorporating segmented bit line memory array
JP4113493B2 (ja) 2003-06-12 2008-07-09 シャープ株式会社 不揮発性半導体記憶装置及びその制御方法
US7237074B2 (en) 2003-06-13 2007-06-26 Sandisk Corporation Tracking cells for a memory system
US7221588B2 (en) 2003-12-05 2007-05-22 Sandisk 3D Llc Memory array incorporating memory cells arranged in NAND strings
US7023739B2 (en) 2003-12-05 2006-04-04 Matrix Semiconductor, Inc. NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same
US20050128807A1 (en) 2003-12-05 2005-06-16 En-Hsing Chen Nand memory array incorporating multiple series selection devices and method for operation of same
US7075817B2 (en) 2004-07-20 2006-07-11 Unity Semiconductor Corporation Two terminal memory array having reference cells
US7177191B2 (en) 2004-12-30 2007-02-13 Sandisk 3D Llc Integrated circuit including memory array incorporating multiple types of NAND string structures
US7877539B2 (en) 2005-02-16 2011-01-25 Sandisk Corporation Direct data file storage in flash memories
US7812404B2 (en) 2005-05-09 2010-10-12 Sandisk 3D Llc Nonvolatile memory cell comprising a diode and a resistance-switching material
JP4728726B2 (ja) 2005-07-25 2011-07-20 株式会社東芝 半導体記憶装置
KR100745602B1 (ko) 2005-12-09 2007-08-02 삼성전자주식회사 상 변화 메모리 장치 및 그것의 메모리 셀 어레이
US20070132049A1 (en) 2005-12-12 2007-06-14 Stipe Barry C Unipolar resistance random access memory (RRAM) device and vertically stacked architecture
JP5016832B2 (ja) 2006-03-27 2012-09-05 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
US7646664B2 (en) 2006-10-09 2010-01-12 Samsung Electronics Co., Ltd. Semiconductor device with three-dimensional array structure
KR100881292B1 (ko) 2007-01-23 2009-02-04 삼성전자주식회사 3차원 적층구조를 가지는 저항성 반도체 메모리 장치 및그의 제어방법
JP5091491B2 (ja) 2007-01-23 2012-12-05 株式会社東芝 不揮発性半導体記憶装置
US7456460B2 (en) 2007-01-29 2008-11-25 International Business Machines Corporation Phase change memory element and method of making the same
US7382647B1 (en) 2007-02-27 2008-06-03 International Business Machines Corporation Rectifying element for a crosspoint based memory array architecture
JP4157582B1 (ja) 2007-03-26 2008-10-01 シャープ株式会社 半導体記憶装置
US7667999B2 (en) 2007-03-27 2010-02-23 Sandisk 3D Llc Method to program a memory cell comprising a carbon nanotube fabric and a steering element
JP2008277543A (ja) 2007-04-27 2008-11-13 Toshiba Corp 不揮発性半導体記憶装置
KR100890641B1 (ko) 2007-05-01 2009-03-27 삼성전자주식회사 저항체를 이용한 비휘발성 메모리 장치
JP4280302B2 (ja) * 2007-06-22 2009-06-17 パナソニック株式会社 抵抗変化型不揮発性記憶装置
US7902537B2 (en) 2007-06-29 2011-03-08 Sandisk 3D Llc Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
US7824956B2 (en) 2007-06-29 2010-11-02 Sandisk 3D Llc Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
JP5060191B2 (ja) 2007-07-18 2012-10-31 株式会社東芝 抵抗変化メモリ装置のデータ書き込み方法
US7755935B2 (en) 2007-07-26 2010-07-13 International Business Machines Corporation Block erase for phase change memory
JP2009004725A (ja) 2007-09-25 2009-01-08 Panasonic Corp 抵抗変化型不揮発性記憶装置
US7846782B2 (en) 2007-09-28 2010-12-07 Sandisk 3D Llc Diode array and method of making thereof
JP2009117006A (ja) * 2007-11-09 2009-05-28 Toshiba Corp 抵抗変化メモリ装置
JP4468433B2 (ja) * 2007-11-30 2010-05-26 株式会社東芝 不揮発性半導体記憶装置
JP2009193627A (ja) * 2008-02-13 2009-08-27 Toshiba Corp 半導体記憶装置
US7830701B2 (en) 2008-09-19 2010-11-09 Unity Semiconductor Corporation Contemporaneous margin verification and memory access for memory cells in cross point memory arrays
US8351236B2 (en) 2009-04-08 2013-01-08 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture
US8199576B2 (en) 2009-04-08 2012-06-12 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a double-global-bit-line architecture
US7983065B2 (en) 2009-04-08 2011-07-19 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines
KR101567024B1 (ko) * 2009-05-15 2015-11-09 삼성전자주식회사 반도체 기억 소자
US8547720B2 (en) 2010-06-08 2013-10-01 Sandisk 3D Llc Non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines
US8526237B2 (en) 2010-06-08 2013-09-03 Sandisk 3D Llc Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereof

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5640343A (en) * 1996-03-18 1997-06-17 International Business Machines Corporation Magnetic memory array using magnetic tunnel junction devices in the memory cells
US6133126A (en) * 1997-09-18 2000-10-17 Siemens Aktiengesellschaft Method for fabricating a dopant region
US20040108528A1 (en) * 2001-06-28 2004-06-10 Sharp Laboratories Of America, Inc. Cross-point resistor memory array and method of fabrication
US6921932B1 (en) * 2002-05-20 2005-07-26 Lovoltech, Inc. JFET and MESFET structures for low voltage, high current and high frequency applications
US20050045919A1 (en) * 2003-08-27 2005-03-03 Nec Corporation Semiconductor device
US20070170543A1 (en) * 2006-01-26 2007-07-26 International Business Machines Corporation Methods and semiconductor structures for latch-up suppression using a conductive region
US20090261386A1 (en) * 2008-04-21 2009-10-22 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device and method of arranging wirings in the semiconductor integrated circuit device
US20100226195A1 (en) * 2009-03-03 2010-09-09 Macronix International Co., Ltd. Integrated circuit self aligned 3d memory array and manufacturing method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Andreasson et al. "Origin of oxygen vacancies in resistive switching memory devices" 2009. Journal of Phyics: Conference Series. Volume 190. Number 1. *

Cited By (185)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8415694B2 (en) * 2000-09-12 2013-04-09 Philips Lumileds Lighting Company Llc Light emitting devices with improved light extraction efficiency
US20100148151A1 (en) * 2000-09-12 2010-06-17 Philips Lumileds Lighting Company, Llc Light emitting devices with improved light extraction efficiency
US8628985B2 (en) 2000-09-12 2014-01-14 Philips Lumileds Lighting Company Llc Light emitting devices with improved light extraction efficiency
US10312422B2 (en) 2000-09-12 2019-06-04 Lumileds Llc Light emitting devices with optical elements and bonding layers
US9583683B2 (en) 2000-09-12 2017-02-28 Lumileds Llc Light emitting devices with optical elements and bonding layers
US8664120B2 (en) 2007-06-01 2014-03-04 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method
US8343874B2 (en) * 2007-06-01 2013-01-01 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method
US20080299773A1 (en) * 2007-06-01 2008-12-04 Shinya Watanabe Semiconductor device manufacturing method
US9601343B2 (en) 2007-06-01 2017-03-21 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method
US9142419B2 (en) 2007-06-01 2015-09-22 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method
US8351236B2 (en) 2009-04-08 2013-01-08 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture
US8780605B2 (en) 2009-04-08 2014-07-15 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture
US9190134B2 (en) 2009-04-08 2015-11-17 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture
US9721653B2 (en) 2009-04-08 2017-08-01 Sandisk Technologies Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture
US8199576B2 (en) 2009-04-08 2012-06-12 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a double-global-bit-line architecture
US9466790B2 (en) 2009-04-08 2016-10-11 Sandisk Technologies Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines
US8547720B2 (en) 2010-06-08 2013-10-01 Sandisk 3D Llc Non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines
US8526237B2 (en) 2010-06-08 2013-09-03 Sandisk 3D Llc Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereof
US8824191B2 (en) 2010-06-08 2014-09-02 Sandisk 3D Llc Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereof
US9245629B2 (en) 2010-06-08 2016-01-26 Sandisk 3D Llc Method for non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines
US9224496B2 (en) 2010-08-11 2015-12-29 Shine C. Chung Circuit and system of aggregated area anti-fuse in CMOS processes
US8644049B2 (en) 2010-08-20 2014-02-04 Shine C. Chung Circuit and system of using polysilicon diode as program selector for one-time programmable devices
US10127992B2 (en) 2010-08-20 2018-11-13 Attopsemi Technology Co., Ltd. Method and structure for reliable electrical fuse programming
US9385162B2 (en) 2010-08-20 2016-07-05 Shine C. Chung Programmably reversible resistive device cells using CMOS logic processes
US8649203B2 (en) 2010-08-20 2014-02-11 Shine C. Chung Reversible resistive memory using polysilicon diodes as program selectors
US9431127B2 (en) 2010-08-20 2016-08-30 Shine C. Chung Circuit and system of using junction diode as program selector for metal fuses for one-time programmable devices
US10923204B2 (en) 2010-08-20 2021-02-16 Attopsemi Technology Co., Ltd Fully testible OTP memory
US10916317B2 (en) 2010-08-20 2021-02-09 Attopsemi Technology Co., Ltd Programmable resistance memory on thin film transistor technology
US9349773B2 (en) 2010-08-20 2016-05-24 Shine C. Chung Memory devices using a plurality of diodes as program selectors for memory cells
US9460807B2 (en) 2010-08-20 2016-10-04 Shine C. Chung One-time programmable memory devices using FinFET technology
US8760904B2 (en) 2010-08-20 2014-06-24 Shine C. Chung One-Time Programmable memories using junction diodes as program selectors
US8760916B2 (en) * 2010-08-20 2014-06-24 Shine C. Chung Circuit and system of using at least one junction diode as program selector for memories
US20120044758A1 (en) * 2010-08-20 2012-02-23 Chung Shine C Circuit and system of using at least one junction diode as program selector for memories
US9478306B2 (en) 2010-08-20 2016-10-25 Attopsemi Technology Co., Ltd. Circuit and system of using junction diode as program selector for one-time programmable devices with heat sink
US8804398B2 (en) 2010-08-20 2014-08-12 Shine C. Chung Reversible resistive memory using diodes formed in CMOS processes as program selectors
US8817563B2 (en) 2010-08-20 2014-08-26 Shine C. Chung Sensing circuit for programmable resistive device using diode as program selector
US8576602B2 (en) 2010-08-20 2013-11-05 Shine C. Chung One-time programmable memories using polysilicon diodes as program selectors
US8830720B2 (en) 2010-08-20 2014-09-09 Shine C. Chung Circuit and system of using junction diode as program selector and MOS as read selector for one-time programmable devices
US9305973B2 (en) 2010-08-20 2016-04-05 Shine C. Chung One-time programmable memories using polysilicon diodes as program selectors
US8854859B2 (en) 2010-08-20 2014-10-07 Shine C. Chung Programmably reversible resistive device cells using CMOS logic processes
US8570800B2 (en) 2010-08-20 2013-10-29 Shine C. Chung Memory using a plurality of diodes as program selectors with at least one being a polysilicon diode
US10249379B2 (en) 2010-08-20 2019-04-02 Attopsemi Technology Co., Ltd One-time programmable devices having program selector for electrical fuses with extended area
US8873268B2 (en) 2010-08-20 2014-10-28 Shine C. Chung Circuit and system of using junction diode as program selector for one-time programmable devices
US9251893B2 (en) 2010-08-20 2016-02-02 Shine C. Chung Multiple-bit programmable resistive memory using diode as program selector
US9496033B2 (en) 2010-08-20 2016-11-15 Attopsemi Technology Co., Ltd Method and system of programmable resistive devices with read capability using a low supply voltage
US9236141B2 (en) 2010-08-20 2016-01-12 Shine C. Chung Circuit and system of using junction diode of MOS as program selector for programmable resistive devices
US8559208B2 (en) 2010-08-20 2013-10-15 Shine C. Chung Programmably reversible resistive device cells using polysilicon diodes
US10229746B2 (en) 2010-08-20 2019-03-12 Attopsemi Technology Co., Ltd OTP memory with high data security
US8913415B2 (en) 2010-08-20 2014-12-16 Shine C. Chung Circuit and system for using junction diode as program selector for one-time programmable devices
US8482972B2 (en) 2010-08-20 2013-07-09 Shine C. Chung Memory devices using a plurality of diodes as program selectors with at least one being a polysilicon diode
US8488364B2 (en) 2010-08-20 2013-07-16 Shine C. Chung Circuit and system of using a polysilicon diode as program selector for resistive devices in CMOS logic processes
US8929122B2 (en) 2010-08-20 2015-01-06 Shine C. Chung Circuit and system of using a junction diode as program selector for resistive devices
US8488359B2 (en) 2010-08-20 2013-07-16 Shine C. Chung Circuit and system of using junction diode as program selector for one-time programmable devices
US20170133101A9 (en) * 2010-08-20 2017-05-11 Shine C. Chung Method and structure for reliable electrical fuse programming
US9711237B2 (en) * 2010-08-20 2017-07-18 Attopsemi Technology Co., Ltd. Method and structure for reliable electrical fuse programming
US9019742B2 (en) 2010-08-20 2015-04-28 Shine C. Chung Multiple-state one-time programmable (OTP) memory to function as multi-time programmable (MTP) memory
US8514606B2 (en) 2010-08-20 2013-08-20 Shine C. Chung Circuit and system of using junction diode as program selector for one-time programmable devices
US9025357B2 (en) 2010-08-20 2015-05-05 Shine C. Chung Programmable resistive memory unit with data and reference cells
US9042153B2 (en) 2010-08-20 2015-05-26 Shine C. Chung Programmable resistive memory unit with multiple cells to improve yield and reliability
US9754679B2 (en) 2010-08-20 2017-09-05 Attopsemi Technology Co., Ltd One-time programmable memory devices using FinFET technology
US9070437B2 (en) 2010-08-20 2015-06-30 Shine C. Chung Circuit and system of using junction diode as program selector for one-time programmable devices with heat sink
US9767915B2 (en) 2010-08-20 2017-09-19 Attopsemi Technology Co., Ltd One-time programmable device with integrated heat sink
US9076513B2 (en) 2010-11-03 2015-07-07 Shine C. Chung Low-pin-count non-volatile memory interface with soft programming capability
US9343176B2 (en) 2010-11-03 2016-05-17 Shine C. Chung Low-pin-count non-volatile memory interface with soft programming capability
US9293220B2 (en) 2010-11-03 2016-03-22 Shine C. Chung Low-pin-count non-volatile memory interface for 3D IC
US9019791B2 (en) 2010-11-03 2015-04-28 Shine C. Chung Low-pin-count non-volatile memory interface for 3D IC
US9281038B2 (en) 2010-11-03 2016-03-08 Shine C. Chung Low-pin-count non-volatile memory interface
US8988965B2 (en) 2010-11-03 2015-03-24 Shine C. Chung Low-pin-count non-volatile memory interface
US8923085B2 (en) 2010-11-03 2014-12-30 Shine C. Chung Low-pin-count non-volatile memory embedded in a integrated circuit without any additional pins for access
US9496265B2 (en) 2010-12-08 2016-11-15 Attopsemi Technology Co., Ltd Circuit and system of a high density anti-fuse
US20120147644A1 (en) * 2010-12-14 2012-06-14 Scheuerlein Roy E Continuous mesh three dimensional non-volatile storage with vertical select devices
US8618614B2 (en) * 2010-12-14 2013-12-31 Sandisk 3D Llc Continuous mesh three dimensional non-volatile storage with vertical select devices
US8885389B2 (en) 2010-12-14 2014-11-11 Sandisk 3D Llc Continuous mesh three dimensional non-volatile storage with vertical select devices
US8883569B2 (en) 2010-12-14 2014-11-11 Sandisk 3D Llc Continuous mesh three dimensional non-volatile storage with vertical select devices
US10192615B2 (en) 2011-02-14 2019-01-29 Attopsemi Technology Co., Ltd One-time programmable devices having a semiconductor fin structure with a divided active region
US9548109B2 (en) 2011-02-14 2017-01-17 Attopsemi Technology Co., Ltd Circuit and system of using FinFET for building programmable resistive devices
US11011577B2 (en) 2011-02-14 2021-05-18 Attopsemi Technology Co., Ltd One-time programmable memory using gate-all-around structures
US9881970B2 (en) 2011-02-14 2018-01-30 Attopsemi Technology Co. LTD. Programmable resistive devices using Finfet structures for selectors
US10586832B2 (en) 2011-02-14 2020-03-10 Attopsemi Technology Co., Ltd One-time programmable devices using gate-all-around structures
US8848423B2 (en) 2011-02-14 2014-09-30 Shine C. Chung Circuit and system of using FinFET for building programmable resistive devices
US8607019B2 (en) 2011-02-15 2013-12-10 Shine C. Chung Circuit and method of a memory compiler based on subtractive approach
US11087841B2 (en) 2011-06-10 2021-08-10 Unity Semiconductor Corporation Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
US9691480B2 (en) 2011-06-10 2017-06-27 Unity Semiconductor Corporation Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
US9870823B2 (en) 2011-06-10 2018-01-16 Unity Semiconductor Corporation Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
US10566056B2 (en) 2011-06-10 2020-02-18 Unity Semiconductor Corporation Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
US10229739B2 (en) 2011-06-10 2019-03-12 Unity Semiconductor Corporation Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
US20120314468A1 (en) * 2011-06-10 2012-12-13 Unity Semiconductor Corporation Memory array with local bitlines and local-to-global bitline pass gates and gain stages
US8891276B2 (en) * 2011-06-10 2014-11-18 Unity Semiconductor Corporation Memory array with local bitlines and local-to-global bitline pass gates and gain stages
US9390796B2 (en) 2011-06-10 2016-07-12 Unity Semiconductor Corporation Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
US20200258940A1 (en) * 2011-08-15 2020-08-13 Unity Semiconductor Corporation Vertical cross-point memory arrays
US8912576B2 (en) 2011-11-15 2014-12-16 Shine C. Chung Structures and techniques for using semiconductor body to construct bipolar junction transistors
US9136261B2 (en) 2011-11-15 2015-09-15 Shine C. Chung Structures and techniques for using mesh-structure diodes for electro-static discharge (ESD) protection
US9324849B2 (en) 2011-11-15 2016-04-26 Shine C. Chung Structures and techniques for using semiconductor body to construct SCR, DIAC, or TRIAC
US9576660B2 (en) 2011-12-30 2017-02-21 Sandisk Technologies Llc Low forming voltage non-volatile storage device
US9269425B2 (en) 2011-12-30 2016-02-23 Sandisk 3D Llc Low forming voltage non-volatile storage device
JP2013153127A (ja) * 2012-01-24 2013-08-08 Toshiba Corp 記憶装置
US8917533B2 (en) 2012-02-06 2014-12-23 Shine C. Chung Circuit and system for testing a one-time programmable (OTP) memory
US9007804B2 (en) 2012-02-06 2015-04-14 Shine C. Chung Circuit and system of protective mechanisms for programmable resistive memories
US8861249B2 (en) 2012-02-06 2014-10-14 Shine C. Chung Circuit and system of a low density one-time programmable memory
US8913449B2 (en) 2012-03-11 2014-12-16 Shine C. Chung System and method of in-system repairs or configurations for memories
CN103474570A (zh) * 2012-06-06 2013-12-25 复旦大学 集成于集成电路的后端结构的电阻型存储器及其制备方法
JP2014049745A (ja) * 2012-08-31 2014-03-17 Toshiba Corp 半導体記憶装置、及びその製造方法
US9252358B2 (en) 2012-08-31 2016-02-02 Kabushiki Kaisha Toshiba Semiconductor memory device and method of manufacturing the same
US9076526B2 (en) 2012-09-10 2015-07-07 Shine C. Chung OTP memories functioning as an MTP memory
CN103682088A (zh) * 2012-09-10 2014-03-26 中国科学院微电子研究所 一种制造交叉点器件的方法
CN103681727A (zh) * 2012-09-17 2014-03-26 复旦大学 双层结构电阻型存储器及其制备方法
US20140085961A1 (en) * 2012-09-26 2014-03-27 Kohji Kanamori Semiconductor memory device
US9183893B2 (en) * 2012-09-26 2015-11-10 Samsung Electronics Co., Ltd. Semiconductor memory device
US9183897B2 (en) 2012-09-30 2015-11-10 Shine C. Chung Circuits and methods of a self-timed high speed SRAM
US9324447B2 (en) 2012-11-20 2016-04-26 Shine C. Chung Circuit and system for concurrently programming multiple bits of OTP memory devices
US10586593B2 (en) 2012-12-07 2020-03-10 Attopsemi Technology Co., Ltd Programmable resistive device and memory using diode as selector
US9818478B2 (en) 2012-12-07 2017-11-14 Attopsemi Technology Co., Ltd Programmable resistive device and memory using diode as selector
CN103904080A (zh) * 2012-12-28 2014-07-02 旺宏电子股份有限公司 三维存储器结构及其操作方法
US9202694B2 (en) 2013-03-04 2015-12-01 Sandisk 3D Llc Vertical bit line non-volatile memory systems and methods of fabrication
US9558949B2 (en) 2013-03-04 2017-01-31 Sandisk Technologies Llc Vertical bit line non-volatile memory systems and methods of fabrication
US9853090B2 (en) 2013-03-04 2017-12-26 Sandisk Technologies Llc Vertical bit line non-volatile memory systems and methods of fabrication
US9165933B2 (en) 2013-03-07 2015-10-20 Sandisk 3D Llc Vertical bit line TFT decoder for high voltage operation
US20140313813A1 (en) * 2013-04-23 2014-10-23 Kabushiki Kaisha Toshiba Semiconductor memory device and operation method thereof
US9019748B2 (en) * 2013-04-23 2015-04-28 Kabushiki Kaisha Toshiba Semiconductor memory device and operation method thereof
US20150145139A1 (en) * 2013-11-22 2015-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Word line coupling prevention using 3d integrated circuit
US9196582B2 (en) * 2013-11-22 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Word line coupling prevention using 3D integrated circuit
US9362338B2 (en) 2014-03-03 2016-06-07 Sandisk Technologies Inc. Vertical thin film transistors in non-volatile storage systems
US9818798B2 (en) 2014-03-03 2017-11-14 Sandisk Technologies Llc Vertical thin film transistors in non-volatile storage systems
US9379246B2 (en) 2014-03-05 2016-06-28 Sandisk Technologies Inc. Vertical thin film transistor selection devices and methods of fabrication
US9711650B2 (en) 2014-03-05 2017-07-18 Sandisk Technologies Llc Vertical thin film transistor selection devices and methods of fabrication
US10109333B2 (en) 2014-03-11 2018-10-23 Everspin Technologies, Inc. Nonvolatile logic and security circuits
US9336872B2 (en) * 2014-03-11 2016-05-10 Everspin Technologies, Inc. Nonvolatile logic and security circuits
US9754652B2 (en) 2014-03-11 2017-09-05 Everspin Technologies, Inc. Nonvolatile logic and security circuits
US20150262662A1 (en) * 2014-03-11 2015-09-17 Everspin Technologies, Inc. Nonvolatile logic and security circuits
US9922709B2 (en) * 2014-05-20 2018-03-20 Sandisk Technologies Llc Memory hole bit line structures
US20160020255A1 (en) * 2014-05-20 2016-01-21 Sandisk 3D Llc Memory hole bit line structures
US9543005B2 (en) 2014-06-04 2017-01-10 Intel Corporation Multistage memory cell read
US9165647B1 (en) * 2014-06-04 2015-10-20 Intel Corporation Multistage memory cell read
US9412473B2 (en) 2014-06-16 2016-08-09 Shine C. Chung System and method of a novel redundancy scheme for OTP
US10090461B2 (en) * 2014-06-26 2018-10-02 Intel Corporation Oxide-based three-terminal resistive switching logic devices
US20170148982A1 (en) * 2014-06-26 2017-05-25 Intel Corporation Oxide-based three-terminal resistive switching logic devices
US20170047339A1 (en) * 2014-09-24 2017-02-16 Sandisk Technologies Llc Process for Word Line Connections in 3D Memory
US9825048B2 (en) * 2014-09-24 2017-11-21 Sandisk Technologies Llc Process for word line connections in 3D memory
US9691498B2 (en) * 2015-03-19 2017-06-27 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
US20160276018A1 (en) * 2015-03-19 2016-09-22 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
US9824768B2 (en) 2015-03-22 2017-11-21 Attopsemi Technology Co., Ltd Integrated OTP memory for providing MTP memory
US9450023B1 (en) 2015-04-08 2016-09-20 Sandisk Technologies Llc Vertical bit line non-volatile memory with recessed word lines
US10490274B2 (en) * 2016-02-15 2019-11-26 SK Hynix Inc. Non-volatile semiconductor memory device with improved pre-charging for high speed operation
US20180366190A1 (en) * 2016-02-15 2018-12-20 SK Hynix Inc. Electronic device
US10535413B2 (en) 2017-04-14 2020-01-14 Attopsemi Technology Co., Ltd Low power read operation for programmable resistive memories
US11062786B2 (en) 2017-04-14 2021-07-13 Attopsemi Technology Co., Ltd One-time programmable memories with low power read operation and novel sensing scheme
US11615859B2 (en) 2017-04-14 2023-03-28 Attopsemi Technology Co., Ltd One-time programmable memories with ultra-low power read operation and novel sensing scheme
US10726914B2 (en) 2017-04-14 2020-07-28 Attopsemi Technology Co. Ltd Programmable resistive memories with low power read operation and novel sensing scheme
US10381304B2 (en) * 2017-07-31 2019-08-13 Globalfoundries Inc. Interconnect structure
US20190035731A1 (en) * 2017-07-31 2019-01-31 Globalfoundries Inc. Interconnect structure
CN111052376A (zh) * 2017-08-29 2020-04-21 美光科技公司 三维存储器阵列
WO2019069048A1 (en) * 2017-10-06 2019-04-11 Arm Ltd RECONFIGURABLE CIRCUIT ARCHITECTURE
GB2567215B (en) * 2017-10-06 2020-04-01 Advanced Risc Mach Ltd Reconfigurable circuit architecture
US11061852B2 (en) * 2017-10-06 2021-07-13 Arm Limited Reconfigurable circuit architecture
US10777566B2 (en) * 2017-11-10 2020-09-15 Macronix International Co., Ltd. 3D array arranged for memory and in-memory sum-of-products operations
US20190148393A1 (en) * 2017-11-10 2019-05-16 Macronix International Co., Ltd. 3d array arranged for memory and in-memory sum-of-products operations
US10770160B2 (en) 2017-11-30 2020-09-08 Attopsemi Technology Co., Ltd Programmable resistive memory formed by bit slices from a standard cell library
EP3506360A1 (en) * 2017-12-29 2019-07-03 IMEC vzw Three-dimensional semiconductor memory device and method for manufacturing thereof
US10825868B2 (en) 2017-12-29 2020-11-03 Imec Vzw Three-dimensional semiconductor device and method of fabricating same
US10719296B2 (en) 2018-01-17 2020-07-21 Macronix International Co., Ltd. Sum-of-products accelerator array
US10957392B2 (en) 2018-01-17 2021-03-23 Macronix International Co., Ltd. 2D and 3D sum-of-products array for neuromorphic computing system
CN108538879A (zh) * 2018-03-09 2018-09-14 上海新储集成电路有限公司 一种三维存储器的存储单元结构
US11706934B2 (en) 2018-04-24 2023-07-18 Micron Technology, Inc. Cross-point memory array and related fabrication techniques
US12087758B2 (en) 2018-04-24 2024-09-10 Micron Technology, Inc. Buried lines and related fabrication techniques
US12035543B2 (en) 2018-04-24 2024-07-09 Micron Technology, Inc. Cross-point memory array with access lines
WO2019209441A1 (en) 2018-04-24 2019-10-31 Micron Technology, Inc. Cross-point memory array and related fabrication techniques
EP3785266A4 (en) * 2018-04-24 2022-01-19 Micron Technology, Inc. CROSS-POINT MEMORY NETWORK AND ASSOCIATED FABRICATION TECHNIQUES
US11138497B2 (en) 2018-07-17 2021-10-05 Macronix International Co., Ltd In-memory computing devices for neural networks
US11636325B2 (en) 2018-10-24 2023-04-25 Macronix International Co., Ltd. In-memory data pooling for machine learning
US11562229B2 (en) 2018-11-30 2023-01-24 Macronix International Co., Ltd. Convolution accelerator using in-memory computation
US11934480B2 (en) 2018-12-18 2024-03-19 Macronix International Co., Ltd. NAND block architecture for in-memory multiply-and-accumulate operations
US11119674B2 (en) 2019-02-19 2021-09-14 Macronix International Co., Ltd. Memory devices and methods for operating the same
US10783963B1 (en) 2019-03-08 2020-09-22 Macronix International Co., Ltd. In-memory computation device with inter-page and intra-page data circuits
US11132176B2 (en) 2019-03-20 2021-09-28 Macronix International Co., Ltd. Non-volatile computing method in flash memory
US10910393B2 (en) 2019-04-25 2021-02-02 Macronix International Co., Ltd. 3D NOR memory having vertical source and drain structures
US11139306B2 (en) 2019-05-28 2021-10-05 Winbond Electronics Corp. Memory device and method for fabricating the same
WO2021236166A1 (en) * 2020-05-18 2021-11-25 Sandisk Technologies Llc Three-dimensional memory device including ferroelectric-metal-insulator memory cells and methods of making the same
US11302716B2 (en) 2020-05-18 2022-04-12 Sandisk Technologies Llc Three-dimensional memory device including ferroelectric-metal-insulator memory cells and methods of making the same
US11282848B2 (en) 2020-05-18 2022-03-22 Sandisk Technologies Llc Three-dimensional memory device including ferroelectric-metal-insulator memory cells and methods of making the same
US11393525B2 (en) 2020-09-17 2022-07-19 Kioxia Corporation Semiconductor memory device
US11996143B2 (en) 2020-09-17 2024-05-28 Kioxia Corporation Semiconductor memory device
US11737274B2 (en) 2021-02-08 2023-08-22 Macronix International Co., Ltd. Curved channel 3D memory device
US11916011B2 (en) 2021-04-14 2024-02-27 Macronix International Co., Ltd. 3D virtual ground memory and manufacturing methods for same
US11710519B2 (en) 2021-07-06 2023-07-25 Macronix International Co., Ltd. High density memory with reference memory using grouped cells and corresponding operations
TWI834125B (zh) * 2021-07-09 2024-03-01 台灣積體電路製造股份有限公司 記憶體裝置以及其形成方法

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