TWI655684B - 從晶圓背側及前側切割晶圓 - Google Patents
從晶圓背側及前側切割晶圓 Download PDFInfo
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- TWI655684B TWI655684B TW103132296A TW103132296A TWI655684B TW I655684 B TWI655684 B TW I655684B TW 103132296 A TW103132296 A TW 103132296A TW 103132296 A TW103132296 A TW 103132296A TW I655684 B TWI655684 B TW I655684B
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Abstract
描述用於背側雷射劃線加上前側雷射劃線及電漿蝕刻切割晶圓或基板之方式。舉例而言,一種切割半導體晶圓之方法,半導體晶圓具有在該半導體晶圓之前側上的複數個積體電路及在該半導體晶圓之背側上的金屬化層,該方法涉及使用第一雷射劃線處理圖案化在背側上的金屬化層,以在背側上提供第一複數個雷射刻劃線。該方法亦涉及在前側上形成遮罩。該方法亦涉及使用第二雷射劃線處理從前側圖案化遮罩,以提供圖案化之遮罩,該圖案化之遮罩具有第二複數個刻劃線曝露出半導體晶圓介於積體電路之間的區域,其中第二複數個刻劃線與第一複數個刻劃線對準。該方法亦涉及電漿蝕刻半導體晶圓通過第二複數個刻劃線以分割積體電路。
Description
本申請案主張申請於2013年9月19日之美國臨時申請案序號第61/879,787號之優先權之權益,該申請案之全文內容以引用之方式併入本文。
本發明之實施例涉及半導體處理之領域,且特定而言,涉及切割半導體晶圓之方法,各晶圓上具有複數個積體電路。
在半導體晶圓處理中,積體電路形成於由矽或其他半導體材料所組成的晶圓(亦稱為基板)上。一般而言,利用半導電的、導電的或絕緣的任一之各種材料層來形成積體電路。使用各種熟知的處理來摻雜、沉積及蝕刻這些材料以形成積體電路。各晶圓經處理以形成大量的、含有被稱作晶粒(dice)的積體電路的個別區域。
於積體電路形成處理之後,晶圓被「切割(diced)」以將個別晶粒彼此分離用於封裝或用於在較大電路內以未封
裝的形式使用。用於晶圓切割的兩個主要技術為劃線(scribing)及鋸切(sawing)。使用劃線,鑽石尖端(diamond tipped)劃線沿著預先形成的刻劃線(scribe lines)移動跨越晶圓表面。這些刻劃線沿著晶粒之間的空間延伸。這些空間通常被稱作「切割道(streets)」。鑽石劃線在晶圓表面沿著切割道形成淺劃痕(scratch)。當施加壓力時,例如使用滾軸(roller),使晶圓沿著刻劃線分離。晶圓中的破裂遵循晶圓基板之晶格結構。劃線可用於厚度約10密耳(千分之一吋)或更薄的晶圓。對於較厚的晶圓,鋸切為目前用於切割之較佳的方法。
使用鋸切,於每分鐘高轉數下旋轉的鑽石尖端鋸接觸晶圓表面且沿著切割道鋸切晶圓。晶圓安裝在支撐部件上,支撐部件例如跨越膜片框架而拉伸的附著膜,且鋸重複地施加至垂直切割道及水平切割道兩者。劃線或鋸切任一帶來的問題為碎片(chips)及鑿痕(gouges)可能沿著晶粒之被切斷的邊緣形成。此外,裂縫(cracks)可能從晶粒的邊緣形成且傳播到基板中而導致積體電路為無效的。碎片(chipping)和裂縫(cracking)是劃線所特別具有的問題,因為方形或矩形的晶粒僅有一邊可以沿著結晶結構之<110>方向被劃線。因此,該晶粒的另一邊的裂開導致鋸齒狀的分割線。因為碎片和裂縫,在晶圓上的晶粒之間需要額外的間隔以避免損害積體電路,舉例而言,碎片和裂縫被維持在與真正的積體電路之間具有一段距離處。由於間隔需求,沒有那麼多的晶粒可以被形成在一個標準尺寸的晶圓上,且浪費了可以另外被用作電路的晶圓可用區(wafer real estate)。鋸切的使用加劇了半導體
晶圓上之可用區的浪費。鋸之刀刃近似15微米厚。因此,為確保由鋸所引起的環繞切口的裂縫及其他損壞不會傷害積體電路,晶粒之各者之電路經常必須分離三百微米到五百微米。此外,在切割之後,各晶粒需要基本的清洗以移除由鋸切處理所導致的微粒及其他污染物。
亦使用過電漿切割,但亦可能具有限制條件。舉例而言,妨礙電漿切割實施的一個限制條件可能為成本。用於圖案化光阻的標準微影術操作可能導致實施成本過高。可能妨礙電漿切割實施的另一個限制條件在於沿著切割道切割常見金屬(例如,銅)的電漿處理可能會產生生產問題或產量限制。
本發明之實施例包含切割半導體晶圓之方法,各晶圓上具有複數個積體電路。
在一個實施例中,一種切割半導體晶圓之方法,半導體晶圓具有在該半導體晶圓之前側上的複數個積體電路及在該半導體晶圓之背側上的金屬化層,該方法涉及使用第一雷射劃線處理圖案化在背側上的金屬化層,以在背側上提供第一複數個雷射刻劃線。該方法亦涉及在前側上形成遮罩。該方法亦涉及使用第二雷射劃線處理從前側圖案化遮罩,以提供第二複數個刻劃線給圖案化之遮罩,第二複數個刻劃線曝露出半導體晶圓介於積體電路之間的區域,其中第二複數個刻劃線與第一複數個刻劃線對準。該方法亦涉及電漿蝕刻半導體晶圓通過第二複數個刻劃線,以分割積體電路。
在另一個實施例中,一種切割半導體晶圓之方法,半導體晶圓具有在該半導體晶圓之前側上的複數個積體電路及在該半導體晶圓之背側上的金屬化層,該方法涉及在半導體晶圓之前側上形成遮罩。金屬化層及半導體晶圓之背側具有第一複數個刻劃線於其中。該方法亦涉及使用雷射劃線處理從前側圖案化遮罩,以提供第二複數個刻劃線給圖案化之遮罩,第二複數個刻劃線曝露出半導體晶圓介於積體電路之間的區域。第二複數個刻劃線與第一複數個刻劃線對準。該方法亦涉及電漿蝕刻半導體晶圓通過第二複數個刻劃線,以分割積體電路。
在另一個實施例中,一種切割單晶矽基板之方法,單晶矽基板具有在單晶矽基板之前側上的複數個積體電路及在單晶矽基板之背側上的金屬化層,該方法涉及使用第一飛秒系雷射劃線處理圖案化在單晶矽基板之背側上的金屬化層,以在背側上提供第一複數個雷射刻劃線。該方法亦涉及在單晶矽基板之前側上形成水溶性遮罩。該方法亦涉及使用第二飛秒系雷射劃線處理從前側圖案化水溶性遮罩,以提供第二複數個刻劃線給圖案化之水溶性遮罩,第二複數個刻劃線曝露出單晶矽基板介於積體電路之間的區域。第二複數個刻劃線與第一複數個刻劃線對準。該方法亦涉及電漿蝕刻半導體晶圓通過第二複數個刻劃線,以分割積體電路。該方法亦涉及使用水溶液移除圖案化之水溶性遮罩。
100‧‧‧流程圖
102‧‧‧操作
104‧‧‧操作
106‧‧‧操作
108‧‧‧操作
110‧‧‧操作
112‧‧‧操作
114‧‧‧操作
116‧‧‧操作
202‧‧‧遮罩/遮罩層
204‧‧‧晶圓
206‧‧‧積體電路
207‧‧‧切割道
208‧‧‧圖案化之遮罩
210‧‧‧雷射刻劃線
212‧‧‧溝
250‧‧‧保護層或帶
252‧‧‧背側金屬化層
252’‧‧‧圖案化之背側金屬化層
254‧‧‧雷射刻劃線
256‧‧‧溝
300A‧‧‧經由奈秒處理
300B‧‧‧經由皮秒處理
300C‧‧‧經由飛秒處理
302A‧‧‧顯著損害
302B‧‧‧損害
302C‧‧‧最小至無損害
400‧‧‧佈局
402‧‧‧佈局
500‧‧‧半導體晶圓或基板
502‧‧‧半導體晶圓或基板
600‧‧‧處理工具
602‧‧‧工廠介面
604‧‧‧負載鎖定腔室
606‧‧‧群集工具
608‧‧‧電漿蝕刻腔室
610‧‧‧雷射劃線設備
612‧‧‧沉積腔室
614‧‧‧濕式/乾式站
700‧‧‧電腦系統
702‧‧‧處理器
704‧‧‧主要記憶體
706‧‧‧靜態記憶體
708‧‧‧網路介面裝置
710‧‧‧影像顯示單元
712‧‧‧字母數字輸入裝置
714‧‧‧游標控制裝置
716‧‧‧訊號產生裝置
718‧‧‧次要記憶體
720‧‧‧網路
722‧‧‧軟體
726‧‧‧處理邏輯
730‧‧‧匯流排
第1圖為根據本發明之一個實施例的流程圖,流程
圖包含用於背側雷射劃線加上前側雷射劃線及電漿蝕刻切割處理的操作。
第2A圖至第2E圖繪示根據本發明之一個實施例,呈現在背側雷射劃線加上前側雷射劃線及電漿蝕刻切割處理中的各種操作的橫截面視圖。
第3圖繪示根據本發明之一個實施例,相對於較長脈衝時間使用飛秒範圍的雷射脈衝之效應。
第4圖繪示根據本發明之一個實施例,相對於可能受限於最小寬度的習知切割,藉由使用較窄切割道所達成的半導體晶圓上的壓縮。
第5圖繪示根據本發明之一個實施例,相對於柵格對準方式,自由形式積體電路配置允許較緊密封裝且因此每晶圓更多晶粒。
第6圖繪示根據本發明之一個實施例,用於雷射劃線及電漿切割晶圓或基板的工具佈局之方塊圖。
第7圖繪示根據本發明之一個實施例示例性電腦系統之方塊圖。
描述切割半導體晶圓之方法,各晶圓上具有複數個積體電路。在以下的描述中記載了眾多具體細節,例如飛秒系雷射劃線及電漿蝕刻條件及材料體系(material regimes),用於提供本發明之實施例之徹底瞭解。對於本領域具有習知技藝者而言將為顯而易見的是,在沒有這些具體細節的情況下可實踐本發明之實施例。在其他情況下,熟知態樣例如積體
電路製造並未被詳細描述,用以非不必要地使本發明之實施例模糊。此外,應瞭解,圖式中所示的各種實施例為說明性表示且未必是按比例繪製。
涉及初始雷射劃線處理及後續電漿處理的混合式晶圓或基板切割處理可被實施用於晶粒分割(singulation)。雷射劃線處理可用以潔淨地移除遮罩層、有機介電層及無機介電層,及在晶圓之兩側上的裝置層,以及切穿介於其間的基板。額外的雷射劃線操作可用以移除背側金屬化層。切割處理之電漿蝕刻或處理部分然後可被採用來產生潔淨晶粒或晶片分割或切割。
更一般而言,一或更多個實施例是針對從晶圓或基板背側及前側以組合的方式切割晶圓或基板。具體實施例包含切割具有背側金屬化層的晶圓的方法及系統。舉例而言,對於高功率半導體裝置,晶圓承受背側金屬化層以為了有效熱逸散及其他功能目的是常見的。由於蝕刻背側金屬化層可能為耗時、昂貴或難以達成的,切割具有背側金屬化層的晶圓對於習知刀刃切割技術呈現困難且亦可能造成雷射劃線/電漿蝕刻方式困難。雷射切穿(cut-through)切割方式可將其處理好,但該方式在保持裝置側及側壁免受損害上可能具有限制條件。一或更多個實施例促使基於雷射劃線/電漿蝕刻的切割技術適用於切割具有背側金屬化層的晶圓。
更特定而言,某些晶圓或基板在晶圓或基板背側上承受金屬層及/或介電層。在一個實施例中,作為第一操作,晶圓晶粒側(IC側)附著至保護層或堆疊或帶(舉例而言,例如
在背側研磨期間經常使用的那些)上。其次,DPSS奈秒(nanosecond)或皮秒(picosecond)或飛秒(femtosecond)脈衝雷射用以劃線背側金屬化層。然後晶圓被傳送且在晶圓背側上安裝切割帶。從晶圓前側移除保護帶。遵循此方式,實行前側雷射劃線及電漿蝕刻處理以完成切割。
本文所述的實施例之一或更多個優點包含但不限於:這是一個既定的處理,各半導體晶片須被雷射標記用以在被封裝之前的登記及辨識目的。目前超過95%的晶圓在晶圓被切割之前從背側被雷射標記(在各晶粒上)。剩下5%的晶圓針對特殊情況須在切割之後被雷射標記,例如當採用在研磨之前切割(dicing before grinding;DBG)的方式時,但是在後者的情況下最大多數不需要晶圓上有背側金屬化層。在前者的情況下當在切割之前實行晶粒對晶粒雷射標記時,晶圓前側安裝在帶框上,且從背側在各晶粒上進行雷射標記。為了確保標記精確地位於各晶粒上,晶圓須預對準及繪製地圖。在標記之後,移除前側帶且將晶圓背側安裝於用於切割的切割帶上。用於標記的雷射為低成本奈秒脈衝紅外(波長約1um)雷射源或第二諧波(500~540nm)雷射源。這些雷射源與背側金屬化層極佳地耦合。
因此,一或更多個實施例涉及針對標記處理使用相同的雷射以在相同的設置中劃線且移除背側金屬化層,此舉符合現有的處理流程。用以實施背側金屬化層劃線處理的額外的投資為最小化。針對超薄晶圓例如小於50um,為了避免來自雷射背側標記及背側金屬化層劃線對於晶粒的過度熱損
害,可能需要短脈衝雷射,例如單位數(single digit)奈秒雷射、皮秒雷射或飛秒雷射。波長步進、第二諧波(舉例而言,500~540nm)雷射源將優先選用以顯著降低雷射吸收深度從於1.0um紅外處的近似1um降至於第二諧波處的近似0.1um。
因此,如以下更詳細所述,一或更多個實施例涉及從晶圓背側及前側兩者切割。作為一個實例,第1圖為根據本發明之一個實施例的流程圖100,流程圖100包含用於背側雷射劃線加上前側雷射劃線及電漿蝕刻切割處理的操作。第2A圖至第2E圖繪示對應於流程圖100之操作,呈現在背側雷射劃線加上前側雷射劃線及電漿蝕刻切割處理中的各種操作的橫截面視圖。
參照流程圖100之操作102及操作104,且對應第2A圖,晶圓測試之後保護層或帶250附著至晶圓204前側,亦即,在晶圓204具有積體電路206於晶圓204上的側上。積體電路206由切割道207所分隔,切割道207可包含與積體電路206之金屬化層及介電層相似的金屬化層及介電層。舉例而言,切割道207可由介電材料層、半導體材料層及金屬化層所組成。在一個實施例中,切割道207中之一或更多者包含與積體電路206之真實裝置相似的測試裝置。應理解,積體電路206(及切割道207)不須如圖示般的平坦。反之,可存在由於引入凸塊/支柱及其他類似特徵造成的地貌。在晶圓或基板204之背側上包含背側金屬化252層(及對應的介電層)。
參照流程圖100之操作106,且對應第2B圖,背側金屬化層252以第一雷射劃線處理來劃線,以提供具有雷射刻劃線254於其中的圖案化之背側金屬化層252’。雷射刻劃線254可於晶圓204之表面處終止或延伸進入晶圓204作為溝256。於此時亦可實行晶圓204之背側之雷射標記。
參照流程圖100之操作108及操作110,且對應第2C圖,切割帶附著至晶圓背側(舉例而言,在圖案化之金屬化層252’上)。遮罩層202形成於晶圓204前側上,亦即,在積體電路206及切割道207上或在積體電路206及切割道207的上方。遮罩層204可以塗佈及烘烤操作來形成。
參照流程圖100之操作112,且對應第2D圖,遮罩202及切割道207以第二雷射劃線處理來劃線,以提供具有雷射刻劃線210於其中的圖案化之遮罩208,及從切割道207移除材料。雷射刻劃線210可於晶圓204之表面處終止或延伸進入晶圓204作為溝212。根據本發明之一個實施例,刻劃線210與在第一雷射劃線操作期間所形成的刻劃線254對準。
參照流程圖100之操作114及操作116,且對應第2E圖,電漿蝕刻處理用以將晶圓204分割成個別IC(亦即,作為個別IC 206)。在一個實施例中,實行電漿蝕刻通過刻劃線210,藉由圖案化之遮罩208以在電漿蝕刻期間保護IC 206。在一個如此實施例中,電漿蝕刻處理用以連接刻劃線210及刻劃線254,在沒有來自切割道或背側金屬化層材料的干擾的情況下有效地分割IC。在一個實施例中,可實行切割之後晶圓操作,例如遮罩材料移除及背側帶層之移除等等。
因此,根據本發明之實施例,背側雷射劃線及前側雷射劃線及電漿蝕刻之組合用以將半導體晶圓切割成個別或分割的積體電路。在一個實施例中,兩雷射劃線操作皆用作為若非全部為非熱處理的話則為實質上非熱處理。舉例而言,背側及前側雷射劃線可侷限於無或可忽略不計的熱損害區域。在一個實施例中,本文的方式用於分割具有超低k薄膜的積體電路,及在前表面及背表面兩者上皆具有金屬化層的晶圓。以習知切割,鋸可能需要減慢以適應如此的低k薄膜。
在一個實施例中,被劃線的半導體晶圓或基板是由適合於對抗製造處理的材料所組成,且半導體處理層可適合地設置在該半導體晶圓或基板上。舉例而言,在一個實施例中,半導體晶圓或基板是由IV族系的材料所組成,例如但不限於,結晶矽、鍺或矽/鍺。在一個特定的實施例中,提供半導體晶圓包含提供單晶矽基板。在一個特定的實施例中,單晶矽基板以雜質原子來摻雜。在另一個實施例中,半導體晶圓或基板是由III-V材料所組成,例如,舉例而言,用於發光二極體(LED)之製造中的III-V材料基板。
在一個實施例中,半導體晶圓或基板在其前側上設置有半導體裝置之陣列。該等半導體裝置之實例包含但不限於,記憶體裝置或製造在矽基板中且封在介電層中的互補式金屬氧化物半導體(CMOS)電晶體。復數個金屬互連可形成在裝置或電晶體上方,及在環繞的介電層中,且可用以電性耦合裝置或電晶體以形成積體電路。介電層中之一或更多者可
為低k介電層。在一個實施例中,半導體晶圓或基板在晶圓或基板之背側上設置有金屬化層(及對應的介電層)。更一般而言,具有不同材料類型(舉例而言,導體、絕緣體、半導體)及厚度的功能層可設置於基板之背側及前側兩者上。該等材料可包含但不限於,有機材料例如聚合物、金屬或無機介電質例如二氧化矽及氮化矽。亦可包含低K介電層(舉例而言,具有介電常數低於二氧化矽之介電常數4.0的層)。在一個特定的實施例中,低K介電層是由碳摻雜的氧化矽所組成。
在遮罩層202是水溶性遮罩層的情況下,在一個實施例中,水溶性層在水性介質中容易溶解。舉例而言,在一個實施例中,水溶性層是由可在鹼性溶液、酸性溶液或去離子水中之一或更多者中溶解的材料所組成。在一個實施例中,當加熱處理時,例如在近似攝氏50度~160度的範圍中加熱時,水溶性層維持水溶性層之水溶性。舉例而言,在一個實施例中,水溶性層在曝露於用於雷射及電漿蝕刻分割處理中的腔室條件之後溶解於水溶液中。在一個實施例中,水溶性晶粒層是由例如但不限於聚乙烯醇(polyvinyl alcohol)、聚丙烯酸(polyacrylic acid)、葡萄聚醣(dextran)、聚甲基丙烯酸(polymethacrylic acid)、聚乙烯亞胺(polyethylene imine)或聚氧化乙烯(polyethylene oxide)的材料所組成。在特定的實施例中,水溶性層具有在水溶液中在近似每分鐘1微米~15微米之範圍中的蝕刻率,且更特定而言,近似每分鐘1.3微米。在另一個特定的實施例中,水溶性層由旋塗式(spin-on)技術所形成。
在遮罩層202是UV可固化的遮罩層的情況下,在一個實施例中,遮罩層具有對於UV光的易感性,易感性降低UV可固化層之附著性達至少近似80%。在一個如此實施例中,UV層是由聚氯乙烯(polyvinyl chloride)或丙烯酸系(acrylic-based)材料所組成。在一個實施例中,UV可固化層是由具有附著性質的材料或材料之堆疊所組成,該附著性質當曝露於UV光時弱化。在一個實施例中,UV可固化附著膜對於近似365nm的UV光敏感。在一個如此實施例中,此敏感性促使LED光之使用以實行固化。
在一個實施例中,前側或背側雷射劃線處理中之一或兩者涉及使用具有脈衝寬度在飛秒範圍中的雷射。特定而言,具有波長在可見光譜加上紫外(UV)範圍及紅外(IR)範圍(總共寬帶光譜)的雷射可用以提供飛秒系雷射,亦即,具有脈衝寬度在飛秒等級(10-15秒)的雷射。在一個實施例中,燒蝕(ablation)並非波長相依或實質上並非波長相依且因此適用於複雜膜,例如低k介電層及背側金屬化層。
第3圖繪示根據本發明之一個實施例,相對於較長頻率使用在飛秒範圍中的雷射脈衝之效應。參照第3圖,相對於較長脈衝寬度(舉例而言,以經由300B之皮秒處理的損害302B及以經由300A之奈秒處理的顯著損害302A),藉由使用具有脈衝寬度在飛秒範圍中的雷射,熱損壞問題被減輕或消除(舉例而言,以經由300C之飛秒處理的最小至無損害302C)。如第3圖所描繪,在經由300C之形成期間損害之消除或減輕可起因於缺乏低能量再耦合(如針對皮秒系雷射燒蝕
所見)或熱平衡(如針對奈秒系雷射燒蝕所見)。然而,如上所提及,針對本文實施例可考慮奈秒系、皮秒系或飛秒系雷射劃線。
如上所提及,在一個實施例中,蝕刻半導體晶圓或基板包含使用電漿蝕刻處理。在一個實施例中,超高密度電漿源是用於晶粒分割處理之電漿蝕刻部分。適用於實行這種電漿蝕刻處理的處理腔室之實例為可自美國加州桑尼韋爾市的應用材料公司(Applied Materials of Sunnyvale,CA,USA)購得的Applied Centura® SilviaTM Etch系統。Applied Centura® SilviaTM Etch系統結合電容性和電感性RF耦合,從而給予比起只有電容性耦合可能給予的更為獨立的離子密度及離子能量控制,甚至具有由磁性增強所提供的改良。這種組合促使離子密度與離子能量有效解耦,以便在沒有高的、潛在破壞性的直流偏壓位準的情況下達成相對高密度的電漿,即使在非常低的壓力下亦然。此舉造成異常寬的處理窗口。然而,可使用任何能夠處理及/或蝕刻矽的電漿蝕刻腔室。在特定的實施例中,蝕刻處理是基於自反應性氣體產生的電漿,該反應性氣體通常為氟系氣體,例如SF6、C4F8、CHF3、XeF2或任何其它能夠以相對較快的蝕刻速率蝕刻矽的反應物氣體。
在另一個實施例中,複數個積體電路可由具有近似10微米或更小的寬度的切割道所分隔。背側雷射劃線及前側雷射劃線及電漿蝕刻切割方式之使用,至少部分起因於雷射之緊密輪廓控制,可促使積體電路之佈局的如此壓縮
(compaction)。舉例而言,第4圖繪示根據本發明之一個實施例,相對於可能受限於最小寬度的習知切割,藉由使用較窄切割道所達成的在半導體晶圓或基板上的壓縮。
參照第4圖,在半導體晶圓上的壓縮是藉由相對於可能受限於最小寬度的習知切割(舉例而言,在佈局400中近似70微米之寬度或更大之寬度)使用較窄切割道(舉例而言,在佈局402中近似10微米之寬度或更小之寬度)所達成。然而,應瞭解,並非總是希望減低切割道寬度至低於10微米,即使否則由飛秒系雷射劃線處理所實現。舉例而言,某些應用可能要求至少40微米的切割道寬度,用以在分離積體電路的切割道中製造虛擬(dummy)裝置或測試裝置。
在另一個實施例中,複數個積體電路可以非受限制的佈局安置於半導體晶圓或基板上。舉例而言,第5圖繪示允許較密集封裝的自由形式積體電路安置。根據本發明之一個實施例,較密集封裝可提供相對於柵格對準方式每晶圓更多晶粒。參照第5圖,相對於柵格對準方式(舉例而言,在半導體晶圓或基板500上的受限制的佈局),自由形式佈局(舉例而言,在半導體晶圓或基板502上的非受限制的佈局)允許較密集封裝且因此每晶圓更多晶粒。在一個實施例中,雷射燒蝕及電漿蝕刻分割處理之速率與晶粒尺寸、佈局或切割道之數目無關。
單一處理工具可經配置以實行在背側雷射劃線及前側雷射劃線及電漿蝕刻分割處理中的許多或全部操作。舉例而言,第6圖繪示根據本發明之一個實施例,用於雷射及電
漿切割晶圓或基板的工具佈局之方塊圖。
參照第6圖,處理工具600包含工廠介面602(FI),工廠介面602具有與工廠介面602耦合的複數個負載鎖定腔室604。群集工具606與工廠介面602耦合。群集工具606包含一或更多個電漿蝕刻腔室,例如電漿蝕刻腔室608。雷射劃線設備610也與工廠介面602耦合。在一個實施例中,如第6圖所繪示,處理工具600之整體佔地面積可為近似3500毫米(3.5公尺)乘以近似3800毫米(3.8公尺)。
在一個實施例中,雷射劃線設備610容置奈秒系、皮秒系或飛秒系雷射,且較佳地為飛秒系雷射。奈秒系、皮秒系或飛秒系雷射適用於實行雷射及蝕刻分割處理之背側及/或前側雷射燒蝕部分,例如上述的雷射燒蝕處理。在一個實施例中,雷射劃線設備600中還包含可移動的台階,該可移動的台階經配置以相對於皮秒系或飛秒系雷射移動晶圓或基板(或晶圓或基板之載體)。在一個具體的實施例中,奈秒系、皮秒系或飛秒系雷射也是可移動的。在一個實施例中,如第6圖所繪示,雷射劃線設備610之整體佔地面積可為近似2240毫米乘以近似1270毫米。
在一個實施例中,該一或更多個電漿蝕刻腔室608為可自美國加州森尼韋爾市的應用材料公司購得的Applied Centura® SilviaTM Etch系統。可將蝕刻腔室具體設計為針對在用以產生分割的積體電路的處理中所使用的矽蝕刻或處理,該等積體電路容置於單晶矽基板或晶圓上或單晶矽基板或晶圓中。在一個實施例中,電漿蝕刻腔室608中包含高密
度電漿源,以促進高的矽蝕刻速率。在一個實施例中,處理工具600之群集工具606部分中包含多於一個的蝕刻腔室,以促使高製造產量的分割或切割處理。
工廠介面602可為適合的常壓接口,以在具有雷射劃線設備610的外部製造設施與群集工具606之間連繫。工廠介面602可包含具有手臂或葉片的機器人,用於將晶圓(或晶圓之載體)從儲存單元(例如前開式晶圓傳送盒)傳送進入群集工具606或雷射劃線設備610中之任一者或二者。
群集工具606可包含其它適合實行在分割之方法中的功能的腔室。舉例而言,在一個實施例中,取代額外的蝕刻腔室,包含沉積腔室612。沉積腔室612可經配置用於在雷射劃線晶圓或基板之前於晶圓或基板之背側及/或前側上或於晶圓或基板之背側及/或前側上方的遮罩沉積。在一個如此的實施例中,沉積腔室612適用於沉積水溶性遮罩層。在另一個實施例中,取代額外的蝕刻腔室,包含濕式/乾式站614。濕式/乾式站可適用於清洗殘留物及碎片或適用於在基板或晶圓之雷射劃線及電漿蝕刻分割處理後續移除水溶性遮罩。在另一個實施例中,沉積腔室612適用於沉積UV可固化遮罩層,且工具包含UV源。在一個實施例中,還包含計量站作為處理工具600之部件。
可提供本發明之實施例作為電腦程式產品或軟體,該電腦程式產品或軟體可包含機器可讀取媒體,該機器可讀取媒體具有儲存於該機器可讀取媒體上的指令,該等指令可用以程式化電腦系統(或其他電子裝置)以根據本發明之實施
例實行處理。在一個實施例中,電腦系統與關聯第6圖所述的處理工具600耦合。機器可讀取媒體包含任何用於以機器(舉例而言,電腦)能讀取的形式來儲存或傳送資訊的機制。舉例而言,機器可讀取(舉例而言,電腦可讀取)媒體包含機器(舉例而言,電腦)可讀取儲存媒體(舉例而言,唯讀記憶體(「ROM」)、隨機存取記憶體(「RAM」)、磁碟儲存媒體、光學儲存媒體、快閃記憶體裝置等等)、機器(舉例而言,電腦)可讀取傳送媒體(電性、光學、聲學或其他形式的傳播訊號(舉例而言,紅外訊號、數位訊號等))等等。
第7圖繪示以電腦系統700之示例形式的機器之圖示表示,在電腦系統700內可執行用於導致該機器實行本文所述的方法之任何一或更多者的一組指令。在替代的實施例中,機器可連結(舉例而言,網路連結)至在區域網路(LAN)、內部網路、外部網路或網際網路中的其他機器。機器可在客戶端-伺服器網路環境中以伺服器或客戶端機器之能力操作,或在點對點(peer-to-peer)(或分佈式)網路環境中作為個別機器(peer machine)。該機器可為個人電腦(PC)、平板PC、機上盒(STB)、個人數位助理(PDA)、行動電話、網路應用設備、伺服器、網路路由器、開關或橋接器,或能夠執行一組指明該機器將採取的行動之指令(依序的或其他方式)的任何機器。此外,雖然僅繪示單一機器,但用語「機器」亦應用來包含單獨地或聯合地執行一組(或多組)指令以實行本文所述的方法之任何一或更多者之機器(舉例而言,電腦)之任何組合。
示例的電腦系統700包含處理器702、主要記憶體704(舉例而言,唯讀記憶體(ROM)、快閃記憶體、動態隨機存取記憶體(DRAM)例如同步DRAM(SDRAM)或Rambus DRAM(RDRAM)等)、靜態記憶體706(舉例而言,快閃記憶體、靜態隨機存取記憶體(SRAM)等),及次要記憶體718(舉例而言,資料儲存裝置),處理器702、主要記憶體704、靜態記憶體706及次要記憶體718透過匯流排730彼此溝通。
處理器702代表一或更多個通用處理裝置例如微處理器、中央處理單元或類似者。更特定而言,處理器702可為複雜指令集計算(complex instruction set computing;CISC)微處理器、精簡指令集計算(reduced instruction set computing;RISC)微處理器、超長指令字集(very long instruction word;VLIW)微處理器、實施其他指令集的處理器或實施指令集之組合的處理器。處理器702亦可為一或更多個專用處理裝置例如特殊應用積體電路(application specific integrated circuit;ASIC)、現場可程式化閘陣列(field programmable gate array;FPGA)、數位訊號處理器(digital signal processor;DSP)、網路處理器或類似者。處理器702經配置以執行處理邏輯726用於實行本文所述之操作。
電腦系統700可進一步包含網路介面裝置708。電腦系統700亦可包含影像顯示單元710(舉例而言,液晶顯示器(LCD)、發光二極體顯示器(LED)或陰極射線管(CRT))、字母數字輸入裝置712(舉例而言,鍵盤)、游標控制裝置714(舉例而言,滑鼠)及訊號產生裝置716(舉例而言,揚聲器)。
次要記憶體718可包含機器可存取儲存媒體(或更具體而言為電腦可讀取儲存媒體)731,體現本文所述之方法或功能之任何一或更多者的一或更多組指令(舉例而言,軟體722)儲存於機器可存取儲存媒體731上。在由電腦系統700執行軟體722期間,軟體722亦可完全地或至少部分地駐留於主要記憶體704內及/或於處理器702內,主要記憶體704及處理器702亦構成機器可讀取儲存媒體。軟體722可進一步經由網路介面裝置708透過網路720傳送或接收。
雖然機器可存取儲存媒體731在示例實施例中圖示為單一媒體,用語「機器可讀取儲存媒體」應解讀為包含儲存該一或更多組指令的單一媒體或多個媒體(舉例而言,中央式或分散式資料庫,及/或連接的快取及伺服器)。用語「機器可讀取儲存媒體」亦應解讀為包含能夠儲存或編碼由該機器所執行之一組指令的任何媒體,且該組指令導致該機器實行本發明之方法之任何一或更多者。用語「機器可讀取儲存媒體」因此應解讀為包含但不限於固態記憶體,及光學及磁性媒體。根據本發明之一個實施例,機器可存取儲存媒體具有儲存於其上的指令,該等指令導致資料處理系統實行上述切割具有複數個積體電路的半導體晶圓之方法。
因此,已揭示用於晶圓或基板之背側雷射劃線加上前側雷射劃線及電漿蝕刻切割的方式。
Claims (8)
- 一種切割一半導體晶圓之方法,該半導體晶圓包括在該半導體晶圓之一前側上的複數個積體電路及在該半導體晶圓之一背側上的金屬化層,該方法包括以下步驟:在不使用一遮罩的情況下使用一第一雷射劃線處理圖案化在該背側上的該金屬化層,以在該背側上提供第一複數個雷射刻劃線,及於該第一雷射劃線處理期間晶粒標記該半導體晶圓之該背側,該第一雷射劃線處理使用與該晶粒標記相同的雷射;在執行該第一雷射劃線處理之後,在該半導體晶圓之該前側上形成一遮罩;使用一第二雷射劃線處理從該半導體晶圓之該前側圖案化該遮罩,以提供一圖案化之遮罩及提供第二複數個刻劃線,該第二複數個刻劃線曝露出該半導體晶圓介於該等積體電路之間的區域,其中該第二複數個刻劃線與該第一複數個刻劃線對準;及電漿蝕刻該半導體晶圓通過該第二複數個刻劃線,以分割該等積體電路。
- 如請求項1所述之方法,其中該第一雷射劃線處理及該第二雷射劃線處理涉及使用相同的雷射條件。
- 如請求項1所述之方法,其中該第一雷射劃線處理及該第二雷射劃線處理涉及使用一飛秒系雷射。
- 如請求項1所述之方法,其中該第一複數個刻劃線包括部分地形成進入該半導體晶圓之該背側中的數個溝。
- 如請求項1所述之方法,其中該第二複數個刻劃線包括部分地形成進入該半導體晶圓之該前側中的數個溝。
- 如請求項1所述之方法,其中在該前側上形成該遮罩的步驟包括以下步驟:形成一水溶性遮罩。
- 如請求項1所述之方法,其中在該前側上形成該遮罩的步驟包括以下步驟:形成一UV可固化遮罩。
- 如請求項1所述之方法,其中該第一雷射劃線處理及該第二雷射劃線處理涉及使用不同的雷射條件。
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Also Published As
Publication number | Publication date |
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PT3047517T (pt) | 2021-05-27 |
KR20160055933A (ko) | 2016-05-18 |
TW201517153A (zh) | 2015-05-01 |
EP3047517A1 (en) | 2016-07-27 |
JP2016533025A (ja) | 2016-10-20 |
EP3047517A4 (en) | 2017-05-03 |
US9224650B2 (en) | 2015-12-29 |
JP6422484B2 (ja) | 2018-11-14 |
US20150079761A1 (en) | 2015-03-19 |
EP3047517B1 (en) | 2021-03-17 |
EP3869546A1 (en) | 2021-08-25 |
WO2015041842A1 (en) | 2015-03-26 |
EP3869546B1 (en) | 2024-05-15 |
ES2871419T3 (es) | 2021-10-28 |
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