TWI605505B - 從晶圓背側切割晶圓 - Google Patents
從晶圓背側切割晶圓 Download PDFInfo
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Classifications
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/02—Positioning or observing the workpiece, e.g. with respect to the point of impact; Aligning, aiming or focusing the laser beam
- B23K26/06—Shaping the laser beam, e.g. by masks or multi-focusing
- B23K26/062—Shaping the laser beam, e.g. by masks or multi-focusing by direct control of the laser beam
- B23K26/0622—Shaping the laser beam, e.g. by masks or multi-focusing by direct control of the laser beam by shaping pulses
- B23K26/0624—Shaping the laser beam, e.g. by masks or multi-focusing by direct control of the laser beam by shaping pulses using ultrashort pulses, i.e. pulses of 1ns or less
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/18—Working by laser beam, e.g. welding, cutting or boring using absorbing layers on the workpiece, e.g. for marking or protecting purposes
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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- B23K26/36—Removing material
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/40—Removing material taking account of the properties of the material involved
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/16—Composite materials, e.g. fibre reinforced
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- B23K2103/172—Multilayered materials wherein at least one of the layers is non-metallic
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/50—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
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- Condensed Matter Physics & Semiconductors (AREA)
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Description
本申請案主張西元2012年12月20日申請的美國臨時專利申請案第61/740,301號的權益,該申請案全文內容以引用方式併入本文中。
本發明的實施例係關於半導體處理領域,且特別係關於切割半導體晶圓的方法,每一晶圓具有複數個積體電路於上。
在半導體晶圓處理中,積體電路形成在由矽或其他半導體材料組成的晶圓(亦稱作基板)上。通常,各種半導體、導體或絕緣材料層用於形成積體電路。利用各種已知製程來摻雜、沉積及蝕刻該等材料,以形成積體電路。各晶圓經處理而形成大量個別區域,區域含有稱為晶粒的積體電路。
在積體電路形成製程後,「切割」晶圓,以將個別晶粒彼此分開供封裝或以未封裝形式用於較大電路內。兩種主要晶圓切割技術為劃線及鋸切。採行劃線時,鑽石尖端劃片沿著預成形刻劃線移動越過晶圓表面。該等刻劃線沿著晶粒的間隔延伸。該等間隔一般稱作「切割道」。鑽石劃片沿
著切割道在晶圓表面形成淺劃痕。如利用輥施加壓力後,晶圓即沿著刻劃線分開。晶圓中的裂縫依循晶圓基板的晶格結構而行。劃線可用於厚度約10密耳(千分之一吋)或以下的晶圓。對較厚晶圓而言,鋸切係目前較佳的切割方法。
採行鋸切時,每分鐘高轉速旋轉的鑽石尖端鋸子接觸晶圓表面及沿著切割道鋸切晶圓。晶圓裝設在支撐構件上,例如延展整個膜框的黏著膜,鋸子反覆用於垂直與水平切割道。採行劃線或鋸切的問題在於碎片和鑿孔會沿著晶粒的斷裂邊緣形成。此外,裂痕會形成及從晶粒邊緣傳佈到基板內,導致積體電路無效。碎裂和破裂在劃線方面尤其嚴重,因為在晶體結構的<110>方向上,方形或矩形晶粒只有一側可被劃線。是以劈開晶粒另一側將產生鋸齒狀分離線。由於碎裂和破裂,晶圓上的晶粒間需有額外間距,以免破壞積體電路,例如使碎片和裂痕與實際積體電路保持距離。因應間距要求,標準尺寸晶圓上無法形成許多晶粒,以致浪費了用於電路的晶圓地產(real estate)。使用鋸子加劇了半導體晶圓上的地產浪費。鋸刃厚度為約15微米。故為確保鋸切周圍的破裂和其他破壞不會損害積體電路,各晶粒的電路往往需分開300至500微米。另外,切割後,需實質清洗各晶粒,以移除微粒和鋸切製程產生的其他污染物。
亦可採行電漿切割,但電漿切割也有所限制。例如,阻礙電漿切割實施的一限制為成本。用於圖案化光阻的標準微影操作將致使實施成本過高。可能阻礙電漿切割實施的另一限制為沿著切割道切割時,電漿處理常用金屬(例如銅)
會造成生產問題或產量限制。
本發明的實施例包括切割半導體晶圓的方法,每一晶圓具有複數個積體電路於上。
在一實施例中,切割具有複數個積體電路的半導體晶圓的方法包括塗鋪保護帶至晶圓前側,晶圓具有附接至晶圓背側的切割帶。自晶圓背側移除切割帶,以露出晶粒附接膜,晶粒附接膜置於晶圓背側與切割帶之間。塗鋪水溶性遮罩至晶圓背側。於晶圓背側上進行雷射劃線,以切穿遮罩、晶粒附接膜和晶圓,包括包含在晶圓的前側與背側內的所有層。進行電漿蝕刻,以處理或清洗由雷射劃線所露出的晶圓表面。清洗晶圓背側,及塗鋪第二切割帶至晶圓背側。自晶圓前側移除保護帶。
在另一實施例中,切割具有複數個積體電路的半導體晶圓的方法包括塗鋪保護帶至晶圓前側,晶圓具有附接至晶圓背側的切割帶。自晶圓背側移除切割帶。接著塗鋪晶粒附接膜至晶圓背側。接著塗鋪水溶性遮罩至晶圓背側。於晶圓背側上進行雷射劃線,以切穿遮罩、晶粒附接膜和晶圓,包括包含在晶圓的前側與背側內的所有層。進行電漿蝕刻,以處理或清洗由雷射劃線所露出的晶圓表面。清洗晶圓背側,及塗鋪第二切割帶至晶圓背側。自晶圓前側移除保護帶。
在又一實施例中,提供切割具有複數個積體電路的半導體晶圓的方法,積體電路被半導體晶圓前側的保護帶覆蓋,並且在半導體晶圓背側具有金屬化層。方法涉及露出晶
粒附接膜,晶粒附接膜置於半導體晶圓背側上。方法亦涉及塗鋪遮罩至半導體晶圓背側上露出的晶粒附接膜。方法亦涉及從半導體晶圓背側雷射劃線,以切穿遮罩、晶粒附接膜、半導體晶圓背側上的金屬化層、半導體晶圓和半導體晶圓前側上的積體電路。方法亦涉及電漿蝕刻以處理或清洗由雷射劃線所露出的半導體晶圓表面。方法亦涉及塗鋪切割帶至經雷射劃線的半導體晶圓背側。
100‧‧‧流程圖
102、104、106、108、110、112、114‧‧‧操作
202、204、208、210、212‧‧‧結構
203、205、207、209、211‧‧‧操作
300A-C‧‧‧通孔
302A-C‧‧‧破壞
400、402‧‧‧佈局
500、502‧‧‧基板
600‧‧‧製程工具
602‧‧‧工作介面
604‧‧‧負載鎖定室
606‧‧‧叢集工具
608‧‧‧電漿蝕刻腔室
610‧‧‧雷射劃線設備
612‧‧‧沉積腔室
614‧‧‧濕潤/乾燥站
700‧‧‧電腦系統
702‧‧‧處理器
704、706、718‧‧‧記憶體
708‧‧‧網路介面裝置
710‧‧‧視訊顯示單元
712‧‧‧文數輸入裝置
714‧‧‧游標控制裝置
716‧‧‧訊號產生裝置
720‧‧‧網路
722‧‧‧軟體
726‧‧‧邏輯
730‧‧‧匯流排
731‧‧‧電腦可存取儲存媒體
第1圖為根據本發明一實施例的流程圖,包括背側雷射加上電漿蝕刻切割製程的操作。
第2A圖及第2B圖為根據本發明一實施例,表示背側雷射加上電漿蝕刻切割製程的各種操作截面圖。
第3圖圖示根據本發明一實施例,使用飛秒範圍的雷射脈衝對照較長脈衝時間的作用。
第4圖圖示根據本發明一實施例,利用窄切割道對照習知切割在半導體晶圓上達成的密實性,習知切割受限於最小寬度。
第5圖圖示根據本發明一實施例,容許緊密填裝、使得每晶圓有更多晶粒的自由曲面積體電路配置對照網格對準方式。
第6圖為根據本發明一實施例,用於雷射及電漿切割晶圓或基板的工具佈局方塊圖。
第7圖為根據本發明一實施例的示例性電腦系統方塊圖。
茲描述切割半導體晶圓的方法,每一晶圓具有複數個積體電路於上。在以下說明中提出許多特定細節,例如飛秒基雷射劃線和電漿蝕刻條件與材料體系,以對本發明實施例有更徹底的瞭解。熟諳此技術者將明白,本發明實施例可不依該等特定細節實踐。在其他情況下,並不詳述諸如積體電路製造等已知態樣,以免讓本發明實施例變得晦澀難懂。另外,應理解圖式所示各種實施例為代表性說明,故未必按比例繪製。
涉及初始雷射劃線與後續電漿處理的混合式晶圓或基板切割製程可用於晶粒單粒化。雷射劃線製程可用於乾淨地移除遮罩層、有機與無機介電層和晶圓兩側的裝置層,及切穿介入基板。切割製程的電漿蝕刻或處理部分接著可用於產生乾淨的晶粒或晶片單粒化或切割。
更特定言之,一或更多實施例係針對從晶圓或基板背側切割晶圓或基板。特定實施例包括一或更多晶圓切割、背側切割、背側金屬/介電結構、皮秒紫外線(UV)雷射劃線、紅外線飛秒雷射劃線、全厚度雷射切割及使用水溶性遮罩。所述涉及一般雷射劃線加上電漿蝕刻的混合式製程方式可用於自晶圓或基板單粒化積體電路(IC)晶片或晶粒。其他潛在應用包括MEMS晶圓切割。所述方式與飛秒雷射劃線加上電漿蝕刻的混合式處理相比,飛秒雷射劃線加上電漿蝕刻的混合式處理涉及使用飛秒雷射來乾淨地移除遮罩層、有機與無機介電層和裝置層,然後電漿蝕穿矽層(例如晶圓或基板)
而實踐晶片單粒化或切割。一或更多實施例卻涉及利用雷射製程持續劃線穿過晶圓或基板(例如從背側),然後進行修整或清洗矽蝕刻製程。
更大體而言,一些晶圓或基板在晶圓或基板背側上承有金屬及/或介電層。此外,晶粒附接膜常常加設於晶圓背側,且和晶圓或基板一起經切割製程處理,例如在切割製程時切割或圖案化晶粒附接膜。在習知雷射加上蝕刻切割製程中,附加雷射劃線操作需要後電漿蝕刻,以移除此類背側非矽層。附加雷射操作涉及耗時的晶圓重新對準。另外,從晶圓或基板前側雷射劃線與電漿蝕刻需於晶圓或基板前側上使用厚遮罩層,以充分保護金屬凸塊和支柱。由於蝕刻期間,前側會接觸或至少面對電漿,故也可能會氧化凸塊及污染晶圓或基板的裝置側。因此若附加背側非矽層變成待單粒化結構的主要部分,則從前側切割將引發產量與品質問題。
故如以下所詳述,一或更多實施例涉及從晶圓或基板背側切割。例如,第1圖為根據本發明一實施例的流程圖100,包括背側雷射加上電漿蝕刻切割製程的操作。參照流程圖100,在操作102中,塗鋪保護帶至晶圓前側,晶圓具有附接至晶圓背側的切割帶。在操作104中,自晶圓背側移除切割帶,以露出晶粒附接膜,晶粒附接膜置於晶圓背側與切割帶之間。或者,若最初無晶粒附接膜置於晶圓背側與切割帶之間,則在此操作中,塗鋪晶粒附接膜至晶圓背側。在操作106中,塗鋪水溶性遮罩至晶圓背側,例如晶粒附接膜上。在操作108中,於晶圓背側上進行雷射劃線,以切穿晶粒附接
膜和晶圓,包括晶圓前側與背側上的所有層(例如背側和前側金屬或介電層及/或裝置層)。在操作110中,進行電漿蝕刻,以處理或清洗由雷射劃線所露出的晶圓表面(例如由雷射劃線所露出的矽側壁)。蝕刻製程可用於清洗碎屑及/或增強晶粒強度。在操作112中,清洗晶圓背側,及塗鋪第二切割帶至晶圓背側。在操作114中,自晶圓前側移除保護帶。
做為一結構實例,第2A圖及第2B圖為根據本發明一實施例,表示背側雷射加上電漿蝕刻切割製程的各種操作截面圖。
參照第2A圖,結構202包括矽基板,矽基板具有置於基板前側的裝置層和置於基板背側的金屬及/或介電層。在操作203中,如所得結構204所示,保護帶裝設於晶圓前側,例如裝置層上。基板由保護帶裝設在框架上。又,晶粒附接膜和切割帶置於基板背側,例如置於基板背側的金屬及/或介電層上。在操作205中,如所得結構208所示,水溶性遮罩置於基板背側的晶粒附接膜上。在操作207中,亦如所得結構208所示,從基板背側進行雷射劃線製程,以穿過水溶性遮罩、晶粒附接膜與金屬及/或介電層、矽基板和裝置層。雷射劃線製程止於基板前側的保護帶上或內。此外,在操作207中,電漿蝕刻製程用於清洗露出的矽基板側壁。此外,電漿蝕刻製程可用於自側壁移除一定量的矽,以增強晶粒強度。在操作209中,以如水基清洗製程移除水溶性遮罩,以提供結構210。接著參照第2B圖,在操作211中,如所得結構212所示,塗鋪切割帶至基板背側,例如已劃線的晶粒附
接膜上。接著自已切割的基板前側移除保護帶(和對應框架)。如此可獲得自矽基板單粒化的複數個晶片或晶粒。晶粒或晶片由切割帶固定於如第二框架上,以供運送。
本文所述從晶圓或基板背側切割的實施例可包括下列一或更多優點:(1)由於凸塊未涉及背側金屬化,遮罩厚度(例如水溶性遮罩厚度)遠比前側製程所需的厚度薄。因此打開遮罩需時較短,此可彌補雷射劃線製程切穿整個晶圓所需的任何額外時間。又,使用較少遮罩材料可節省成本。另外,如相較於涉及多層塗層的厚遮罩塗佈製程,可縮短遮罩塗佈及烘烤時間。對照可能內陷氣泡、導致晶圓中產生蝕刻缺陷的厚遮罩,使用薄遮罩塗佈亦可改善塗層品質。(2)利用電漿蝕刻來修補已切割側壁涉及蝕去明顯較少的矽及大幅縮短蝕刻時間。(3)對照前側劃線、然後蝕刻、接著背側劃線的製程,從背側切割不會實質影響產量,因為該製程係雷射切割加上電漿。(4)因未觸碰前側,故能有效減少凸塊氧化和裝置側污染的機會,並可放到冷卻夾具上。(5)雷射性能規格可放寬,因而可使用較長波長及/或較長脈寬的雷射。藉由放寬雷射源選項,可降低雷射成本。可能適合的雷射源包括皮秒UV雷射、紅外線飛秒雷射(例如取代SHG(~500nm)-飛秒雷射,此係用於前側切割的較佳雷射源)。由於背側雷射切割涉及先雷射移除矽,在碰到裝置層前,矽會吸收寬波長/脈寬的光子,因此更有彈性。
故根據本發明一實施例,背側皮秒或飛秒基雷射劃線與電漿蝕刻結合用於將半導體晶圓切割成個別化或單粒化
積體電路。在一實施例中,皮秒或飛秒基雷射劃線若非全然、基本上也用作非熱製程。例如,背側皮秒或飛秒基雷射劃線可以無或可忽略的熱破壞區定位。在一實施例中,所述方式用於單粒化具極低k膜的積體電路和正面與背面具金屬化層的晶圓。採行習知切割時,需配合此低k膜減慢鋸切。
根據本發明一實施例,水溶性遮罩用於背側雷射劃線與蝕刻製程。在一實施例中,水溶性遮罩係可於水性介質中快速溶解的膜。例如,在一實施例中,水溶性遮罩由可溶於一或更多的鹼性溶液、酸性溶液、去離子水的材料組成。在一實施例中,水溶性遮罩的厚度為約5微米至60微米。在一特定實施例中,水溶性遮罩的厚度為約20微米。在一實施例中,水溶性遮罩經加熱後仍維持其水溶性,例如加熱達約50℃至160℃。例如,在一實施例中,水溶性遮罩可溶於水溶液,然後暴露在用於雷射與電漿蝕刻單粒化製程的腔室條件下。在一實施例中,水溶性遮罩由聚乙烯醇、聚丙烯酸、葡聚醣、聚甲基丙烯酸、聚乙烯亞胺或聚環氧乙烷材料組成,但不以此為限。在一特定實施例中,水溶性遮罩於水溶液中的蝕刻速率為約1至15微米/分鐘,更特別為約1.3微米/分鐘。在另一特定實施例中,水溶性遮罩係由旋塗技術形成。
在一實施例中,待劃線半導體晶圓或基板係由適合承受製造製程且供半導體處理層適當放置於上的材料組成。例如,在一實施例中,半導體晶圓或基板由IV族系材料組成,例如結晶矽、鍺或矽/鍺,但不以此為限。在一特定實施例中,提供半導體晶圓包括提供單晶矽基板。在一特定實施例中,
單晶矽基板摻雜雜質原子。在另一實施例中,半導體晶圓或基板由III-V材料組成,例如用於製造發光二極體(LED)的III-V材料基板。
在一實施例中,半導體晶圓或基板已於前側設置半導體裝置陣列。此類半導體裝置實例包括記憶裝置或製造於矽基板且包圍在介電層中的互補式金氧半導體(CMOS)電晶體,但不以此為限。複數個金屬內連線可形成在裝置或電晶體上並位於周圍介電層中,金屬內連線可用於電氣耦接裝置或電晶體而形成積體電路。一或更多介電層可為低k介電層。在一實施例中,半導體晶圓或基板已於晶圓或基板背側設置金屬化層(和對應介電層)。更大體而言,許多不同材料類型(例如導體、絕緣體、半導體)和厚度的功能層可設在基板的背側與前側。此類材料可包括有機材料(例如聚合物)、金屬或無機介電質(例如二氧化矽和氮化矽),但不以此為限。低k介電層亦可包括在內(例如介電常數小於4.0的二氧化矽層)。在特定一實施例中,低k介電層由碳摻雜的氧化矽材料組成。
在一實施例中,雷射劃線製程包括使用具飛秒範圍脈寬的雷射。特定言之,具可見光光譜加上紫外線(UV)與紅外線(IR)範圍波長(三者總體為寬帶光譜)的雷射可用於提供飛秒基雷射,即脈寬為飛秒等級(10-15秒)的雷射。在一實施例中,剝離並非或實質不為波長相依,因此適合複雜膜,例如低k介電層和背側金屬化層。
第3圖圖示根據本發明一實施例,使用飛秒範圍的
雷射脈衝對照較長頻率的作用。參照第3圖,對照較長脈寬(例如以皮秒處理通孔300B造成的破壞302B和以奈秒處理通孔300A造成的顯著破壞302A),使用飛秒範圍的雷射脈寬,可減輕或消除熱破壞問題(例如以飛秒處理通孔300C乃最小化成無破壞302C)。如第3圖所示,消除或減輕通孔300C形成期間的破壞係因缺少低能再耦合(如皮秒基雷射剝離所見)或熱平衡(如奈秒基雷射剝離所見)所致。然如上所述,皮秒或飛秒基可用於所述實施例係因與前側雷射劃線製程相比,在背側雷射劃線製程期間可放寬參數。
如上所述,在一實施例中,蝕刻半導體晶圓或基板包括利用電漿蝕刻製程。在一實施例中,極高密度電漿源用於晶粒單粒化製程的電漿蝕刻部分。適於進行電漿蝕刻製程的處理腔室一例為取自美國加州Sunnyvale的應用材料公司的Applied Centura® SilviaTM蝕刻系統。Applied Centura® SilviaTM蝕刻系統結合電容與感應射頻(RF)耦合,此比僅利用電容耦合更能個別控制離子密度和離子能量,即使有磁性增強改善亦然。此結合能有效使離子密度和離子能量去耦合,即使在很低的壓力下,也可達到相當高的密度電漿,又無可能有害的高DC偏壓位準。此將造成異常寬廣的製程視窗。然任何能處理及/或蝕刻矽的電漿蝕刻腔室都可採用。在一特定實施例中,蝕刻製程係以反應氣體產生的電漿為基礎,反應氣體通常係氟系氣體,例如SF6、C4F8、CHF3、XeF2或任何能以較快蝕刻速率蝕刻矽的其他反應物氣體。
在另一實施例中,複數個積體電路由寬度約10微米
或以下的切割道隔開。至少在某種程度上因控制雷射緊密輪廓所致,利用背側皮秒或飛秒基雷射劃線方式能使積體電路佈局密實。例如,第4圖圖示根據本發明一實施例,利用窄切割道對照習知切割在半導體晶圓或基板上達成的密實性,習知切割受限於最小寬度。
參照第4圖,使用窄切割道(例如在佈局402中寬度約10微米或以下)對照受限於最小寬度(例如在佈局400中寬度約70微米或以上)的習知切割,在半導體晶圓上達成的密實性。然應理解即使飛秒基雷射劃線製程可達成,也非總是期切割道寬度縮減成小於10微米。例如,一些應用需切割道寬度為至少40微米,以於分隔積體電路的切割道上製造虛設或測試裝置。
在另一實施例中,複數個積體電路依非限制佈局配置在半導體晶圓或基板上。例如,第5圖圖示容許緊密填裝的自由曲面積體電路配置。根據本發明一實施例,對照網格對準方式,緊密填裝可提供每晶圓更多晶粒。參照第5圖,自由曲面佈局(例如半導體晶圓或基板502上的非限制佈局)容許緊密填裝,故對照網格對準方式(例如半導體晶圓或基板500上的限制佈局),可使每晶圓有更多晶粒。在一實施例中,雷射剝離與電漿蝕刻單粒化製程的速度與晶粒尺寸、佈局或切割道數量無關。
單一製程工具可配置以進行背側皮秒或飛秒基雷射剝離與電漿蝕刻單粒化製程中的許多或所有操作。例如,第6圖為根據本發明一實施例,用於雷射與電漿切割晶圓或基板
的工具佈局方塊圖。
參照第6圖,製程工具600包括工作介面(FI)602,工作介面602具有複數個負載鎖定室604與之耦接。叢集工具606耦接工作介面602。叢集工具606包括一或更多電漿蝕刻腔室,例如電漿蝕刻腔室608。雷射劃線設備610亦耦接至工作介面602。在一實施例中,如第6圖所示,製程工具600的整體佔地面積為約3500毫米(3.5公尺)×約3800毫米(3.8公尺)。
在一實施例中,雷射劃線設備610內放置皮秒或飛秒基雷射。皮秒或飛秒基雷射適於進行雷射與蝕刻單粒化製程的背側雷射剝離部分,例如上述雷射剝離製程。在一實施例中,雷射劃線設備610亦包括移動平臺,移動平臺配置以相對皮秒或飛秒基雷射移動晶圓或基板(或晶圓或基板載具)。在一特定實施例中,皮秒或飛秒基雷射亦可移動。在一實施例中,如第6圖所示,雷射劃線設備610的整體佔地面積為約2240毫米×約1270毫米。
在一實施例中,一或更多電漿蝕刻腔室608係取自美國加州Sunnyvale的應用材料公司的Applied Centura® SilviaTM蝕刻系統。蝕刻腔室可特別設計用於矽蝕刻或製程處理,以製造位於單晶矽基板或晶圓上或內的單粒化積體電路。在一實施例中,電漿蝕刻腔室608包括高密度電漿源,以促進高矽蝕刻速率。在一實施例中,製程工具600的叢集工具606包括超過一個蝕刻腔室,以使單粒化或切割製程達高製造產量。
工作介面602可為適合的大氣埠,以接合具有雷射劃線設備610的外側製造設施和叢集工具606。工作介面602可包括具有手臂或葉片的機器人,以將晶圓(或晶圓載具)從儲放單元(例如前開式晶圓盒)傳送到叢集工具606或雷射劃線設備610或二者。
叢集工具606可包括其他適合執行單粒化方法中的功能的腔室。例如,在一實施例中,可包括沉積腔室612來代替附加蝕刻腔室。沉積腔室612可配置以在雷射劃線晶圓或基板前,沉積遮罩至晶圓或基板的背側上或上方。在此一實施例中,沉積腔室612適於沉積水溶性遮罩層。在另一實施例中,可包括濕潤/乾燥站614來代替附加蝕刻腔室。濕潤/乾燥站適於在基板或晶圓的雷射劃線與電漿蝕刻單粒化製程後,清洗殘餘物和破片、或移除水溶性遮罩。在一實施例中,亦包括測量站做為製程工具600的部件。
本發明的實施例可提供做為電腦程式產品或軟體,電腦程式產品或軟體可包括內含儲存指令的機器可讀取媒體,用以程式化電腦系統(或其他電子裝置)而進行根據本發明實施例的製程。在一實施例中,電腦系統耦接第6圖所述製程工具600。機器可讀取媒體包括任何用來儲存或傳遞機器(例如電腦)可讀取形式資訊的機構。例如,機器可讀取(例如電腦可讀取)媒體包括機器(例如電腦)可讀取儲存媒體(例如唯讀記憶體(ROM)、隨機存取記憶體(RAM)、磁碟儲存媒體、光學儲存媒體、快閃記憶體裝置等)、機器(例如電腦)可讀取傳輸媒體(電子、光學、聲音或其他形
式的傳播訊號(例如紅外線訊號、數位訊號等))等。
第7圖為示例性電腦系統700的機器示意圖,電腦系統700可執行指令集,以促使機器進行本文所述任一或更多方法。在替代實施例中,機器可連接(例如網路聯結)至區域網路(LAN)、企業內部網路、企業外部網路或網際網路中的其他機器。機器可由主從網路環境中的伺服器或客戶機操作,或當作同級間(或分散式)網路環境中的同級點機器。機器可為個人電腦(PC)、平板PC、機上盒(STB)、個人數位助理(PDA)、手機、網路設備、伺服器、網路路由器、交換機或橋接器,或任何能(循序或按其他方式)執行指令集的機器,指令集指定機器執行動作。另外,雖然只圖示單一機器,但「機器」一詞亦應視同包括任何機器(例如電腦)的集合,該等機器個別或共同執行一組(或多組)指令,以進行本文所述任一或更多方法。
示例性電腦系統700包括處理器702、主記憶體704(例如唯讀記憶體(ROM)、快閃記憶體、諸如同步DRAM(SDRAM)或Rambus DRAM(RDRAM)等動態隨機存取記憶體(DRAM))、靜態記憶體706(例如快閃記憶體、靜態隨機存取記憶體(SRAM)等)和次記憶體718(例如資料儲存裝置),處理器702、記憶體704、706、718透過匯流排730互相通信連接。
處理器702代表一或更多通用處理裝置,例如微處理器、中央處理單元等。更特別地,處理器702可為複雜指令集運算(CISC)微處理器、精簡指令集運算(RISC)微處
理器、超長指令字組(VLIW)微處理器、實行其他指令集的處理器或實行指令集組合的處理器。處理器702亦可為一或更多特殊用途處理裝置,例如特定功能積體電路(ASIC)、場可程式閘陣列(FPGA)、數位訊號處理器(DSP)、網路處理器等。處理器702配置以執行處理邏輯726,以進行本文所述操作。
電腦系統700可進一步包括網路介面裝置708。電腦系統700亦可包括視訊顯示單元710(例如液晶顯示器(LCD)、發光二極體顯示器(LED)或陰極射線管(CRT))、文數輸入裝置712(例如鍵盤)、游標控制裝置714(例如滑鼠)和訊號產生裝置416(例如揚聲器)。
次記憶體718可包括機器可存取儲存媒體(或更特定言之為電腦可讀取儲存媒體)731,機器可存取儲存媒體731儲存收錄所述任一或更多方法或功能的一或更多組指令(例如軟體722)。軟體722亦可完全或至少部分常駐在主記憶體704及/或處理器702內,電腦系統700執行軟體722時,主記憶體704和處理器702亦構成機器可讀取儲存媒體。軟體722可進一步透過網路介面裝置708在網路720上傳送或接收。
雖然在一示例性實施例中,機器可存取儲存媒體731係顯示為單一媒體,但「機器可讀取儲存媒體」一詞應視同包括單一媒體或多個媒體(例如集中式或分散式資料庫及/或相關高速緩衝儲存器和伺服器),用以儲存一或更多組指令。「機器可讀取儲存媒體」一詞亦應視同包括任何能儲存或編
碼機器執行的指令集而使機器進行本發明之任一或更多方法的媒體。因此,「機器可讀取儲存媒體」一詞宜視同包括固態記憶體和光學與磁性媒體,但不以此為限。
根據本發明一實施例,機器可存取儲存媒體具有儲存指令,用以促使資料處理系統進行上述切割具有複數個積體電路的半導體晶圓的方法。
故揭示切割半導體晶圓的方法,每一晶圓具有複數個積體電路。根據本發明一實施例,方法包括塗鋪保護帶至晶圓前側,晶圓具有附接至晶圓背側的切割帶。自晶圓背側移除切割帶,以露出晶粒附接膜,晶粒附接膜置於晶圓背側與切割帶之間。或者,若最初無晶粒附接膜置於晶圓背側與切割帶之間,則在此操作中,塗鋪晶粒附接膜至晶圓背側。塗鋪水溶性遮罩至晶圓背側。於晶圓背側上進行雷射劃線,以切穿晶粒附接膜和晶圓,包括晶圓前側與背側上的所有層。進行電漿蝕刻,以處理或清洗由雷射劃線所露出的晶圓表面。清洗晶圓背側,及塗鋪第二切割帶至晶圓背側。自晶圓前側移除保護帶。在一實施例中,晶圓背側包括背側金屬化與介電層,晶圓前側包括裝置層。
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Claims (20)
- 一種切割一半導體晶圓的方法,該半導體晶圓包含複數個積體電路,該方法包含:塗鋪一保護帶至一晶圓前側,該晶圓具有附接至一晶圓背側的一切割帶;自該晶圓背側移除該切割帶,以露出一晶粒附接膜,該晶粒附接膜置於該晶圓背側與該切割帶之間;及隨後,塗鋪一遮罩至該晶圓背側;及隨後,從該晶圓背側雷射劃線,以切穿該遮罩、該晶粒附接膜和該晶圓,包括包含在該晶圓的該前側與該背側內的所有層;電漿蝕刻以處理或清洗由該雷射劃線所露出該晶圓的多個表面;及隨後,清洗該晶圓背側,及塗鋪一第二切割帶至該晶圓背側;及隨後,自該晶圓前側移除該保護帶。
- 如請求項1所述之方法,其中塗鋪該遮罩至該晶圓背側包含塗鋪一水溶性遮罩至該晶圓背側。
- 如請求項2所述之方法,其中清洗該晶圓背側包含以一水溶液移除該水溶性遮罩。
- 如請求項1所述之方法,其中從該晶圓背側雷射劃線包含利用一飛秒基雷射劃線製程。
- 如請求項1所述之方法,其中從該晶圓背側雷射劃線包含利用一皮秒基雷射劃線製程。
- 如請求項1所述之方法,其中該晶圓背側包括多個背側金屬化與介電層,該晶圓前側包括多個裝置層。
- 如請求項1所述之方法,其中該晶圓係一單晶矽基板。
- 一種切割一半導體晶圓的方法,該半導體晶圓包含複數個積體電路,該方法包含:塗鋪一保護帶至一晶圓前側,該晶圓具有附接至該晶圓背側的一切割帶;自該晶圓背側移除該切割帶;及隨後,塗鋪一晶粒附接膜至該晶圓背側;及隨後,塗鋪一遮罩至該晶圓背側;及隨後,從該晶圓背側雷射劃線,以切穿該遮罩、該晶粒附接膜和該晶圓,包括包含在該晶圓的該前側與該背側內的所有層;電漿蝕刻以處理或清洗由該雷射劃線所露出該晶圓的多個表面;及隨後,清洗該晶圓背側,及塗鋪一第二切割帶至該晶圓背側;及隨後,自該晶圓前側移除該保護帶。
- 如請求項8所述之方法,其中塗鋪該遮罩至該晶圓背側包含塗鋪一水溶性遮罩至該晶圓背側。
- 如請求項9所述之方法,其中清洗該晶圓背側包含以一水溶液移除該水溶性遮罩。
- 如請求項8所述之方法,其中從該晶圓背側雷射劃線包含利用一飛秒基雷射劃線製程。
- 如請求項8所述之方法,其中從該晶圓背側雷射劃線包含利用一皮秒基雷射劃線製程。
- 如請求項8所述之方法,其中該晶圓背側包括多個背側金屬化與介電層,該晶圓前側包括多個裝置層。
- 如請求項8所述之方法,其中該晶圓係一單晶矽基板。
- 一種切割一半導體晶圓的方法,該半導體晶圓包含複數個積體電路,該等積體電路被一半導體晶圓前側的一保護帶覆蓋,並且包含在一半導體晶圓背側的一金屬化層,該方法包含:露出一晶粒附接膜,該晶粒附接膜置於該半導體晶圓背側上;塗鋪一遮罩至該半導體晶圓背側上露出的該晶粒附接 膜;從該半導體晶圓背側雷射劃線,以切穿該遮罩、該晶粒附接膜、該半導體晶圓背側上的該金屬化層、該半導體晶圓和該半導體晶圓前側上的該等積體電路;電漿蝕刻以處理或清洗由該雷射劃線所露出該半導體晶圓的多個表面;及塗鋪一切割帶至經雷射劃線的該半導體晶圓背側。
- 如請求項15所述之方法,其中塗鋪該遮罩至該半導體晶圓背側包含塗鋪一水溶性遮罩至該半導體晶圓背側。
- 如請求項16所述之方法,進一步包含:在該雷射劃線之後及在塗鋪一第二切割帶之前,以一水溶液移除該水溶性遮罩,以清洗該半導體晶圓背側。
- 如請求項15所述之方法,其中從該半導體晶圓背側雷射劃線包含利用一飛秒基雷射劃線製程。
- 如請求項15所述之方法,其中從該半導體晶圓背側雷射劃線包含利用一皮秒基雷射劃線製程。
- 如請求項15所述之方法,其中該晶圓係一單晶矽基板。
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