TWI637491B - 非揮發性記憶體 - Google Patents
非揮發性記憶體 Download PDFInfo
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- TWI637491B TWI637491B TW106112112A TW106112112A TWI637491B TW I637491 B TWI637491 B TW I637491B TW 106112112 A TW106112112 A TW 106112112A TW 106112112 A TW106112112 A TW 106112112A TW I637491 B TWI637491 B TW I637491B
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- gate structure
- volatile memory
- substrate
- item
- floating gate
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- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000010410 layer Substances 0.000 claims description 57
- 229910021332 silicide Inorganic materials 0.000 claims description 24
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 239000011241 protective layer Substances 0.000 claims description 12
- 238000002955 isolation Methods 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 239000002356 single layer Substances 0.000 claims description 4
- 125000005842 heteroatom Chemical group 0.000 claims 1
- 238000000034 method Methods 0.000 description 37
- 239000000463 material Substances 0.000 description 15
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 238000005192 partition Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
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- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
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- G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
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- G—PHYSICS
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
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- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
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- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
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- G11C8/14—Word line organisation; Word line lay-out
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
Abstract
一種非揮發性記憶體,包括多個記憶胞。各個記憶胞包括基底、浮置閘極結構、選擇閘極結構與第一摻雜區。浮置閘極結構設置於基底上。選擇閘極結構設置於基底上,且位於浮置閘極結構的一側。第一摻雜區設置於浮置閘極結構的另一側的基底中。相鄰兩個記憶胞之間的第一摻雜區相鄰且彼此分離。
Description
本發明是有關於一種記憶體結構,且特別是有關於一種非揮發性記憶體。
由於非揮發性記憶體具有存入的資料在斷電後也不會消失的優點,因此許多電器產品中必須具備此類記憶體,以維持電器產品開機時的正常操作。然而,在非揮發性記憶體中,相鄰的記憶胞在進行程式化操作時,容易產生程式化干擾(program disturbance)的問題。
本發明提供一種非揮發性記憶體,其可有效地防止在相鄰的記憶胞之間產生程式化干擾。
本發明提出一種非揮發性記憶體,包括多個記憶胞。各個記憶胞包括基底、浮置閘極結構、選擇閘極結構與第一摻雜區。浮置閘極結構設置於基底上。選擇閘極結構設置於基底上,且位於浮置閘極結構的一側。第一摻雜區設置於浮置閘極結構的另一側的基底中。相鄰兩個記憶胞之間的第一摻雜區相鄰且彼此分離。
依照本發明的一實施例所述,在上述的非揮發性記憶體中,相鄰兩個記憶胞可為鏡像對稱。
依照本發明的一實施例所述,在上述的非揮發性記憶體中,更包括多個第一接觸窗。第一接觸窗分別耦接至第一摻雜區且彼此分離設置。
依照本發明的一實施例所述,在上述的非揮發性記憶體中,第一接觸窗可彼此耦接。
依照本發明的一實施例所述,在上述的非揮發性記憶體中,更包括第一內連線結構。第一接觸窗藉由第一內連線結構進行耦接。
依照本發明的一實施例所述,在上述的非揮發性記憶體中,更包括隔離結構。隔離結構設置於相鄰的第一摻雜區之間。
依照本發明的一實施例所述,在上述的非揮發性記憶體中,各個記憶胞更包括第二摻雜區與第三摻雜區。第二摻雜區與第三摻雜區分別設置於選擇閘極結構的一側與另一側的基底中。第三摻雜區位於選擇閘極結構與浮置閘極結構之間。
依照本發明的一實施例所述,在上述的非揮發性記憶體中,更包括第二接觸窗。第二接觸窗耦接至各個記憶胞中的第二摻雜區。
依照本發明的一實施例所述,在上述的非揮發性記憶體中,更包括第二內連線結構。第二內連線結構耦接至第二接觸窗。
依照本發明的一實施例所述,在上述的非揮發性記憶體中,更包括保護層。保護層覆蓋浮置閘極結構。
依照本發明的一實施例所述,在上述的非揮發性記憶體中,保護層可延伸至浮置閘極結構與選擇閘極結構之間。
依照本發明的一實施例所述,在上述的非揮發性記憶體中,保護層更可延伸至選擇閘極結構上方且覆蓋部分選擇閘極結構。
依照本發明的一實施例所述,在上述的非揮發性記憶體中,更包括終止層。終止層設置於保護層上且覆蓋浮置閘極結構與選擇閘極結構。
依照本發明的一實施例所述,在上述的非揮發性記憶體中,浮置閘極結構包括浮置閘極與第一介電層。浮置閘極設置於基底上。第一介電層設置於浮置閘極與基底之間。
依照本發明的一實施例所述,在上述的非揮發性記憶體中,浮置閘極例如是單層的摻雜多晶矽層。
依照本發明的一實施例所述,在上述的非揮發性記憶體中,浮置閘極不耦接至任何外部電壓。
依照本發明的一實施例所述,在上述的非揮發性記憶體中,選擇閘極結構包括選擇閘極與第二介電層。選擇閘極設置於基底上。第二介電層設置於選擇閘極與基底之間。
依照本發明的一實施例所述,在上述的非揮發性記憶體中,選擇閘極耦接至外部電壓。
依照本發明的一實施例所述,在上述的非揮發性記憶體中,選擇閘極結構更包括金屬矽化物層。金屬矽化物層設置於選擇閘極上。
依照本發明的一實施例所述,在上述的非揮發性記憶體中,非揮發性記憶體可為記憶體陣列,且記憶體陣列是以上述相鄰兩個記憶胞作為基本單元重複排列而成。
基於上述,在本發明所提出的非揮發性記憶體中,相鄰兩個記憶胞之間的第一摻雜區相鄰且彼此分離。藉此,在對選定的記憶胞進行程式化操作時,可有效地防止在相鄰的記憶胞之間產生程式化干擾,進而可提升記憶體元件的操作效能。
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
圖1為本發明一實施例的非揮發性記憶體的上視圖。圖2為沿圖1中的I-I’剖面線的剖面圖。圖1省略繪示圖2中的部分構件,以更清楚地描述其餘構件之間的關係。
請同時參照圖1與圖2,非揮發性記憶體100,包括多個記憶胞MC。各個記憶胞MC包括基底102、浮置閘極結構104、選擇閘極結構106與摻雜區108。非揮發性記憶體100例如是反或(NOR)型非揮發性記憶體。基底102例如是矽基底。此外,多個記憶胞MC可共用基底102。
浮置閘極結構104設置於基底102上。浮置閘極結構104包括浮置閘極110與介電層112。浮置閘極110設置於基底102上。浮置閘極110例如是單層的摻雜多晶矽層。浮置閘極110的形成方法例如是化學氣相沉積法。在此實施例中,浮置閘極110是以不耦接至任何外部電壓為例來進行說明。介電層112設置於浮置閘極110與基底102之間。介電層112的材料例如是氧化矽。介電層112的形成方法例如是熱氧化法或化學氣相沉積法。
此外,浮置閘極結構104更可包括間隙壁114。間隙壁114設置於浮置閘極110的側壁上。間隙壁114的材料例如是氮化矽。間隙壁114的形成方法例如是化學氣相沉積法。
選擇閘極結構106設置於基底102上,且位於浮置閘極結構104的一側。選擇閘極結構106包括選擇閘極116與介電層118。選擇閘極116設置於基底102上。選擇閘極116的材料例如是摻雜多晶矽。選擇閘極116的形成方法例如是化學氣相沉積法。在此實施例中,選擇閘極116是以耦接至外部電壓為例來進行說明。介電層118設置於選擇閘極116與基底102之間。介電層118的材料例如是氧化矽。介電層118的形成方法例如是熱氧化法或化學氣相沉積法。
此外,選擇閘極結構106更可包括金屬矽化物層120與間隙壁122中的至少一者。金屬矽化物層120設置於選擇閘極116上。金屬矽化物層120的材料例如是矽化鈷或矽化鎳(cobalt/nickel silicide)。金屬矽化物層120的形成方法例如是進行自對準金屬矽化物製程。間隙壁122設置於選擇閘極116的側壁上。間隙壁122的材料例如是氮化矽。間隙壁122的形成方法例如是化學氣相沉積法。
摻雜區108設置於浮置閘極結構104的另一側的基底102中。相鄰兩個記憶胞MC之間的摻雜區108相鄰且彼此分離,藉此可有效地防止在相鄰的記憶胞MC之間產生程式化干擾。上述相鄰兩個記憶胞MC可為鏡像對稱。摻雜區108可為P型摻雜區或N型摻雜區。摻雜區108的形成方法例如是離子植入法。
各個記憶胞MC更包括摻雜區124與摻雜區126。摻雜區124與摻雜區126分別設置於選擇閘極結構106的一側與另一側的基底102中。摻雜區126位於選擇閘極結構106與浮置閘極結構104之間。摻雜區124與摻雜區126分別可為P型摻雜區或N型摻雜區。摻雜區124與摻雜區126的形成方法例如是離子植入法。
非揮發性記憶體100更可包括多個接觸窗128、內連線結構130、隔離結構132、接觸窗134、內連線結構136、金屬矽化物層138、金屬矽化物層140、保護層142、終止層144與介電層146中的至少一者。
接觸窗128分別耦接至摻雜區108且彼此分離設置。接觸窗128可彼此耦接。舉例來說,接觸窗128可藉由內連線結構130進行耦接,且可藉由內連線結構130耦接至位元線(未繪示)。接觸窗128的材料例如是鎢。內連線結構130的材料例如是銅或鋁。接觸窗128與內連線結構130的形成方法例如是金屬鑲嵌法或是組合使用沉積製程、微影製程與蝕刻製程。
隔離結構132設置於相鄰的摻雜區108之間,用以隔離相鄰的摻雜區108。隔離結構132例如是淺溝渠隔離結構(STI)。隔離結構132的材料例如是氧化矽。
接觸窗134耦接至各個記憶胞MC中的摻雜區124。內連線結構136耦接至接觸窗134。摻雜區124可藉由內連線結構136耦接至源極線(未繪示)。接觸窗134的材料例如是鎢。內連線結構136的材料例如是銅或鋁。接觸窗134與內連線結構136的形成方法例如是金屬鑲嵌法或是組合使用沉積製程、微影製程與蝕刻製程。
在圖2中,內連線結構130與內連線結構136僅為示意性的繪示,本發明並不以此為限。實際上,內連線結構130與內連線結構136可為導線或導線與插塞的組合,所屬技術領域具有通常知識者可依照需求對內連線結構130與內連線結構136的型態進行設計與調整。
金屬矽化物層138與金屬矽化物層140分別設置於摻雜區108與摻雜區124上。金屬矽化物層138與金屬矽化物層140的材料例如是矽化鈷或矽化鎳。金屬矽化物層138與金屬矽化物層140的形成方法例如是進行自對準金屬矽化物製程。
保護層142覆蓋浮置閘極結構104。保護層142可用以暴露出要形成金屬矽化物層120、金屬矽化物層138與金屬矽化物層140的部分。保護層142的材料例如是氧化矽。保護層142的形成方法例如是化學氣相沉積法。在此實施例中,保護層142可延伸至浮置閘極結構104與選擇閘極結構106之間。在另一實施例中,保護層142更可延伸至選擇閘極結構106上方且覆蓋部分選擇閘極結構106。
終止層144設置於保護層142上且覆蓋浮置閘極結構104與選擇閘極結構106,可用以作為蝕刻終止層。終止層144的材料例如是氮化矽。終止層144的形成方法例如是化學氣相沉積法。
介電層146設置於終止層144上,且可暴露出內連線結構130與內連線結構136。介電層146可為單層結構或多層結構。介電層146的材料例如是氧化矽。介電層146的形成方法例如是化學氣相沉積法。
此外,非揮發性記憶體100可為記憶體陣列,且記憶體陣列是以上述相鄰兩個記憶胞MC作為基本單元重複排列而成。在圖1的記憶體陣列中,字元線WL可將位於X方向上的多個選擇閘極116進行耦接。在此實施例中,選擇閘極116可為字元線WL的一部分,但本發明並不以此為限。位元線(未繪示)可將位於Y方向上的多個摻雜區108進行耦接。源極線(未繪示)可將位於Y方向上的多個摻雜區124進行耦接。此外,所屬技術領域具有通常知識者可依據實際需求對記憶體陣列的字元線、位元線與源極線的配線方式與數量進行設計與調整。
基於上述實施例可知,在非揮發性記憶體100中,相鄰兩個記憶胞MC之間的摻雜區108相鄰且彼此分離。藉此,在對選定的記憶胞MC進行程式化操作時,可有效地防止在相鄰的記憶胞MC之間產生程式化干擾,進而可提升記憶體元件的操作效能。
圖3為圖1的非揮發性記憶體的電路簡圖。在圖3中,依序對字元線、位元線與源極線進行標號。
請同時參照圖1與圖3,非揮發性記憶體100包括多個記憶胞MC、字元線WL1~字元線WL10、位元線BL1~位元線BL4與源極線SL1~源極線SL4。記憶胞MC的選擇閘極116分別耦接至字元線WL1~字元線WL10,記憶胞MC的摻雜區108分別耦接至位元線BL1~位元線BL4,記憶胞MC的摻雜區124分別耦接至源極線SL1~源極線SL4,而形成記憶體陣列。此外,所屬技術領域具有通常知識者可依照需求對記憶體陣列中的字元線、位元線與源極線的數量進行調整。在另一實施例中,源極線SL1~源極線SL4可全部連接在一起。
圖4為本發明一實施例的非揮發性記憶體的上視圖。
請同時參照圖1與圖4,圖4的非揮發性記憶體200與圖1的非揮發性記憶體100的差異如下。圖1的非揮發性記憶體100為單一記憶胞中儲存一位元資料(one-cell-per-bit)類型的記憶體,而圖4的非揮發性記憶體200為兩個記憶胞中儲存一位元資料(two-cells-per-bit)類型的記憶體。詳細來說,圖1的內連線結構130僅將在Y方向上相鄰的接觸窗128進行耦接。圖4的內連線結構130a除了將在Y方向上相鄰的接觸窗128進行耦接之外,且內連線結構130a更將在X方向上相鄰兩個記憶胞MC中的接觸窗128進行耦接。此外,在圖4的非揮發性記憶體200中,可將圖1中在X方向上相鄰的兩個記憶胞MC中的摻雜區124藉由摻雜的方式進行連接而形成摻雜區124a。如此一來,可使得圖4的非揮發性記憶體200為兩個記憶胞中儲存一位元資料(two cells per bit)類型的記憶體,藉此可使得非揮發性記憶體200具有更高的可靠度。此外,在圖4的非揮發性記憶體200中,可將圖1中在X方向上相鄰的兩個記憶胞MC中的摻雜區126進行連接而形成摻雜區126a。另外,摻雜區124a的形狀與摻雜區126a的形狀是並不限於圖4中的形狀,所屬技術領域具有通常知識者可依照產品設計需求對摻雜區124a的形狀與摻雜區126a的形狀進行調整。在另一實施例中,亦可將圖1中在X方向上相鄰的兩個記憶胞MC中的摻雜區124藉由內連線結構(未繪示)進行連接,來取代藉由摻雜的方式進行連接。
綜上所述,在上述實施例的非揮發性記憶體中,由於相鄰兩個記憶胞之間的摻雜區相鄰且彼此分離(亦即,相鄰兩個記憶胞之間的摻雜區物理性地隔離(physically isolated)),因此可有效地防止在相鄰的記憶胞之間產生程式化干擾,進而可提升記憶體元件的操作效能。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100、200‧‧‧非揮發性記憶體
102‧‧‧基底
104‧‧‧浮置閘極結構
106‧‧‧選擇閘極結構
108、124、124a、126、126a‧‧‧摻雜區
110‧‧‧浮置閘極
112、118、146‧‧‧介電層
114、122‧‧‧間隙壁
116‧‧‧選擇閘極
120、138、140‧‧‧金屬矽化物層
128、134‧‧‧接觸窗
130、130a、136‧‧‧內連線結構
132‧‧‧隔離結構
142‧‧‧保護層
144‧‧‧終止層
MC‧‧‧記憶胞
BL1~BL4‧‧‧位元線
SL1~SL4‧‧‧源極線
WL、WL1~WL10‧‧‧字元線
X、Y‧‧‧方向
圖1為本發明一實施例的非揮發性記憶體的上視圖。 圖2為沿圖1中的I-I’剖面線的剖面圖。 圖3為圖1的非揮發性記憶體的電路簡圖。 圖4為本發明另一實施例的非揮發性記憶體的上視圖。
Claims (18)
- 一種非揮發性記憶體,包括多個記憶胞,且各該記憶胞包括:一基底;一浮置閘極結構,設置於該基底上;一選擇閘極結構,設置於該基底上,且位於該浮置閘極結構的一側;以及一第一摻雜區,設置於該浮置閘極結構的另一側的該基底中,其中相鄰兩個記憶胞之間的該些第一摻雜區相鄰且彼此分離,且該相鄰兩個記憶胞為鏡像對稱。
- 如申請專利範圍第1項所述的非揮發性記憶體,更包括多個第一接觸窗,分別耦接至該些第一摻雜區且彼此分離設置。
- 如申請專利範圍第2項所述的非揮發性記憶體,其中該些第一接觸窗彼此耦接。
- 如申請專利範圍第3項所述的非揮發性記憶體,更包括一第一內連線結構,其中該些第一接觸窗藉由該第一內連線結構進行耦接。
- 如申請專利範圍第1項所述的非揮發性記憶體,更包括一隔離結構,設置於相鄰的該些第一摻雜區之間。
- 如申請專利範圍第1項所述的非揮發性記憶體,更包括一保護層,覆蓋該浮置閘極結構。
- 如申請專利範圍第6項所述的非揮發性記憶體,其中該保護層延伸至該浮置閘極結構與該選擇閘極結構之間。
- 如申請專利範圍第7項所述的非揮發性記憶體,其中該保護層更延伸至該選擇閘極結構上方且覆蓋部分該選擇閘極結構。
- 如申請專利範圍第6項所述的非揮發性記憶體,更包括一終止層,設置於該保護層上且覆蓋該浮置閘極結構與該選擇閘極結構。
- 如申請專利範圍第1項所述的非揮發性記憶體,其中該浮置閘極結構包括:一浮置閘極,設置於該基底上;以及一第一介電層,設置於該浮置閘極與該基底之間。
- 如申請專利範圍第10項所述的非揮發性記憶體,其中該浮置閘極包括單層的摻雜多晶矽層。
- 如申請專利範圍第10項所述的非揮發性記憶體,其中該浮置閘極不耦接至任何外部電壓。
- 如申請專利範圍第1項所述的非揮發性記憶體,其中該選擇閘極結構包括:一選擇閘極,設置於該基底上;以及一第二介電層,設置於該選擇閘極與該基底之間。
- 如申請專利範圍第13項所述的非揮發性記憶體,其中該選擇閘極耦接至外部電壓。
- 如申請專利範圍第13項所述的非揮發性記憶體,其中該選擇閘極結構更包括一金屬矽化物層,設置於該選擇閘極上。
- 如申請專利範圍第1項所述的非揮發性記憶體,其中非揮發性記憶體包括一記憶體陣列,且該記憶體陣列是以該相鄰兩個記憶胞作為基本單元重複排列而成。
- 一種非揮發性記憶體,包括多個記憶胞,且各該記憶胞包括:一基底;一浮置閘極結構,設置於該基底上;一選擇閘極結構,設置於該基底上,且位於該浮置閘極結構的一側;一第一摻雜區,設置於該浮置閘極結構的另一側的該基底中,其中相鄰兩個記憶胞之間的該些第一摻雜區相鄰且彼此分離;一第二摻雜區與一第三摻雜區,分別設置於該選擇閘極結構的一側與另一側的該基底中,其中該第三摻雜區位於該選擇閘極結構與該浮置閘極結構之間;以及一第二接觸窗,耦接至各該記憶胞中的該第二摻雜區。
- 如申請專利範圍第17項所述的非揮發性記憶體,更包括一第二內連線結構,耦接至該第二接觸窗。
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