TWI621161B - 用於內連線的釕金屬特徵部填補 - Google Patents

用於內連線的釕金屬特徵部填補 Download PDF

Info

Publication number
TWI621161B
TWI621161B TW105117505A TW105117505A TWI621161B TW I621161 B TWI621161 B TW I621161B TW 105117505 A TW105117505 A TW 105117505A TW 105117505 A TW105117505 A TW 105117505A TW I621161 B TWI621161 B TW I621161B
Authority
TW
Taiwan
Prior art keywords
feature
substrate
metal layer
filling
gas
Prior art date
Application number
TW105117505A
Other languages
English (en)
Chinese (zh)
Other versions
TW201709293A (zh
Inventor
Kai-Hung YU
尤凱鴻
Gerrit J. Leusink
赫里特 Ｊ 盧森克
Cory Wajda
科瑞 瓦伊達
Tadahiro Ishizaka
石坂忠大
Takahiro Hakamata
袴田隆宏
Original Assignee
Tokyo Electron Limited
東京威力科創股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Limited, 東京威力科創股份有限公司 filed Critical Tokyo Electron Limited
Publication of TW201709293A publication Critical patent/TW201709293A/zh
Application granted granted Critical
Publication of TWI621161B publication Critical patent/TWI621161B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01342—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid by deposition, e.g. evaporation, ALD or laser deposition
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/16—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal carbonyl compounds
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • C23C16/45553—Atomic layer deposition [ALD] characterized by the use of precursors specially adapted for ALD
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/46—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/059—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by reflowing or applying pressure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/096—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by contacting with gases, liquids or plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4432—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H10P14/432—Chemical deposition, e.g. chemical vapour deposition [CVD] using selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/045—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD]

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
TW105117505A 2015-06-05 2016-06-03 用於內連線的釕金屬特徵部填補 TWI621161B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201562171739P 2015-06-05 2015-06-05
US62/171,739 2015-06-05

Publications (2)

Publication Number Publication Date
TW201709293A TW201709293A (zh) 2017-03-01
TWI621161B true TWI621161B (zh) 2018-04-11

Family

ID=57441803

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105117505A TWI621161B (zh) 2015-06-05 2016-06-03 用於內連線的釕金屬特徵部填補

Country Status (6)

Country Link
US (2) US9711449B2 (https=)
JP (1) JP7066929B2 (https=)
KR (1) KR102542758B1 (https=)
CN (1) CN107836034B (https=)
TW (1) TWI621161B (https=)
WO (1) WO2016196937A1 (https=)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10049927B2 (en) 2016-06-10 2018-08-14 Applied Materials, Inc. Seam-healing method upon supra-atmospheric process in diffusion promoting ambient
US10541174B2 (en) 2017-01-20 2020-01-21 Tokyo Electron Limited Interconnect structure and method of forming the same
US10224224B2 (en) 2017-03-10 2019-03-05 Micromaterials, LLC High pressure wafer processing systems and related methods
US10622214B2 (en) 2017-05-25 2020-04-14 Applied Materials, Inc. Tungsten defluorination by high pressure treatment
JP6947914B2 (ja) 2017-08-18 2021-10-13 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ 高圧高温下のアニールチャンバ
US10276411B2 (en) 2017-08-18 2019-04-30 Applied Materials, Inc. High pressure and high temperature anneal chamber
JP7277871B2 (ja) * 2017-10-04 2023-05-19 東京エレクトロン株式会社 相互接続のためのルテニウム金属機能フィリング
US10790188B2 (en) 2017-10-14 2020-09-29 Applied Materials, Inc. Seamless ruthenium gap fill
US10672649B2 (en) 2017-11-08 2020-06-02 International Business Machines Corporation Advanced BEOL interconnect architecture
EP4321649B1 (en) 2017-11-11 2025-08-20 Micromaterials LLC Gas delivery system for high pressure processing chamber
JP2021503714A (ja) 2017-11-17 2021-02-12 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ 高圧処理システムのためのコンデンサシステム
US10269698B1 (en) 2017-12-20 2019-04-23 International Business Machines Corporation Binary metallization structure for nanoscale dual damascene interconnects
TWI799494B (zh) 2018-01-19 2023-04-21 荷蘭商Ａｓｍ 智慧財產控股公司 沈積方法
SG11202008256WA (en) 2018-03-09 2020-09-29 Applied Materials Inc High pressure annealing process for metal containing materials
US10950429B2 (en) 2018-05-08 2021-03-16 Applied Materials, Inc. Methods of forming amorphous carbon hard mask layers and hard mask layers formed therefrom
US10748783B2 (en) 2018-07-25 2020-08-18 Applied Materials, Inc. Gas delivery module
JP7547037B2 (ja) * 2018-08-20 2024-09-09 エーエスエム・アイピー・ホールディング・ベー・フェー 周期的堆積プロセスによって基材の誘電体表面上にモリブデン金属膜を堆積させる方法および関連する半導体デバイス構造
JP7182970B2 (ja) * 2018-09-20 2022-12-05 東京エレクトロン株式会社 埋め込み方法及び処理システム
US11631680B2 (en) 2018-10-18 2023-04-18 Applied Materials, Inc. Methods and apparatus for smoothing dynamic random access memory bit line metal
WO2020117462A1 (en) 2018-12-07 2020-06-11 Applied Materials, Inc. Semiconductor processing system
US20200279943A1 (en) * 2019-02-28 2020-09-03 Tokyo Electron Limited Dual silicide wrap-around contacts for semiconductor devices
US11901222B2 (en) 2020-02-17 2024-02-13 Applied Materials, Inc. Multi-step process for flowable gap-fill film
JP7206355B2 (ja) * 2020-11-12 2023-01-17 アプライド マテリアルズ インコーポレイテッド ダイナミックランダムアクセスメモリビット線金属を滑らかにするための方法及び装置
US20220165852A1 (en) * 2020-11-23 2022-05-26 Applied Materials, Inc. Methods and apparatus for metal fill in metal gate stack
US20220223472A1 (en) 2021-01-11 2022-07-14 Applied Materials, Inc. Ruthenium Reflow For Via Fill
KR102659491B1 (ko) * 2021-08-12 2024-04-23 한국과학기술연구원 배선 재료용 저저항 필름의 제조 방법
US20240282709A1 (en) * 2023-02-22 2024-08-22 Applied Materials, Inc. Layered Substrate with Ruthenium Layer and Method for Producing
US20240355673A1 (en) * 2023-04-20 2024-10-24 Applied Materials, Inc. Hybrid molybdenum fill scheme for low resistivity semiconductor applications
US20240363410A1 (en) * 2023-04-25 2024-10-31 Tokyo Electron Limited Methods for making semiconductor devices that include metal cap layers

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090130843A1 (en) * 2007-09-27 2009-05-21 Tokyo Electron Limited Method of forming low-resistivity recessed features in copper metallization

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6475903B1 (en) 1993-12-28 2002-11-05 Intel Corporation Copper reflow process
JP3393436B2 (ja) * 1996-12-03 2003-04-07 ソニー株式会社 配線の形成方法
JPH10209157A (ja) * 1997-01-21 1998-08-07 Hitachi Ltd 半導体装置の製造方法
KR100227843B1 (ko) * 1997-01-22 1999-11-01 윤종용 반도체 소자의 콘택 배선 방법 및 이를 이용한 커패시터 제조방법
KR100230418B1 (ko) * 1997-04-17 1999-11-15 윤종용 백금족 금속층 형성방법 및 이를 이용한 커패시터 제조방법
JP2000091269A (ja) * 1998-09-10 2000-03-31 Fujitsu Ltd 半導体装置の製造方法
KR100408410B1 (ko) * 2001-05-31 2003-12-06 삼성전자주식회사 엠아이엠(ｍｉｍ) 커패시터를 갖는 반도체 소자 및 그제조 방법
KR100416602B1 (ko) * 2001-08-08 2004-02-05 삼성전자주식회사 스택형 캐패시터의 제조 방법
US7270848B2 (en) * 2004-11-23 2007-09-18 Tokyo Electron Limited Method for increasing deposition rates of metal layers from metal-carbonyl precursors
US7273814B2 (en) 2005-03-16 2007-09-25 Tokyo Electron Limited Method for forming a ruthenium metal layer on a patterned substrate
TW200734482A (en) * 2005-03-18 2007-09-16 Applied Materials Inc Electroless deposition process on a contact containing silicon or silicide
US20070059502A1 (en) * 2005-05-05 2007-03-15 Applied Materials, Inc. Integrated process for sputter deposition of a conductive barrier layer, especially an alloy of ruthenium and tantalum, underlying copper or copper alloy seed layer
US7968455B2 (en) * 2006-10-17 2011-06-28 Enthone Inc. Copper deposition for filling features in manufacture of microelectronic devices
US7829454B2 (en) 2007-09-11 2010-11-09 Tokyo Electron Limited Method for integrating selective ruthenium deposition into manufacturing of a semiconductior device
US7776740B2 (en) * 2008-01-22 2010-08-17 Tokyo Electron Limited Method for integrating selective low-temperature ruthenium deposition into copper metallization of a semiconductor device
JP2010067638A (ja) * 2008-09-08 2010-03-25 Tokyo Electron Ltd ルテニウム膜の成膜方法
JP2010199349A (ja) 2009-02-26 2010-09-09 Toshiba Corp 半導体装置の製造方法
TWI536451B (zh) * 2010-04-26 2016-06-01 應用材料股份有限公司 使用具金屬系前驅物之化學氣相沉積與原子層沉積製程之ｎ型金氧半導體金屬閘極材料、製造方法及設備
US8637390B2 (en) * 2010-06-04 2014-01-28 Applied Materials, Inc. Metal gate structures and methods for forming thereof
US9048296B2 (en) * 2011-02-11 2015-06-02 International Business Machines Corporation Method to fabricate copper wiring structures and structures formed thereby
JP5862353B2 (ja) * 2011-08-05 2016-02-16 東京エレクトロン株式会社 半導体装置の製造方法
KR101444527B1 (ko) * 2011-08-05 2014-09-24 도쿄엘렉트론가부시키가이샤 반도체 장치의 제조 방법
KR20130096949A (ko) * 2012-02-23 2013-09-02 삼성전자주식회사 반도체 소자의 형성 방법
US8517769B1 (en) 2012-03-16 2013-08-27 Globalfoundries Inc. Methods of forming copper-based conductive structures on an integrated circuit device
US9245798B2 (en) 2012-04-26 2016-01-26 Applied Matrials, Inc. Semiconductor reflow processing for high aspect ratio fill
TWI576961B (zh) * 2012-04-26 2017-04-01 應用材料股份有限公司 用於高深寬比塡充的半導體重流處理
JP2014033139A (ja) * 2012-08-06 2014-02-20 Ulvac Japan Ltd デバイスの製造方法
EP2779224A3 (en) * 2013-03-15 2014-12-31 Applied Materials, Inc. Methods for producing interconnects in semiconductor devices
JP2014204014A (ja) * 2013-04-08 2014-10-27 三菱電機株式会社 半導体装置およびその製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090130843A1 (en) * 2007-09-27 2009-05-21 Tokyo Electron Limited Method of forming low-resistivity recessed features in copper metallization

Also Published As

Publication number Publication date
JP7066929B2 (ja) 2022-05-16
KR102542758B1 (ko) 2023-06-12
US10056328B2 (en) 2018-08-21
TW201709293A (zh) 2017-03-01
US20170317022A1 (en) 2017-11-02
US20160358815A1 (en) 2016-12-08
JP2018516465A (ja) 2018-06-21
CN107836034B (zh) 2022-07-19
WO2016196937A1 (en) 2016-12-08
KR20180005743A (ko) 2018-01-16
CN107836034A (zh) 2018-03-23
US9711449B2 (en) 2017-07-18

Similar Documents

Publication Publication Date Title
TWI621161B (zh) 用於內連線的釕金屬特徵部填補
CN102881675B (zh) 用于高性能互连的结构和方法
US8058728B2 (en) Diffusion barrier and adhesion layer for an interconnect structure
US8766372B2 (en) Copper-filled trench contact for transistor performance improvement
US8372739B2 (en) Diffusion barrier for integrated circuits formed from a layer of reactive metal and method of fabrication
US7727883B2 (en) Method of forming a diffusion barrier and adhesion layer for an interconnect structure
US7521358B2 (en) Process integration scheme to lower overall dielectric constant in BEoL interconnect structures
JP7277871B2 (ja) 相互接続のためのルテニウム金属機能フィリング
JP7492618B2 (ja) 二重金属電力レールを有する集積回路の製造方法
US9318383B2 (en) Integrated cluster to enable next generation interconnect
TW200522264A (en) Method for forming metal wiring in semiconductor device
US20170194192A1 (en) Metal filling and planarization of recessed features
JP4457884B2 (ja) 半導体装置
JP2009010037A (ja) 半導体装置及びその製造方法
TW455954B (en) Manufacturing process using thermal annealing process to reduce the generation of hillock on the surface of Cu damascene structure
US20180053688A1 (en) Method of metal filling recessed features in a substrate
JP2004031497A (ja) 半導体装置およびその製造方法
JP2004014816A (ja) 半導体製造方法および半導体装置