TWI517151B - 半導體記憶裝置 - Google Patents
半導體記憶裝置 Download PDFInfo
- Publication number
- TWI517151B TWI517151B TW103122670A TW103122670A TWI517151B TW I517151 B TWI517151 B TW I517151B TW 103122670 A TW103122670 A TW 103122670A TW 103122670 A TW103122670 A TW 103122670A TW I517151 B TWI517151 B TW I517151B
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- Taiwan
- Prior art keywords
- signal
- circuit
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- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 54
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- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 49
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- 101100058943 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CAK1 gene Proteins 0.000 description 9
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- MKXZASYAUGDDCJ-NJAFHUGGSA-N dextromethorphan Chemical compound C([C@@H]12)CCC[C@]11CCN(C)[C@H]2CC2=CC=C(OC)C=C21 MKXZASYAUGDDCJ-NJAFHUGGSA-N 0.000 description 6
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- 101001128135 Homo sapiens NACHT, LRR and PYD domains-containing protein 4 Proteins 0.000 description 4
- 101000982939 Homo sapiens PAN2-PAN3 deadenylation complex catalytic subunit PAN2 Proteins 0.000 description 4
- 101000742934 Homo sapiens Retinol dehydrogenase 14 Proteins 0.000 description 4
- 102100031898 NACHT, LRR and PYD domains-containing protein 4 Human genes 0.000 description 4
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- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 4
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- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 3
- 101001109455 Homo sapiens NACHT, LRR and PYD domains-containing protein 6 Proteins 0.000 description 3
- 101001113056 Homo sapiens PAN2-PAN3 deadenylation complex subunit PAN3 Proteins 0.000 description 3
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- 102100040856 Dual specificity protein kinase CLK3 Human genes 0.000 description 2
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- 101000749304 Homo sapiens Dual specificity protein kinase CLK3 Proteins 0.000 description 2
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- 102100029469 WD repeat and HMG-box DNA-binding protein 1 Human genes 0.000 description 2
- 101710097421 WD repeat and HMG-box DNA-binding protein 1 Proteins 0.000 description 2
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4061—Calibration or ate or cycle tuning
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004026999A JP2005222581A (ja) | 2004-02-03 | 2004-02-03 | 半導体記憶装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201440044A TW201440044A (zh) | 2014-10-16 |
| TWI517151B true TWI517151B (zh) | 2016-01-11 |
Family
ID=34805858
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW103122670A TWI517151B (zh) | 2004-02-03 | 2005-01-31 | 半導體記憶裝置 |
| TW094102871A TWI383394B (zh) | 2004-02-03 | 2005-01-31 | 半導體記憶裝置 |
| TW100114414A TWI460725B (zh) | 2004-02-03 | 2005-01-31 | 半導體記憶裝置 |
Family Applications After (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW094102871A TWI383394B (zh) | 2004-02-03 | 2005-01-31 | 半導體記憶裝置 |
| TW100114414A TWI460725B (zh) | 2004-02-03 | 2005-01-31 | 半導體記憶裝置 |
Country Status (4)
| Country | Link |
|---|---|
| US (4) | US7336557B2 (enExample) |
| JP (1) | JP2005222581A (enExample) |
| KR (1) | KR101120838B1 (enExample) |
| TW (3) | TWI517151B (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12283309B2 (en) | 2022-04-28 | 2025-04-22 | Winbond Electronics Corp. | Pseudo-static random-access memory and reading method thereof |
Families Citing this family (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6209071B1 (en) | 1996-05-07 | 2001-03-27 | Rambus Inc. | Asynchronous request/synchronous data dynamic random access memory |
| US7245552B2 (en) * | 2005-06-22 | 2007-07-17 | Infineon Technologies Ag | Parallel data path architecture |
| EP2098969A4 (en) * | 2006-12-26 | 2013-01-02 | Nec Corp | LOGIC CIRCUIT DESIGN DEVICE FOR ASYNCHRONOUS LOGIC CIRCUITS, LOGIC CIRCUIT DESIGN METHOD, AND LOGIC CIRCUIT DESIGN PROGRAM |
| KR100856130B1 (ko) * | 2007-01-08 | 2008-09-03 | 삼성전자주식회사 | 동기/ 비동기 동작이 가능한 반도체 메모리 장치 및 상기반도체 메모리 장치의 데이터 입/ 출력 방법 |
| JP4679528B2 (ja) * | 2007-01-30 | 2011-04-27 | 株式会社東芝 | リフレッシュトリガー付き半導体記憶装置 |
| KR100945802B1 (ko) * | 2008-06-24 | 2010-03-08 | 주식회사 하이닉스반도체 | 클럭을 생성하는 반도체 집적 회로 |
| CN101640065B (zh) * | 2008-07-29 | 2012-07-04 | 国际商业机器公司 | 用于嵌入式dram的刷新控制器及刷新控制方法 |
| KR101697686B1 (ko) * | 2009-07-01 | 2017-01-20 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그 구동 방법 |
| JP2011018427A (ja) * | 2009-07-10 | 2011-01-27 | Renesas Electronics Corp | 半導体記憶装置 |
| KR101043722B1 (ko) * | 2010-02-04 | 2011-06-27 | 주식회사 하이닉스반도체 | 레이턴시 제어회로 및 이를 포함하는 반도체 메모리장치 |
| US8422315B2 (en) * | 2010-07-06 | 2013-04-16 | Winbond Electronics Corp. | Memory chips and memory devices using the same |
| KR20120081352A (ko) * | 2011-01-11 | 2012-07-19 | 에스케이하이닉스 주식회사 | 리프레시 제어 회로, 이를 이용한 메모리 장치 및 그 리프레시 제어 방법 |
| JP5932236B2 (ja) * | 2011-04-13 | 2016-06-08 | ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． | 半導体装置及びシステム |
| US9129666B1 (en) * | 2011-08-25 | 2015-09-08 | Rambus Inc. | Robust commands for timing calibration or recalibration |
| TWI498889B (zh) * | 2012-03-26 | 2015-09-01 | Etron Technology Inc | 記憶體及更新記憶體的方法 |
| US9350386B2 (en) | 2012-04-12 | 2016-05-24 | Samsung Electronics Co., Ltd. | Memory device, memory system, and method of operating the same |
| JP2013229068A (ja) * | 2012-04-24 | 2013-11-07 | Ps4 Luxco S A R L | 半導体装置及びこれを備える情報処理システム |
| US8754691B2 (en) | 2012-09-27 | 2014-06-17 | International Business Machines Corporation | Memory array pulse width control |
| JP2014096191A (ja) | 2012-11-09 | 2014-05-22 | Renesas Electronics Corp | 半導体記憶装置 |
| US9064603B1 (en) | 2012-11-28 | 2015-06-23 | Samsung Electronics Co., Ltd. | Semiconductor memory device and memory system including the same |
| US20150003172A1 (en) * | 2013-06-26 | 2015-01-01 | Sua KIM | Memory module including buffer chip controlling refresh operation of memory devices |
| TWI553641B (zh) * | 2013-12-09 | 2016-10-11 | 慧榮科技股份有限公司 | 資料儲存裝置及其模式偵測方法 |
| US9600179B2 (en) * | 2014-07-30 | 2017-03-21 | Arm Limited | Access suppression in a memory device |
| US10394641B2 (en) * | 2017-04-10 | 2019-08-27 | Arm Limited | Apparatus and method for handling memory access operations |
| JP6871286B2 (ja) * | 2019-02-21 | 2021-05-12 | 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． | 疑似スタティックランダムアクセスメモリの制御回路及び制御方法 |
| JP6894459B2 (ja) * | 2019-02-25 | 2021-06-30 | 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． | 疑似スタティックランダムアクセスメモリとその動作方法 |
| KR102861798B1 (ko) * | 2020-05-19 | 2025-09-18 | 에스케이하이닉스 주식회사 | 커맨드 입력을 제어하기 위한 전자장치 |
| TWI740581B (zh) * | 2020-07-20 | 2021-09-21 | 華邦電子股份有限公司 | 虛擬靜態隨機存取記憶體裝置 |
| JP6999791B1 (ja) * | 2020-12-28 | 2022-01-19 | 華邦電子股▲ふん▼有限公司 | 半導体記憶装置 |
| JP2023069655A (ja) | 2021-11-08 | 2023-05-18 | 華邦電子股▲ふん▼有限公司 | 疑似スタティックランダムアクセスメモリ |
| KR102656401B1 (ko) * | 2022-06-23 | 2024-04-09 | 윈본드 일렉트로닉스 코포레이션 | 반도체 기억장치 및 이의 제어 방법 |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6310821B1 (en) * | 1998-07-10 | 2001-10-30 | Kabushiki Kaisha Toshiba | Clock-synchronous semiconductor memory device and access method thereof |
| US5537564A (en) * | 1993-03-08 | 1996-07-16 | Zilog, Inc. | Technique for accessing and refreshing memory locations within electronic storage devices which need to be refreshed with minimum power consumption |
| KR950014089B1 (ko) | 1993-11-08 | 1995-11-21 | 현대전자산업주식회사 | 동기식 디램의 히든 셀프 리프레쉬 방법 및 장치 |
| JPH09259080A (ja) * | 1996-03-19 | 1997-10-03 | Fujitsu Ltd | 半導体装置 |
| JP3625955B2 (ja) * | 1996-04-16 | 2005-03-02 | 沖電気工業株式会社 | 画像用半導体メモリ回路 |
| TW430793B (en) * | 1999-05-20 | 2001-04-21 | Ind Tech Res Inst | Self-row identification hidden-type refresh-circuit and refresh method |
| JP2001035149A (ja) * | 1999-06-30 | 2001-02-09 | Ind Technol Res Inst | 行セルフ識別隠れ式リフレッシュ回路及び方法 |
| KR100311044B1 (ko) * | 1999-10-05 | 2001-10-18 | 윤종용 | 클럭 주파수에 따라 레이턴시 조절이 가능한 레이턴시 결정 회로 및 레이턴시 결정 방법 |
| JP2002324393A (ja) * | 2001-04-25 | 2002-11-08 | Mitsubishi Electric Corp | 半導体記憶装置 |
| KR100390906B1 (ko) * | 2001-05-25 | 2003-07-12 | 주식회사 하이닉스반도체 | 가상형 스태틱 랜덤 억세스 메모리장치 및 그의 구동방법 |
| JP4743999B2 (ja) | 2001-05-28 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
| WO2003005368A1 (fr) * | 2001-07-04 | 2003-01-16 | Hitachi, Ltd. | Dispositif a semiconducteur et module de memoire |
| JP4262912B2 (ja) * | 2001-10-16 | 2009-05-13 | Ｎｅｃエレクトロニクス株式会社 | 半導体記憶装置 |
| JP4022392B2 (ja) * | 2001-12-11 | 2007-12-19 | Ｎｅｃエレクトロニクス株式会社 | 半導体記憶装置およびそのテスト方法並びにテスト回路 |
| JP2003289103A (ja) * | 2002-03-28 | 2003-10-10 | Mitsubishi Electric Corp | 半導体装置と半導体実装装置 |
| JP2003297080A (ja) * | 2002-03-29 | 2003-10-17 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JP2004005821A (ja) * | 2002-05-31 | 2004-01-08 | Toshiba Corp | 同期型半導体記憶装置 |
| JP2004102508A (ja) * | 2002-09-06 | 2004-04-02 | Renesas Technology Corp | 半導体記憶装置 |
| JP4184104B2 (ja) * | 2003-01-30 | 2008-11-19 | 株式会社ルネサステクノロジ | 半導体装置 |
| JP2004259318A (ja) * | 2003-02-24 | 2004-09-16 | Renesas Technology Corp | 同期型半導体記憶装置 |
| JP4191018B2 (ja) * | 2003-11-26 | 2008-12-03 | エルピーダメモリ株式会社 | 半導体記憶装置のリフレッシュ制御方式 |
| JP5038742B2 (ja) * | 2007-03-01 | 2012-10-03 | ルネサスエレクトロニクス株式会社 | セルフリフレッシュ制御回路、半導体装置 |
-
2004
- 2004-02-03 JP JP2004026999A patent/JP2005222581A/ja active Pending
-
2005
- 2005-01-31 TW TW103122670A patent/TWI517151B/zh not_active IP Right Cessation
- 2005-01-31 TW TW094102871A patent/TWI383394B/zh not_active IP Right Cessation
- 2005-01-31 TW TW100114414A patent/TWI460725B/zh not_active IP Right Cessation
- 2005-02-02 KR KR1020050009640A patent/KR101120838B1/ko not_active Expired - Fee Related
- 2005-02-03 US US11/049,059 patent/US7336557B2/en not_active Expired - Fee Related
-
2008
- 2008-01-04 US US12/007,032 patent/US7480200B2/en not_active Expired - Fee Related
- 2008-12-12 US US12/333,913 patent/US7983103B2/en not_active Expired - Fee Related
-
2011
- 2011-04-07 US US13/081,821 patent/US20110199844A1/en not_active Abandoned
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12283309B2 (en) | 2022-04-28 | 2025-04-22 | Winbond Electronics Corp. | Pseudo-static random-access memory and reading method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| US7336557B2 (en) | 2008-02-26 |
| US20050169091A1 (en) | 2005-08-04 |
| TWI383394B (zh) | 2013-01-21 |
| US7983103B2 (en) | 2011-07-19 |
| KR20060041602A (ko) | 2006-05-12 |
| KR101120838B1 (ko) | 2012-06-27 |
| TW200603159A (en) | 2006-01-16 |
| JP2005222581A (ja) | 2005-08-18 |
| US20090091997A1 (en) | 2009-04-09 |
| US7480200B2 (en) | 2009-01-20 |
| US20110199844A1 (en) | 2011-08-18 |
| US20080123456A1 (en) | 2008-05-29 |
| TW201203245A (en) | 2012-01-16 |
| TW201440044A (zh) | 2014-10-16 |
| TWI460725B (zh) | 2014-11-11 |
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