TWI435430B - 具高靜電放電性能之低電壓輸出驅動器 - Google Patents
具高靜電放電性能之低電壓輸出驅動器 Download PDFInfo
- Publication number
- TWI435430B TWI435430B TW096101899A TW96101899A TWI435430B TW I435430 B TWI435430 B TW I435430B TW 096101899 A TW096101899 A TW 096101899A TW 96101899 A TW96101899 A TW 96101899A TW I435430 B TWI435430 B TW I435430B
- Authority
- TW
- Taiwan
- Prior art keywords
- diode
- type
- semiconductor structure
- electrostatic discharge
- floating gate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 claims description 36
- 238000007667 floating Methods 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 23
- 238000000034 method Methods 0.000 description 13
- 230000015556 catabolic process Effects 0.000 description 9
- 238000013461 design Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005421 electrostatic potential Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0626—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a localised breakdown region, e.g. built-in avalanching region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
本申請案請求2006年1月18提出申請、核發給Luo和Demirlioglu的美國臨時申請案第60/760,081號,代理人案號VISH-8759.PRO,名稱為“Low Voltage Output Driver with High Performance Electrostatic Discharge Performance”,為所有目的其全部內容已以參照方式併入本文。
本申請案是2005年7月26日提出申請、核發給Luo等人的共同待決並共同擁有的美國專利申請案第11/190,682號,代理人案號VISH-8744,名稱為“Electrostatic Discharge Protection Circuit for Integrated Circuits”,為所有目的其全部內容已以參照方式併入本文。
本發明的實施例是關於積體電路領域。更特別地,本發明的實施例關於用於積體電路的靜電放電(ESD)防護。
靜電放電(ESD)發生於具有不同靜電電勢之主體之間透過接觸或透過經離子化環境放電進行能量轉移之時。具有不充分ESD防護之積體電路(IC)經受毀滅性失效,包括諸如已破裂鈍化、電熱遷移、已濺汙鋁、接點穿突、介電失效等。可選擇地,ESD事件可損壞元件,即使該元件繼續發揮功效。此類型損壞組成潛在缺陷,其等難於感測並顯著地縮短此等被損壞IC的壽命。
在傳統技藝中,通常依靠輸出(例如,晶片外)驅動電路之物理和電氣尺寸,來提供靜電放電防護。輸出驅動器本體一般是透過利用較大總寬的多指型件結構和較寬的接觸多晶矽間隔,提供增強ESD防護。
但是,針對靜電放電防護之此傳統途徑之有效性隨著積體電路技術的進步而下降。甚至更小元件的幾何尺寸和降低電路面積之總體趨向有利於降低晶片尺寸。因此,用於輸出電路之有用晶粒面積繼續減小,這減少此等輸出電路之ESD吸收/緩解能力。
不幸地,對比以前甚至更高水準的靜電放電防護之需要漸增。這增加了對獨立的ESD元件及用於ESD防護之輸出驅動器之使用。
傳統靜電放電防護電路之一個缺點是它們易遭受閉鎖。既然若ESD在ESD防護電路內造成閉鎖,積體電路可停止作用,因此閉鎖是顯著問題。再者,所生成的無意持續供應電流可破壞IC。
一般而言,輸出驅動器之閘極連接到內電路,例如以接收欲被輸出之信號。此連接形式一般使輸出驅動器回應ESD事件,比如果輸出驅動器閘極接地,快速得多的驟回。為完全保護輸出驅動器,分離的ESD元件必須具有比輸出驅動器的崩潰電壓低的觸發電壓,以及即使在高ESD電流控制時也具有極低導通電阻。
當保持電壓低於ESD防護電路操作電壓且觸發驟回時,因驟回條件可由較高操作電壓維持,因此閉鎖可發生。當驟回觸發電壓設置太高時,如果ESD事件造成比氧化物崩潰電壓大的電壓,則對積體電路的損壞可發生。
IC製造者試圖設計在用於IC應用的ESD防護元件裏之驟回觸發電壓和驟回保持電壓之間具有所需關係的金屬氧化物半導體場效應電晶體(MOSFET)。但是,因為這些參數受到IC製造製程以及電路性能考量之限制。因此,驟回觸發電壓和驟回保持電壓之間之最佳組合並不總是可得。應當瞭解,如果IC之操作電壓比驟回保持電壓高,且ESD事件所造成的操作電壓尖峰驅動MOSFET進入由操作電壓維持的驟回條件,則積體電路可失效。如上所述,這可導致整個IC失效。
因此,存在對具有高靜電放電性能之低電壓輸出驅動器之系統和方法之需要。也存在對也滿足上述需要的驟回觸發電壓和驟回保持電壓之所需組合之需要。進而存在對形成與積體電路設計和製造的既存系統和方法相容和互補之具高靜電放電性能之低電壓輸出驅動器之系統和方法。依據本發明之實施例滿足這些需要。
依據本發明之實施例將二極體元件嵌入一輸出驅動器電路內。
因此,揭示用於具高靜電放電性能之低電壓輸出驅動器之系統和方法。在一個實施例中,半導體結構包括一用於驅動晶片外輸出和浮置場閘極元件之電路。該浮置場閘極元件包括一嵌入二極體,其特徵為具有比齊納二極體低的溫度依賴性。該嵌入二極體之保持電壓可比該嵌入二極體之操作電壓大,且該嵌入二極體之驟回觸發二極體可比該半導體結構之氧化物崩潰電壓低。
依據本發明另一實施例,一種用於驅動一具有增強靜電放電防護的晶片外輸出之半導體結構,包含:耦接到輸出墊之多個第一指型件,及交錯於該等第一指型件之間並耦接到接地墊之多個第二指型件。該半導體結構進而包括插入該等第一指型件和該等第二指型件之間之多個浮置場閘極。該等第一指型件包含一嵌入混成二極體,其特徵為具有一比其操作電壓大的驟回保持電壓和一比該半導體結構之一氧化物崩潰電壓低的驟回觸發電壓。
依據本發明又一實施例,一種半導體結構包含一用於驅動一晶片外輸出之電路。該電路包含一下拉元件。該半導體結構進而包括嵌入該電路之一混成二極體元件,其特徵為具有比該下拉元件的一觸發電壓低的觸發電壓。
依據本發明又另一實施例,一種用於在ESD事件過程中提供防護的一積體電路(IC)之靜電放電(ESD)防護電路,包含一電流流動控制元件和串聯地耦接到該電流流動控制元件之一電流流動方向控制元件。該靜電放電防護電路之一驟回保持電壓比該靜電放電防護電路之一操作電壓大,且該靜電放電防護電路之一驟回觸發電壓比該IC之一氧化物崩潰電壓低。
併入並形成為該說明書的部分之所附圖式,揭示本發明的實施例,並且和詳細說明一起,用於解釋本發明的原理。除非另有表示,圖式沒有依比例繪出。
第1A圖揭示依據本發明實施例,具有高靜電放電性能的例示性低電壓輸出驅動器線路的部分的側視剖面圖。
第1B圖是依據本發明實施例之堆疊器結構示例的詳圖。
第2圖揭示依據本發明實施例,具有高靜電放電性能的例示性低電壓輸出驅動器線路200的平面圖。
現在將詳細參照本發明的各種實施例,其等示例揭示於所附圖式中。雖則本發明將結合這些實施例進行描述,但應當理解它們無意將本發明限制於這些實施例。相反,本發明意圖涵蓋可包含在由所呈申請專利範圍所界定的本發明之精神和範圍以內的替代、修改及等效實施例。進言之,在本發明的下列詳細描述中,為使透徹理解本發明而提出無數具體細節。但是,此領域中具有通常知識者將會認識到,本發明無需這些具體細節就可實施。在其他示例中,沒有對眾所周知的方法、程式、元件和線路進行詳細描述以免混淆本發明的方面。
在傳統技術中,諸如齊納二極體等二極體可和輸出驅動器電路一起使用以提供增強的靜電放電性能。傳統上,此種二極體是附加到輸出驅動器電路的分離電路。依據本發明之實施例在輸出驅動器電路的集極或汲極形成嵌入式二極體,例如,和利用分離二極體的傳統技藝方法對比,此種二極體是輸出驅動器電路的部分。該嵌入電路導致觸發電壓(Vtrig)急劇降低和回應正向靜電放電的基體電流(Isub)顯著增加。大基體電流增強來自射極或源極的電子注入,因而減小因傳導性調變所導致之導通電阻。
但是,此益處可因進行深度p+植入導致元件的甘梅數(Gummel number)增加而被抵消。為對其改良,二極體可形成於具有浮置場閘極的多指型場ESD內。在此情況下,導通電阻可減小到十分之一歐姆等級上。因此,此新穎ESD結構很適合用於低電壓輸出防護並且能夠使人體模型(HBM)失效臨界值大於9kV。
第1A圖揭示依據本發明實施例之具有高靜電放電性能之例示性低電壓輸出驅動器電路100的部分之側視剖面圖。舉例而言,電路100可形成為輸出驅動器電路的集極及/或汲極的部分。輸出驅動器電路100可形成於p型材料160內。p型材料160可係p井、磊晶層或塊體基體。一般而言,p型材料160將和基體的電勢相同。可由後面第2圖裏看出,第1圖裏所揭示之結構具有較第1圖的局部性平面更大或更小的實質範圍,例如,它們延伸進和延伸出紙面。
輸出驅動器電路100包含配置於p+接面120上的n++區110的多個堆疊器125。堆疊器125的n++區110耦接到輸出墊150,其可包含鈍化金屬,典型地用於耦接到積體電路封裝的外部銷。
多個浮置閘極130,例如場氧化物,與堆疊器125的任一側面(在此圖裏)相鄰。在浮置閘極130的另一側面上,例如與堆疊器125相對的側面,是n型材料的接地區140。因此,低電壓輸出驅動器電路100包含浮置閘極130、堆疊器125、浮置閘極130和接地區140之多種示例。
以另一種檢視低電壓輸出驅動器電路100的方法觀看第1圖圖式,堆疊器125具有兩個相鄰的浮置閘極130。各接地區140具有兩個相鄰的浮置閘極130。各浮置閘極130具有位於一個側面上的堆疊器125和位於另一個側面上的接地區140。
理當瞭解,n++區110、浮置閘極130和n+區140,結合p型材料160之示例,形成p通道場效應電晶體。此種元件可用於將輸出墊150耦接到大地,例如降低輸出端。
第1B圖是依據本發明實施例之堆疊器125的詳細圖式。堆疊器125包含配置于p+材料區120上的n++材料區110。理當瞭解,區110延伸超出(水平地,從第1B圖看來)區120。舉例而言,區110也接觸p型材料160。
進而理當瞭解,堆疊器125形成兩種不同類型的二極體。二極體107形成于n++區110和p型材料160之間。二極體107是具有正溫度係數的p/n類型的二極體。二極體105形成于n++區110和p+接面120之間。二極體105是具有負溫度係數的齊納型二極體。齊納二極體105一般具有,低於n++區110、浮置閘極130和n+區140,結合p型材料160之示例所形成之下拉電晶體的觸發電壓。
藉由將具有相反溫度係數的兩類二極體結合,例如具有正溫度係數的二極體和具有負溫度係數的二極體,堆疊器125形成具有比傳統技藝的二極體呈實質較少(數量上)溫度變化的新穎混成二極體結構。二極體107之區域應該大約等於二極體105之區域,視摻雜濃度、電阻等而定。
第2圖揭示依據本發明實施例,具有高靜電放電性能的例示性低電壓輸出驅動器線路200的平面圖。雖然揭示較少元件,但輸出驅動器電路200一般與第1A圖的輸出驅動器電路100相似。
輸出驅動器電路200包含輸出墊250,其可包含鈍化金屬,典型用於耦接積體電路封裝的外部銷。輸出墊250之指型件橫越n++材料210下行(如第2圖所示)。沒有顯示指型件之全部範圍以揭示下面的特徵。n++材料210配置於p+材料的區域上(在第2圖中不清楚),如第I圖所揭示之。作為有益結果,結合下層的p+材料和p型材料(未圖示)之區210形成具有較小溫度係數的的新穎二極體結構,如之前關於第1B圖所述之。
區260是配置於金屬280上的p+材料的接地墊。區280的指型件向上行進(如第2圖所示)並橫越n型接地區240。沒有顯示指型件的全部範圍以揭示下面的特徵。接地區260從p井、磊晶層或塊體基體接地。浮置閘極230夾於指型件210和指型件240之間。
特徵210之寬度(如第2圖所示)在輸出驅動器電路200的靜電放電性能中起重要作用。越高的ESD電阻需要越大寬度,尤其是觸點和浮置閘極230之間的較大間隔270。相對地,晶粒之考量上則要較小間隔270。在例示性BiCMOS雙井、雙閘極0.3μm製程裏,發現大約3至5μm之間隔270是最佳的。理當瞭解,此等間隔一般比既定製程的接觸間隔之最小設計規則小得多。
輸出驅動器200顯示比混成二極體125(第1B圖)的操作電壓大的驟回保持電壓,及比造成主積體電路損壞所需的低的驟回觸發電壓。此電氣配置避免肇因於驟回保持電壓低於混成二極體125而造成的閉鎖和肇因於驟回觸發電壓太高所造成的IC損壞。
利用嵌入式混成二極體125,可確保操作電壓之部分由混成二極體以傳導模式加以維持,使得餘下操作電壓不足以維持驟回。結果,在ESD事件其間,包括混成二極體125之輸出驅動器電路200可汲取感應電流,因此作用為相關聯的積體電路(IC)之ESD防護元件。在ESD事件之後,操作電壓不能維持該傳導模式,迫使混成二極體不導通,因此防護輸出驅動器電路200和相關聯的積體電路不受損害。
依據本發明之實施例提供具高靜電放電性能之低電壓輸出驅動器。依據本發明之實施例也提供驟回觸發電壓和驟回保持電壓之所需結合。進言之,依據本發明之實施例提供與積體電路設計和製造之既存系統和方法相容並互補的具有高靜電放電性能之低電壓輸出驅動器之系統和方法。
廣泛地,前述在此已呈現。揭示具高靜電放電性能之低電壓輸出驅動器之系統和方法。在一個實施例中,半導體結構包括用於驅動晶片外輸出之電路和浮置場閘極元件。該浮置場閘極元件包括嵌入二極體,其特徵為具有比齊納二極體低的溫度依賴性。嵌入二極體之保持電壓可比嵌入電壓之操作電壓大,且嵌入二極體之驟回觸發電壓可比半導體結構之氧化物崩潰電壓低。
因此對本發明之各種實施例進行了描述。雖則本發明是藉特別實施例進行描述的,但本發明不應當理解為受此等實施例限制,而是由後文的申請專利範圍界定。
以下技術概念係被本案所請發明支持。
技術概念1 一種半導體結構,包含:一種用於驅動晶片外輸出的電路;一浮置場閘極元件;以及其中該浮置場閘極元件包含一嵌入二極體,其特徵為具有比齊納二極體低的溫度依賴性。
技術概念2 如技術概念1之半導體結構,其中該嵌入二極體包含一p/n型二極體。
技術概念3 如技術概念2之半導體結構,其中該嵌入二極體進一步包含一齊納二極體。
技術概念4 如技術概念3之半導體結構,其中該p/n型二極體和該齊納二極體包含一共用的n型
區。
技術概念5 如技術概念4之半導體結構,其中該嵌入二極體之一驟回保持電壓較該嵌入二極體之一操作電壓為大,且該嵌入二極體之一驟回觸發二極體較該半導體結構之一氧化物崩潰電壓為低。
技術概念6 如技術概念5之半導體結構,其可操作為以一操作電壓供電,其中在該嵌入二極體導通時,該操作電壓之一部分係由該嵌入二極體維持。
技術概念7 如技術概念6之半導體結構,其中在一靜電放電(ESD)事件之後,該嵌入二極體係截止。
技術概念8 一種具有增強之靜電放電防護之用於驅動一晶片外輸出之半導體結構,包含:耦接到一輸出墊之多個第一指型件;交錯於該等第一指型件之間並耦接到一接地墊之多個第二指型件;插置於該等第一指型件和該等第二指型件之間之多個浮置場閘極;以及其中該等第一指型件包含一嵌入混成二極體,其特徵為具有比其操作電壓為大的一驟回保持電壓和比該半導體結構之一氧化物崩潰電壓為低的一驟回觸發電壓。
技術概念9 如技術概念8之半導體結構,其中該嵌入混成二極體之特徵為具有比一齊納二極體低的溫度依賴性。
技術概念10 如技術概念8之半導體結構,其中該嵌入混成二極體之特徵為具有比一p/n二極體低的溫度依賴性。
技術概念11 如技術概念8之半導體結構,其中該嵌入混成二極體包含一齊納二極體。
技術概念12 如技術概念8之半導體結構,其中該嵌入混成二極體包含一p/n二極體。
技術概念13 如技術概念12之半導體結構,其中該p/n二極體包含一p型材料井。
技術概念14 如技術概念8之半導體結構,其中該嵌入混成二極體包含一齊納二極體和一p/n二極體,該等兩者共用一共用的n型材料區。
技術概念15 一種半導體結構,包含:一用於驅動一晶片外輸出之電路;其中該電路包含一下拉元件;以及一嵌入該電路之一混成二極體元件,其特徵為具有比該下拉元件的一觸發電壓為低的觸發電壓。
技術概念16 一種用於在ESD事件過程中提供防護的一供用於積體電路(IC)之靜電放電(ESD)防護電路,該電路包含:
一電流流動控制元件;以及串聯地耦接到該電流流動控制元件之一電流流動方向控制元件,其中該靜電放電防護電路之一驟回保持電壓比該靜電放電防護電路之一操作電壓為大,且該靜電放電防護電路之一驟回觸發電壓比該IC之一氧化物崩潰電壓為低。
技術概念17 如技術概念16之ESD防護電路,其中該電流流動控制元件是一電晶體。
技術概念18 如技術概念17之ESD防護電路,其中該電晶體是一MOSFET。
技術概念19 如技術概念17之ESD防護電路,其中該電晶體和該二極體在一ESD事件之後係不導通。
技術概念20 如技術概念16之ESD防護電路,其中該電流流動方向控制元件是嵌入該電流流動控制元件內的一個二極體。
技術概念21 如技術概念20之ESD防護電路,其可操作為以一操作電壓供電,其中在該二極體導通時,該操作電流之一部分係由該二極體維持。
100‧‧‧低電壓輸出驅動器電路
105‧‧‧二極體
107‧‧‧二極體
110‧‧‧n++區
120‧‧‧p+接面
125‧‧‧堆疊器
130‧‧‧浮置閘極
140‧‧‧接地區
150‧‧‧輸出墊
160‧‧‧P型材料
200‧‧‧低電壓輸出驅動器線路
210‧‧‧n++材料
240‧‧‧n型接地區
250‧‧‧輸出墊
260‧‧‧接地區
270‧‧‧間隔
280‧‧‧金屬
第1A圖揭示依據本發明實施例,具有高靜電放電性能的例示性低電壓輸出驅動器線路的部分的側視剖面圖。
第1B圖是依據本發明實施例之堆疊器結構示例的詳圖。
第2圖揭示依據本發明實施例,具有高靜電放電性能的例示性低電壓輸出驅動器線路200的平面圖。
100...低電壓輸出驅動器電路
110...n++區
120...p+接面
125...堆疊器
130...浮置閘極
140...接地區
150...輸出墊
160...P型材料
Claims (9)
- 一種半導體結構,包含:一浮置閘極元件;以及其中該浮置閘極元件包含一第一浮置閘極、一第二浮置閘極及一堆疊器,其中該第一浮置閘極及該第二浮置閘極係與該堆疊器之相對側相鄰且位於其上並且係為場氧化物,其中該堆疊器包括一第一類型的二極體及一第二類型的二極體。
- 如申請專利範圍第1項之半導體結構,其中該第一類型的二極體包含一p/n型二極體。
- 如申請專利範圍第2項之半導體結構,其中該第二類型的二極體包含一齊納二極體。
- 如申請專利範圍第3項之半導體結構,其中該p/n型二極體和該齊納二極體包含一共用的n型區。
- 一種用於靜電放電防護之半導體結構,包含:耦接到一輸出墊之多個第一指型件;交錯於該等第一指型件之間並耦接到一接地墊之多個第二指型件;插置於該等第一指型件和該等第二指型件之間之多個浮置閘極,其中該等浮置閘極係為場氧化物;以及其中該等第一指型件包含一堆疊器,其中該堆疊器包括一第一類型的二極體及一第二類型的二極體,其中該等浮置閘極之一第一浮置閘極及一第二浮置閘極係與該堆疊器之相對側相鄰且位於其上並且係為場氧化 物。
- 如申請專利範圍第5項之半導體結構,其中該第二類型的二極體包含一齊納二極體。
- 如申請專利範圍第6項之半導體結構,其中該第一類型的二極體包含一p/n型二極體。
- 如申請專利範圍第7項之半導體結構,其中該p/n型二極體包含一p型材料井。
- 如申請專利範圍第7項之半導體結構,其中該p/n型二極體和該齊納二極體共用一共用的n型材料區。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US76008106P | 2006-01-18 | 2006-01-18 | |
US11/655,493 US9111754B2 (en) | 2005-07-26 | 2007-01-18 | Floating gate structure with high electrostatic discharge performance |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200735324A TW200735324A (en) | 2007-09-16 |
TWI435430B true TWI435430B (zh) | 2014-04-21 |
Family
ID=38287959
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW096101899A TWI435430B (zh) | 2006-01-18 | 2007-01-18 | 具高靜電放電性能之低電壓輸出驅動器 |
Country Status (7)
Country | Link |
---|---|
US (1) | US9111754B2 (zh) |
EP (1) | EP1977450B1 (zh) |
JP (2) | JP2009524248A (zh) |
KR (1) | KR101139438B1 (zh) |
CN (1) | CN101361193B (zh) |
TW (1) | TWI435430B (zh) |
WO (1) | WO2007084688A1 (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007096211A (ja) * | 2005-09-30 | 2007-04-12 | Ricoh Co Ltd | 半導体装置 |
US7544545B2 (en) | 2005-12-28 | 2009-06-09 | Vishay-Siliconix | Trench polysilicon diode |
JP5296450B2 (ja) * | 2008-08-13 | 2013-09-25 | セイコーインスツル株式会社 | 半導体装置 |
DE102008047850B4 (de) | 2008-09-18 | 2015-08-20 | Austriamicrosystems Ag | Halbleiterkörper mit einer Schutzstruktur und Verfahren zum Herstellen derselben |
US9124354B2 (en) * | 2011-05-12 | 2015-09-01 | St-Ericsson Sa | Isolation and protection circuit for a receiver in a wireless communication device |
CN105609500B (zh) * | 2016-01-28 | 2018-10-12 | 嘉兴爱禾电子有限公司 | 一种共极集成二极管 |
US10381473B2 (en) | 2016-12-02 | 2019-08-13 | Vishay-Siliconix | High-electron-mobility transistor with buried interconnect |
US10693288B2 (en) | 2018-06-26 | 2020-06-23 | Vishay SIliconix, LLC | Protection circuits with negative gate swing capability |
US10833063B2 (en) | 2018-07-25 | 2020-11-10 | Vishay SIliconix, LLC | High electron mobility transistor ESD protection structures |
US11632142B1 (en) | 2021-11-09 | 2023-04-18 | Macom Technology Solutions Holdings, Inc. | Hybrid diode silicon on insulator front end module and related method |
Family Cites Families (105)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4677369A (en) | 1985-09-19 | 1987-06-30 | Precision Monolithics, Inc. | CMOS temperature insensitive voltage reference |
US4748103A (en) | 1986-03-21 | 1988-05-31 | Advanced Power Technology | Mask-surrogate semiconductor process employing dopant protective region |
JP2667392B2 (ja) | 1986-09-26 | 1997-10-27 | 株式会社デンソー | 多結晶半導体ダイオードの製造方法 |
US20020074585A1 (en) | 1988-05-17 | 2002-06-20 | Advanced Power Technology, Inc., Delaware Corporation | Self-aligned power MOSFET with enhanced base region |
US5283201A (en) | 1988-05-17 | 1994-02-01 | Advanced Power Technology, Inc. | High density power device fabrication process |
US4922371A (en) * | 1988-11-01 | 1990-05-01 | Teledyne Semiconductor | ESD protection circuit for MOS integrated circuits |
US5055896A (en) | 1988-12-15 | 1991-10-08 | Siliconix Incorporated | Self-aligned LDD lateral DMOS transistor with high-voltage interconnect capability |
US5072266A (en) | 1988-12-27 | 1991-12-10 | Siliconix Incorporated | Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry |
DE4200884A1 (de) | 1991-01-16 | 1992-07-23 | Micron Technology Inc | Integrierte halbleiterschaltungsvorrichtung |
JPH0590520A (ja) * | 1991-09-26 | 1993-04-09 | Nissan Motor Co Ltd | 半導体保護装置 |
US5416351A (en) * | 1991-10-30 | 1995-05-16 | Harris Corporation | Electrostatic discharge protection |
JPH05291501A (ja) * | 1992-04-13 | 1993-11-05 | Nissan Motor Co Ltd | 半導体保護装置 |
US5648281A (en) | 1992-09-21 | 1997-07-15 | Siliconix Incorporated | Method for forming an isolation structure and a bipolar transistor on a semiconductor substrate |
US5559044A (en) | 1992-09-21 | 1996-09-24 | Siliconix Incorporated | BiCDMOS process technology |
JP3167457B2 (ja) | 1992-10-22 | 2001-05-21 | 株式会社東芝 | 半導体装置 |
JP3311070B2 (ja) | 1993-03-15 | 2002-08-05 | 株式会社東芝 | 半導体装置 |
US5404041A (en) | 1993-03-31 | 1995-04-04 | Texas Instruments Incorporated | Source contact placement for efficient ESD/EOS protection in grounded substrate MOS integrated circuit |
GB9306895D0 (en) | 1993-04-01 | 1993-05-26 | Philips Electronics Uk Ltd | A method of manufacturing a semiconductor device comprising an insulated gate field effect device |
WO1994027325A1 (en) | 1993-05-07 | 1994-11-24 | Vlsi Technology, Inc. | Integrated circuit structure and method |
US5430315A (en) | 1993-07-22 | 1995-07-04 | Rumennik; Vladimir | Bi-directional power trench MOS field effect transistor having low on-state resistance and low leakage current |
US5416036A (en) | 1993-10-04 | 1995-05-16 | United Microelectronics Corporation | Method of improvement ESD for LDD process |
US5374565A (en) | 1993-10-22 | 1994-12-20 | United Microelectronics Corporation | Method for ESD protection improvement |
JP2630242B2 (ja) | 1993-12-28 | 1997-07-16 | 日本電気株式会社 | 温度検出用ダイオード付パワーmosfet |
US5529941A (en) | 1994-03-28 | 1996-06-25 | Vlsi Technology, Inc. | Method for making an integrated circuit structure |
JPH07273320A (ja) | 1994-03-31 | 1995-10-20 | Toshiba Corp | 半導体装置 |
US5455444A (en) | 1994-04-22 | 1995-10-03 | United Microelectronics Corporation | Double polysilicon electrostatic discharge protection device for SRAM and DRAM memory devices |
US5519242A (en) * | 1994-08-17 | 1996-05-21 | David Sarnoff Research Center, Inc. | Electrostatic discharge protection circuit for a NMOS or lateral NPN transistor |
US5545909A (en) | 1994-10-19 | 1996-08-13 | Siliconix Incorporated | Electrostatic discharge protection device for integrated circuit |
US5733794A (en) | 1995-02-06 | 1998-03-31 | Motorola, Inc. | Process for forming a semiconductor device with ESD protection |
US5637900A (en) * | 1995-04-06 | 1997-06-10 | Industrial Technology Research Institute | Latchup-free fully-protected CMOS on-chip ESD protection circuit |
US5567634A (en) | 1995-05-01 | 1996-10-22 | National Semiconductor Corporation | Method of fabricating self-aligned contact trench DMOS transistors |
US5661322A (en) | 1995-06-02 | 1997-08-26 | Siliconix Incorporated | Bidirectional blocking accumulation-mode trench power MOSFET |
US5998837A (en) | 1995-06-02 | 1999-12-07 | Siliconix Incorporated | Trench-gated power MOSFET with protective diode having adjustable breakdown voltage |
US6078090A (en) | 1997-04-02 | 2000-06-20 | Siliconix Incorporated | Trench-gated Schottky diode with integral clamping diode |
US6140678A (en) | 1995-06-02 | 2000-10-31 | Siliconix Incorporated | Trench-gated power MOSFET with protective diode |
DE69617098T2 (de) | 1995-06-02 | 2002-04-18 | Siliconix Inc | Grabengate-Leistungs-MOSFET mit Schutzdioden in periodischer Anordnung |
US6049108A (en) | 1995-06-02 | 2000-04-11 | Siliconix Incorporated | Trench-gated MOSFET with bidirectional voltage clamping |
WO1997013279A1 (en) | 1995-10-02 | 1997-04-10 | Siliconix Incorporated | Trench-gated mosfet including integral temperature detection diode |
JPH09129877A (ja) | 1995-10-30 | 1997-05-16 | Toyota Central Res & Dev Lab Inc | 半導体装置の製造方法、絶縁ゲート型半導体装置の製造方法および絶縁ゲート型半導体装置 |
US5637898A (en) | 1995-12-22 | 1997-06-10 | North Carolina State University | Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance |
US5672527A (en) | 1996-03-08 | 1997-09-30 | United Microelectronics Corp. | Method for fabricating an electrostatic discharge protection circuit |
US5585299A (en) | 1996-03-19 | 1996-12-17 | United Microelectronics Corporation | Process for fabricating a semiconductor electrostatic discharge (ESD) protective device |
US5912494A (en) | 1996-04-02 | 1999-06-15 | Winbond Electronics Corporation | Internal ESD protection structure with contact diffusion |
US5674761A (en) | 1996-05-02 | 1997-10-07 | Etron Technology, Inc. | Method of making ESD protection device structure for low supply voltage applications |
US5850095A (en) | 1996-09-24 | 1998-12-15 | Texas Instruments Incorporated | ESD protection circuit using zener diode and interdigitated NPN transistor |
US5882967A (en) * | 1997-05-07 | 1999-03-16 | International Business Machines Corporation | Process for buried diode formation in CMOS |
JP3502531B2 (ja) | 1997-08-28 | 2004-03-02 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
KR100239424B1 (ko) | 1997-09-26 | 2000-01-15 | 김영환 | 정전기 보호회로 |
US6268242B1 (en) | 1997-12-31 | 2001-07-31 | Richard K. Williams | Method of forming vertical mosfet device having voltage clamped gate and self-aligned contact |
US6060752A (en) | 1997-12-31 | 2000-05-09 | Siliconix, Incorporated | Electrostatic discharge protection circuit |
JPH11233641A (ja) * | 1998-02-10 | 1999-08-27 | Seiko Epson Corp | 半導体装置及び半導体装置の製造方法 |
US5953601A (en) | 1998-02-17 | 1999-09-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | ESD implantation scheme for 0.35 μm 3.3V 70A gate oxide process |
JP3705919B2 (ja) | 1998-03-05 | 2005-10-12 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
US6044018A (en) * | 1998-06-17 | 2000-03-28 | Mosel Vitelic, Inc. | Single-poly flash memory cell for embedded application and related methods |
JP3413569B2 (ja) | 1998-09-16 | 2003-06-03 | 株式会社日立製作所 | 絶縁ゲート型半導体装置およびその製造方法 |
JP3574359B2 (ja) * | 1998-09-18 | 2004-10-06 | セイコーエプソン株式会社 | 半導体装置 |
KR100505619B1 (ko) | 1998-09-29 | 2005-09-26 | 삼성전자주식회사 | 반도체소자의정전하방전회로,그구조체및그구조체의제조방법 |
US5998833A (en) | 1998-10-26 | 1999-12-07 | North Carolina State University | Power semiconductor devices having improved high frequency switching and breakdown characteristics |
US6255683B1 (en) | 1998-12-29 | 2001-07-03 | Infineon Technologies Ag | Dynamic random access memory |
JP3743189B2 (ja) | 1999-01-27 | 2006-02-08 | 富士通株式会社 | 不揮発性半導体記憶装置及びその製造方法 |
US6268639B1 (en) | 1999-02-11 | 2001-07-31 | Xilinx, Inc. | Electrostatic-discharge protection circuit |
US6277695B1 (en) | 1999-04-16 | 2001-08-21 | Siliconix Incorporated | Method of forming vertical planar DMOSFET with self-aligned contact |
US6413822B2 (en) | 1999-04-22 | 2002-07-02 | Advanced Analogic Technologies, Inc. | Super-self-aligned fabrication process of trench-gate DMOS with overlying device layer |
US6347026B1 (en) | 1999-05-26 | 2002-02-12 | Lsi Logic Corporation | Input and power protection circuit implemented in a complementary metal oxide semiconductor process using salicides |
US6191447B1 (en) | 1999-05-28 | 2001-02-20 | Micro-Ohm Corporation | Power semiconductor devices that utilize tapered trench-based insulating regions to improve electric field profiles in highly doped drift region mesas and methods of forming same |
US6211018B1 (en) | 1999-08-14 | 2001-04-03 | Electronics And Telecommunications Research Institute | Method for fabricating high density trench gate type power device |
JP3708764B2 (ja) * | 1999-09-07 | 2005-10-19 | Necエレクトロニクス株式会社 | 半導体装置 |
JP3348711B2 (ja) * | 1999-12-03 | 2002-11-20 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
JP3573674B2 (ja) | 1999-12-27 | 2004-10-06 | Necエレクトロニクス株式会社 | 半導体集積回路の入出力保護装置とその保護方法 |
US6548860B1 (en) | 2000-02-29 | 2003-04-15 | General Semiconductor, Inc. | DMOS transistor structure having improved performance |
JP2001257349A (ja) | 2000-03-09 | 2001-09-21 | Sanyo Electric Co Ltd | Mosfetの保護装置 |
JP3675303B2 (ja) | 2000-05-31 | 2005-07-27 | セイコーエプソン株式会社 | 静電気保護回路が内蔵された半導体装置及びその製造方法 |
JP2002016080A (ja) | 2000-06-28 | 2002-01-18 | Toshiba Corp | トレンチゲート型mosfetの製造方法 |
US6700158B1 (en) | 2000-08-18 | 2004-03-02 | Fairchild Semiconductor Corporation | Trench corner protection for trench MOSFET |
JP2002110978A (ja) | 2000-10-02 | 2002-04-12 | Toshiba Corp | 電力用半導体素子 |
US6631060B2 (en) | 2000-11-30 | 2003-10-07 | Winbond Electronics Corporation | Field oxide device with zener junction for electrostatic discharge (ESD) protection and other applications |
JP2002208677A (ja) | 2001-01-12 | 2002-07-26 | Toyota Industries Corp | 温度検出機能を備える半導体装置 |
US6815775B2 (en) | 2001-02-02 | 2004-11-09 | Industrial Technology Research Institute | ESD protection design with turn-on restraining method and structures |
JP4932088B2 (ja) | 2001-02-19 | 2012-05-16 | ルネサスエレクトロニクス株式会社 | 絶縁ゲート型半導体装置の製造方法 |
JP2002270841A (ja) | 2001-03-13 | 2002-09-20 | Denso Corp | 半導体装置及びその製造方法 |
JP2002274640A (ja) | 2001-03-19 | 2002-09-25 | Honda Motor Co Ltd | パレットストッパ装置 |
US6882000B2 (en) | 2001-08-10 | 2005-04-19 | Siliconix Incorporated | Trench MIS device with reduced gate-to-drain capacitance |
US6514839B1 (en) * | 2001-10-05 | 2003-02-04 | Taiwan Semiconductor Manufacturing Company | ESD implantation method in deep-submicron CMOS technology for high-voltage-tolerant applications with light-doping concentrations |
US20030071310A1 (en) | 2001-10-11 | 2003-04-17 | Salling Craig T. | Method to increase substrate potential in MOS transistors used in ESD protection circuits |
AU2002343551A1 (en) | 2001-11-02 | 2003-11-11 | Fairchild Semiconductor Corporation | Improving the triggering of an esd nmos through the use of an n-type buried layer |
KR100406180B1 (ko) | 2001-12-22 | 2003-11-17 | 주식회사 하이닉스반도체 | 플래쉬 메모리 셀의 제조 방법 |
US6838722B2 (en) | 2002-03-22 | 2005-01-04 | Siliconix Incorporated | Structures of and methods of fabricating trench-gated MIS devices |
US6855593B2 (en) | 2002-07-11 | 2005-02-15 | International Rectifier Corporation | Trench Schottky barrier diode |
US8629019B2 (en) | 2002-09-24 | 2014-01-14 | Vishay-Siliconix | Method of forming self aligned contacts for a power MOSFET |
US7190563B2 (en) | 2002-10-18 | 2007-03-13 | Agere Systems Inc. | Electrostatic discharge protection in a semiconductor device |
JP3931138B2 (ja) | 2002-12-25 | 2007-06-13 | 三菱電機株式会社 | 電力用半導体装置及び電力用半導体装置の製造方法 |
TW200411897A (en) * | 2002-12-30 | 2004-07-01 | Winbond Electronics Corp | Robust ESD protection structures |
JP2004247455A (ja) * | 2003-02-13 | 2004-09-02 | Seiko Epson Corp | 半導体装置 |
US6861701B2 (en) | 2003-03-05 | 2005-03-01 | Advanced Analogic Technologies, Inc. | Trench power MOSFET with planarized gate bus |
JP2004296883A (ja) * | 2003-03-27 | 2004-10-21 | Sharp Corp | 半導体装置とその製造方法 |
US6919603B2 (en) | 2003-04-30 | 2005-07-19 | Texas Instruments Incorporated | Efficient protection structure for reverse pin-to-pin electrostatic discharge |
US7019368B1 (en) | 2003-07-11 | 2006-03-28 | Actel Corporation | Low-capacitance input/output and electrostatic discharge circuit for protecting an integrated circuit from electrostatic discharge |
US20050036251A1 (en) | 2003-08-12 | 2005-02-17 | Micrel, Incorporated | Electrostatic discharge protection for trim-diodes |
US7129557B2 (en) | 2004-05-25 | 2006-10-31 | International Business Machines Corporation | Autonomic thermal monitor and controller for thin film devices |
US7781826B2 (en) * | 2006-11-16 | 2010-08-24 | Alpha & Omega Semiconductor, Ltd. | Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter |
US7279773B2 (en) * | 2005-03-15 | 2007-10-09 | Delphi Technologies, Inc. | Protection device for handling energy transients |
US20060268479A1 (en) * | 2005-05-31 | 2006-11-30 | Atmel Germany Gmbh | ESD protection structure |
US7583485B1 (en) | 2005-07-26 | 2009-09-01 | Vishay-Siliconix | Electrostatic discharge protection circuit for integrated circuits |
US7544545B2 (en) | 2005-12-28 | 2009-06-09 | Vishay-Siliconix | Trench polysilicon diode |
JP2011233641A (ja) | 2010-04-26 | 2011-11-17 | Disco Abrasive Syst Ltd | 板状物のレーザー加工方法 |
-
2007
- 2007-01-18 EP EP07718296.2A patent/EP1977450B1/en active Active
- 2007-01-18 WO PCT/US2007/001473 patent/WO2007084688A1/en active Application Filing
- 2007-01-18 TW TW096101899A patent/TWI435430B/zh active
- 2007-01-18 KR KR1020087013982A patent/KR101139438B1/ko active IP Right Grant
- 2007-01-18 US US11/655,493 patent/US9111754B2/en active Active
- 2007-01-18 JP JP2008551423A patent/JP2009524248A/ja active Pending
- 2007-01-18 CN CN2007800016046A patent/CN101361193B/zh active Active
-
2013
- 2013-01-09 JP JP2013001443A patent/JP5738903B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
TW200735324A (en) | 2007-09-16 |
JP2009524248A (ja) | 2009-06-25 |
US9111754B2 (en) | 2015-08-18 |
EP1977450A1 (en) | 2008-10-08 |
CN101361193A (zh) | 2009-02-04 |
JP5738903B2 (ja) | 2015-06-24 |
US20070236843A1 (en) | 2007-10-11 |
WO2007084688A1 (en) | 2007-07-26 |
EP1977450B1 (en) | 2015-06-10 |
CN101361193B (zh) | 2013-07-10 |
KR20080100164A (ko) | 2008-11-14 |
KR101139438B1 (ko) | 2012-04-27 |
EP1977450A4 (en) | 2010-07-21 |
JP2013123060A (ja) | 2013-06-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI435430B (zh) | 具高靜電放電性能之低電壓輸出驅動器 | |
JP4213323B2 (ja) | 静電放電保護回路 | |
JP4401500B2 (ja) | 静電放電における寄生バイポーラ効果を低減する半導体装置および方法 | |
US6861711B2 (en) | Thick gate oxide transistor and electrostatic discharge protection utilizing thick gate oxide transistors | |
JP6190824B2 (ja) | 共通ソースfetよりゲート酸化物が厚いバッファ段fetを有する静電放電保護回路 | |
US6888710B2 (en) | Insulated gate bipolar transistor and electrostatic discharge cell protection utilizing insulated gate bipolar transistors | |
US7309896B2 (en) | Electrostatic discharge protection device | |
US7145204B2 (en) | Guardwall structures for ESD protection | |
US7361957B2 (en) | Device for electrostatic discharge protection and method of manufacturing the same | |
US7449751B2 (en) | High voltage operating electrostatic discharge protection device | |
US6864537B1 (en) | Thick gate oxide transistor and electrostatic discharge protection utilizing thick gate oxide transistors | |
JP2002324842A (ja) | 半導体保護回路 | |
US8324688B2 (en) | Electrostatic discharge protection device for high voltage operation | |
US8823106B2 (en) | ESD protective element and plasma display including the ESD protective element | |
WO2005112134A2 (en) | High current mos device with avalanche protection and method of operation | |
JP2001035935A (ja) | 半導体装置 | |
KR100504203B1 (ko) | 반도체장치의 보호소자 | |
KR101349998B1 (ko) | 정전기 방전 보호 장치 | |
KR100650625B1 (ko) | 정전기 방전 방지 소자 | |
TWI458091B (zh) | 靜電放電防護裝置 | |
CN117937404A (zh) | 静电放电保护电路以及电子电路 | |
KR20110103814A (ko) | 정전기 방지 구조를 가진 금속 산화막 반도체 전계효과 트랜지스터 |