CN101361193A - 具有高静电放电性能的浮动栅极结构 - Google Patents
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Abstract
具有高静电放电性能的浮动栅极结构的系统和方法。在一个实施例中,半导体结构包括浮动场栅极器件。该浮动场栅极器件包括嵌入式二极管,该嵌入式二极管的特征为具有比齐纳二极管更小的温度依赖性。该嵌入式二极管的击穿电压大于相关联的集成电路的工作电压,并且该嵌入式二极管的快速恢复触发电压低于半导体结构的击穿电压。
Description
相关申请
本申请要求美国临时申请第60/760081号的优先权,其代理人卷号为VISH-8759.PRO,该申请于2006年1月18日提交,名称为“LowVoltage Output Driver with High Performance Electrostatic DischargePerformance(具有高静电放电性能的低压输出驱动器)”,权利人是Luo和Demirlioglu,该申请的全部内容结合在本文中作为参考。
本申请是共同待决的同为Luo等人所拥有的2005年7月26日提交的美国专利申请第11/190,682号的部分继续申请,后者的代理人卷号为No.VISH-8744,名称为“Electrostatic Discharge Protection Circuitfor Integrated Circuits(集成电路的静电放电保护电路)”,该申请的全部内容结合在本文中作为参考。
技术领域
这里给出的实施例涉及集成电路领域。更特别地,这里给出的实施例是关于集成电路的静电放电(ESD)保护。
背景技术
当具有不同静电势的主体之间存在能量转移时,就会发生静电放电(ESD)事件,要么通过接触要么通过已电离的环境放电。ESD保护不充分的集成电路(IC)会受到灾难性的破坏,包括,例如,钝化层破裂、电热迁移、铝溅射、触点尖刺(contact spiking)、介电失效等等。可替代地,ESD事件可损坏器件,即使器件能够继续工作。该类损坏构成潜在的缺陷,这类损坏难以检测并显著缩短受损IC的寿命。
在传统技术中,通常依靠输出(例如,芯片外的(off-chip))驱动器电路的物理和电气尺寸来提供静电放电保护。输出驱动器自身通常通过利用多指结构(multiple-finger structure)的大的总宽度和触电到多晶硅(contact-to-poly)的宽的间距来提供增强的ESD保护。
然而,该传统静电放电保护方法的有效性随着集成电路技术的进步而降低。器件的几何尺寸更小和减小电路面积的总趋势有利于减小芯片尺寸。因此,输出电路可用的晶片(die)面积持续减小,这减小了这种输出电路的ESD吸收/迁移能力。
不幸的是,与从前相比,对更高水平的静电放电保护的需求在增加。这促生了使用与输出驱动器并联的独立ESD器件来用于ESD保护。
通常,输出驱动器的栅极连接到内部电路,例如,以接收要输出的信号。该种形式的连接通常使得输出器件对ESD事件的响应的急速回复(snapback)比输出驱动器的栅极接地的情况要快得多。为了完全保护输出驱动器,独立的ESD器件必须具有比输出驱动器击穿电压低的触发器电压,并具有超低的导通电阻,即使在高ESD电流条件下。
本文所使用的术语击穿电压是指氧化物击穿电压和结击穿电压。通常,这两个电压中较低的电压是集成电路不能工作的电压点,且可能发生实际物理损伤。根据多种构造和工艺变量,这些电压中的任一个可以(在振幅方面)比另一个低。
ESD保护器件也应具有大于电路的最大操作电压的保持电压,从而防止电路在ESD事件期间导通。否则,电路可能会由于电路自身无法支撑的高ESD电流而受到永久性的损坏。当急速回复触发电压大于击穿电压时,如果ESD事件导致电压大于最低击穿电压,则可能会对集成电路造成损伤。
IC制造商试图设计这样的金属氧化物半导体场效应晶体管(MOSFET),该MOSFET在快速恢复触发电压和快速恢复保持电压之间具有所需的关系,以便用在IC应用的ESD保护器件中。然而,这些参数受IC制造工艺和电路性能考虑方面的限制。因此,不是总能实现快速恢复触发电压和快速恢复保持电压的最佳结合。
发明内容
因此,需要具有高静电放电性能的浮动栅极结构的系统和方法。也需要理想组合快速恢复触发电压和快速恢复保持电压的系统和方法,该理想组合也满足上述需要。进一步需要具有高静电放电性能的浮动栅极结构的系统和方法,该静电放电性能与现有的集成电路设计和制造系统和方法兼容并互补。根据本发明的实施例提供了这些需要。
根据本发明的实施例将二极管器件嵌入到浮动栅极静电放电保护结构中。
因此,本发明公开了具有高静电放电性能的浮动栅极结构的系统和方法。在一个实施例中,半导体结构包括浮动场栅极器件。浮动场栅极器件包括嵌入式二极管,其特征为具有比齐纳二极管更小的温度依赖性。嵌入式二极管的击穿电压可大于相关联的集成电路的操作电压,且嵌入式二极管的快速恢复触发电压比半导体结构的击穿电压要低。
根据本发明的另一个实施例,静电放电保护的半导体结构包括耦合到输出端衰减器的多个第一耙指,和交织在第一耙指之间的并且耦合到接地衰减器的多个第二耙指。半导体结构进一步包括多个浮动场栅极,该多个浮动场栅极介于第一耙指和第二耙指之间。第一耙指包括嵌入式混合二极管,嵌入式混合二极管的特征为具有低于半导体结构击穿电压的二极管击穿电压和小于半导体结构击穿电压的快速恢复触发电压。
根据本发明的可替代实施例,半导体结构包括用于驱动芯片外的输出的电路。该电路包括下拉(pull-down)器件。半导体结构进一步包括嵌入在电路中的混合二极管器件,其特征为具有低于下拉器件击穿电压的触发电压。
根据本发明的另一实施例,在ESD事件期间用于提供保护的集成电路(IC)的静电放电(ESD)保护电路包括电流控制组件和与电流控制组件串联的电流方向控制组件。静电放电保护电路的快速恢复保持电压大于集成电路的工作电压,且静电放电保护电路的快速恢复触发电压低于IC的氧化物击穿电压。
附图说明
附图包括在本说明书中并构成本说明书的一部分,附图示出了本发明的各实施例,附图与说明书一起用于解释本发明的原理。除非另外指出,否则附图不是按比例的。
图1A示出了根据本发明的实施例的示例性的具有高静电放电性能的低压输出驱动器电路的一部分的侧面截面图。
图1B是根据本发明的实施例的叠层结构的一个例子的详细图示。
图2A示出了根据本发明的实施例的具有高静电放电性能的示例性低压输出驱动器浮动栅极结构200的一部分的平面图。
图2B示出了根据本发明的实施例的嵌入式混合二极管的多种可替代布局。
具体实施方式
现将详细参考本发明的多个实施例,附图中示出了本发明实施例的例子。虽然下面将结合这些实施例来说明本发明,但可以理解,本发明不局限于这些实施例。相反,本发明涵盖了所有可包括在权利要求限定的本发明的精神和保护范围内的替代、修改和等效物。而且,在下面的本发明的详细说明中,给出了大量具体细节以使读者能够透彻地理解本发明。然而,本领域技术人员将会理解,可以在不使用这些具体细节的情况下来实施本发明。换句话说,公知的方法、过程、组件和电路都没有详细说明,以免不必要地影响对本发明的理解。具有高静电放电性能的浮动栅极结构
在传统技术中,可沿着输出驱动器电路的一侧使用二极管,例如齐纳二极管,从而提供增强的静电放电性能。传统上,这样的二极管是除输出驱动器电路外的独立电路。根据本发明的实施例在浮动栅极ESD保护结构的发射极或源极处形成嵌入式二极管,例如,这样的二极管是浮动栅极ESD保护结构的一部分,这与传统技术利用独立二极管的方法不同。该嵌入式二极管导致响应于正静电放电,触发电压(Vtrig)急剧减小,且衬底电流(Isub)急剧增加。大衬底电流增强了电子从发射极或源极的注入,导致由于电导率调制而引起的导通电阻的减小。
然而,在执行深p+注入时,该益处可由于器件Gummel数的不利的增加而被抵消。为了对此进行改善,二极管可在具有浮动场栅极的多指结构场ESD器件中形成。可以理解,术语“场栅极”不排除包括多晶硅的栅极。在这种情况下,导通电阻可降低到零点几个ohm的量级。因此,新型的ESD结构非常适合于低电压输出保护,并使人体模型(HBM)ESD故障阈值大于9kV。
图1A示出了根据本发明的实施例的具有高静电放电性能的浮动栅极结构100的一部分的侧面截面图。例如,浮动栅极结构100可被形成作为浮动栅极ESD保护结构的源极和/或发射极的一部分。浮动栅极结构100可以在例如p型材料160中形成。P型材料160可以是p阱、外延层或容积衬底。通常,p型材料160将与衬底具有相同的电势。如从图2中可以看到,图1中所示的结构实际上在图1的剖面的上面和下面延伸,例如,向纸张内的方向延伸和从纸张延伸出来。
可以理解,根据本发明的实施例也适于在n型材料中形成。由于公知的半导体结构的二元性,本领域普通技术人员可以用n型导电性取代p型导电性,从而得到本发明的可替代实施例。这样的变化被认为是包括在本发明的保护范围内。
浮动栅极结构100包括在p+结120上方布置的n++区110的多个叠层(stack)125。叠层125的n++区110被耦合到输出端衰减器150,叠层125可包括钝化金属,典型地用于耦合到集成电路封装的外部引脚上。
多个浮动栅极130,例如场氧化层,邻近叠层125的任一侧(在该示图中)。在浮动栅极130的另一侧,例如与叠层125相反的一侧,是n型材料的接地区140。因此浮动栅极结构100包括浮动栅极130、叠层125、浮动栅极130和接地区140中的多个实例。
作为图1的示图中的浮动栅极结构100的另一种观察方式,叠层125具有两个相邻浮动栅极130。每个接地区140具有两个邻近浮动栅极130。每个浮动栅极130的一侧上有叠层125并且另一侧上有接地区140。
可以理解,n++区110、浮动栅极130和n+区140与p型材料160结合而形成p沟道场效应晶体管。这样的器件可用于将输出端衰减器150耦合到地,从而下拉输出端子。
图1B是根据本发明的实施例的叠层125的详细示图。叠层125包括布置在p+材料的区域120上方的n++材料的区域110。可以理解,区域110延伸(沿水平方向,如图1B的图中)到区域120之外。例如,区域110也接触p型材料160。
可以进一步理解,叠层125形成两个不同类型的二极管。二极管107形成于作为阴极的n++区域110与作为阳极的p型材料160之间。二极管107是具有正温度系数的p/n型二极管。二极管105形成于作为阴极的n++区域110与作为阳极的p+结120之间。二极管105是具有负温度系数的齐纳型二极管。齐纳二极管105通常具有比由例如n++区域110、浮动栅极130和n+区域140与p型材料160结合而形成的下拉晶体管更低的触发电压。
通过组合具有相反的温度系数的两种类型二极管,例如,具有正温度系数的二极管和具有负温度系数的二极管,叠层125形成新型的混合二极管结构,并且该结构的温度变化基本上小于(在大小上)传统技术的二极管。根据掺杂浓度、电阻等,二极管107的面积应约等于二极管105的面积。可以理解,在根据本发明的可替代实施例中,可能需要新型混合二极管的其他温度系数,且这类其他温度系数可通过形成不同比率的二极管面积来实现。
可以理解,浮动栅极结构100的二极管击穿电压可通过公知的掺杂浓度的变化等来调整。进一步,可将二极管击穿电压构造成不同于关联的集成电路,如由浮动栅极结构100保护的集成电路的击穿电压。这类二极管击穿电压应小于相关联的集成电路的击穿电压。
图2A示出了根据本发明的实施例的具有高静电放电性能的示例性浮动栅极结构200的一部分的平面图。浮动栅极结构200通常类似于图1A的浮动栅极结构100,虽然示出的元件较少。
浮动栅极结构200包括输出端衰减器250,浮动栅极结构200可包括钝化金属,通常用于耦合到集成电路封装的外部引脚。输出端衰减器250的耙指在n++材料210的区域上方向下延伸(在图2的示图中)。图中没有示出耙指的全部长度以便示出耙指下面的特征部分。N++材料210被布置在p+材料区域的上方(图2中被遮蔽),如图1所示。作为一个有益的结果,区域210与其下面的p+材料区域的和p型材料区域(未示出)结合而形成具有较小温度系数的新型混合二极管结构,如前面参考图1B所说明的那样。
区域260是布置在金属280上方的p+材料的接地衰减器。区域280的耙指结构向上延伸并延伸到n型接地区域240的上方(参看图2)。图中没有示出耙指的全部长度,以便示出耙指下面的特征部分。接地衰减器260从p阱、外延层或容积衬底而接地。浮动栅极230被布置在耙指210和耙指240之间。
特征部分210的宽度(参看图2)在输出驱动器浮动栅极结构200的静电放电性能方面具有重要作用。较高的ESD电阻有利于较大的宽度,特别是触点和浮动栅极230之间的较大的间隔270。相反,晶片面积方面的考虑希望间隔270较小。在示例性BiCMOS双阱、双栅极0.3μm工艺中,发现约3到5μm的分隔270是最佳的。可以理解,这样的分隔通常比给定工艺的触点分隔的最小设计规则要大得多。
浮动栅极结构200具有比混合二极管125的工作电压(图1B)更大的快速恢复保持电压,和比导致损坏主集成电路(host integratedcircuit)所需的电压低的快速恢复触发电压。该电子布置避免了由于快速恢复保持电压低于混合二极管125的工作电压而导致的闩锁(latchup),并避免了由于快速恢复触发电压太高而导致的IC损坏。
使用嵌入式混合二极管125可确保部分保持电压由导通模式下的混合二极管维持,使得剩余保持电压不足以引起闩锁。结果,在ESD事件期间,包括混合二极管125的浮动栅极结构200可泄漏ESD感生的电流,因此用作关联的集成电路(IC)的ESD保护器件。在ESD事件后,工作电压不能维持导通模式,迫使混合二极管截止,从而保护浮动栅极结构200和关联的集成电路免遭损坏。
图2B示出了根据本发明的实施例的嵌入式混合二极管的多种可替代布局。在可替代布局282中,浮动场栅极231位于n++材料211下面。p+材料221被布置在n++材料211上面。
在可替代布局284中,多个p+“岛”222和223覆盖在n++材料212上。P+岛222和223可采用多种形状,包括但不限于所示的圆形和正方形。在可替代布局286中,p+材料“带”224在n++材料213边缘附近形成。例如,带224可在材料213平面的上面或下面。
在另一个可替代布局288中,p+材料岛,例如岛222和/或223,是在n++材料214边缘附近形成的。根据本发明的实施例,这些和其他可替代布局可用来改变新型嵌入式二极管的特性。
根据本发明的实施例,提供了具有高静电放电性能的浮动栅极结构的系统和方法。根据本发明的实施例还提供了快速恢复触发电压和快速恢复保持电压的理想组合。进一步,根据本发明的实施例提供了用于形成具有高静电放电性能的浮动栅极结构的系统和方法,该系统和方法与现有的集成电路设计和制造的系统和方法兼容并互补。
概括说来,该说明书公开了具有高静电放电性能的浮动栅极结构的系统和方法。在一个实施例中,半导体结构包括浮动场栅极器件。浮动场栅极器件包括嵌入式二极管,该二极管的特征为具有比齐纳二极管更低的温度依赖性。嵌入式二极管的击穿电压大于相关联的集成电路的工作电压,且嵌入式二极管的快速恢复触发电压低于半导体结构的击穿电压。
以上描述了本发明的不同实施例。虽然本发明已经就特定实施例做了说明,但可以理解,本发明不应被解释为受到这些实施例的限制,而是应当按照权利要求来解释。
Claims (22)
1.一种半导体结构,包括:
浮动场栅极器件;并且
其中,所述浮动场栅极器件包括嵌入式二极管,该嵌入式二极管的特征在于具有比齐纳二极管更低的温度依赖性。
2.如权利要求1所述的半导体结构,其中,所述嵌入式二极管包括p/n型二极管。
3.如权利要求2所述的半导体结构,其中,所述嵌入式二极管进一步包括齐纳二极管。
4.如权利要求3所述的半导体结构,其中,所述p/n型二极管和所述齐纳二极管包括公共阴极。
5.如权利要求4所述的半导体结构,其中,所述嵌入式二极管的快速恢复保持电压大于相关联的集成电路的工作电压,并且所述嵌入式二极管的快速恢复触发电压低于所述半导体结构的击穿电压。
6.如权利要求5所述的半导体结构,其通过ESD触发电压来触发,其中,当所述嵌入式二极管导通时,ESD保持电压的一部分由所述嵌入式二极管维持。
7.如权利要求6所述的半导体结构,其中,所述嵌入式二极管在静电放电(ESD)事件之后截止。
8.一种用于静电放电保护的半导体结构,包括:
耦合到输出端衰减器的多个第一耙指;
交织在所述第一耙指之间并耦合到接地衰减器的多个第二耙指;
介于所述第一耙指和第二耙指之间的多个浮动场栅极;并且
其中,所述第一耙指包括嵌入式混合二极管,该嵌入式混合二极管的特征在于具有比所述半导体结构的击穿电压更低的二极管击穿电压,并具有比所述半导体结构的所述击穿电压更低的快速恢复触发电压。
9.如权利要求8所述的半导体结构,其中,所述嵌入式混合二极管的特征在于具有比齐纳二极管更低的温度依赖性。
10.如权利要求8所述的半导体结构,其中,所述嵌入式混合二极管的特征在于具有比p/n二极管更低的温度依赖性。
11.如权利要求8所述的半导体结构,其中,所述嵌入式混合二极管包括齐纳二极管。
12.如权利要求8所述的半导体结构,其中,所述嵌入式混合二极管包括p/n二极管。
13.如权利要求12所述的半导体结构,其中,所述p/n二极管包括阳极材料的阱。
14.如权利要求8所述的半导体结构,其中,所述嵌入式混合二极管包括齐纳二极管和p/n二极管,这二者共用一个公共阴极。
15.如权利要求8所述的半导体结构,其中,所述ESD结构对其击穿电压进行调整。
16.一种半导体结构,包括:
用于驱动芯片外的输出的电路;
其中,所述电路包括下拉器件;以及
嵌入在所述电路中的混合二极管器件,其特征在于具有比所述下拉器件的击穿电压更低的触发电压。
17.一种用于在ESD事件期间对集成电路(IC)提供保护的静电放电(ESD)保护电路,所述电路包括:
电流控制组件;和
与所述电流控制组件串联的电流方向控制组件,
其中,所述静电放电保护电路的快速恢复保持电压大于集成电路的工作电压,并且所述静电放电保护电路的快速恢复触发电压低于所述IC的氧化物击穿电压。
18.如权利要求17所述的ESD保护电路,其中,所述电流控制组件是晶体管。
19.如权利要求17所述的ESD保护电路,其中,所述晶体管是MOSFET。
20.如权利要求18所述的ESD保护电路,其中,所述晶体管和所述二极管在ESD事件之后关断。
21.如权利要求17所述的ESD保护电路,其中,所述电流方向控制组件是嵌入到所述电流控制组件中的二极管。
22.如权利要求21所述的ESD保护电路,其由ESD触发电压来触发,其中,当所述二极管导通时,保持电压的一部分由所述二极管维持。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105609500A (zh) * | 2016-01-28 | 2016-05-25 | 嘉兴爱禾电子有限公司 | 一种共极集成二极管 |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007096211A (ja) * | 2005-09-30 | 2007-04-12 | Ricoh Co Ltd | 半導体装置 |
US7544545B2 (en) | 2005-12-28 | 2009-06-09 | Vishay-Siliconix | Trench polysilicon diode |
JP5296450B2 (ja) * | 2008-08-13 | 2013-09-25 | セイコーインスツル株式会社 | 半導体装置 |
DE102008047850B4 (de) * | 2008-09-18 | 2015-08-20 | Austriamicrosystems Ag | Halbleiterkörper mit einer Schutzstruktur und Verfahren zum Herstellen derselben |
US9124354B2 (en) * | 2011-05-12 | 2015-09-01 | St-Ericsson Sa | Isolation and protection circuit for a receiver in a wireless communication device |
US10381473B2 (en) | 2016-12-02 | 2019-08-13 | Vishay-Siliconix | High-electron-mobility transistor with buried interconnect |
US10693288B2 (en) | 2018-06-26 | 2020-06-23 | Vishay SIliconix, LLC | Protection circuits with negative gate swing capability |
US10833063B2 (en) | 2018-07-25 | 2020-11-10 | Vishay SIliconix, LLC | High electron mobility transistor ESD protection structures |
US11632142B1 (en) | 2021-11-09 | 2023-04-18 | Macom Technology Solutions Holdings, Inc. | Hybrid diode silicon on insulator front end module and related method |
Family Cites Families (105)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4677369A (en) | 1985-09-19 | 1987-06-30 | Precision Monolithics, Inc. | CMOS temperature insensitive voltage reference |
US4748103A (en) | 1986-03-21 | 1988-05-31 | Advanced Power Technology | Mask-surrogate semiconductor process employing dopant protective region |
JP2667392B2 (ja) | 1986-09-26 | 1997-10-27 | 株式会社デンソー | 多結晶半導体ダイオードの製造方法 |
US5283201A (en) | 1988-05-17 | 1994-02-01 | Advanced Power Technology, Inc. | High density power device fabrication process |
US20020074585A1 (en) | 1988-05-17 | 2002-06-20 | Advanced Power Technology, Inc., Delaware Corporation | Self-aligned power MOSFET with enhanced base region |
US4922371A (en) * | 1988-11-01 | 1990-05-01 | Teledyne Semiconductor | ESD protection circuit for MOS integrated circuits |
US5055896A (en) | 1988-12-15 | 1991-10-08 | Siliconix Incorporated | Self-aligned LDD lateral DMOS transistor with high-voltage interconnect capability |
US5072266A (en) | 1988-12-27 | 1991-12-10 | Siliconix Incorporated | Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry |
DE4200884A1 (de) * | 1991-01-16 | 1992-07-23 | Micron Technology Inc | Integrierte halbleiterschaltungsvorrichtung |
JPH0590520A (ja) * | 1991-09-26 | 1993-04-09 | Nissan Motor Co Ltd | 半導体保護装置 |
US5416351A (en) * | 1991-10-30 | 1995-05-16 | Harris Corporation | Electrostatic discharge protection |
JPH05291501A (ja) * | 1992-04-13 | 1993-11-05 | Nissan Motor Co Ltd | 半導体保護装置 |
US5559044A (en) | 1992-09-21 | 1996-09-24 | Siliconix Incorporated | BiCDMOS process technology |
US5648281A (en) | 1992-09-21 | 1997-07-15 | Siliconix Incorporated | Method for forming an isolation structure and a bipolar transistor on a semiconductor substrate |
JP3167457B2 (ja) | 1992-10-22 | 2001-05-21 | 株式会社東芝 | 半導体装置 |
JP3311070B2 (ja) | 1993-03-15 | 2002-08-05 | 株式会社東芝 | 半導体装置 |
US5404041A (en) | 1993-03-31 | 1995-04-04 | Texas Instruments Incorporated | Source contact placement for efficient ESD/EOS protection in grounded substrate MOS integrated circuit |
GB9306895D0 (en) | 1993-04-01 | 1993-05-26 | Philips Electronics Uk Ltd | A method of manufacturing a semiconductor device comprising an insulated gate field effect device |
WO1994027325A1 (en) | 1993-05-07 | 1994-11-24 | Vlsi Technology, Inc. | Integrated circuit structure and method |
US5430315A (en) | 1993-07-22 | 1995-07-04 | Rumennik; Vladimir | Bi-directional power trench MOS field effect transistor having low on-state resistance and low leakage current |
US5416036A (en) | 1993-10-04 | 1995-05-16 | United Microelectronics Corporation | Method of improvement ESD for LDD process |
US5374565A (en) | 1993-10-22 | 1994-12-20 | United Microelectronics Corporation | Method for ESD protection improvement |
JP2630242B2 (ja) | 1993-12-28 | 1997-07-16 | 日本電気株式会社 | 温度検出用ダイオード付パワーmosfet |
US5529941A (en) | 1994-03-28 | 1996-06-25 | Vlsi Technology, Inc. | Method for making an integrated circuit structure |
JPH07273320A (ja) | 1994-03-31 | 1995-10-20 | Toshiba Corp | 半導体装置 |
US5455444A (en) | 1994-04-22 | 1995-10-03 | United Microelectronics Corporation | Double polysilicon electrostatic discharge protection device for SRAM and DRAM memory devices |
US5519242A (en) * | 1994-08-17 | 1996-05-21 | David Sarnoff Research Center, Inc. | Electrostatic discharge protection circuit for a NMOS or lateral NPN transistor |
US5545909A (en) | 1994-10-19 | 1996-08-13 | Siliconix Incorporated | Electrostatic discharge protection device for integrated circuit |
US5733794A (en) | 1995-02-06 | 1998-03-31 | Motorola, Inc. | Process for forming a semiconductor device with ESD protection |
US5637900A (en) * | 1995-04-06 | 1997-06-10 | Industrial Technology Research Institute | Latchup-free fully-protected CMOS on-chip ESD protection circuit |
US5567634A (en) | 1995-05-01 | 1996-10-22 | National Semiconductor Corporation | Method of fabricating self-aligned contact trench DMOS transistors |
US6140678A (en) | 1995-06-02 | 2000-10-31 | Siliconix Incorporated | Trench-gated power MOSFET with protective diode |
US5998837A (en) | 1995-06-02 | 1999-12-07 | Siliconix Incorporated | Trench-gated power MOSFET with protective diode having adjustable breakdown voltage |
US5661322A (en) | 1995-06-02 | 1997-08-26 | Siliconix Incorporated | Bidirectional blocking accumulation-mode trench power MOSFET |
JP2988871B2 (ja) | 1995-06-02 | 1999-12-13 | シリコニックス・インコーポレイテッド | トレンチゲートパワーmosfet |
US6049108A (en) | 1995-06-02 | 2000-04-11 | Siliconix Incorporated | Trench-gated MOSFET with bidirectional voltage clamping |
US6078090A (en) | 1997-04-02 | 2000-06-20 | Siliconix Incorporated | Trench-gated Schottky diode with integral clamping diode |
EP0864178A4 (en) | 1995-10-02 | 2001-10-10 | Siliconix Inc | SLIDED GRID MOSFET HAVING AN INTEGRATED TEMPERATURE SENSING DIODE |
JPH09129877A (ja) | 1995-10-30 | 1997-05-16 | Toyota Central Res & Dev Lab Inc | 半導体装置の製造方法、絶縁ゲート型半導体装置の製造方法および絶縁ゲート型半導体装置 |
US5637898A (en) | 1995-12-22 | 1997-06-10 | North Carolina State University | Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance |
US5672527A (en) | 1996-03-08 | 1997-09-30 | United Microelectronics Corp. | Method for fabricating an electrostatic discharge protection circuit |
US5585299A (en) | 1996-03-19 | 1996-12-17 | United Microelectronics Corporation | Process for fabricating a semiconductor electrostatic discharge (ESD) protective device |
US5912494A (en) | 1996-04-02 | 1999-06-15 | Winbond Electronics Corporation | Internal ESD protection structure with contact diffusion |
US5674761A (en) | 1996-05-02 | 1997-10-07 | Etron Technology, Inc. | Method of making ESD protection device structure for low supply voltage applications |
US5850095A (en) | 1996-09-24 | 1998-12-15 | Texas Instruments Incorporated | ESD protection circuit using zener diode and interdigitated NPN transistor |
US5882967A (en) * | 1997-05-07 | 1999-03-16 | International Business Machines Corporation | Process for buried diode formation in CMOS |
JP3502531B2 (ja) | 1997-08-28 | 2004-03-02 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
KR100239424B1 (ko) * | 1997-09-26 | 2000-01-15 | 김영환 | 정전기 보호회로 |
US6268242B1 (en) | 1997-12-31 | 2001-07-31 | Richard K. Williams | Method of forming vertical mosfet device having voltage clamped gate and self-aligned contact |
US6060752A (en) | 1997-12-31 | 2000-05-09 | Siliconix, Incorporated | Electrostatic discharge protection circuit |
JPH11233641A (ja) * | 1998-02-10 | 1999-08-27 | Seiko Epson Corp | 半導体装置及び半導体装置の製造方法 |
US5953601A (en) | 1998-02-17 | 1999-09-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | ESD implantation scheme for 0.35 μm 3.3V 70A gate oxide process |
JP3705919B2 (ja) | 1998-03-05 | 2005-10-12 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
US6044018A (en) * | 1998-06-17 | 2000-03-28 | Mosel Vitelic, Inc. | Single-poly flash memory cell for embedded application and related methods |
JP3413569B2 (ja) | 1998-09-16 | 2003-06-03 | 株式会社日立製作所 | 絶縁ゲート型半導体装置およびその製造方法 |
JP3574359B2 (ja) * | 1998-09-18 | 2004-10-06 | セイコーエプソン株式会社 | 半導体装置 |
KR100505619B1 (ko) | 1998-09-29 | 2005-09-26 | 삼성전자주식회사 | 반도체소자의정전하방전회로,그구조체및그구조체의제조방법 |
US5998833A (en) | 1998-10-26 | 1999-12-07 | North Carolina State University | Power semiconductor devices having improved high frequency switching and breakdown characteristics |
US6255683B1 (en) | 1998-12-29 | 2001-07-03 | Infineon Technologies Ag | Dynamic random access memory |
JP3743189B2 (ja) | 1999-01-27 | 2006-02-08 | 富士通株式会社 | 不揮発性半導体記憶装置及びその製造方法 |
US6268639B1 (en) | 1999-02-11 | 2001-07-31 | Xilinx, Inc. | Electrostatic-discharge protection circuit |
US6277695B1 (en) | 1999-04-16 | 2001-08-21 | Siliconix Incorporated | Method of forming vertical planar DMOSFET with self-aligned contact |
US6413822B2 (en) | 1999-04-22 | 2002-07-02 | Advanced Analogic Technologies, Inc. | Super-self-aligned fabrication process of trench-gate DMOS with overlying device layer |
US6347026B1 (en) | 1999-05-26 | 2002-02-12 | Lsi Logic Corporation | Input and power protection circuit implemented in a complementary metal oxide semiconductor process using salicides |
US6191447B1 (en) | 1999-05-28 | 2001-02-20 | Micro-Ohm Corporation | Power semiconductor devices that utilize tapered trench-based insulating regions to improve electric field profiles in highly doped drift region mesas and methods of forming same |
US6211018B1 (en) | 1999-08-14 | 2001-04-03 | Electronics And Telecommunications Research Institute | Method for fabricating high density trench gate type power device |
JP3708764B2 (ja) * | 1999-09-07 | 2005-10-19 | Necエレクトロニクス株式会社 | 半導体装置 |
JP3348711B2 (ja) * | 1999-12-03 | 2002-11-20 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
JP3573674B2 (ja) | 1999-12-27 | 2004-10-06 | Necエレクトロニクス株式会社 | 半導体集積回路の入出力保護装置とその保護方法 |
US6548860B1 (en) | 2000-02-29 | 2003-04-15 | General Semiconductor, Inc. | DMOS transistor structure having improved performance |
JP2001257349A (ja) | 2000-03-09 | 2001-09-21 | Sanyo Electric Co Ltd | Mosfetの保護装置 |
JP3675303B2 (ja) | 2000-05-31 | 2005-07-27 | セイコーエプソン株式会社 | 静電気保護回路が内蔵された半導体装置及びその製造方法 |
JP2002016080A (ja) | 2000-06-28 | 2002-01-18 | Toshiba Corp | トレンチゲート型mosfetの製造方法 |
US6700158B1 (en) | 2000-08-18 | 2004-03-02 | Fairchild Semiconductor Corporation | Trench corner protection for trench MOSFET |
JP2002110978A (ja) | 2000-10-02 | 2002-04-12 | Toshiba Corp | 電力用半導体素子 |
US6631060B2 (en) | 2000-11-30 | 2003-10-07 | Winbond Electronics Corporation | Field oxide device with zener junction for electrostatic discharge (ESD) protection and other applications |
JP2002208677A (ja) | 2001-01-12 | 2002-07-26 | Toyota Industries Corp | 温度検出機能を備える半導体装置 |
US6815775B2 (en) | 2001-02-02 | 2004-11-09 | Industrial Technology Research Institute | ESD protection design with turn-on restraining method and structures |
JP4932088B2 (ja) | 2001-02-19 | 2012-05-16 | ルネサスエレクトロニクス株式会社 | 絶縁ゲート型半導体装置の製造方法 |
JP2002270841A (ja) | 2001-03-13 | 2002-09-20 | Denso Corp | 半導体装置及びその製造方法 |
JP2002274640A (ja) | 2001-03-19 | 2002-09-25 | Honda Motor Co Ltd | パレットストッパ装置 |
US6882000B2 (en) | 2001-08-10 | 2005-04-19 | Siliconix Incorporated | Trench MIS device with reduced gate-to-drain capacitance |
US6514839B1 (en) * | 2001-10-05 | 2003-02-04 | Taiwan Semiconductor Manufacturing Company | ESD implantation method in deep-submicron CMOS technology for high-voltage-tolerant applications with light-doping concentrations |
US20030071310A1 (en) | 2001-10-11 | 2003-04-17 | Salling Craig T. | Method to increase substrate potential in MOS transistors used in ESD protection circuits |
JP4426967B2 (ja) | 2001-11-02 | 2010-03-03 | フェアチャイルド セミコンダクター コーポレイション | N型埋込層を使用することによるesdnmosのトリガリングの改善 |
KR100406180B1 (ko) | 2001-12-22 | 2003-11-17 | 주식회사 하이닉스반도체 | 플래쉬 메모리 셀의 제조 방법 |
US6838722B2 (en) | 2002-03-22 | 2005-01-04 | Siliconix Incorporated | Structures of and methods of fabricating trench-gated MIS devices |
US6855593B2 (en) | 2002-07-11 | 2005-02-15 | International Rectifier Corporation | Trench Schottky barrier diode |
US8629019B2 (en) | 2002-09-24 | 2014-01-14 | Vishay-Siliconix | Method of forming self aligned contacts for a power MOSFET |
US7190563B2 (en) | 2002-10-18 | 2007-03-13 | Agere Systems Inc. | Electrostatic discharge protection in a semiconductor device |
JP3931138B2 (ja) | 2002-12-25 | 2007-06-13 | 三菱電機株式会社 | 電力用半導体装置及び電力用半導体装置の製造方法 |
TW200411897A (en) * | 2002-12-30 | 2004-07-01 | Winbond Electronics Corp | Robust ESD protection structures |
JP2004247455A (ja) * | 2003-02-13 | 2004-09-02 | Seiko Epson Corp | 半導体装置 |
US6861701B2 (en) | 2003-03-05 | 2005-03-01 | Advanced Analogic Technologies, Inc. | Trench power MOSFET with planarized gate bus |
JP2004296883A (ja) * | 2003-03-27 | 2004-10-21 | Sharp Corp | 半導体装置とその製造方法 |
US6919603B2 (en) | 2003-04-30 | 2005-07-19 | Texas Instruments Incorporated | Efficient protection structure for reverse pin-to-pin electrostatic discharge |
US7019368B1 (en) | 2003-07-11 | 2006-03-28 | Actel Corporation | Low-capacitance input/output and electrostatic discharge circuit for protecting an integrated circuit from electrostatic discharge |
US20050036251A1 (en) | 2003-08-12 | 2005-02-17 | Micrel, Incorporated | Electrostatic discharge protection for trim-diodes |
US7129557B2 (en) | 2004-05-25 | 2006-10-31 | International Business Machines Corporation | Autonomic thermal monitor and controller for thin film devices |
US7781826B2 (en) * | 2006-11-16 | 2010-08-24 | Alpha & Omega Semiconductor, Ltd. | Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter |
US7279773B2 (en) * | 2005-03-15 | 2007-10-09 | Delphi Technologies, Inc. | Protection device for handling energy transients |
US20060268479A1 (en) * | 2005-05-31 | 2006-11-30 | Atmel Germany Gmbh | ESD protection structure |
US7583485B1 (en) | 2005-07-26 | 2009-09-01 | Vishay-Siliconix | Electrostatic discharge protection circuit for integrated circuits |
US7544545B2 (en) | 2005-12-28 | 2009-06-09 | Vishay-Siliconix | Trench polysilicon diode |
JP2011233641A (ja) | 2010-04-26 | 2011-11-17 | Disco Abrasive Syst Ltd | 板状物のレーザー加工方法 |
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CN105609500A (zh) * | 2016-01-28 | 2016-05-25 | 嘉兴爱禾电子有限公司 | 一种共极集成二极管 |
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EP1977450B1 (en) | 2015-06-10 |
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