TWI355684B - Doped intride film, doped oxide film and other dop - Google Patents

Doped intride film, doped oxide film and other dop Download PDF

Info

Publication number
TWI355684B
TWI355684B TW094118424A TW94118424A TWI355684B TW I355684 B TWI355684 B TW I355684B TW 094118424 A TW094118424 A TW 094118424A TW 94118424 A TW94118424 A TW 94118424A TW I355684 B TWI355684 B TW I355684B
Authority
TW
Taiwan
Prior art keywords
layer
doped
precursor
ruthenium
tantalum nitride
Prior art date
Application number
TW094118424A
Other languages
English (en)
Other versions
TW200614349A (en
Inventor
Ashima B Chakravarti
Judson Holt
Kevin K Chan
Sadanand Deshpande
Rangarajan Jagannathan
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200614349A publication Critical patent/TW200614349A/zh
Application granted granted Critical
Publication of TWI355684B publication Critical patent/TWI355684B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/308—Oxynitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3145—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers formed by deposition from a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3148—Silicon Carbide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/318—Inorganic layers composed of nitrides
    • H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

1355684 【發明所屬之技術領域】 本發明大體來說係有關於用來製造半導體元件之 層，特別是氮化物層及氧化物層。 【先前技術】 為了改善互補式金屬氧化物半導體（CMOS)元件之 驅動電流，具應力之層已用來做為間隙壁或中段製程線層
(也稱為前金屬介電沉積（PMD)線層）。現業界已知造成高 張應力或高壓應力氮化物層的沉積機制（例如快速熱化學 氣相沉積（RTCVD)、電漿輔助化學氣相沉積（PEC VD)、使 ，用矽（Si)前驅物之高密度電漿（HDP)，例如矽烷（siH4)、二 氣矽烷（DCS)、乙矽烷（Disilane)、六氯乙带炫 (Hexachlorodisilane) ' 雙三級丁胺基矽燒（bistertiary butyl amino silane)(BTBAS)、以及氨（NH3))。但是，在已 知沉積機制内只可能在一小範圍内調整應力。& t a 右不女描增
或薄膜品質將難以大範圍的調整應力。 此外，益發需要在較低溫下沉積由引浊μ 延矽化鎳（NiSi) 製程驅動之後段製程之氮化物/氧化物層e 匕研究過許多 低溫前驅物，但並沒有理想的結果》 通常在一 LPCVD爐管中係在700°C及承< 史向溫度下使 用DCS及氨來沉積氮化矽層。 【發明内容】 5 1355684 有均勻分布摻質濃度之經摻雜的氮化矽層（例如具有均勻 分布之鍺濃度之摻雜鍺之氮化矽層）等。根據本發明之一種 方法之一實例係，例如，添加鍺（―鍺前驅物）至矽烷及氨 之混合物中，因此形成一摻雜鍺之氮化矽層。 在本發明之進一步較佳實施例中，可應用前驅物改 變（例如，混合至少兩種前驅物等）來調整所製造之層之至 少一種化學或物理性質（例如所製造之層之應力、濕蝕刻速 率、乾蝕刻速率、蝕刻終點、沉積速率、物理、電氣及/ 或光學性質等）。 本發明方法選擇性地可進一步包含為非矽摻質測量 來自該非矽前驅物之訊號之步驟，該訊號測量係為了控制 蝕刻。 在本發明方法之某些實施例中，沉積可有利地在與 省略該非梦前驅物相比較低之溫度下進行，例如，低於約 700 °C之沉積溫度（包含但不限於低至室溫之沉積溫度） 等。可使用本發明方法之沉積之較佳實例係，例如， RTCVD(快速升溫化學氣相沉積）、pECVD(電漿輔助化學氣 相沉積）、LPCVD(低壓化學氣相沉積）、遠端氮化物電漿、 原子層沉積（ALD)等。 本發明之其他較佳實施例提供具有範圍在約3 GPa (壓應力）至3 GPa (張應力）内之可調應力之某些層，例如 氮化矽、氧化矽、氮氧化矽或碳化矽層（例如摻雜鍺之層 等）；氮化矽層’其中該層係具有均勻分佈之鍺之摻雜鍺之 氮化矽層；一摻雜鋁之氧化矽層；一摻-雜鍺之氮化矽層等； 1355684 一摻雜鍺之層，其中該摻雜鍺之層具有與由相同製程製造 但沒有摻雜鍺之層相較大至少約10 GPa之應力（較佳地， 大 1.2 GPa)。 本發明之層可包含一或多種摻質，例如多種摻質。 可在本發明之層内使用之摻質之實例包含，例如鍺（Ge)、 碳（C)、硼（B)、鋁（A1)、鎵（Ga)、銦（In)等，該等摻質可單 獨或合併使用。
【實施方式】 在本發明中，於經摻雜之氮化物層、經摻雜之氧化 物層、經摻雜之氮氧化物層或經摻榦之碳化物層之製造期 間，至少控制以下幾點之一：沉積速率；所形成之層之化 學及/或物理性質（例如可調應力）。此控制係由引進一額 外之非矽前驅物來達成，否則其並非製造氮化物層、氧化 物層、氮氧化物層、或碳化物層之習知試劑，並且該額外 之非矽前驅物之實例係鍺前驅物及碳前驅物。 本發明藉由在沉積製程期間包含一非矽前驅物摻質 (例如鍺前驅物等）來實現其優勢，例如氮化梦層之沉積、 氣化矽層之沉積、氮氧化矽層之沉積、碳化矽層之沉積等。 例如，在一實施例中，本發明藉由在氮化物層及氧 化物層及氮氧化物層及碳化物層之沉積中添加錄來使低溫 沉積氮化物層 '氧化物層、氮氧化物層及/或碳化物層成 為可能，特別是經摻雜之氮化物或氧化物層。本發明人利 用鍺化梦蟲Ba層可在比梦遙晶層低之溫度下形成之事實， 9 1355684 並且進一步發現在矽前驅物中添加鍺前驅物可降低該層之 沉積溫度。 用於本發明之鍺前驅物可以是，例如，已知之鍺前 驅物，例如在，例如’2002年8月6日核准之美國專利第 6,429,098號以及2000年9月12曰核准予Bensahel等（法 國電信（France Telecom))之美國專利第6，1 17,750號中，或 者是2001年7月1〇日核准予Reinberg(美光科技公司 (Micron Technology Inc·))之美國專利第 6,258,664 號中所
提到之鍺前驅物。鍺前驅物係可商業購得的。用於本發明 之鍺前驅物之一實例為氫化鍺（GeH4)。 本發明提供在沉積氮化矽、氧化矽、氮氧化矽、碳 化矽等時使用至少一鍺前驅物，若想要的話，其沉積有利 地可藉由低溫沉積’例如在7 0 0 °C或更低溫下之沉積，例 如室溫或其他溫度。在一較佳實例中，本發明方法可在室 /皿下於一 P3i電衆浸没工具（P3i piasma imniersion tool)中 進行，以沉積氮化物》 當在本發明中包含該非矽前驅物以製造氮化矽或氧 化矽層或氮氧化矽層或碳化矽層時，該製造製程若非如此 可關於内容物以習知方式進行，例如，使用氮前驅物（例如 氨等）以及梦前驅物（例如DCS等）等。為製造氮化矽層，一 氮前驅物係經包含在内。為製造氧化矽層，一氧前驅物係 經包含在内。為製造氮化矽或氡化矽層，一矽前驅物係經 包含在内。應理解該矽前驅物可以與該氮或氧前驅物相同 或不同。例如，BTBAS可做為矽前驅物及氮前驅物。在本
10 聲明 乃中，在某些實施例中，一試劑（例如BTBAS等）可選擇 ^用來做為兩或多種前驅物》 根據本發明利用鍺前驅物及/或碟前媒物來形成氮 ife, 7或氧化物或氮氧化物或碳化物層之一例示溫度較佳地 夂低於700°C之溫度下，更佳地在低於65CTC之溫度下， <更佳地在500 °C或更低之溫度下。例如，在摻雜鍺之 中，可使用500 r或更低之優勢溫度來沉積摻雜鍺之 氡 <卜 Q矽層。應瞭解當本發明有利地使偏好之相對低沉積溫 戍為可能時，並不需要求在所有實施例中使用低沉積溫 尺’例如，一層可在各種沉積溫度下根據本發明有利地經 應力調整。 所提到之用於本發明中之非矽前驅物並沒有特別限 制’並且做為實例可提到錯前驅物、碟前驅物、鋁前驅物、 ’前驅物、砷前驅物、铪前驅物、鎵前驅物、銦前驅物、 以及，沒有限制，其他摻質前驅物等。 本發明也可應用在MOL阻障技術上。例如，眾所 周知MOL阻障氮化物可增進元件可靠度（負偏壓溫度不穩 定性（NBTI)等）。本發明係透過鍺前驅物及/或碳前驅物之 使用的方式提供利用不同前駆物組合來調整該阻障氮化物 層之化學及/或物理性質之能力》可利用此種能力達到顯 著之元件可靠度增益》 並不特別限制根據本發明所製造之層之厚度’並且 厚度可取決於應用來選擇。層厚度範圍可從薄的限度（例如 5 00埃之層，或1〇埃，或更薄），至厚的限度（例如1〇〇0 1355684
埃之層，或50 00埃之層，或更厚），以及介於其佐 例如範圍約10至5 00 0埃之層，以及更薄或更厚 所需要者。 根據本發明所製造之層之摻質濃度並不特 可根據需要調整。摻質（例如鍺等）濃度之一實例 如，約1至10%範圍内，或者在另一實例中，： %。 本發明包含使用多種非矽前驅物之實施例 前驅物及碳前驅物；鍺前驅物及硼前驅物等。例 積氮化矽或氧化矽層期間添加多種前驅物可提 應，如可能偏好者。 本發明可用以，例如，對蝕刻終點發出訊彳 當執行習知氮化矽蝕刻時，其實存有欲在氮化梦 蝕刻並且不要過蝕刻至矽之問題。但是，此種钱 常不敏銳，因此蝕刻進入矽在習知方法中時常發 本發明，若使用經摻雜之氮化矽（例如摻雜鍺之 可利用鍺在該氮化矽中之存在來對蝕刻終點發出 此有利地避免過蝕刻，例如使用光學放射光譜來 如可尋找鍺氟化物訊號）。 前述此種蝕刻終止之實例並沒有限制，並 係延伸至使用在經摻雜之氮化物層或經摻雜之氧 之摻質之各種訊號。例如，可提供一經掺雜做為 層之薄的氮化矽層（例如摻雜鍺之氮化矽層等）， 控該摻質訊號（例如鍺訊號等）來判定該層起始處 3之厚度， ，如應用 定，並且 係在，例 約1至50 ，例如錯 如，在沉 供增強效 號。例如， 終點終止 刻終點時 生。利用 氮化矽）， 訊號’因 偵測鍺（例 且本發明 1化物層中 钱刻終止 並且可監 。關於蝕 12 1355684 刻方面，可提供本發明之多種不同實施。另一個實例是在 摻雜鍺之氮化物下方之摻雜碳或硼之薄層。對於此種結構 來說，可偵測鍺訊號之中斷及碳訊號之出現，為了更佳之 蝕刻結果。在一蝕刻製程中使用本發明之進一步實例係使 用兩種不同摻質，例如在每一個個別層中提供一種摻質， 或在同一層中提供兩種不同摻質。應瞭解本發明包含使用 受控制之不同訊號以求得最佳敏感度，並且上述只是一些 實例。
本發明之另一用途在於藉由包含摻質來改變所製造 之層（例如氮化矽、氧化矽）之應力，與不包含摻質之層相 比。例如，在氮化矽層之例子中，發現包含鍺摻質可將該 層之應力改變至張應力區。傳統上，RTCVD氮化矽層具有 約1至1.5 GPa (張應力）之應力。在氮化矽層中包含鍺提 供顯著之提升該層應力之改變，例如應力超過1.5 GPa (張 應力）之摻雜鍺之氮化矽層，例如2 GPa (張應力）或更高等 之應力。當在相同應力工具上測量根據本發明摻雜之層以 及比較之非摻雜層時，可在該經摻雜之層獲得1 GPa或更 大之△(較佳地，例如1.2 GPa或更大之Δ)。此外，本發 明可用來將一層之應力從壓應力改變為張應力，其意咮著 一層之本質之顯著改變。 因此，本發明有利地可用來按照所需調整氮化矽或 氧化矽層或氮氧化矽或碳化矽層之應力。 此外，本發明可用來製造經摻雜之氮化矽層、經摻 雜之氧化矽層、經摻雜之氮氧化矽層、以及經摻雜之碳化 13 1355684 矽層，例如，摻雜鍺之氮化矽層、摻雜鋁之氧化矽廣 '捧 雜硼之氮化矽層等。 實例1:在一 LPCVD爐管中’分別以兩種不同溫度， 700及650°C，將氫化鍺添加至DCS及氨之混合物中。也 在785C下沉積一標準氮化矽層做為控制。因此沉積出兩 層摻雜鍺之氮化矽層及一層標準氮化矽層。結果在第 2、3圖之圖表中總結。 在第1圖中，上面作圖係在785 〇c下沉積之層具 有DCS// NH3 = 0·3。第1圖中之中間作圖係在700°c下沉積 之層，具有（〇〇8 + 〇6)/>1113 = 0.3，〇6/〇〇8 = 0.25。第1圖 . 中之底部作圖係在65(TC下沉積之層，具有與在7〇〇<t下沉 _ 積之層相同之比例。 從第3圖，清楚看到藉由添加氫化鍺至該製程氣體 中，達到沉積速率之顯著增加。此外，此實例k捧雜錯 之層與標準高溫層有相同性質（由濕蝕刻速率判定）。 將鍺添加至矽前驅物及氨之混合物中容許：増加現 製程之沉積速率，使該製程更具有可製造性；降低製程 之沉積速率，使其可延伸至未來技術；及/或控制 之層之應力。 實例2.重要地’本發明已確認一層中之應力 由氮化物層形成期間添加鍺來調整。可考慮下述結果，兩 者旁為#基板.⑴對於砂—氮層應力為4E9 因/平方公分）（壓庙*、 （運 (壓應力）；（ii)對於鍺化矽一氮層，應 8.2E9Dyne/cm2(張應力）。 屬力為
14 1355684 如上面數據顯示’在習知氮化梦層和本發明摻雜錯 之氮化矽層間幾乎有數量級之應力差異。 應瞭解本發明關於沉積速率及/或應力調整之優勢 並不限於氮化物層’而是可以應用在氧化物層（例如氧化發 層等）及其他層上，例如其他非晶層。 實例3:在矽炫及氨之混合物中添加鍺，形成摻雜 鍺之氮化矽層。氫化鍺製程之沉積速率增加，與相同之無 氫化鍺製程相比。對於無鍺製程，所製造之層之應力係〇4 ® GPa (壓應力）。對於使用鍺之本發明製程，應力係〇 8 Gpa (張應力）。因此，根據本發明之鍺之使用達到1.2 GPa之 應力改變，其係一實質上之改進。 實例4:參考第4圖’示出根據本發明之一實施例 之具應力之層之實例。所示之具應力之氮化物線層40(根 據本發明製造）係與間隙壁41 '具有層44(金屬矽化物）之 閘極（多晶）並用，且閘極係位於一通道（絕緣層上矽）上。 實例5 :參考第5A-5C圖，示出根據本發明之終點 ^ 偵測之反摻雜之氮化物或氡化物層乏實例。參見第5人圖， 於一氮化物或氧化物層50(具有第二摻質）上提供包含閘極 52間隙壁氮化物51(具有第一摻質）之元件。根據第5B 圖所示之初始RIE步驟處理第5A圖之初沉積（as dep〇sited) 層，其中在初始RIE期間，偵測到該第一掺質。接著，執 行最終RIE步驟，如第5C圓所示者，其中達到蚀刻終點。 在該最終RIE步驟期間，偵測到較少量之第一摻質（在該間 隙壁氛化物5 1或經蝕刻之間隙壁氮化物5丨，中），並且第
15 1355684
二摻質（在氮化物或氧化物層5 0中）之偵測開 终點步驟後，一可控制之蝕刻間隙壁氮化物 雖然已經根據其較佳實施例描述過本 技藝者會瞭解本發明可在所附申請專利範圍 内經過調整而實施。 【圖式簡單說明】
前述及其他目的、觀點及優勢可從上 佳實施例之詳細描述並一併參考圖示而·更加 第1圖係一氮化矽層及兩個LPCVD (SiGe Nitride) 層 之 橢 圓 量 測 ineasurements)(49 點）之圖表。 第2圖係一氮化矽層及兩個鍺化矽氮 速率之圖表，基於橢圓測量法，4 9點，且第 第1圖圖表之層相關。 第3圖係沉積速率做為併入鍺之函數 具有及不具有鍺之作圖，且第3圖係與繪製 層相關。 第4圖係示出根據本發明之一實施例 之側視圖，且該具應力線層係與間隙壁、閘 用。 第5 A-5 C圖描繪出根據本發明之一實 測法。 始。在該蝕刻 5 1 ’餘留下來。 發明，但熟知 之精神及範圍 面本發明之較 清楚，其中： 鍺化矽氮化物 (ellipsometry 化物層之蝕刻 2圖係與繪製 之圖表，連同 第1圖圖表之 之具應力線層 極、及通道併 施例之終點偵 (§) 16 1355684 【主要元件符號說明】 40 氮化物線層 41 間隙壁 44 層 50 氮化物或氧化物層 5 1 間隙壁氮化物 5 15 經蝕刻之間隙壁氮化物 52 閘極
17

Claims (1)

1355684
拾、申請專利範圍： 1. 一種製造經摻雜之氮化矽層、經摻雜 雜之氮氧化矽層或經摻雜之碳化矽層之 步驟： 提供至少一種珍前驅物， 在經掺雜之氮化矽層、經掺雜之氧 氮氧化矽層的情況中，提供下列至少一 一氧前驅物， 提供至少一種非矽前驅物，以及 自該至少一種矽前驅物以及該至少 成具有.經調節至一選擇程度之一應力I 層、經摻雜之氧化矽層、經摻雜之氮氧 碳化矽層，當該層為一經摻雜之氧化矽 不是硼也不是磷， 其中該等提供步驟藉由沉積而達成 下執行。 2.如申請專利範圍第1項所述之方法， 一種攻前驅物及提供至少一種非ί夕前驅 且係以提供一氣流之方式進行。 3.如申請專利範圍第1項所述之方法， 係一鍺前驅物。 _專利案啤月修:ρ ! _ I _ ’ 之氧化發層、經換 方法，其包含下列 化矽層或經摻雜之 種：一氣前驅物或 一種非矽前驅物形 而經摻雜之氮化矽 化石夕層或經摻雜之 時，該非矽前驅物 ，且沉積是在室溫 其中上述提供至少 物係同時發生，並 其中該非矽前驅物 18 1355684 I年月日修正替換頁 UtMUo-B, tl|；4_ 4.如中請專利範圍第1項所述之方法，其中該非矽前驅物 係選自瑞前驅物、硼前驅物、鋁前驅物、砷前驅物、铪前 驅物、錄前驅物以及銦前驅物所組成之群組。 5 _如申誚·專利範圍第1項所述之方法，其中該經摻雜氮化 矽層係以鍺或碳摻雜。 6.如申請專利範圍第1項所述之方法，其中該非矽前驅物 係一有機錯化合物或一鍺前驅物，其係選自氫化鍺 (GeH4)、甲基氫化鍺（GeH3CH3)、二硼烷（dib〇rane)、三甲 基銘（TMA)、乙缔（c2h2)碳前驅物、三曱基鎵（trimethyl Ga) 一 曱基銦（trimethyl In)、三炫基氨基鎵（trialkyl amino Ga)、二院基氨基銦（trjaikyi amino In)、氫化鎵（GaH3)、氫
化銦（InH3)、氫化銘（aih3)以及三異丙氧基銘（aluminum isopropoxide)所組成之群組β 7. 如申請專利範圍第1項所述之方法，其中該等提供步驟 藉由沉積而達成，且該沉積係快速升溫化學氣相沉積 (RTCVD)、電漿輔助化學氣相沉積（PECVD)、低壓化學氣 相}儿積（LPCVD)、退端電聚氮化物或原子層沉積（ald)。 8. 如申請專利範圍第1項所述之方法，更包含下列步驟： 測量來自該非矽前驅物之一非矽摻質之一訊號，該訊號測 19 1355684 量係為了控制餘刻。 9 · 一種製造經摻雜之氮化矽層、經摻雜之氧化矽層、經摻 雜之氮氧化矽層或經摻雜之碳化矽層之方法，其包含下列 步驟： 提供至少一種碎前驅物，
在經摻雜之氮化矽層、經摻雜之氧化矽層或經摻雜之 氮氧化矽層的情況中，提供一氮前驅物或一氧前驅物之至 少一者，以及 提供至少一種非矽前驅物，其中該非矽前驅物係鍺、 碳、鋁、硼、砷、姶、鎵或銦之烷基氫化物或烷基氨基氫 化物， 其中形成經摻雜之氮化矽層、經摻雜之氧化矽層、經 掺雜之氮氧化矽層或經摻雜之碳化矽層，但當該層為一經 摻雜之氧化矽時，該非矽前驅物不是硼也不是磷。
1 0. —種製造經摻雜之氮化矽層、經摻雜之氧化矽層、經 摻雜之氮氧化矽層或經摻雜之碳化矽層之方法，其包含下 列步驟： 提供至少一種矽前驅物， 在經摻雜之氮化矽層、經摻雜之氧化矽層或經摻雜之 氮氧化矽層的情況中，提供一氮前驅物或一氧前驅物之至 少一者，以及 20 1355684 擐供至少一種非矽前驅物， 利用一前驅物改變（precursor modification)以調整一 製造之層的至少一物理性質， 其中形成經摻雜之氮化矽層、經摻雜之氧化矽層、經 摻雜之氮氧化矽層或經摻雜之碳化矽層，但當該層為一經 摻雜之氧化矽時，該非矽前驅物不是硼也不是磷，且其中 存在下列一或多者：
a) 該前驅物改變係至少兩種前驅物之一混合物， b) 該至少一物理性質係一製造之層的應力，以及 c) 該至少一物理性質係選自由濕蝕刻速率、乾蝕刻速 率、蝕刻終點、沉積速率以及電氣及/或光學性質所組成 之群組。
1 1 ·如申請專利範圍第8項所述之方法，其中該前驅物改 變係至少兩種前驅物之一混合物。 12. 如申請專利範圍第8項所述之方法，其中該至少一物 理性質係一製造之層之應力。 13. 如申請專利範圍第8項所述之方法，其中存在c)。 1 4 · 一種製造經摻雜之氮化矽層、經摻雜之氧化矽層、經 21 1355684 ifo。％。!鮮替換頁 L ~--- 摻雜之氮氧化矽層或經摻雜之碳化矽層之方法，其包含下 列步驟： 提供至少一種矽前驅物， 在經摻雜之氮化矽層、經摻雜之氧化矽層或經摻雜之 氮氧化矽層的情況中，提供一氮前驅物或一氧前驅物之至 少一者，以及 提供至少一種非矽前驅物，
其中形成經摻雜之氮化矽層、經摻雜之氧化矽層、經 摻雜之氮氧化矽層或經摻雜之碳化矽層，但當該層為一經 摻雜之氧化矽時，該非矽前驅物不是硼也不是磷，以及 其中該等提供步驟藉由沉積而達成，且沉積是在與省 略該非矽前驅物相比較低之溫度下進行。 1 5. —種製造經摻雜之氮化矽層、經摻雜之氧化矽層、經 摻雜之氮氧化矽層或經摻雜之碳化矽層之方法，其包含下 列步驟： ‘ 提供至少一種矽前驅物， 在經摻雜之氮化矽層、經摻雜之氧化矽層或經摻雜之 氣氧化石夕層的情況中，提供一氣前驅物或一氧前驅物之至 少一者； 提供至少一種非矽前驅物，其選自由鋁前驅物、姶前 驅物以及銦前驅物所組成之群組；以及 自該至少一種梦前雜物以及該至少一種非石夕前驅物形 22 1355684
成具有經調節至一選擇程度之一應力的經摻雜之氮化矽 層、經摻雜之氧化矽層、經摻雜之氮氧化矽層或經摻雜之 碳化矽層。
23
TW094118424A 2004-06-29 2005-06-03 Doped intride film, doped oxide film and other dop TWI355684B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/710,245 US20050287747A1 (en) 2004-06-29 2004-06-29 Doped nitride film, doped oxide film and other doped films

Publications (2)

Publication Number Publication Date
TW200614349A TW200614349A (en) 2006-05-01
TWI355684B true TWI355684B (en) 2012-01-01

Family

ID=35506413

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094118424A TWI355684B (en) 2004-06-29 2005-06-03 Doped intride film, doped oxide film and other dop

Country Status (4)

Country Link
US (4) US20050287747A1 (zh)
JP (1) JP5078240B2 (zh)
CN (1) CN100428424C (zh)
TW (1) TWI355684B (zh)

Families Citing this family (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7119016B2 (en) * 2003-10-15 2006-10-10 International Business Machines Corporation Deposition of carbon and nitrogen doped poly silicon films, and retarded boron diffusion and improved poly depletion
US20050287747A1 (en) * 2004-06-29 2005-12-29 International Business Machines Corporation Doped nitride film, doped oxide film and other doped films
US7288205B2 (en) * 2004-07-09 2007-10-30 Applied Materials, Inc. Hermetic low dielectric constant layer for barrier applications
JP2006165335A (ja) * 2004-12-08 2006-06-22 Toshiba Corp 半導体装置
US20060172556A1 (en) * 2005-02-01 2006-08-03 Texas Instruments Incorporated Semiconductor device having a high carbon content strain inducing film and a method of manufacture therefor
US7462527B2 (en) * 2005-07-06 2008-12-09 International Business Machines Corporation Method of forming nitride films with high compressive stress for improved PFET device performance
US20070065576A1 (en) * 2005-09-09 2007-03-22 Vikram Singh Technique for atomic layer deposition
US20070087581A1 (en) * 2005-09-09 2007-04-19 Varian Semiconductor Equipment Associates, Inc. Technique for atomic layer deposition
US7371649B2 (en) * 2005-09-13 2008-05-13 United Microelectronics Corp. Method of forming carbon-containing silicon nitride layer
US20070082507A1 (en) * 2005-10-06 2007-04-12 Applied Materials, Inc. Method and apparatus for the low temperature deposition of doped silicon nitride films
US7416995B2 (en) * 2005-11-12 2008-08-26 Applied Materials, Inc. Method for fabricating controlled stress silicon nitride films
CN101473382A (zh) 2006-05-12 2009-07-01 高级技术材料公司 相变化记忆体材料的低温沉积
US7514370B2 (en) * 2006-05-19 2009-04-07 International Business Machines Corporation Compressive nitride film and method of manufacturing thereof
US7501355B2 (en) 2006-06-29 2009-03-10 Applied Materials, Inc. Decreasing the etch rate of silicon nitride by carbon addition
KR100772836B1 (ko) 2006-07-21 2007-11-01 동부일렉트로닉스 주식회사 반도체소자의 제조 방법
KR100761857B1 (ko) * 2006-09-08 2007-09-28 삼성전자주식회사 반도체 소자의 미세패턴 형성방법 및 이를 이용한 반도체소자의 제조방법
CN101495672B (zh) 2006-11-02 2011-12-07 高级技术材料公司 对于金属薄膜的cvd/ald有用的锑及锗复合物
US20080124946A1 (en) * 2006-11-28 2008-05-29 Air Products And Chemicals, Inc. Organosilane compounds for modifying dielectrical properties of silicon oxide and silicon nitride films
US7790635B2 (en) * 2006-12-14 2010-09-07 Applied Materials, Inc. Method to increase the compressive stress of PECVD dielectric films
US20080145978A1 (en) * 2006-12-18 2008-06-19 Air Liquide Electronics U.S. Lp Deposition of silicon germanium nitrogen precursors for strain engineering
US20080293194A1 (en) * 2007-05-24 2008-11-27 Neng-Kuo Chen Method of making a P-type metal-oxide semiconductor transistor and method of making a complementary metal-oxide semiconductor transistor
US8084356B2 (en) * 2007-09-29 2011-12-27 Lam Research Corporation Methods of low-K dielectric and metal process integration
US8834968B2 (en) 2007-10-11 2014-09-16 Samsung Electronics Co., Ltd. Method of forming phase change material layer using Ge(II) source, and method of fabricating phase change memory device
KR101458953B1 (ko) 2007-10-11 2014-11-07 삼성전자주식회사 Ｇｅ（Ⅱ）소오스를 사용한 상변화 물질막 형성 방법 및상변화 메모리 소자 제조 방법
US20090096106A1 (en) * 2007-10-12 2009-04-16 Air Products And Chemicals, Inc. Antireflective coatings
US8987039B2 (en) * 2007-10-12 2015-03-24 Air Products And Chemicals, Inc. Antireflective coatings for photovoltaic applications
US7994066B1 (en) * 2007-10-13 2011-08-09 Luxtera, Inc. Si surface cleaning for semiconductor circuits
US7994042B2 (en) * 2007-10-26 2011-08-09 International Business Machines Corporation Techniques for impeding reverse engineering
JP5650880B2 (ja) * 2007-10-31 2015-01-07 アドバンスド テクノロジー マテリアルズ，インコーポレイテッド 非晶質Ｇｅ／Ｔｅ蒸着方法
JP2009164260A (ja) 2007-12-28 2009-07-23 Toshiba Corp 不揮発性半導体メモリ
JP2009200095A (ja) * 2008-02-19 2009-09-03 Tokyo Electron Ltd 薄膜およびその薄膜を用いた半導体装置の製造方法
US20090215225A1 (en) 2008-02-24 2009-08-27 Advanced Technology Materials, Inc. Tellurium compounds useful for deposition of tellurium containing materials
JP2009260151A (ja) * 2008-04-18 2009-11-05 Tokyo Electron Ltd 金属ドープ層の形成方法、成膜装置及び記憶媒体
US8343824B2 (en) * 2008-04-29 2013-01-01 International Rectifier Corporation Gallium nitride material processing and related device structures
US20110180905A1 (en) * 2008-06-10 2011-07-28 Advanced Technology Materials, Inc. GeSbTe MATERIAL INCLUDING SUPERFLOW LAYER(S), AND USE OF Ge TO PREVENT INTERACTION OF Te FROM SbXTeY AND GeXTeY RESULTING IN HIGH Te CONTENT AND FILM CRYSTALLINITY
US8330136B2 (en) 2008-12-05 2012-12-11 Advanced Technology Materials, Inc. High concentration nitrogen-containing germanium telluride based memory devices and processes of making
KR20120106888A (ko) 2009-05-22 2012-09-26 어드밴스드 테크놀러지 머티리얼즈, 인코포레이티드 저온 ｇｓｔ 방법
WO2010151856A2 (en) * 2009-06-26 2010-12-29 Cornell University Chemical vapor deposition process for aluminum silicon nitride
US8410468B2 (en) * 2009-07-02 2013-04-02 Advanced Technology Materials, Inc. Hollow GST structure with dielectric fill
US20110124182A1 (en) * 2009-11-20 2011-05-26 Advanced Techology Materials, Inc. System for the delivery of germanium-based precursor
CN102194751A (zh) * 2010-03-11 2011-09-21 中芯国际集成电路制造(上海)有限公司 制作互补型金属氧化物半导体器件的方法
TW201132787A (en) 2010-03-26 2011-10-01 Advanced Tech Materials Germanium antimony telluride materials and devices incorporating same
WO2011125395A1 (ja) 2010-04-09 2011-10-13 株式会社日立国際電気 半導体装置の製造方法、基板処理方法および基板処理装置
US9997357B2 (en) 2010-04-15 2018-06-12 Lam Research Corporation Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors
US20110256734A1 (en) 2010-04-15 2011-10-20 Hausmann Dennis M Silicon nitride films and methods
US9390909B2 (en) 2013-11-07 2016-07-12 Novellus Systems, Inc. Soft landing nanolaminates for advanced patterning
US8993460B2 (en) * 2013-01-10 2015-03-31 Novellus Systems, Inc. Apparatuses and methods for depositing SiC/SiCN films via cross-metathesis reactions with organometallic co-reactants
US9892917B2 (en) 2010-04-15 2018-02-13 Lam Research Corporation Plasma assisted atomic layer deposition of multi-layer films for patterning applications
US8637411B2 (en) 2010-04-15 2014-01-28 Novellus Systems, Inc. Plasma activated conformal dielectric film deposition
US9373500B2 (en) 2014-02-21 2016-06-21 Lam Research Corporation Plasma assisted atomic layer deposition titanium oxide for conformal encapsulation and gapfill applications
US9611544B2 (en) 2010-04-15 2017-04-04 Novellus Systems, Inc. Plasma activated conformal dielectric film deposition
US9257274B2 (en) 2010-04-15 2016-02-09 Lam Research Corporation Gapfill of variable aspect ratio features with a composite PEALD and PECVD method
US9190609B2 (en) 2010-05-21 2015-11-17 Entegris, Inc. Germanium antimony telluride materials and devices incorporating same
US8614478B2 (en) 2010-07-26 2013-12-24 Infineon Technologies Austria Ag Method for protecting a semiconductor device against degradation, a semiconductor device protected against hot charge carriers and a manufacturing method therefor
US8786012B2 (en) 2010-07-26 2014-07-22 Infineon Technologies Austria Ag Power semiconductor device and a method for forming a semiconductor device
CN102386089B (zh) * 2010-09-03 2013-06-12 中芯国际集成电路制造(上海)有限公司 制备半导体器件结构的方法
US9685320B2 (en) 2010-09-23 2017-06-20 Lam Research Corporation Methods for depositing silicon oxide
KR101381900B1 (ko) * 2010-10-01 2014-04-04 한국전자통신연구원 링 공진기의 공진파장 가변 방법
JP5689398B2 (ja) * 2010-12-21 2015-03-25 東京エレクトロン株式会社 窒化シリコン膜の成膜方法及び成膜装置
JP5847566B2 (ja) 2011-01-14 2016-01-27 株式会社日立国際電気 半導体装置の製造方法、基板処理方法、基板処理装置およびプログラム
EP3929326A3 (en) 2011-06-03 2022-03-16 Versum Materials US, LLC Compositions and processes for depositing carbon-doped silicon-containing films
JP5959307B2 (ja) 2011-06-22 2016-08-02 株式会社日立国際電気 半導体装置の製造方法、基板処理方法、基板処理装置およびプログラム
JP5793398B2 (ja) * 2011-10-28 2015-10-14 東京エレクトロン株式会社 シード層の形成方法及びシリコン含有薄膜の成膜方法
TWI606136B (zh) 2011-11-04 2017-11-21 Ａｓｍ國際股份有限公司 沉積摻雜氧化矽的方法以及用於沉積摻雜氧化矽至基板上的原子層沉積製程
US9049061B2 (en) * 2012-03-21 2015-06-02 The Institute of Microelectronics Chinese Academy of Science CMOS device and method for manufacturing the same
JP5758829B2 (ja) 2012-03-27 2015-08-05 東京エレクトロン株式会社 ボロン含有シリコン酸炭窒化膜の形成方法およびシリコン酸炭窒化膜の形成方法
CN102623333B (zh) * 2012-04-17 2014-09-03 上海华力微电子有限公司 一种形成双应力层氮化硅薄膜的方法
CN102623334B (zh) * 2012-04-17 2014-10-22 上海华力微电子有限公司 一种形成双应力层氮化硅薄膜的方法
CN102623409B (zh) * 2012-04-17 2014-08-13 上海华力微电子有限公司 一种形成双应力层氮化硅薄膜的方法
US9355839B2 (en) 2012-10-23 2016-05-31 Lam Research Corporation Sub-saturated atomic layer deposition and conformal film deposition
US9640757B2 (en) 2012-10-30 2017-05-02 Entegris, Inc. Double self-aligned phase change memory device structure
SG2013083241A (en) 2012-11-08 2014-06-27 Novellus Systems Inc Conformal film deposition for gapfill
SG2013083654A (en) 2012-11-08 2014-06-27 Novellus Systems Inc Methods for depositing films on sensitive substrates
US9500773B2 (en) * 2013-06-07 2016-11-22 Lawrence Livermore National Security, Llc High voltage photoconductive switch package
US9214334B2 (en) 2014-02-18 2015-12-15 Lam Research Corporation High growth rate process for conformal aluminum nitride
US9478438B2 (en) 2014-08-20 2016-10-25 Lam Research Corporation Method and apparatus to deposit pure titanium thin film at low temperature using titanium tetraiodide precursor
US9478411B2 (en) 2014-08-20 2016-10-25 Lam Research Corporation Method to tune TiOx stoichiometry using atomic layer deposited Ti film to minimize contact resistance for TiOx/Ti based MIS contact scheme for CMOS
US9564312B2 (en) 2014-11-24 2017-02-07 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
US9799509B2 (en) 2014-11-26 2017-10-24 Asm Ip Holding B.V. Cyclic aluminum oxynitride deposition
US9837281B2 (en) 2014-11-26 2017-12-05 Asm Ip Holding B.V. Cyclic doped aluminum nitride deposition
JP6378070B2 (ja) * 2014-12-15 2018-08-22 東京エレクトロン株式会社 成膜方法
US10566187B2 (en) 2015-03-20 2020-02-18 Lam Research Corporation Ultrathin atomic layer deposition film accuracy thickness control
US9502238B2 (en) 2015-04-03 2016-11-22 Lam Research Corporation Deposition of conformal films by atomic layer deposition and atomic layer etch
WO2016205196A2 (en) * 2015-06-16 2016-12-22 Air Products And Chemicals, Inc. Halidosilane compounds and compositions and processes for depositing silicon-containing films using same
US10526701B2 (en) 2015-07-09 2020-01-07 Lam Research Corporation Multi-cycle ALD process for film uniformity and thickness profile modulation
CN105047559B (zh) * 2015-08-12 2018-01-12 沈阳拓荆科技有限公司 通过调整宝石球高度获得不同性能氮化硅薄膜的方法
CN105256375B (zh) * 2015-09-02 2017-10-31 光昱（厦门）新能源有限公司 一种提高太阳能电池扩散炉碳化硅桨抗疲劳强度的方法
CN117265512A (zh) * 2015-09-11 2023-12-22 弗萨姆材料美国有限责任公司 用于沉积保形的金属或准金属氮化硅膜的方法和所得的膜
KR102153564B1 (ko) * 2015-10-06 2020-09-08 버슘머트리얼즈 유에스, 엘엘씨 컨포멀한 금속 또는 메탈로이드 실리콘 니트라이드 막을 증착시키는 방법
US9773643B1 (en) 2016-06-30 2017-09-26 Lam Research Corporation Apparatus and method for deposition and etch in gap fill
US10062563B2 (en) 2016-07-01 2018-08-28 Lam Research Corporation Selective atomic layer deposition with post-dose treatment
US10037884B2 (en) 2016-08-31 2018-07-31 Lam Research Corporation Selective atomic layer deposition for gapfill using sacrificial underlayer
CN106449907B (zh) * 2016-11-18 2019-04-12 电子科技大学 一种p型指数掺杂结构GaN光电阴极材料的生长方法
US10529563B2 (en) * 2017-03-29 2020-01-07 Asm Ip Holdings B.V. Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures
US10269559B2 (en) 2017-09-13 2019-04-23 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer
CN108417481B (zh) * 2018-03-22 2021-02-23 京东方科技集团股份有限公司 氮化硅介电层的处理方法、薄膜晶体管和显示装置
US11276573B2 (en) * 2019-12-04 2022-03-15 Applied Materials, Inc. Methods of forming high boron-content hard mask materials
US11674222B2 (en) * 2020-09-29 2023-06-13 Applied Materials, Inc. Method of in situ ceramic coating deposition
US20220195606A1 (en) * 2020-12-23 2022-06-23 Raytheon Technologies Corporation Method for metal vapor infiltration of cmc parts and articles containing the same

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2557079C2 (de) * 1975-12-18 1984-05-24 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren zum Herstellen einer Maskierungsschicht
JPS5298473A (en) * 1976-02-13 1977-08-18 Hitachi Ltd Thin film material
NL171942C (nl) * 1976-02-13 1983-06-01 Hitachi Ltd Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij op een halfgeleiderlichaam een menglaag van nitriden van silicium en germanium wordt aangebracht.
JPS5693375A (en) * 1979-12-26 1981-07-28 Shunpei Yamazaki Photoelectric conversion device
JPS56122123A (en) * 1980-03-03 1981-09-25 Shunpei Yamazaki Semiamorphous semiconductor
JPS56169333A (en) * 1980-05-29 1981-12-26 Fujitsu Ltd Semiconductor device
US4892753A (en) * 1986-12-19 1990-01-09 Applied Materials, Inc. Process for PECVD of silicon oxide using TEOS decomposition
US4743563A (en) * 1987-05-26 1988-05-10 Motorola, Inc. Process of controlling surface doping
JPH01176067A (ja) * 1987-12-29 1989-07-12 Hoya Corp 窒化シリコン膜の成膜方法
JP2663508B2 (ja) * 1988-05-12 1997-10-15 ソニー株式会社 気相成長方法
JPH02233531A (ja) * 1989-03-07 1990-09-17 Sony Corp 塗布ガラス組成物及び半導体装置
JPH0770531B2 (ja) * 1989-06-30 1995-07-31 川崎製鉄株式会社 埋め込み酸化膜の形成方法
JPH04165623A (ja) * 1990-10-30 1992-06-11 Nec Corp シリコンボロンナイトライド膜の形成方法
US5347100A (en) * 1991-03-29 1994-09-13 Hitachi, Ltd. Semiconductor device, process for the production thereof and apparatus for microwave plasma treatment
WO1992020833A1 (en) * 1991-05-17 1992-11-26 Lam Research Corporation A PROCESS FOR DEPOSITING A SIOx FILM HAVING REDUCED INTRINSIC STRESS AND/OR REDUCED HYDROGEN CONTENT
US5478765A (en) * 1994-05-04 1995-12-26 Regents Of The University Of Texas System Method of making an ultra thin dielectric for electronic devices
EP0724286A1 (en) * 1995-01-25 1996-07-31 Applied Materials, Inc. A method of forming a thin film of silicon oxide for a semiconductor device
JP3597305B2 (ja) * 1996-03-05 2004-12-08 株式会社半導体エネルギー研究所 液晶表示装置およびその作製方法
US5741737A (en) * 1996-06-27 1998-04-21 Cypress Semiconductor Corporation MOS transistor with ramped gate oxide thickness and method for making same
TW335511B (en) * 1996-08-02 1998-07-01 Applied Materials Inc Stress control by fluorination of silica film
US5997634A (en) * 1996-11-14 1999-12-07 Micron Technology, Inc. Method of forming a crystalline phase material
JPH113869A (ja) * 1997-06-11 1999-01-06 Nec Corp 半導体装置の製造方法
US5972765A (en) * 1997-07-16 1999-10-26 International Business Machines Corporation Use of deuterated materials in semiconductor processing
US6306722B1 (en) * 1999-05-03 2001-10-23 United Microelectronics Corp. Method for fabricating shallow trench isolation structure
US6121164A (en) * 1997-10-24 2000-09-19 Applied Materials, Inc. Method for forming low compressive stress fluorinated ozone/TEOS oxide film
US6280651B1 (en) * 1998-12-16 2001-08-28 Advanced Technology Materials, Inc. Selective silicon oxide etchant formulation including fluoride salt, chelating agent, and glycol solvent
FR2773177B1 (fr) * 1997-12-29 2000-03-17 France Telecom Procede d'obtention d'une couche de germanium ou silicium monocristallin sur un substrat de silicium ou germanium monocristallin, respectivement, et produits multicouches obtenus
US5976991A (en) * 1998-06-11 1999-11-02 Air Products And Chemicals, Inc. Deposition of silicon dioxide and silicon oxynitride using bis(tertiarybutylamino) silane
US6462371B1 (en) * 1998-11-24 2002-10-08 Micron Technology Inc. Films doped with carbon for use in integrated circuit technology
US6258664B1 (en) * 1999-02-16 2001-07-10 Micron Technology, Inc. Methods of forming silicon-comprising materials having roughened outer surfaces, and methods of forming capacitor constructions
US6261975B1 (en) * 1999-03-04 2001-07-17 Applied Materials, Inc. Method for depositing and planarizing fluorinated BPSG films
CN100385694C (zh) * 1999-03-10 2008-04-30 日立金属株式会社 热电转换材料及其制作方法
JP4597479B2 (ja) * 2000-11-22 2010-12-15 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US6768857B2 (en) * 2001-05-11 2004-07-27 International Business Machines Corporation Method for manufacturing an optical device with a defined total device stress
US7043133B2 (en) * 2001-07-12 2006-05-09 Little Optics, Inc. Silicon-oxycarbide high index contrast, low-loss optical waveguides and integrated thermo-optic devices
DE60213555T2 (de) * 2002-03-28 2007-08-09 Fluid Automation Systems S.A. Elektromagnetisches Ventil
KR100769783B1 (ko) * 2002-03-29 2007-10-24 가부시끼가이샤 도시바 표시 입력 장치 및 표시 입력 시스템
JP2003297956A (ja) * 2002-04-04 2003-10-17 Toshiba Corp 半導体記憶装置及びその製造方法
US6624093B1 (en) * 2002-10-09 2003-09-23 Wisys Technology Foundation Method of producing high dielectric insulator for integrated circuit
US20040198069A1 (en) * 2003-04-04 2004-10-07 Applied Materials, Inc. Method for hafnium nitride deposition
US6930058B2 (en) * 2003-04-21 2005-08-16 Micron Technology, Inc. Method of depositing a silicon dioxide comprising layer doped with at least one of P, B and Ge
US7119016B2 (en) * 2003-10-15 2006-10-10 International Business Machines Corporation Deposition of carbon and nitrogen doped poly silicon films, and retarded boron diffusion and improved poly depletion
US6939814B2 (en) * 2003-10-30 2005-09-06 International Business Machines Corporation Increasing carrier mobility in NFET and PFET transistors on a common wafer
US7129126B2 (en) * 2003-11-05 2006-10-31 International Business Machines Corporation Method and structure for forming strained Si for CMOS devices
US20050109276A1 (en) * 2003-11-25 2005-05-26 Applied Materials, Inc. Thermal chemical vapor deposition of silicon nitride using BTBAS bis(tertiary-butylamino silane) in a single wafer chamber
US7001844B2 (en) * 2004-04-30 2006-02-21 International Business Machines Corporation Material for contact etch layer to enhance device performance
US20050287747A1 (en) * 2004-06-29 2005-12-29 International Business Machines Corporation Doped nitride film, doped oxide film and other doped films

Also Published As

Publication number Publication date
US20080054228A1 (en) 2008-03-06
JP2006013503A (ja) 2006-01-12
US20060138566A1 (en) 2006-06-29
US7361611B2 (en) 2008-04-22
US20050287747A1 (en) 2005-12-29
TW200614349A (en) 2006-05-01
CN100428424C (zh) 2008-10-22
US20060237846A1 (en) 2006-10-26
CN1716548A (zh) 2006-01-04
US7595010B2 (en) 2009-09-29
JP5078240B2 (ja) 2012-11-21

Similar Documents

Publication Publication Date Title
TWI355684B (en) Doped intride film, doped oxide film and other dop
US20210254238A1 (en) Method for depositing low temperature phosphorous-doped silicon
KR102623651B1 (ko) 실리콘 게르마늄 주석 층을 형성하는 방법 및 관련 반도체 소자 구조
TWI811348B (zh) 藉由循環沉積製程於基板上沉積氧化物膜之方法及相關裝置結構
KR20190093498A (ko) 기판 표면 위에 반도체 구조체를 증착하기 위한 방법 및 이와 관련된 반도체 구조체
TWI404123B (zh) 半導體膜之選擇性磊晶成長
KR100925310B1 (ko) 고 완화율 및 저 적층 결함 밀도를 갖는 박막 ｓｇｏｉ웨이퍼를 형성하는 방법
US20070251444A1 (en) PEALD Deposition of a Silicon-Based Material
US20110003451A1 (en) Intermediate product for a multichannel fet and process for obtaining an intermediate product
TW200845137A (en) Semiconductor wafer and process for its production
KR101821707B1 (ko) 인장 변형 적용들을 위한 고인장 실리콘 합금의 에피택시
WO2008096884A1 (ja) ｎ型導電性窒化アルミニウム半導体結晶及びその製造方法
US8617938B2 (en) Device and method for boron diffusion in semiconductors
Joshi et al. LPCVD and PECVD silicon nitride for microelectronics technology
CN100576451C (zh) 栅极侧壁层的形成方法
CN104956498B (zh) 半导体层序列和用于制造半导体层序列的方法
CN109148503A (zh) 图像传感器及其形成方法
CN100561672C (zh) 栅极侧壁层的形成方法
US20230230833A1 (en) Method for forming a layer provided with silicon
CN113725066A (zh) 用于沉积含硼和镓的硅锗层的方法
US20040018674A1 (en) Method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetration
CN102655092A (zh) 晶体管的制备方法
KR101141244B1 (ko) 고유전율 물질인 하프늄옥사이드 산화막의 두께 조절을 이용한 게이트 산화막 형성방법 및 이를 이용한 게이트 전극
CN107749394B (zh) 一种氮化硅薄膜制备方法
US8158495B2 (en) Process for forming a silicon-based single-crystal portion

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees